ARM: tegra: thermal: Edp into cooling device
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  * Copyright (c) 2011-2012, NVIDIA Corporation.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/serial_8250.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/panjit_ts.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/gpio.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/spi/spi.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44
45
46 #include <sound/wm8903.h>
47 #include <sound/max98095.h>
48 #include <media/tegra_dtv.h>
49
50 #include <asm/hardware/gic.h>
51
52 #include <mach/edp.h>
53 #include <mach/clk.h>
54 #include <mach/iomap.h>
55 #include <mach/irqs.h>
56 #include <mach/pinmux.h>
57 #include <mach/iomap.h>
58 #include <mach/io_dpd.h>
59 #include <mach/io.h>
60 #include <mach/i2s.h>
61 #include <mach/tegra_asoc_pdata.h>
62 #include <mach/tegra_wm8903_pdata.h>
63 #include <mach/usb_phy.h>
64 #include <mach/thermal.h>
65 #include <mach/pci.h>
66 #include <mach/gpio-tegra.h>
67 #include <mach/tegra_fiq_debugger.h>
68 #include <linux/thermal.h>
69
70 #include <asm/hardware/gic.h>
71 #include <asm/mach-types.h>
72 #include <asm/mach/arch.h>
73
74 #include "board.h"
75 #include "clock.h"
76 #include "board-cardhu.h"
77 #include "board-touch.h"
78 #include "devices.h"
79 #include "gpio-names.h"
80 #include "fuse.h"
81 #include "pm.h"
82 #include "baseband-xmm-power.h"
83 #include "wdt-recovery.h"
84 #include "common.h"
85
86 static struct balanced_throttle throttle_list[] = {
87         {
88                 .tegra_cdev = {
89                         .id = CDEV_BTHROT_ID_TJ,
90                 },
91                 .throt_tab_size = 10,
92                 .throt_tab = {
93                         {      0, 1000 },
94                         { 640000, 1000 },
95                         { 640000, 1000 },
96                         { 640000, 1000 },
97                         { 640000, 1000 },
98                         { 640000, 1000 },
99                         { 760000, 1000 },
100                         { 760000, 1050 },
101                         {1000000, 1050 },
102                         {1000000, 1100 },
103                 },
104         },
105 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
106         {
107                 .tegra_cdev = {
108                         .id = CDEV_BTHROT_ID_SKIN,
109                 },
110                 .throt_tab_size = 6,
111                 .throt_tab = {
112                         { 640000, 1200 },
113                         { 640000, 1200 },
114                         { 760000, 1200 },
115                         { 760000, 1200 },
116                         {1000000, 1200 },
117                         {1000000, 1200 },
118                 },
119         },
120 #endif
121 };
122
123 /* All units are in millicelsius */
124 static struct tegra_thermal_data thermal_data = {
125         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
126 #ifdef CONFIG_TEGRA_EDP_LIMITS
127         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
128         .hysteresis_edp = 3000,
129 #endif
130         .temp_throttle = 85000,
131         .binds = {
132                 /* Thermal Throttling */
133                 {
134                         .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
135                         .cdev_id = CDEV_BTHROT_ID_TJ,
136                         .type = THERMAL_TRIP_PASSIVE,
137                         .passive = {
138                                 .trip_temp = 85000,
139                                 .tc1 = 0,
140                                 .tc2 = 1,
141                                 .passive_delay = 2000,
142                         }
143                 },
144                 /* EDP Capping */
145                 {
146                         .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
147                         .cdev_id = CDEV_EDPTABLE_ID_EDP,
148                         .type = THERMAL_TRIP_ACTIVE,
149                         .get_trip_temp = tegra_edp_get_trip_temp,
150                         .get_trip_size = tegra_edp_get_trip_size,
151                 },
152 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
153                 /* Skin Thermal Throttling */
154                 {
155                         .tdev_id = THERMAL_DEVICE_ID_SKIN,
156                         .cdev_id = CDEV_BTHROT_ID_SKIN,
157                         .type = THERMAL_TRIP_PASSIVE,
158                         .passive = {
159                                 .trip_temp = 43000,
160                                 .tc1 = 10,
161                                 .tc2 = 1,
162                                 .passive_delay = 15000,
163                         }
164                 },
165 #endif
166                 {
167                         .tdev_id = THERMAL_DEVICE_ID_NULL,
168                 },
169         },
170 };
171
172 static struct tegra_skin_data skin_data = {
173 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
174         .skin_device_id = THERMAL_DEVICE_ID_THERM_EST_SKIN,
175         .temp_throttle_skin = 43000,
176         .skin_temp_offset = 9793,
177         .skin_period = 1100,
178         .skin_devs_size = 2,
179         .skin_devs = {
180                 {
181                         THERMAL_DEVICE_ID_NCT_EXT,
182                         {
183                                 2, 1, 1, 1,
184                                 1, 1, 1, 1,
185                                 1, 1, 1, 0,
186                                 1, 1, 0, 0,
187                                 0, 0, -1, -7
188                         }
189                 },
190                 {
191                         THERMAL_DEVICE_ID_NCT_INT,
192                         {
193                                 -11, -7, -5, -3,
194                                 -3, -2, -1, 0,
195                                 0, 0, 1, 1,
196                                 1, 2, 2, 3,
197                                 4, 6, 11, 18
198                         }
199                 },
200         },
201 #else
202         .skin_device_id = THERMAL_DEVICE_ID_NULL,
203 #endif
204 };
205
206
207 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
208         {
209                 .name           = "bt_rfkill",
210                 .shutdown_gpio  = TEGRA_GPIO_PU0,
211                 .reset_gpio     = TEGRA_GPIO_INVALID,
212                 .type           = RFKILL_TYPE_BLUETOOTH,
213         },
214 };
215
216 static struct platform_device cardhu_bt_rfkill_device = {
217         .name = "rfkill_gpio",
218         .id             = -1,
219         .dev = {
220                 .platform_data = &cardhu_bt_rfkill_pdata,
221         },
222 };
223
224 static struct resource cardhu_bluesleep_resources[] = {
225         [0] = {
226                 .name = "gpio_host_wake",
227                         .start  = TEGRA_GPIO_PU6,
228                         .end    = TEGRA_GPIO_PU6,
229                         .flags  = IORESOURCE_IO,
230         },
231         [1] = {
232                 .name = "gpio_ext_wake",
233                         .start  = TEGRA_GPIO_PU1,
234                         .end    = TEGRA_GPIO_PU1,
235                         .flags  = IORESOURCE_IO,
236         },
237         [2] = {
238                 .name = "host_wake",
239                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
240         },
241 };
242
243 static struct platform_device cardhu_bluesleep_device = {
244         .name           = "bluesleep",
245         .id             = -1,
246         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
247         .resource       = cardhu_bluesleep_resources,
248 };
249
250 static noinline void __init cardhu_setup_bluesleep(void)
251 {
252         cardhu_bluesleep_resources[2].start =
253                 cardhu_bluesleep_resources[2].end =
254                         gpio_to_irq(TEGRA_GPIO_PU6);
255         platform_device_register(&cardhu_bluesleep_device);
256         return;
257 }
258
259 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
260         /* name         parent          rate            enabled */
261         { "pll_m",      NULL,           0,              false},
262         { "hda",        "pll_p",        108000000,      false},
263         { "hda2codec_2x","pll_p",       48000000,       false},
264         { "pwm",        "pll_p",        3187500,        false},
265         { "blink",      "clk_32k",      32768,          true},
266         { "i2s0",       "pll_a_out0",   0,              false},
267         { "i2s1",       "pll_a_out0",   0,              false},
268         { "i2s3",       "pll_a_out0",   0,              false},
269         { "spdif_out",  "pll_a_out0",   0,              false},
270         { "d_audio",    "clk_m",        12000000,       false},
271         { "dam0",       "clk_m",        12000000,       false},
272         { "dam1",       "clk_m",        12000000,       false},
273         { "dam2",       "clk_m",        12000000,       false},
274         { "audio1",     "i2s1_sync",    0,              false},
275         { "audio3",     "i2s3_sync",    0,              false},
276         { "vi_sensor",  "pll_p",        150000000,      false},
277         { "i2c1",       "pll_p",        3200000,        false},
278         { "i2c2",       "pll_p",        3200000,        false},
279         { "i2c3",       "pll_p",        3200000,        false},
280         { "i2c4",       "pll_p",        3200000,        false},
281         { "i2c5",       "pll_p",        3200000,        false},
282         { "vi",         "pll_p",        0,              false},
283         { NULL,         NULL,           0,              0},
284 };
285
286 static struct pn544_i2c_platform_data nfc_pdata = {
287         .irq_gpio = TEGRA_GPIO_PX0,
288         .ven_gpio = TEGRA_GPIO_PP3,
289         .firm_gpio = TEGRA_GPIO_PO7,
290         };
291
292 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
293         {
294                 I2C_BOARD_INFO("pn544", 0x28),
295                 .platform_data = &nfc_pdata,
296         },
297 };
298 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
299         .adapter_nr     = 0,
300         .bus_count      = 1,
301         .bus_clk_rate   = { 100000, 0 },
302         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
303         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
304         .arb_recovery = arb_lost_recovery,
305 };
306
307 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
308         .adapter_nr     = 1,
309         .bus_count      = 1,
310         .bus_clk_rate   = { 400000, 0 },
311         .is_clkon_always = true,
312         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
313         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
314         .arb_recovery = arb_lost_recovery,
315 };
316
317 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
318         .adapter_nr     = 2,
319         .bus_count      = 1,
320         .bus_clk_rate   = { 100000, 0 },
321         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
322         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
323         .arb_recovery = arb_lost_recovery,
324 };
325
326 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
327         .adapter_nr     = 3,
328         .bus_count      = 1,
329         .bus_clk_rate   = { 10000, 0 },
330         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
331         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
332         .arb_recovery = arb_lost_recovery,
333 };
334
335 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
336         .adapter_nr     = 4,
337         .bus_count      = 1,
338         .bus_clk_rate   = { 400000, 0 },
339         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
340         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
341         .arb_recovery = arb_lost_recovery,
342 };
343
344
345 #if 0
346 struct tegra_wired_jack_conf audio_wr_jack_conf = {
347         .hp_det_n = TEGRA_GPIO_PW2,
348         .en_mic_ext = TEGRA_GPIO_PX1,
349         .en_mic_int = TEGRA_GPIO_PX0,
350 };
351 #endif
352
353 static struct wm8903_platform_data cardhu_wm8903_pdata = {
354         .irq_active_low = 0,
355         .micdet_cfg = 0,
356         .micdet_delay = 100,
357         .gpio_base = CARDHU_GPIO_WM8903(0),
358         .gpio_cfg = {
359                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
360                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
361                         WM8903_GP2_DIR,
362                 WM8903_GPIO_CONFIG_ZERO,
363                 0,
364                 0,
365         },
366 };
367
368 /* Equalizer filter coefs generated from the MAXIM MAX98095
369  * evkit software tool */
370 static struct max98095_eq_cfg max98095_eq_cfg[] = {
371         {
372                 .name = "FLAT",
373                 .rate = 44100,
374                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
375                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
376                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
377                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
378                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
379         },
380         {
381                 .name = "LOWPASS1K",
382                 .rate = 44100,
383                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
384                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
385                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
386                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
387                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
388         },
389         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
390                 .name = "HIBOOST",
391                 .rate = 44100,
392                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
393                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
394                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
395                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
396                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
397         },
398         { /* BASS=12dB, TREBLE=+12dB */
399                 .name = "LOUD12DB",
400                 .rate = 44100,
401                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
402                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
403                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
404                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
405                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
406         },
407         {
408                 .name = "FLAT",
409                 .rate = 16000,
410                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
411                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
412                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
413                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
414                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
415         },
416         {
417                 .name = "LOWPASS1K",
418                 .rate = 16000,
419                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
420                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
421                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
422                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
423                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
424         },
425         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
426                 .name = "HIBOOST",
427                 .rate = 16000,
428                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
429                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
430                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
431                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
432                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
433         },
434         { /* BASS=12dB, TREBLE=+12dB */
435                 .name = "LOUD12DB",
436                 .rate = 16000,
437                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
438                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
439                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
440                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
441                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
442         },
443 };
444
445 static struct max98095_pdata cardhu_max98095_pdata = {
446         /* equalizer configuration */
447         .eq_cfg = max98095_eq_cfg,
448         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
449
450         /* Biquad filter response configuration */
451         .bq_cfg = NULL,
452         .bq_cfgcnt = 0,
453
454         /* microphone configuration */
455         .digmic_left_mode = 1,
456         .digmic_right_mode = 1,
457 };
458
459 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
460         I2C_BOARD_INFO("wm8903", 0x1a),
461         .platform_data = &cardhu_wm8903_pdata,
462 };
463
464 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
465         I2C_BOARD_INFO("aic3262-codec", 0x18),
466 };
467
468 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
469         I2C_BOARD_INFO("max98095", 0x10),
470         .platform_data = &cardhu_max98095_pdata,
471 };
472
473 static void cardhu_i2c_init(void)
474 {
475         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
476         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
477         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
478         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
479         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
480
481         platform_device_register(&tegra_i2c_device5);
482         platform_device_register(&tegra_i2c_device4);
483         platform_device_register(&tegra_i2c_device3);
484         platform_device_register(&tegra_i2c_device2);
485         platform_device_register(&tegra_i2c_device1);
486
487         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
488                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
489         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
490         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
491         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
492
493         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
494         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
495 }
496
497 static struct platform_device *cardhu_uart_devices[] __initdata = {
498         &tegra_uarta_device,
499         &tegra_uartb_device,
500         &tegra_uartc_device,
501         &tegra_uartd_device,
502         &tegra_uarte_device,
503 };
504 static struct uart_clk_parent uart_parent_clk[] = {
505         [0] = {.name = "clk_m"},
506         [1] = {.name = "pll_p"},
507 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
508         [2] = {.name = "pll_m"},
509 #endif
510 };
511
512 static struct tegra_uart_platform_data cardhu_uart_pdata;
513 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
514
515 static void __init uart_debug_init(void)
516 {
517         struct board_info board_info;
518         int debug_port_id;
519
520         tegra_get_board_info(&board_info);
521
522         debug_port_id = get_tegra_uart_debug_port_id();
523         if (debug_port_id < 0) {
524                 debug_port_id = 0;
525                         /* UARTB is debug port
526                          *       for SLT - E1186/E1187/PM269
527                          *       for E1256/E1257
528                          */
529                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
530                         ((board_info.board_id == BOARD_E1186) ||
531                         (board_info.board_id == BOARD_E1187) ||
532                         (board_info.board_id == BOARD_PM269))) ||
533                         (board_info.board_id == BOARD_E1256) ||
534                         (board_info.board_id == BOARD_E1257))
535                                 debug_port_id = 1;
536         }
537
538 #ifdef CONFIG_TEGRA_IRDA
539         if ((board_info.board_id == BOARD_E1186) ||
540                 (board_info.board_id == BOARD_E1198)) {
541                 if (debug_port_id == 1) {
542                         cardhu_irda_pdata.is_irda = false;
543                         pr_err("UARTB is not available for IrDA\n");
544                 }
545         }
546 #endif
547
548         switch (debug_port_id) {
549         case 0:
550                 /* UARTA is the debug port. */
551                 pr_info("Selecting UARTA as the debug console\n");
552                 cardhu_uart_devices[0] = &debug_uarta_device;
553                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
554                 debug_uart_port_base = ((struct plat_serial8250_port *)(
555                         debug_uarta_device.dev.platform_data))->mapbase;
556                 break;
557
558         case 1:
559                 /* UARTB is the debug port. */
560                 pr_info("Selecting UARTB as the debug console\n");
561                 cardhu_uart_devices[1] = &debug_uartb_device;
562                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
563                 debug_uart_port_base = ((struct plat_serial8250_port *)(
564                         debug_uartb_device.dev.platform_data))->mapbase;
565                 break;
566
567         case 2:
568                 /* UARTC is the debug port. */
569                 pr_info("Selecting UARTC as the debug console\n");
570                 cardhu_uart_devices[2] = &debug_uartc_device;
571                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
572                 debug_uart_port_base = ((struct plat_serial8250_port *)(
573                         debug_uartc_device.dev.platform_data))->mapbase;
574                 break;
575
576         case 3:
577                 /* UARTD is the debug port. */
578                 pr_info("Selecting UARTD as the debug console\n");
579                 cardhu_uart_devices[3] = &debug_uartd_device;
580                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
581                 debug_uart_port_base = ((struct plat_serial8250_port *)(
582                         debug_uartd_device.dev.platform_data))->mapbase;
583                 break;
584
585         case 4:
586                 /* UARTE is the debug port. */
587                 pr_info("Selecting UARTE as the debug console\n");
588                 cardhu_uart_devices[4] = &debug_uarte_device;
589                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
590                 debug_uart_port_base = ((struct plat_serial8250_port *)(
591                         debug_uarte_device.dev.platform_data))->mapbase;
592                 break;
593
594         default:
595                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
596                 cardhu_uart_devices[0] = &debug_uarta_device;
597                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
598                 debug_uart_port_base = ((struct plat_serial8250_port *)(
599                         debug_uarta_device.dev.platform_data))->mapbase;
600                 break;
601         }
602         return;
603 }
604
605 static void __init cardhu_uart_init(void)
606 {
607         struct clk *c;
608         int i;
609         struct board_info board_info;
610
611         tegra_get_board_info(&board_info);
612
613         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
614                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
615                 if (IS_ERR_OR_NULL(c)) {
616                         pr_err("Not able to get the clock for %s\n",
617                                                 uart_parent_clk[i].name);
618                         continue;
619                 }
620                 uart_parent_clk[i].parent_clk = c;
621                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
622         }
623         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
624         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
625         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
626         cardhu_loopback_uart_pdata.parent_clk_count =
627                                                 ARRAY_SIZE(uart_parent_clk);
628         cardhu_loopback_uart_pdata.is_loopback = true;
629         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
630         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
631         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
632         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
633         /* UARTE is used for loopback test purpose */
634         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
635
636         /* Register low speed only if it is selected */
637         if (!is_tegra_debug_uartport_hs()) {
638                 uart_debug_init();
639                 /* Clock enable for the debug channel */
640                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
641                         pr_info("The debug console clock name is %s\n",
642                                                 debug_uart_clk->name);
643                         c = tegra_get_clock_by_name("pll_p");
644                         if (IS_ERR_OR_NULL(c))
645                                 pr_err("Not getting the parent clock pll_p\n");
646                         else
647                                 clk_set_parent(debug_uart_clk, c);
648
649                         clk_enable(debug_uart_clk);
650                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
651                 } else {
652                         pr_err("Not getting the clock %s for debug console\n",
653                                         debug_uart_clk->name);
654                 }
655         }
656
657 #ifdef CONFIG_TEGRA_IRDA
658         if (((board_info.board_id == BOARD_E1186) ||
659                 (board_info.board_id == BOARD_E1198)) &&
660                         cardhu_irda_pdata.is_irda) {
661                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
662                 cardhu_irda_pdata.parent_clk_count =
663                                         ARRAY_SIZE(uart_parent_clk);
664
665                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
666         }
667 #endif
668
669         platform_add_devices(cardhu_uart_devices,
670                                 ARRAY_SIZE(cardhu_uart_devices));
671 }
672
673 static struct platform_device tegra_camera = {
674         .name = "tegra_camera",
675         .id = -1,
676 };
677
678 static struct platform_device *cardhu_spi_devices[] __initdata = {
679         &tegra_spi_device4,
680 };
681
682 static struct platform_device *touch_spi_device[] __initdata = {
683         &tegra_spi_device1,
684 };
685
686 struct spi_clk_parent spi_parent_clk[] = {
687         [0] = {.name = "pll_p"},
688 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
689         [1] = {.name = "pll_m"},
690         [2] = {.name = "clk_m"},
691 #else
692         [1] = {.name = "clk_m"},
693 #endif
694 };
695
696 static struct tegra_spi_platform_data cardhu_spi_pdata = {
697         .is_dma_based           = true,
698         .max_dma_buffer         = (16 * 1024),
699         .is_clkon_always        = false,
700         .max_rate               = 100000000,
701 };
702
703 static void __init cardhu_spi_init(void)
704 {
705         int i;
706         struct clk *c;
707         struct board_info board_info, display_board_info;
708
709         tegra_get_board_info(&board_info);
710         tegra_get_display_board_info(&display_board_info);
711
712         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
713                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
714                 if (IS_ERR_OR_NULL(c)) {
715                         pr_err("Not able to get the clock for %s\n",
716                                                 spi_parent_clk[i].name);
717                         continue;
718                 }
719                 spi_parent_clk[i].parent_clk = c;
720                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
721         }
722         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
723         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
724         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
725         platform_add_devices(cardhu_spi_devices,
726                                 ARRAY_SIZE(cardhu_spi_devices));
727
728         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
729                 platform_add_devices(touch_spi_device,
730                                 ARRAY_SIZE(touch_spi_device));
731         }
732         if (board_info.board_id == BOARD_E1198) {
733                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
734                 platform_device_register(&tegra_spi_device2);
735                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
736                 platform_device_register(&tegra_spi_slave_device1);
737         }
738 }
739
740 static void __init cardhu_dtv_init(void)
741 {
742         struct board_info board_info;
743
744         tegra_get_board_info(&board_info);
745
746         if (board_info.board_id == BOARD_E1186)
747                 platform_device_register(&tegra_dtv_device);
748 }
749
750 static struct resource tegra_rtc_resources[] = {
751         [0] = {
752                 .start = TEGRA_RTC_BASE,
753                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
754                 .flags = IORESOURCE_MEM,
755         },
756         [1] = {
757                 .start = INT_RTC,
758                 .end = INT_RTC,
759                 .flags = IORESOURCE_IRQ,
760         },
761 };
762
763 static struct platform_device tegra_rtc_device = {
764         .name = "tegra_rtc",
765         .id   = -1,
766         .resource = tegra_rtc_resources,
767         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
768 };
769
770 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
771         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
772         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
773         .gpio_hp_mute           = -1,
774         .gpio_int_mic_en        = -1,
775         .gpio_ext_mic_en        = -1,
776         .i2s_param[HIFI_CODEC]  = {
777                 .audio_port_id  = 0,
778                 .is_i2s_master  = 1,
779                 .i2s_mode       = TEGRA_DAIFMT_I2S,
780         },
781         .i2s_param[BASEBAND]    = {
782                 .audio_port_id  = -1,
783         },
784         .i2s_param[BT_SCO]      = {
785                 .audio_port_id  = 3,
786                 .is_i2s_master  = 1,
787                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
788         },
789 };
790
791 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
792         .gpio_spkr_en           = -1,
793         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
794         .gpio_hp_mute           = -1,
795         .gpio_int_mic_en        = -1,
796         .gpio_ext_mic_en        = -1,
797         .i2s_param[HIFI_CODEC]  = {
798                 .audio_port_id  = 0,
799                 .is_i2s_master  = 1,
800                 .i2s_mode       = TEGRA_DAIFMT_I2S,
801         },
802         .i2s_param[BASEBAND]    = {
803                 .audio_port_id  = -1,
804         },
805         .i2s_param[BT_SCO]      = {
806                 .audio_port_id  = 3,
807                 .is_i2s_master  = 1,
808                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
809         },
810 };
811
812 static struct platform_device cardhu_audio_wm8903_device = {
813         .name   = "tegra-snd-wm8903",
814         .id     = 0,
815         .dev    = {
816                 .platform_data = &cardhu_audio_wm8903_pdata,
817         },
818 };
819
820 static struct platform_device cardhu_audio_max98095_device = {
821         .name   = "tegra-snd-max98095",
822         .id     = 0,
823         .dev    = {
824                 .platform_data = &cardhu_audio_max98095_pdata,
825         },
826 };
827
828 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
829         .gpio_spkr_en           = -1,
830         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
831         .gpio_hp_mute           = -1,
832         .gpio_int_mic_en        = -1,
833         .gpio_ext_mic_en        = -1,
834         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
835         .i2s_param[HIFI_CODEC]  = {
836                 .audio_port_id  = 0,
837                 .is_i2s_master  = 1,
838                 .i2s_mode       = TEGRA_DAIFMT_I2S,
839                 .sample_size    = 16,
840         },
841         .i2s_param[BT_SCO]      = {
842                 .sample_size    = 16,
843                 .audio_port_id  = 3,
844                 .is_i2s_master  = 1,
845                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
846         },
847 };
848
849 static struct platform_device cardhu_audio_aic326x_device = {
850         .name   = "tegra-snd-aic326x",
851         .id     = 0,
852         .dev    = {
853                 .platform_data  = &cardhu_audio_aic326x_pdata,
854         },
855 };
856
857 static struct platform_device *cardhu_devices[] __initdata = {
858         &tegra_pmu_device,
859         &tegra_rtc_device,
860         &tegra_udc_device,
861         &tegra_wdt0_device,
862         &tegra_wdt1_device,
863         &tegra_wdt2_device,
864 #if defined(CONFIG_TEGRA_AVP)
865         &tegra_avp_device,
866 #endif
867         &tegra_camera,
868 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
869         &tegra_se_device,
870 #endif
871         &tegra_ahub_device,
872         &tegra_dam_device0,
873         &tegra_dam_device1,
874         &tegra_dam_device2,
875         &tegra_i2s_device0,
876         &tegra_i2s_device1,
877         &tegra_i2s_device3,
878         &tegra_spdif_device,
879         &spdif_dit_device,
880         &bluetooth_dit_device,
881         &baseband_dit_device,
882         &cardhu_bt_rfkill_device,
883         &tegra_pcm_device,
884         &cardhu_audio_wm8903_device,
885         &cardhu_audio_max98095_device,
886         &cardhu_audio_aic326x_device,
887         &tegra_hda_device,
888         &tegra_cec_device,
889 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
890         &tegra_aes_device,
891 #endif
892 };
893
894 #define E1506_MXT_CONFIG_CRC 0x62F903
895 static const u8 e1506_config[] = {
896         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
897         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
898         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
899         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
900         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
901         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
902         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
903         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
904         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
906         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
907         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
908         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
909         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
910         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
911         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
912         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
913         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
914         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
915         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
916         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
917         0x00
918 };
919
920 #define MXT_CONFIG_CRC  0xD62DE8
921 static const u8 config[] = {
922         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
923         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
924         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
925         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
926         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
927         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
928         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
929         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
930         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
931         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
932         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
933         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
934         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
935         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
936         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
937         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
938         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
939         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
940         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
941         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
942 };
943
944 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
945 static const u8 config_sku2000[] = {
946         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
947         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
948         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
949         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
950         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
951         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
952         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
953         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
954         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
955         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
956         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
957         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
958         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
959         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
960         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
961         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
962         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
963         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
964         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
965         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
966 };
967
968 static struct mxt_platform_data atmel_mxt_info = {
969         .x_line         = 27,
970         .y_line         = 42,
971         .x_size         = 768,
972         .y_size         = 1366,
973         .blen           = 0x20,
974         .threshold      = 0x3C,
975         .voltage        = 3300000,              /* 3.3V */
976         .orient         = 5,
977         .config         = config,
978         .config_length  = 157,
979         .config_crc     = MXT_CONFIG_CRC,
980         .irqflags       = IRQF_TRIGGER_FALLING,
981 /*      .read_chg       = &read_chg, */
982         .read_chg       = NULL,
983 };
984
985 static struct mxt_platform_data e1506_atmel_mxt_info = {
986         .x_line         = 19,
987         .y_line         = 11,
988         .x_size         = 960,
989         .y_size         = 540,
990         .blen           = 0x10,
991         .threshold      = 0x32,
992         .voltage        = 3300000,              /* 3.3V */
993         .orient         = 3,
994         .config         = e1506_config,
995         .config_length  = 168,
996         .config_crc     = E1506_MXT_CONFIG_CRC,
997         .irqflags       = IRQF_TRIGGER_FALLING,
998 /*      .read_chg       = &read_chg, */
999         .read_chg       = NULL,
1000 };
1001
1002 static struct i2c_board_info __initdata atmel_i2c_info[] = {
1003         {
1004                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
1005                 .platform_data = &atmel_mxt_info,
1006         }
1007 };
1008
1009 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
1010         {
1011                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
1012                 .platform_data = &e1506_atmel_mxt_info,
1013         }
1014 };
1015
1016 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
1017         /* name         parent          rate            enabled */
1018         { "sbc1",       "pll_p",        52000000,       true},
1019         { NULL,         NULL,           0,              0},
1020 };
1021
1022 static int __init cardhu_touch_init(void)
1023 {
1024         struct board_info BoardInfo, DisplayBoardInfo;
1025
1026         tegra_get_board_info(&BoardInfo);
1027         tegra_get_display_board_info(&DisplayBoardInfo);
1028         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
1029                 tegra_clk_init_from_table(spi_clk_init_table);
1030
1031                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
1032         } else {
1033                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1034                 gpio_direction_input(TEGRA_GPIO_PH4);
1035
1036                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1037                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1038                 msleep(1);
1039                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1040                 msleep(100);
1041
1042                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1043                         atmel_mxt_info.config = config_sku2000;
1044                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1045                 }
1046
1047                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1048                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1049                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1050                 } else {
1051                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1052                         i2c_register_board_info(1, atmel_i2c_info, 1);
1053                 }
1054         }
1055
1056         return 0;
1057 }
1058
1059 #if defined(CONFIG_USB_SUPPORT)
1060
1061 static void cardu_usb_hsic_postsupend(void)
1062 {
1063 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1064         baseband_xmm_set_power_status(BBXMM_PS_L2);
1065 #endif
1066 }
1067
1068 static void cardu_usb_hsic_preresume(void)
1069 {
1070 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1071         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1072 #endif
1073 }
1074
1075 static void cardu_usb_hsic_phy_ready(void)
1076 {
1077 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1078         baseband_xmm_set_power_status(BBXMM_PS_L0);
1079 #endif
1080 }
1081
1082 static void cardu_usb_hsic_phy_off(void)
1083 {
1084 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1085         baseband_xmm_set_power_status(BBXMM_PS_L3);
1086 #endif
1087 }
1088
1089 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1090         .post_suspend = cardu_usb_hsic_postsupend,
1091         .pre_resume = cardu_usb_hsic_preresume,
1092         .port_power = cardu_usb_hsic_phy_ready,
1093         .post_phy_off = cardu_usb_hsic_phy_off,
1094 };
1095
1096 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1097         .port_otg = false,
1098         .has_hostpc = true,
1099         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1100         .op_mode        = TEGRA_USB_OPMODE_HOST,
1101         .u_data.host = {
1102                 .vbus_gpio = -1,
1103                 .hot_plug = false,
1104                 .remote_wakeup_supported = false,
1105                 .power_off_on_suspend = false,
1106         },
1107         .ops = &hsic_xmm_plat_ops,
1108 };
1109 #endif
1110
1111 static int hsic_enable_gpio = -1;
1112 static int hsic_reset_gpio = -1;
1113
1114 void hsic_platform_open(void)
1115 {
1116         int reset_gpio = 0, enable_gpio = 0;
1117
1118         if (hsic_enable_gpio != -1)
1119                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1120         if (hsic_reset_gpio != -1)
1121                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1122         /* hsic enable signal deasserted, hsic reset asserted */
1123         if (!enable_gpio)
1124                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1125         if (!reset_gpio)
1126                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1127         /* keep hsic reset asserted for 1 ms */
1128         udelay(1000);
1129         /* enable (power on) hsic */
1130         if (!enable_gpio)
1131                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1132         udelay(1000);
1133         /* deassert reset */
1134         if (!reset_gpio)
1135                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1136
1137 }
1138
1139 void hsic_platform_close(void)
1140 {
1141         if (hsic_enable_gpio != -1) {
1142                 gpio_set_value(hsic_enable_gpio, 0);
1143                 gpio_free(hsic_enable_gpio);
1144         }
1145         if (hsic_reset_gpio != -1) {
1146                 gpio_set_value(hsic_reset_gpio, 0);
1147                 gpio_free(hsic_reset_gpio);
1148         }
1149 }
1150
1151 void hsic_power_on(void)
1152 {
1153         if (hsic_enable_gpio != -1) {
1154                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1155                 udelay(1000);
1156         }
1157 }
1158
1159 void hsic_power_off(void)
1160 {
1161         if (hsic_enable_gpio != -1) {
1162                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1163                 udelay(1000);
1164         }
1165 }
1166
1167 #if defined(CONFIG_USB_SUPPORT)
1168 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1169         .open = hsic_platform_open,
1170         .close = hsic_platform_close,
1171         .pre_phy_on = hsic_power_on,
1172         .post_phy_off = hsic_power_off,
1173 };
1174
1175 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1176         .port_otg = false,
1177         .has_hostpc = true,
1178         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1179         .op_mode        = TEGRA_USB_OPMODE_HOST,
1180         .u_data.host = {
1181                 .vbus_gpio = -1,
1182                 .hot_plug = false,
1183                 .remote_wakeup_supported = false,
1184                 .power_off_on_suspend = false,
1185         },
1186         .ops = &hsic_plat_ops,
1187 };
1188
1189 static struct tegra_usb_platform_data tegra_udc_pdata = {
1190         .port_otg = true,
1191         .has_hostpc = true,
1192         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1193         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1194         .u_data.dev = {
1195                 .vbus_pmu_irq = 0,
1196                 .vbus_gpio = -1,
1197                 .charging_supported = false,
1198                 .remote_wakeup_supported = false,
1199         },
1200         .u_cfg.utmi = {
1201                 .hssync_start_delay = 0,
1202                 .elastic_limit = 16,
1203                 .idle_wait_delay = 17,
1204                 .term_range_adj = 6,
1205                 .xcvr_setup = 8,
1206                 .xcvr_lsfslew = 2,
1207                 .xcvr_lsrslew = 2,
1208                 .xcvr_setup_offset = 0,
1209                 .xcvr_use_fuses = 1,
1210         },
1211 };
1212
1213 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1214         .port_otg = false,
1215         .has_hostpc = true,
1216         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1217         .op_mode        = TEGRA_USB_OPMODE_HOST,
1218         .u_data.host = {
1219                 .vbus_gpio = -1,
1220                 .hot_plug = false,
1221                 .remote_wakeup_supported = true,
1222                 .power_off_on_suspend = true,
1223         },
1224         .u_cfg.utmi = {
1225                 .hssync_start_delay = 0,
1226                 .elastic_limit = 16,
1227                 .idle_wait_delay = 17,
1228                 .term_range_adj = 6,
1229                 .xcvr_setup = 15,
1230                 .xcvr_lsfslew = 2,
1231                 .xcvr_lsrslew = 2,
1232                 .xcvr_setup_offset = 0,
1233                 .xcvr_use_fuses = 1,
1234         },
1235 };
1236
1237 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1238         .port_otg = false,
1239         .has_hostpc = true,
1240         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1241         .op_mode = TEGRA_USB_OPMODE_HOST,
1242         .u_data.host = {
1243                 .vbus_gpio = -1,
1244                 .vbus_reg = "vdd_vbus_typea_usb",
1245                 .hot_plug = true,
1246                 .remote_wakeup_supported = true,
1247                 .power_off_on_suspend = true,
1248         },
1249         .u_cfg.utmi = {
1250                 .hssync_start_delay = 0,
1251                 .elastic_limit = 16,
1252                 .idle_wait_delay = 17,
1253                 .term_range_adj = 6,
1254                 .xcvr_setup = 8,
1255                 .xcvr_lsfslew = 2,
1256                 .xcvr_lsrslew = 2,
1257                 .xcvr_setup_offset = 0,
1258                 .xcvr_use_fuses = 1,
1259         },
1260 };
1261
1262 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1263         .port_otg = true,
1264         .has_hostpc = true,
1265         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1266         .op_mode = TEGRA_USB_OPMODE_HOST,
1267         .u_data.host = {
1268                 .vbus_gpio = -1,
1269                 .vbus_reg = "vdd_vbus_micro_usb",
1270                 .hot_plug = true,
1271                 .remote_wakeup_supported = true,
1272                 .power_off_on_suspend = true,
1273         },
1274         .u_cfg.utmi = {
1275                 .hssync_start_delay = 0,
1276                 .elastic_limit = 16,
1277                 .idle_wait_delay = 17,
1278                 .term_range_adj = 6,
1279                 .xcvr_setup = 15,
1280                 .xcvr_lsfslew = 2,
1281                 .xcvr_lsrslew = 2,
1282                 .xcvr_setup_offset = 0,
1283                 .xcvr_use_fuses = 1,
1284         },
1285 };
1286
1287 static struct tegra_usb_otg_data tegra_otg_pdata = {
1288         .ehci_device = &tegra_ehci1_device,
1289         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1290 };
1291 #endif
1292
1293 #if defined(CONFIG_USB_SUPPORT)
1294 static void cardhu_usb_init(void)
1295 {
1296         struct board_info bi;
1297
1298         tegra_get_board_info(&bi);
1299
1300         /* OTG should be the first to be registered */
1301         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1302         platform_device_register(&tegra_otg_device);
1303
1304         /* setup the udc platform data */
1305         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1306
1307         if (bi.board_id == BOARD_PM267) {
1308                 hsic_enable_gpio = EN_HSIC_GPIO;
1309                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1310                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1311                 platform_device_register(&tegra_ehci2_device);
1312         } else if (bi.board_id == BOARD_E1256) {
1313                 hsic_enable_gpio = EN_HSIC_GPIO;
1314                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1315                 platform_device_register(&tegra_ehci2_device);
1316         } else if (bi.board_id == BOARD_E1186) {
1317                 tegra_ehci2_device.dev.platform_data =
1318                                                 &tegra_ehci2_hsic_xmm_pdata;
1319                 /* ehci2 registration happens in baseband-xmm-power  */
1320         } else {
1321                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1322                 platform_device_register(&tegra_ehci2_device);
1323         }
1324
1325         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1326         platform_device_register(&tegra_ehci3_device);
1327
1328 }
1329 #else
1330 static void cardhu_usb_init(void) { }
1331 #endif
1332
1333 static struct baseband_power_platform_data tegra_baseband_power_data = {
1334         .baseband_type = BASEBAND_XMM,
1335         .modem = {
1336         .xmm = {
1337                         .bb_rst = XMM_GPIO_BB_RST,
1338                         .bb_on = XMM_GPIO_BB_ON,
1339                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1340                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1341                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1342                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1343                         .hsic_device = &tegra_ehci2_device,
1344                 },
1345         },
1346 };
1347
1348 static struct platform_device tegra_baseband_power_device = {
1349         .name = "baseband_xmm_power",
1350         .id = -1,
1351         .dev = {
1352                 .platform_data = &tegra_baseband_power_data,
1353         },
1354 };
1355
1356 static struct platform_device tegra_baseband_power2_device = {
1357         .name = "baseband_xmm_power2",
1358         .id = -1,
1359         .dev = {
1360                 .platform_data = &tegra_baseband_power_data,
1361         },
1362 };
1363
1364
1365 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1366         .port_status[0] = 1,
1367         .port_status[1] = 1,
1368         .port_status[2] = 1,
1369         .use_dock_detect        = 0,
1370         .gpio           = 0,
1371 };
1372
1373 static void cardhu_pci_init(void)
1374 {
1375         struct board_info board_info;
1376
1377         tegra_get_board_info(&board_info);
1378         if (board_info.board_id == BOARD_E1291) {
1379                 cardhu_pci_platform_data.port_status[0] = 0;
1380                 cardhu_pci_platform_data.port_status[1] = 0;
1381                 cardhu_pci_platform_data.port_status[2] = 1;
1382                 cardhu_pci_platform_data.use_dock_detect = 1;
1383                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1384         }
1385         if ((board_info.board_id == BOARD_E1186) ||
1386                 (board_info.board_id == BOARD_E1187) ||
1387                 (board_info.board_id == BOARD_E1291)) {
1388                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1389                 platform_device_register(&tegra_pci_device);
1390         }
1391 }
1392
1393 static void cardhu_modem_init(void)
1394 {
1395         struct board_info board_info;
1396         int w_disable_gpio, ret;
1397
1398         tegra_get_board_info(&board_info);
1399         switch (board_info.board_id) {
1400         case BOARD_E1291:
1401         case BOARD_E1198:
1402                 if (((board_info.board_id == BOARD_E1291) &&
1403                                 (board_info.fab < BOARD_FAB_A03)) ||
1404                         ((board_info.board_id == BOARD_E1198) &&
1405                                         (board_info.fab < BOARD_FAB_A02))) {
1406                         w_disable_gpio = TEGRA_GPIO_PH5;
1407                 } else {
1408                         w_disable_gpio = TEGRA_GPIO_PDD5;
1409                 }
1410
1411                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1412                 if (ret < 0)
1413                         pr_err("%s: gpio_request failed for gpio %d\n",
1414                                 __func__, w_disable_gpio);
1415                 else
1416                         gpio_direction_input(w_disable_gpio);
1417
1418                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1419                 if (((board_info.board_id == BOARD_E1291) &&
1420                                 (board_info.fab >= BOARD_FAB_A04)) ||
1421                         ((board_info.board_id == BOARD_E1198) &&
1422                                         (board_info.fab >= BOARD_FAB_A02))) {
1423                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1424                         if (ret < 0) {
1425                                 pr_err("%s(): Error in allocating gpio "
1426                                         "TEGRA_GPIO_PH7\n", __func__);
1427                                 break;
1428                         }
1429                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1430                 }
1431                 break;
1432         case BOARD_E1186:
1433                 platform_device_register(&tegra_baseband_power_device);
1434                 platform_device_register(&tegra_baseband_power2_device);
1435                 break;
1436         default:
1437                 break;
1438         }
1439
1440 }
1441
1442 #ifdef CONFIG_SATA_AHCI_TEGRA
1443 static void cardhu_sata_init(void)
1444 {
1445         platform_device_register(&tegra_sata_device);
1446 }
1447 #else
1448 static void cardhu_sata_init(void) { }
1449 #endif
1450
1451 static void __init tegra_cardhu_init(void)
1452 {
1453         tegra_thermal_init(&thermal_data,
1454                                 &skin_data,
1455                                 throttle_list,
1456                                 ARRAY_SIZE(throttle_list));
1457         tegra_clk_init_from_table(cardhu_clk_init_table);
1458         tegra_enable_pinmux();
1459         tegra_smmu_init();
1460         cardhu_pinmux_init();
1461         cardhu_i2c_init();
1462         cardhu_spi_init();
1463         cardhu_usb_init();
1464 #ifdef CONFIG_TEGRA_EDP_LIMITS
1465         cardhu_edp_init();
1466 #endif
1467         cardhu_uart_init();
1468         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1469         tegra_ram_console_debug_init();
1470         tegra_io_dpd_init();
1471         cardhu_sdhci_init();
1472         cardhu_regulator_init();
1473         cardhu_dtv_init();
1474         cardhu_suspend_init();
1475         cardhu_touch_init();
1476         cardhu_modem_init();
1477         cardhu_kbc_init();
1478         cardhu_scroll_init();
1479         cardhu_keys_init();
1480         cardhu_panel_init();
1481         cardhu_pmon_init();
1482         cardhu_sensors_init();
1483         cardhu_setup_bluesleep();
1484         cardhu_sata_init();
1485         //audio_wired_jack_init();
1486         cardhu_pins_state_init();
1487         cardhu_emc_init();
1488         tegra_release_bootloader_fb();
1489         cardhu_pci_init();
1490 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1491         tegra_wdt_recovery_init();
1492 #endif
1493         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1494 }
1495
1496 static void __init tegra_cardhu_reserve(void)
1497 {
1498 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1499         /* support 1920X1200 with 24bpp */
1500         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1501 #else
1502         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1503 #endif
1504         tegra_ram_console_debug_reserve(SZ_1M);
1505 }
1506
1507 static const char *cardhu_dt_board_compat[] = {
1508         "nvidia,cardhu",
1509         NULL
1510 };
1511
1512 MACHINE_START(CARDHU, "cardhu")
1513         .atag_offset    = 0x100,
1514         .soc            = &tegra_soc_desc,
1515         .map_io         = tegra_map_common_io,
1516         .reserve        = tegra_cardhu_reserve,
1517         .init_early     = tegra30_init_early,
1518         .init_irq       = tegra_init_irq,
1519         .handle_irq     = gic_handle_irq,
1520         .timer          = &tegra_timer,
1521         .init_machine   = tegra_cardhu_init,
1522         .restart        = tegra_assert_system_reset,
1523         .dt_compat      = cardhu_dt_board_compat,
1524 MACHINE_END