ARM: SoC: Tegra: Convert Tegra to SoC descriptor
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <asm/hardware/gic.h>
48
49 #include <mach/clk.h>
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/pinmux.h>
53 #include <mach/iomap.h>
54 #include <mach/io.h>
55 #include <mach/i2s.h>
56 #include <mach/tegra_asoc_pdata.h>
57 #include <mach/tegra_wm8903_pdata.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61 #include <mach/gpio-tegra.h>
62
63 #include <asm/hardware/gic.h>
64 #include <asm/mach-types.h>
65 #include <asm/mach/arch.h>
66
67 #include "board.h"
68 #include "clock.h"
69 #include "board-cardhu.h"
70 #include "board-touch.h"
71 #include "devices.h"
72 #include "gpio-names.h"
73 #include "fuse.h"
74 #include "pm.h"
75 #include "baseband-xmm-power.h"
76 #include "wdt-recovery.h"
77 #include "common.h"
78
79 /* All units are in millicelsius */
80 static struct tegra_thermal_data thermal_data = {
81         .temp_shutdown = 90000,
82         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
83 #ifdef CONFIG_TEGRA_EDP_LIMITS
84         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
85         .hysteresis_edp = 3000,
86 #endif
87 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
88         .temp_throttle = 85000,
89         .tc1 = 0,
90         .tc2 = 1,
91         .passive_delay = 2000,
92 #endif
93 };
94
95 static struct resource cardhu_bcm4329_rfkill_resources[] = {
96         {
97                 .name   = "bcm4329_nshutdown_gpio",
98                 .start  = TEGRA_GPIO_PU0,
99                 .end    = TEGRA_GPIO_PU0,
100                 .flags  = IORESOURCE_IO,
101         },
102 };
103
104 static struct platform_device cardhu_bcm4329_rfkill_device = {
105         .name = "bcm4329_rfkill",
106         .id             = -1,
107         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
108         .resource       = cardhu_bcm4329_rfkill_resources,
109 };
110
111 static struct resource cardhu_bluesleep_resources[] = {
112         [0] = {
113                 .name = "gpio_host_wake",
114                         .start  = TEGRA_GPIO_PU6,
115                         .end    = TEGRA_GPIO_PU6,
116                         .flags  = IORESOURCE_IO,
117         },
118         [1] = {
119                 .name = "gpio_ext_wake",
120                         .start  = TEGRA_GPIO_PU1,
121                         .end    = TEGRA_GPIO_PU1,
122                         .flags  = IORESOURCE_IO,
123         },
124         [2] = {
125                 .name = "host_wake",
126                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
127         },
128 };
129
130 static struct platform_device cardhu_bluesleep_device = {
131         .name           = "bluesleep",
132         .id             = -1,
133         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
134         .resource       = cardhu_bluesleep_resources,
135 };
136
137 static noinline void __init cardhu_setup_bluesleep(void)
138 {
139         cardhu_bluesleep_resources[2].start =
140                 cardhu_bluesleep_resources[2].end =
141                         gpio_to_irq(TEGRA_GPIO_PU6);
142         platform_device_register(&cardhu_bluesleep_device);
143         return;
144 }
145
146 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
147         /* name         parent          rate            enabled */
148         { "pll_m",      NULL,           0,              false},
149         { "hda",        "pll_p",        108000000,      false},
150         { "hda2codec_2x","pll_p",       48000000,       false},
151         { "pwm",        "pll_p",        3187500,        false},
152         { "blink",      "clk_32k",      32768,          true},
153         { "i2s0",       "pll_a_out0",   0,              false},
154         { "i2s1",       "pll_a_out0",   0,              false},
155         { "i2s3",       "pll_a_out0",   0,              false},
156         { "spdif_out",  "pll_a_out0",   0,              false},
157         { "d_audio",    "clk_m",        12000000,       false},
158         { "dam0",       "clk_m",        12000000,       false},
159         { "dam1",       "clk_m",        12000000,       false},
160         { "dam2",       "clk_m",        12000000,       false},
161         { "audio1",     "i2s1_sync",    0,              false},
162         { "audio3",     "i2s3_sync",    0,              false},
163         { "vi_sensor",  "pll_p",        150000000,      false},
164         { "i2c1",       "pll_p",        3200000,        false},
165         { "i2c2",       "pll_p",        3200000,        false},
166         { "i2c3",       "pll_p",        3200000,        false},
167         { "i2c4",       "pll_p",        3200000,        false},
168         { "i2c5",       "pll_p",        3200000,        false},
169         { NULL,         NULL,           0,              0},
170 };
171
172 static struct pn544_i2c_platform_data nfc_pdata = {
173         .irq_gpio = TEGRA_GPIO_PX0,
174         .ven_gpio = TEGRA_GPIO_PP3,
175         .firm_gpio = TEGRA_GPIO_PO7,
176         };
177
178 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
179         {
180                 I2C_BOARD_INFO("pn544", 0x28),
181                 .platform_data = &nfc_pdata,
182         },
183 };
184 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
185         .adapter_nr     = 0,
186         .bus_count      = 1,
187         .bus_clk_rate   = { 100000, 0 },
188         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
189         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
190         .arb_recovery = arb_lost_recovery,
191 };
192
193 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
194         .adapter_nr     = 1,
195         .bus_count      = 1,
196         .bus_clk_rate   = { 400000, 0 },
197         .is_clkon_always = true,
198         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
199         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
200         .arb_recovery = arb_lost_recovery,
201 };
202
203 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
204         .adapter_nr     = 2,
205         .bus_count      = 1,
206         .bus_clk_rate   = { 100000, 0 },
207         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
208         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
209         .arb_recovery = arb_lost_recovery,
210 };
211
212 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
213         .adapter_nr     = 3,
214         .bus_count      = 1,
215         .bus_clk_rate   = { 10000, 0 },
216         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
217         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
218         .arb_recovery = arb_lost_recovery,
219 };
220
221 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
222         .adapter_nr     = 4,
223         .bus_count      = 1,
224         .bus_clk_rate   = { 400000, 0 },
225         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
226         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
227         .arb_recovery = arb_lost_recovery,
228 };
229
230
231 #if 0
232 struct tegra_wired_jack_conf audio_wr_jack_conf = {
233         .hp_det_n = TEGRA_GPIO_PW2,
234         .en_mic_ext = TEGRA_GPIO_PX1,
235         .en_mic_int = TEGRA_GPIO_PX0,
236 };
237 #endif
238
239 static struct wm8903_platform_data cardhu_wm8903_pdata = {
240         .irq_active_low = 0,
241         .micdet_cfg = 0,
242         .micdet_delay = 100,
243         .gpio_base = CARDHU_GPIO_WM8903(0),
244         .gpio_cfg = {
245                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
246                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
247                         WM8903_GP2_DIR,
248                 WM8903_GPIO_CONFIG_ZERO,
249                 0,
250                 0,
251         },
252 };
253
254 /* Equalizer filter coefs generated from the MAXIM MAX98095
255  * evkit software tool */
256 static struct max98095_eq_cfg max98095_eq_cfg[] = {
257         {
258                 .name = "FLAT",
259                 .rate = 44100,
260                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
261                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
262                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
263                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
264                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
265         },
266         {
267                 .name = "LOWPASS1K",
268                 .rate = 44100,
269                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
270                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
271                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
272                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
273                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
274         },
275         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
276                 .name = "HIBOOST",
277                 .rate = 44100,
278                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
279                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
280                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
281                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
282                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
283         },
284         { /* BASS=12dB, TREBLE=+12dB */
285                 .name = "LOUD12DB",
286                 .rate = 44100,
287                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
288                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
289                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
290                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
291                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
292         },
293         {
294                 .name = "FLAT",
295                 .rate = 16000,
296                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
297                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
298                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
299                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
300                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
301         },
302         {
303                 .name = "LOWPASS1K",
304                 .rate = 16000,
305                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
306                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
307                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
308                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
309                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
310         },
311         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
312                 .name = "HIBOOST",
313                 .rate = 16000,
314                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
315                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
316                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
317                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
318                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
319         },
320         { /* BASS=12dB, TREBLE=+12dB */
321                 .name = "LOUD12DB",
322                 .rate = 16000,
323                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
324                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
325                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
326                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
327                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
328         },
329 };
330
331 static struct max98095_pdata cardhu_max98095_pdata = {
332         /* equalizer configuration */
333         .eq_cfg = max98095_eq_cfg,
334         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
335
336         /* Biquad filter response configuration */
337         .bq_cfg = NULL,
338         .bq_cfgcnt = 0,
339
340         /* microphone configuration */
341         .digmic_left_mode = 1,
342         .digmic_right_mode = 1,
343 };
344
345 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
346         I2C_BOARD_INFO("wm8903", 0x1a),
347         .platform_data = &cardhu_wm8903_pdata,
348 };
349
350 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
351         I2C_BOARD_INFO("aic3262-codec", 0x18),
352 };
353
354 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
355         I2C_BOARD_INFO("max98095", 0x10),
356         .platform_data = &cardhu_max98095_pdata,
357 };
358
359 static void cardhu_i2c_init(void)
360 {
361         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
362         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
363         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
364         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
365         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
366
367         platform_device_register(&tegra_i2c_device5);
368         platform_device_register(&tegra_i2c_device4);
369         platform_device_register(&tegra_i2c_device3);
370         platform_device_register(&tegra_i2c_device2);
371         platform_device_register(&tegra_i2c_device1);
372
373         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
374                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
375         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
376         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
377         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
378
379         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
380         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
381 }
382
383 static struct platform_device *cardhu_uart_devices[] __initdata = {
384         &tegra_uarta_device,
385         &tegra_uartb_device,
386         &tegra_uartc_device,
387         &tegra_uartd_device,
388         &tegra_uarte_device,
389 };
390 static struct uart_clk_parent uart_parent_clk[] = {
391         [0] = {.name = "clk_m"},
392         [1] = {.name = "pll_p"},
393 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
394         [2] = {.name = "pll_m"},
395 #endif
396 };
397
398 static struct tegra_uart_platform_data cardhu_uart_pdata;
399 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
400
401 static void __init uart_debug_init(void)
402 {
403         struct board_info board_info;
404         int debug_port_id;
405
406         tegra_get_board_info(&board_info);
407
408         debug_port_id = get_tegra_uart_debug_port_id();
409         if (debug_port_id < 0) {
410                 debug_port_id = 0;
411                         /* UARTB is debug port
412                          *       for SLT - E1186/E1187/PM269
413                          *       for E1256/E1257
414                          */
415                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
416                         ((board_info.board_id == BOARD_E1186) ||
417                         (board_info.board_id == BOARD_E1187) ||
418                         (board_info.board_id == BOARD_PM269))) ||
419                         (board_info.board_id == BOARD_E1256) ||
420                         (board_info.board_id == BOARD_E1257))
421                                 debug_port_id = 1;
422         }
423
424         switch (debug_port_id) {
425         case 0:
426                 /* UARTA is the debug port. */
427                 pr_info("Selecting UARTA as the debug console\n");
428                 cardhu_uart_devices[0] = &debug_uarta_device;
429                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
430                 debug_uart_port_base = ((struct plat_serial8250_port *)(
431                         debug_uarta_device.dev.platform_data))->mapbase;
432                 break;
433
434         case 1:
435                 /* UARTB is the debug port. */
436                 pr_info("Selecting UARTB as the debug console\n");
437                 cardhu_uart_devices[1] = &debug_uartb_device;
438                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
439                 debug_uart_port_base = ((struct plat_serial8250_port *)(
440                         debug_uartb_device.dev.platform_data))->mapbase;
441                 break;
442
443         case 2:
444                 /* UARTC is the debug port. */
445                 pr_info("Selecting UARTC as the debug console\n");
446                 cardhu_uart_devices[2] = &debug_uartc_device;
447                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
448                 debug_uart_port_base = ((struct plat_serial8250_port *)(
449                         debug_uartc_device.dev.platform_data))->mapbase;
450                 break;
451
452         case 3:
453                 /* UARTD is the debug port. */
454                 pr_info("Selecting UARTD as the debug console\n");
455                 cardhu_uart_devices[3] = &debug_uartd_device;
456                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
457                 debug_uart_port_base = ((struct plat_serial8250_port *)(
458                         debug_uartd_device.dev.platform_data))->mapbase;
459                 break;
460
461         case 4:
462                 /* UARTE is the debug port. */
463                 pr_info("Selecting UARTE as the debug console\n");
464                 cardhu_uart_devices[4] = &debug_uarte_device;
465                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
466                 debug_uart_port_base = ((struct plat_serial8250_port *)(
467                         debug_uarte_device.dev.platform_data))->mapbase;
468                 break;
469
470         default:
471                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
472                 cardhu_uart_devices[0] = &debug_uarta_device;
473                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
474                 debug_uart_port_base = ((struct plat_serial8250_port *)(
475                         debug_uarta_device.dev.platform_data))->mapbase;
476                 break;
477         }
478         return;
479 }
480
481 static void __init cardhu_uart_init(void)
482 {
483         struct clk *c;
484         int i;
485
486         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
487                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
488                 if (IS_ERR_OR_NULL(c)) {
489                         pr_err("Not able to get the clock for %s\n",
490                                                 uart_parent_clk[i].name);
491                         continue;
492                 }
493                 uart_parent_clk[i].parent_clk = c;
494                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
495         }
496         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
497         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
498         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
499         cardhu_loopback_uart_pdata.parent_clk_count =
500                                                 ARRAY_SIZE(uart_parent_clk);
501         cardhu_loopback_uart_pdata.is_loopback = true;
502         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
503         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
504         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
505         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
506         /* UARTE is used for loopback test purpose */
507         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
508
509         /* Register low speed only if it is selected */
510         if (!is_tegra_debug_uartport_hs()) {
511                 uart_debug_init();
512                 /* Clock enable for the debug channel */
513                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
514                         pr_info("The debug console clock name is %s\n",
515                                                 debug_uart_clk->name);
516                         c = tegra_get_clock_by_name("pll_p");
517                         if (IS_ERR_OR_NULL(c))
518                                 pr_err("Not getting the parent clock pll_p\n");
519                         else
520                                 clk_set_parent(debug_uart_clk, c);
521
522                         clk_enable(debug_uart_clk);
523                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
524                 } else {
525                         pr_err("Not getting the clock %s for debug console\n",
526                                         debug_uart_clk->name);
527                 }
528         }
529
530         platform_add_devices(cardhu_uart_devices,
531                                 ARRAY_SIZE(cardhu_uart_devices));
532 }
533
534 static struct platform_device tegra_camera = {
535         .name = "tegra_camera",
536         .id = -1,
537 };
538
539 static struct platform_device *cardhu_spi_devices[] __initdata = {
540         &tegra_spi_device4,
541 };
542
543 static struct platform_device *touch_spi_device[] __initdata = {
544         &tegra_spi_device1,
545 };
546
547 struct spi_clk_parent spi_parent_clk[] = {
548         [0] = {.name = "pll_p"},
549 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
550         [1] = {.name = "pll_m"},
551         [2] = {.name = "clk_m"},
552 #else
553         [1] = {.name = "clk_m"},
554 #endif
555 };
556
557 static struct tegra_spi_platform_data cardhu_spi_pdata = {
558         .is_dma_based           = true,
559         .max_dma_buffer         = (16 * 1024),
560         .is_clkon_always        = false,
561         .max_rate               = 100000000,
562 };
563
564 static void __init cardhu_spi_init(void)
565 {
566         int i;
567         struct clk *c;
568         struct board_info board_info, display_board_info;
569
570         tegra_get_board_info(&board_info);
571         tegra_get_display_board_info(&display_board_info);
572
573         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
574                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
575                 if (IS_ERR_OR_NULL(c)) {
576                         pr_err("Not able to get the clock for %s\n",
577                                                 spi_parent_clk[i].name);
578                         continue;
579                 }
580                 spi_parent_clk[i].parent_clk = c;
581                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
582         }
583         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
584         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
585         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
586         platform_add_devices(cardhu_spi_devices,
587                                 ARRAY_SIZE(cardhu_spi_devices));
588
589         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
590                 platform_add_devices(touch_spi_device,
591                                 ARRAY_SIZE(touch_spi_device));
592         }
593         if (board_info.board_id == BOARD_E1198) {
594                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
595                 platform_device_register(&tegra_spi_device2);
596                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
597                 platform_device_register(&tegra_spi_slave_device1);
598         }
599 }
600
601 static void __init cardhu_dtv_init(void)
602 {
603         struct board_info board_info;
604
605         tegra_get_board_info(&board_info);
606
607         if (board_info.board_id == BOARD_E1186)
608                 platform_device_register(&tegra_dtv_device);
609 }
610
611 static struct resource tegra_rtc_resources[] = {
612         [0] = {
613                 .start = TEGRA_RTC_BASE,
614                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
615                 .flags = IORESOURCE_MEM,
616         },
617         [1] = {
618                 .start = INT_RTC,
619                 .end = INT_RTC,
620                 .flags = IORESOURCE_IRQ,
621         },
622 };
623
624 static struct platform_device tegra_rtc_device = {
625         .name = "tegra_rtc",
626         .id   = -1,
627         .resource = tegra_rtc_resources,
628         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
629 };
630
631 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
632         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
633         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
634         .gpio_hp_mute           = -1,
635         .gpio_int_mic_en        = -1,
636         .gpio_ext_mic_en        = -1,
637 };
638
639 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
640         .gpio_spkr_en           = -1,
641         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
642         .gpio_hp_mute           = -1,
643         .gpio_int_mic_en        = -1,
644         .gpio_ext_mic_en        = -1,
645 };
646
647 static struct platform_device cardhu_audio_wm8903_device = {
648         .name   = "tegra-snd-wm8903",
649         .id     = 0,
650         .dev    = {
651                 .platform_data = &cardhu_audio_wm8903_pdata,
652         },
653 };
654
655 static struct platform_device cardhu_audio_max98095_device = {
656         .name   = "tegra-snd-max98095",
657         .id     = 0,
658         .dev    = {
659                 .platform_data = &cardhu_audio_max98095_pdata,
660         },
661 };
662
663 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
664         .gpio_spkr_en           = -1,
665         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
666         .gpio_hp_mute           = -1,
667         .gpio_int_mic_en        = -1,
668         .gpio_ext_mic_en        = -1,
669         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
670         .audio_port_id          = {
671                 [HIFI_CODEC] = 0,
672                 [BASEBAND] = -1,
673                 [BT_SCO] = 3,
674         },
675         .baseband_param         = {
676                 .rate = -1,
677                 .channels = -1,
678         },
679 };
680
681 static struct platform_device cardhu_audio_aic326x_device = {
682         .name   = "tegra-snd-aic326x",
683         .id     = 0,
684         .dev    = {
685                 .platform_data  = &cardhu_audio_aic326x_pdata,
686         },
687 };
688
689 static struct platform_device *cardhu_devices[] __initdata = {
690         &tegra_pmu_device,
691         &tegra_rtc_device,
692         &tegra_udc_device,
693 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
694         &tegra_smmu_device,
695 #endif
696         &tegra_wdt_device,
697 #if defined(CONFIG_TEGRA_AVP)
698         &tegra_avp_device,
699 #endif
700         &tegra_camera,
701 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
702         &tegra_se_device,
703 #endif
704         &tegra_ahub_device,
705         &tegra_dam_device0,
706         &tegra_dam_device1,
707         &tegra_dam_device2,
708         &tegra_i2s_device0,
709         &tegra_i2s_device1,
710         &tegra_i2s_device3,
711         &tegra_spdif_device,
712         &spdif_dit_device,
713         &bluetooth_dit_device,
714         &baseband_dit_device,
715         &cardhu_bcm4329_rfkill_device,
716         &tegra_pcm_device,
717         &cardhu_audio_wm8903_device,
718         &cardhu_audio_max98095_device,
719         &cardhu_audio_aic326x_device,
720         &tegra_hda_device,
721 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
722         &tegra_aes_device,
723 #endif
724 };
725
726 #define E1506_MXT_CONFIG_CRC 0x62F903
727 static const u8 e1506_config[] = {
728         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
729         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
730         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
731         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
732         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
733         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
734         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
735         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
736         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
737         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
738         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
739         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
740         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
741         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
742         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
743         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
744         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
745         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
746         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
747         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
748         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
749         0x00
750 };
751
752 #define MXT_CONFIG_CRC  0xD62DE8
753 static const u8 config[] = {
754         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
755         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
756         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
757         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
758         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
759         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
760         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
761         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
762         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
763         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
764         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
765         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
766         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
767         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
768         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
769         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
770         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
771         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
772         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
773         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
774 };
775
776 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
777 static const u8 config_sku2000[] = {
778         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
779         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
780         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
781         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
782         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
783         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
784         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
785         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
786         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
788         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
789         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
790         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
791         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
792         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
793         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
794         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
795         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
796         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
797         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
798 };
799
800 static struct mxt_platform_data atmel_mxt_info = {
801         .x_line         = 27,
802         .y_line         = 42,
803         .x_size         = 768,
804         .y_size         = 1366,
805         .blen           = 0x20,
806         .threshold      = 0x3C,
807         .voltage        = 3300000,              /* 3.3V */
808         .orient         = 5,
809         .config         = config,
810         .config_length  = 157,
811         .config_crc     = MXT_CONFIG_CRC,
812         .irqflags       = IRQF_TRIGGER_FALLING,
813 /*      .read_chg       = &read_chg, */
814         .read_chg       = NULL,
815 };
816
817 static struct mxt_platform_data e1506_atmel_mxt_info = {
818         .x_line         = 19,
819         .y_line         = 11,
820         .x_size         = 960,
821         .y_size         = 540,
822         .blen           = 0x10,
823         .threshold      = 0x32,
824         .voltage        = 3300000,              /* 3.3V */
825         .orient         = 3,
826         .config         = e1506_config,
827         .config_length  = 168,
828         .config_crc     = E1506_MXT_CONFIG_CRC,
829         .irqflags       = IRQF_TRIGGER_FALLING,
830 /*      .read_chg       = &read_chg, */
831         .read_chg       = NULL,
832 };
833
834 static struct i2c_board_info __initdata atmel_i2c_info[] = {
835         {
836                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
837                 .platform_data = &atmel_mxt_info,
838         }
839 };
840
841 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
842         {
843                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
844                 .platform_data = &e1506_atmel_mxt_info,
845         }
846 };
847
848 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
849         /* name         parent          rate            enabled */
850         { "sbc1",       "pll_p",        52000000,       true},
851         { NULL,         NULL,           0,              0},
852 };
853
854 static int __init cardhu_touch_init(void)
855 {
856         struct board_info BoardInfo, DisplayBoardInfo;
857
858         tegra_get_board_info(&BoardInfo);
859         tegra_get_display_board_info(&DisplayBoardInfo);
860         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
861                 tegra_clk_init_from_table(spi_clk_init_table);
862
863                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
864         } else {
865                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
866                 gpio_direction_input(TEGRA_GPIO_PH4);
867
868                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
869                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
870                 msleep(1);
871                 gpio_set_value(TEGRA_GPIO_PH6, 1);
872                 msleep(100);
873
874                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
875                         atmel_mxt_info.config = config_sku2000;
876                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
877                 }
878
879                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
880                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
881                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
882                 } else {
883                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
884                         i2c_register_board_info(1, atmel_i2c_info, 1);
885                 }
886         }
887
888         return 0;
889 }
890
891 static void cardu_usb_hsic_postsupend(void)
892 {
893 #ifdef CONFIG_TEGRA_BB_XMM_POWER
894         baseband_xmm_set_power_status(BBXMM_PS_L2);
895 #endif
896 }
897
898 static void cardu_usb_hsic_preresume(void)
899 {
900 #ifdef CONFIG_TEGRA_BB_XMM_POWER
901         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
902 #endif
903 }
904
905 static void cardu_usb_hsic_phy_ready(void)
906 {
907 #ifdef CONFIG_TEGRA_BB_XMM_POWER
908         baseband_xmm_set_power_status(BBXMM_PS_L0);
909 #endif
910 }
911
912 static void cardu_usb_hsic_phy_off(void)
913 {
914 #ifdef CONFIG_TEGRA_BB_XMM_POWER
915         baseband_xmm_set_power_status(BBXMM_PS_L3);
916 #endif
917 }
918
919 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
920         .post_suspend = cardu_usb_hsic_postsupend,
921         .pre_resume = cardu_usb_hsic_preresume,
922         .port_power = cardu_usb_hsic_phy_ready,
923         .post_phy_off = cardu_usb_hsic_phy_off,
924 };
925
926 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
927         .port_otg = false,
928         .has_hostpc = true,
929         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
930         .op_mode        = TEGRA_USB_OPMODE_HOST,
931         .u_data.host = {
932                 .vbus_gpio = -1,
933                 .hot_plug = false,
934                 .remote_wakeup_supported = false,
935                 .power_off_on_suspend = false,
936         },
937         .u_cfg.hsic = {
938                 .sync_start_delay = 9,
939                 .idle_wait_delay = 17,
940                 .term_range_adj = 0,
941                 .elastic_underrun_limit = 16,
942                 .elastic_overrun_limit = 16,
943         },
944         .ops = &hsic_xmm_plat_ops,
945 };
946
947
948 static int hsic_enable_gpio = -1;
949 static int hsic_reset_gpio = -1;
950
951 void hsic_platform_open(void)
952 {
953         int reset_gpio = 0, enable_gpio = 0;
954
955         if (hsic_enable_gpio != -1)
956                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
957         if (hsic_reset_gpio != -1)
958                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
959         /* hsic enable signal deasserted, hsic reset asserted */
960         if (!enable_gpio)
961                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
962         if (!reset_gpio)
963                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
964         if (!enable_gpio)
965                 tegra_gpio_enable(hsic_enable_gpio);
966         if (!reset_gpio)
967                 tegra_gpio_enable(hsic_reset_gpio);
968         /* keep hsic reset asserted for 1 ms */
969         udelay(1000);
970         /* enable (power on) hsic */
971         if (!enable_gpio)
972                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
973         udelay(1000);
974         /* deassert reset */
975         if (!reset_gpio)
976                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
977
978 }
979
980 void hsic_platform_close(void)
981 {
982         if (hsic_enable_gpio != -1) {
983                 gpio_set_value(hsic_enable_gpio, 0);
984                 gpio_free(hsic_enable_gpio);
985         }
986         if (hsic_reset_gpio != -1) {
987                 gpio_set_value(hsic_reset_gpio, 0);
988                 gpio_free(hsic_reset_gpio);
989         }
990 }
991
992 void hsic_power_on(void)
993 {
994         if (hsic_enable_gpio != -1) {
995                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
996                 udelay(1000);
997         }
998 }
999
1000 void hsic_power_off(void)
1001 {
1002         if (hsic_enable_gpio != -1) {
1003                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1004                 udelay(1000);
1005         }
1006 }
1007
1008 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1009         .open = hsic_platform_open,
1010         .close = hsic_platform_close,
1011         .pre_phy_on = hsic_power_on,
1012         .post_phy_off = hsic_power_off,
1013 };
1014
1015 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1016         .port_otg = false,
1017         .has_hostpc = true,
1018         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1019         .op_mode        = TEGRA_USB_OPMODE_HOST,
1020         .u_data.host = {
1021                 .vbus_gpio = -1,
1022                 .hot_plug = false,
1023                 .remote_wakeup_supported = false,
1024                 .power_off_on_suspend = false,
1025         },
1026         .u_cfg.hsic = {
1027                 .sync_start_delay = 9,
1028                 .idle_wait_delay = 17,
1029                 .term_range_adj = 0,
1030                 .elastic_underrun_limit = 16,
1031                 .elastic_overrun_limit = 16,
1032         },
1033         .ops = &hsic_plat_ops,
1034 };
1035
1036 static struct tegra_usb_platform_data tegra_udc_pdata = {
1037         .port_otg = true,
1038         .has_hostpc = true,
1039         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1040         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1041         .u_data.dev = {
1042                 .vbus_pmu_irq = 0,
1043                 .vbus_gpio = -1,
1044                 .charging_supported = false,
1045                 .remote_wakeup_supported = false,
1046         },
1047         .u_cfg.utmi = {
1048                 .hssync_start_delay = 0,
1049                 .elastic_limit = 16,
1050                 .idle_wait_delay = 17,
1051                 .term_range_adj = 6,
1052                 .xcvr_setup = 8,
1053                 .xcvr_lsfslew = 2,
1054                 .xcvr_lsrslew = 2,
1055                 .xcvr_setup_offset = 0,
1056                 .xcvr_use_fuses = 1,
1057         },
1058 };
1059
1060 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1061         .port_otg = true,
1062         .has_hostpc = true,
1063         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1064         .op_mode = TEGRA_USB_OPMODE_HOST,
1065         .u_data.host = {
1066                 .vbus_gpio = -1,
1067                 .vbus_reg = "vdd_vbus_micro_usb",
1068                 .hot_plug = true,
1069                 .remote_wakeup_supported = true,
1070                 .power_off_on_suspend = true,
1071         },
1072         .u_cfg.utmi = {
1073                 .hssync_start_delay = 0,
1074                 .elastic_limit = 16,
1075                 .idle_wait_delay = 17,
1076                 .term_range_adj = 6,
1077                 .xcvr_setup = 15,
1078                 .xcvr_lsfslew = 2,
1079                 .xcvr_lsrslew = 2,
1080                 .xcvr_setup_offset = 0,
1081                 .xcvr_use_fuses = 1,
1082         },
1083 };
1084
1085 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1086         .port_otg = false,
1087         .has_hostpc = true,
1088         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1089         .op_mode        = TEGRA_USB_OPMODE_HOST,
1090         .u_data.host = {
1091                 .vbus_gpio = -1,
1092                 .hot_plug = false,
1093                 .remote_wakeup_supported = true,
1094                 .power_off_on_suspend = true,
1095         },
1096         .u_cfg.utmi = {
1097                 .hssync_start_delay = 0,
1098                 .elastic_limit = 16,
1099                 .idle_wait_delay = 17,
1100                 .term_range_adj = 6,
1101                 .xcvr_setup = 15,
1102                 .xcvr_lsfslew = 2,
1103                 .xcvr_lsrslew = 2,
1104                 .xcvr_setup_offset = 0,
1105                 .xcvr_use_fuses = 1,
1106         },
1107 };
1108
1109 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1110         .port_otg = false,
1111         .has_hostpc = true,
1112         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1113         .op_mode        = TEGRA_USB_OPMODE_HOST,
1114         .u_data.host = {
1115                 .vbus_gpio = -1,
1116                 .vbus_reg = "vdd_vbus_typea_usb",
1117                 .hot_plug = true,
1118                 .remote_wakeup_supported = true,
1119                 .power_off_on_suspend = true,
1120         },
1121         .u_cfg.utmi = {
1122                 .hssync_start_delay = 0,
1123                 .elastic_limit = 16,
1124                 .idle_wait_delay = 17,
1125                 .term_range_adj = 6,
1126                 .xcvr_setup = 8,
1127                 .xcvr_lsfslew = 2,
1128                 .xcvr_lsrslew = 2,
1129                 .xcvr_setup_offset = 0,
1130                 .xcvr_use_fuses = 1,
1131         },
1132 };
1133
1134 static struct tegra_usb_otg_data tegra_otg_pdata = {
1135         .ehci_device = &tegra_ehci1_device,
1136         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1137 };
1138
1139 #if CONFIG_USB_SUPPORT
1140 static void cardhu_usb_init(void)
1141 {
1142         struct board_info bi;
1143
1144         tegra_get_board_info(&bi);
1145
1146         /* OTG should be the first to be registered */
1147         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1148         platform_device_register(&tegra_otg_device);
1149
1150         /* setup the udc platform data */
1151         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1152
1153         if (bi.board_id == BOARD_PM267) {
1154                 hsic_enable_gpio = EN_HSIC_GPIO;
1155                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1156                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1157                 platform_device_register(&tegra_ehci2_device);
1158         } else if (bi.board_id == BOARD_E1256) {
1159                 hsic_enable_gpio = EN_HSIC_GPIO;
1160                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1161                 platform_device_register(&tegra_ehci2_device);
1162         } else if (bi.board_id == BOARD_E1186) {
1163                 tegra_ehci2_device.dev.platform_data =
1164                                                 &tegra_ehci2_hsic_xmm_pdata;
1165                 /* ehci2 registration happens in baseband-xmm-power  */
1166         } else {
1167                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1168                 platform_device_register(&tegra_ehci2_device);
1169         }
1170
1171         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1172         platform_device_register(&tegra_ehci3_device);
1173
1174 }
1175 #else
1176 static void cardhu_usb_init(void) { }
1177 #endif
1178
1179 static struct baseband_power_platform_data tegra_baseband_power_data = {
1180         .baseband_type = BASEBAND_XMM,
1181         .modem = {
1182         .xmm = {
1183                         .bb_rst = XMM_GPIO_BB_RST,
1184                         .bb_on = XMM_GPIO_BB_ON,
1185                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1186                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1187                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1188                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1189                         .hsic_device = &tegra_ehci2_device,
1190                 },
1191         },
1192 };
1193
1194 static struct platform_device tegra_baseband_power_device = {
1195         .name = "baseband_xmm_power",
1196         .id = -1,
1197         .dev = {
1198                 .platform_data = &tegra_baseband_power_data,
1199         },
1200 };
1201
1202 static struct platform_device tegra_baseband_power2_device = {
1203         .name = "baseband_xmm_power2",
1204         .id = -1,
1205         .dev = {
1206                 .platform_data = &tegra_baseband_power_data,
1207         },
1208 };
1209
1210
1211 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1212         .port_status[0] = 1,
1213         .port_status[1] = 1,
1214         .port_status[2] = 1,
1215         .use_dock_detect        = 0,
1216         .gpio           = 0,
1217 };
1218
1219 static void cardhu_pci_init(void)
1220 {
1221         struct board_info board_info;
1222
1223         tegra_get_board_info(&board_info);
1224         if (board_info.board_id == BOARD_E1291) {
1225                 cardhu_pci_platform_data.port_status[0] = 0;
1226                 cardhu_pci_platform_data.port_status[1] = 0;
1227                 cardhu_pci_platform_data.port_status[2] = 1;
1228                 cardhu_pci_platform_data.use_dock_detect = 1;
1229                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1230         }
1231         if ((board_info.board_id == BOARD_E1186) ||
1232                 (board_info.board_id == BOARD_E1187) ||
1233                 (board_info.board_id == BOARD_E1291)) {
1234                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1235                 platform_device_register(&tegra_pci_device);
1236         }
1237 }
1238
1239 static void cardhu_modem_init(void)
1240 {
1241         struct board_info board_info;
1242         int w_disable_gpio, ret;
1243
1244         tegra_get_board_info(&board_info);
1245         switch (board_info.board_id) {
1246         case BOARD_E1291:
1247         case BOARD_E1198:
1248                 if (((board_info.board_id == BOARD_E1291) &&
1249                                 (board_info.fab < BOARD_FAB_A03)) ||
1250                         ((board_info.board_id == BOARD_E1198) &&
1251                                         (board_info.fab < BOARD_FAB_A02))) {
1252                         w_disable_gpio = TEGRA_GPIO_PH5;
1253                 } else {
1254                         w_disable_gpio = TEGRA_GPIO_PDD5;
1255                 }
1256
1257                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1258                 if (ret < 0)
1259                         pr_err("%s: gpio_request failed for gpio %d\n",
1260                                 __func__, w_disable_gpio);
1261                 else
1262                         gpio_direction_input(w_disable_gpio);
1263
1264                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1265                 if (((board_info.board_id == BOARD_E1291) &&
1266                                 (board_info.fab >= BOARD_FAB_A04)) ||
1267                         ((board_info.board_id == BOARD_E1198) &&
1268                                         (board_info.fab >= BOARD_FAB_A02))) {
1269                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1270                         if (ret < 0) {
1271                                 pr_err("%s(): Error in allocating gpio "
1272                                         "TEGRA_GPIO_PH7\n", __func__);
1273                                 break;
1274                         }
1275                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1276                 }
1277                 break;
1278         case BOARD_E1186:
1279                 platform_device_register(&tegra_baseband_power_device);
1280                 platform_device_register(&tegra_baseband_power2_device);
1281                 break;
1282         default:
1283                 break;
1284         }
1285
1286 }
1287
1288 #ifdef CONFIG_SATA_AHCI_TEGRA
1289 static void cardhu_sata_init(void)
1290 {
1291         platform_device_register(&tegra_sata_device);
1292 }
1293 #else
1294 static void cardhu_sata_init(void) { }
1295 #endif
1296
1297 static void __init tegra_cardhu_init(void)
1298 {
1299         tegra_thermal_init(&thermal_data);
1300         tegra_clk_init_from_table(cardhu_clk_init_table);
1301         tegra_enable_pinmux();
1302         cardhu_pinmux_init();
1303         cardhu_i2c_init();
1304         cardhu_spi_init();
1305         cardhu_usb_init();
1306 #ifdef CONFIG_TEGRA_EDP_LIMITS
1307         cardhu_edp_init();
1308 #endif
1309         cardhu_uart_init();
1310         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1311         tegra_ram_console_debug_init();
1312         cardhu_sdhci_init();
1313         cardhu_regulator_init();
1314         cardhu_dtv_init();
1315         cardhu_suspend_init();
1316         cardhu_touch_init();
1317         cardhu_modem_init();
1318         cardhu_kbc_init();
1319         cardhu_scroll_init();
1320         cardhu_keys_init();
1321         cardhu_panel_init();
1322         cardhu_pmon_init();
1323         cardhu_sensors_init();
1324         cardhu_setup_bluesleep();
1325         cardhu_sata_init();
1326         //audio_wired_jack_init();
1327         cardhu_pins_state_init();
1328         cardhu_emc_init();
1329         tegra_release_bootloader_fb();
1330         cardhu_pci_init();
1331 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1332         tegra_wdt_recovery_init();
1333 #endif
1334 }
1335
1336 static void __init tegra_cardhu_reserve(void)
1337 {
1338 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1339         /* support 1920X1200 with 24bpp */
1340         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1341 #else
1342         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1343 #endif
1344         tegra_ram_console_debug_reserve(SZ_1M);
1345 }
1346
1347 MACHINE_START(CARDHU, "cardhu")
1348         .atag_offset    = 0x100,
1349         .soc            = &tegra_soc_desc,
1350         .map_io         = tegra_map_common_io,
1351         .reserve        = tegra_cardhu_reserve,
1352         .init_early     = tegra30_init_early,
1353         .init_irq       = tegra_init_irq,
1354         .handle_irq     = gic_handle_irq,
1355         .timer          = &tegra_timer,
1356         .init_machine   = tegra_cardhu_init,
1357         .restart        = tegra_assert_system_reset,
1358 MACHINE_END