ARM: tegra: register pinmux and gpio devices before pinmux init
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <asm/hardware/gic.h>
48
49 #include <mach/clk.h>
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/pinmux.h>
53 #include <mach/iomap.h>
54 #include <mach/io.h>
55 #include <mach/i2s.h>
56 #include <mach/tegra_asoc_pdata.h>
57 #include <mach/tegra_wm8903_pdata.h>
58 #include <asm/mach-types.h>
59 #include <asm/mach/arch.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/gpio-tegra.h>
64
65 #include "board.h"
66 #include "clock.h"
67 #include "board-cardhu.h"
68 #include "devices.h"
69 #include "gpio-names.h"
70 #include "fuse.h"
71 #include "pm.h"
72 #include "baseband-xmm-power.h"
73 #include "wdt-recovery.h"
74
75 /* All units are in millicelsius */
76 static struct tegra_thermal_data thermal_data = {
77         .temp_throttle = 85000,
78         .temp_shutdown = 90000,
79         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
80 #ifdef CONFIG_TEGRA_EDP_LIMITS
81         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
82         .hysteresis_edp = 3000,
83 #endif
84 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
85         .tc1 = 0,
86         .tc2 = 1,
87         .passive_delay = 2000,
88 #else
89         .hysteresis_throttle = 1000,
90 #endif
91 };
92
93 /* !!!TODO: Change for cardhu (Taken from Ventana) */
94 static struct tegra_utmip_config utmi_phy_config[] = {
95         [0] = {
96                         .hssync_start_delay = 0,
97                         .idle_wait_delay = 17,
98                         .elastic_limit = 16,
99                         .term_range_adj = 6,
100                         .xcvr_setup = 15,
101                         .xcvr_setup_offset = 0,
102                         .xcvr_use_fuses = 1,
103                         .xcvr_lsfslew = 2,
104                         .xcvr_lsrslew = 2,
105         },
106         [1] = {
107                         .hssync_start_delay = 0,
108                         .idle_wait_delay = 17,
109                         .elastic_limit = 16,
110                         .term_range_adj = 6,
111                         .xcvr_setup = 15,
112                         .xcvr_setup_offset = 0,
113                         .xcvr_use_fuses = 1,
114                         .xcvr_lsfslew = 2,
115                         .xcvr_lsrslew = 2,
116         },
117         [2] = {
118                         .hssync_start_delay = 0,
119                         .idle_wait_delay = 17,
120                         .elastic_limit = 16,
121                         .term_range_adj = 6,
122                         .xcvr_setup = 8,
123                         .xcvr_setup_offset = 0,
124                         .xcvr_use_fuses = 1,
125                         .xcvr_lsfslew = 2,
126                         .xcvr_lsrslew = 2,
127         },
128 };
129
130 static struct resource cardhu_bcm4329_rfkill_resources[] = {
131         {
132                 .name   = "bcm4329_nshutdown_gpio",
133                 .start  = TEGRA_GPIO_PU0,
134                 .end    = TEGRA_GPIO_PU0,
135                 .flags  = IORESOURCE_IO,
136         },
137 };
138
139 static struct platform_device cardhu_bcm4329_rfkill_device = {
140         .name = "bcm4329_rfkill",
141         .id             = -1,
142         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
143         .resource       = cardhu_bcm4329_rfkill_resources,
144 };
145
146 static struct resource cardhu_bluesleep_resources[] = {
147         [0] = {
148                 .name = "gpio_host_wake",
149                         .start  = TEGRA_GPIO_PU6,
150                         .end    = TEGRA_GPIO_PU6,
151                         .flags  = IORESOURCE_IO,
152         },
153         [1] = {
154                 .name = "gpio_ext_wake",
155                         .start  = TEGRA_GPIO_PU1,
156                         .end    = TEGRA_GPIO_PU1,
157                         .flags  = IORESOURCE_IO,
158         },
159         [2] = {
160                 .name = "host_wake",
161                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
162                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
163                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
164         },
165 };
166
167 static struct platform_device cardhu_bluesleep_device = {
168         .name           = "bluesleep",
169         .id             = -1,
170         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
171         .resource       = cardhu_bluesleep_resources,
172 };
173
174 static noinline void __init cardhu_setup_bluesleep(void)
175 {
176         platform_device_register(&cardhu_bluesleep_device);
177         tegra_gpio_enable(TEGRA_GPIO_PU6);
178         tegra_gpio_enable(TEGRA_GPIO_PU1);
179         return;
180 }
181
182 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
183         /* name         parent          rate            enabled */
184         { "pll_m",      NULL,           0,              false},
185         { "hda",        "pll_p",        108000000,      false},
186         { "hda2codec_2x","pll_p",       48000000,       false},
187         { "pwm",        "pll_p",        3187500,        false},
188         { "blink",      "clk_32k",      32768,          true},
189         { "i2s0",       "pll_a_out0",   0,              false},
190         { "i2s1",       "pll_a_out0",   0,              false},
191         { "i2s3",       "pll_a_out0",   0,              false},
192         { "spdif_out",  "pll_a_out0",   0,              false},
193         { "d_audio",    "clk_m",        12000000,       false},
194         { "dam0",       "clk_m",        12000000,       false},
195         { "dam1",       "clk_m",        12000000,       false},
196         { "dam2",       "clk_m",        12000000,       false},
197         { "audio1",     "i2s1_sync",    0,              false},
198         { "audio3",     "i2s3_sync",    0,              false},
199         { "vi_sensor",  "pll_p",        150000000,      false},
200         { "i2c1",       "pll_p",        3200000,        false},
201         { "i2c2",       "pll_p",        3200000,        false},
202         { "i2c3",       "pll_p",        3200000,        false},
203         { "i2c4",       "pll_p",        3200000,        false},
204         { "i2c5",       "pll_p",        3200000,        false},
205         { NULL,         NULL,           0,              0},
206 };
207
208 static struct pn544_i2c_platform_data nfc_pdata = {
209         .irq_gpio = TEGRA_GPIO_PX0,
210         .ven_gpio = TEGRA_GPIO_PP3,
211         .firm_gpio = TEGRA_GPIO_PO7,
212         };
213
214 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
215         {
216                 I2C_BOARD_INFO("pn544", 0x28),
217                 .platform_data = &nfc_pdata,
218                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
219         },
220 };
221 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
222         .adapter_nr     = 0,
223         .bus_count      = 1,
224         .bus_clk_rate   = { 100000, 0 },
225         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
226         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
227         .arb_recovery = arb_lost_recovery,
228 };
229
230 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
231         .adapter_nr     = 1,
232         .bus_count      = 1,
233         .bus_clk_rate   = { 100000, 0 },
234         .is_clkon_always = true,
235         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
236         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
237         .arb_recovery = arb_lost_recovery,
238 };
239
240 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
241         .adapter_nr     = 2,
242         .bus_count      = 1,
243         .bus_clk_rate   = { 100000, 0 },
244         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
245         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
246         .arb_recovery = arb_lost_recovery,
247 };
248
249 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
250         .adapter_nr     = 3,
251         .bus_count      = 1,
252         .bus_clk_rate   = { 100000, 0 },
253         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
254         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
255         .arb_recovery = arb_lost_recovery,
256 };
257
258 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
259         .adapter_nr     = 4,
260         .bus_count      = 1,
261         .bus_clk_rate   = { 400000, 0 },
262         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
263         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
264         .arb_recovery = arb_lost_recovery,
265 };
266
267
268 #if 0
269 struct tegra_wired_jack_conf audio_wr_jack_conf = {
270         .hp_det_n = TEGRA_GPIO_PW2,
271         .en_mic_ext = TEGRA_GPIO_PX1,
272         .en_mic_int = TEGRA_GPIO_PX0,
273 };
274 #endif
275
276 static struct wm8903_platform_data cardhu_wm8903_pdata = {
277         .irq_active_low = 0,
278         .micdet_cfg = 0,
279         .micdet_delay = 100,
280         .gpio_base = CARDHU_GPIO_WM8903(0),
281         .gpio_cfg = {
282                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
283                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
284                         WM8903_GP2_DIR,
285                 WM8903_GPIO_CONFIG_ZERO,
286                 0,
287                 0,
288         },
289 };
290
291 /* Equalizer filter coefs generated from the MAXIM MAX98095
292  * evkit software tool */
293 static struct max98095_eq_cfg max98095_eq_cfg[] = {
294         {
295                 .name = "FLAT",
296                 .rate = 44100,
297                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
298                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
299                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
300                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
301                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
302         },
303         {
304                 .name = "LOWPASS1K",
305                 .rate = 44100,
306                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
307                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
308                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
309                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
310                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
311         },
312         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
313                 .name = "HIBOOST",
314                 .rate = 44100,
315                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
316                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
317                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
318                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
319                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
320         },
321         { /* BASS=12dB, TREBLE=+12dB */
322                 .name = "LOUD12DB",
323                 .rate = 44100,
324                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
325                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
326                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
327                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
328                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
329         },
330         {
331                 .name = "FLAT",
332                 .rate = 16000,
333                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
334                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
335                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
336                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
337                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
338         },
339         {
340                 .name = "LOWPASS1K",
341                 .rate = 16000,
342                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
343                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
344                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
345                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
346                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
347         },
348         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
349                 .name = "HIBOOST",
350                 .rate = 16000,
351                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
352                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
353                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
354                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
355                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
356         },
357         { /* BASS=12dB, TREBLE=+12dB */
358                 .name = "LOUD12DB",
359                 .rate = 16000,
360                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
361                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
362                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
363                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
364                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
365         },
366 };
367
368 static struct max98095_pdata cardhu_max98095_pdata = {
369         /* equalizer configuration */
370         .eq_cfg = max98095_eq_cfg,
371         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
372
373         /* Biquad filter response configuration */
374         .bq_cfg = NULL,
375         .bq_cfgcnt = 0,
376
377         /* microphone configuration */
378         .digmic_left_mode = 1,
379         .digmic_right_mode = 1,
380 };
381
382 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
383         I2C_BOARD_INFO("wm8903", 0x1a),
384         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
385         .platform_data = &cardhu_wm8903_pdata,
386 };
387
388 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
389         I2C_BOARD_INFO("aic3262-codec", 0x18),
390         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
391 };
392
393 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
394         I2C_BOARD_INFO("max98095", 0x10),
395         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
396         .platform_data = &cardhu_max98095_pdata,
397 };
398
399 static void cardhu_i2c_init(void)
400 {
401         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
402         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
403         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
404         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
405         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
406
407         platform_device_register(&tegra_i2c_device5);
408         platform_device_register(&tegra_i2c_device4);
409         platform_device_register(&tegra_i2c_device3);
410         platform_device_register(&tegra_i2c_device2);
411         platform_device_register(&tegra_i2c_device1);
412
413         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
414         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
415         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
416
417         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
418 }
419
420 static struct platform_device *cardhu_uart_devices[] __initdata = {
421         &tegra_uarta_device,
422         &tegra_uartb_device,
423         &tegra_uartc_device,
424         &tegra_uartd_device,
425         &tegra_uarte_device,
426 };
427 static struct uart_clk_parent uart_parent_clk[] = {
428         [0] = {.name = "clk_m"},
429         [1] = {.name = "pll_p"},
430 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
431         [2] = {.name = "pll_m"},
432 #endif
433 };
434
435 static struct tegra_uart_platform_data cardhu_uart_pdata;
436 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
437
438 static void __init uart_debug_init(void)
439 {
440         struct board_info board_info;
441         int debug_port_id;
442
443         tegra_get_board_info(&board_info);
444
445         debug_port_id = get_tegra_uart_debug_port_id();
446         if (debug_port_id < 0) {
447                 debug_port_id = 0;
448                         /* UARTB is debug port
449                          *       for SLT - E1186/E1187/PM269
450                          *       for E1256/E1257
451                          */
452                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
453                         ((board_info.board_id == BOARD_E1186) ||
454                         (board_info.board_id == BOARD_E1187) ||
455                         (board_info.board_id == BOARD_PM269))) ||
456                         (board_info.board_id == BOARD_E1256) ||
457                         (board_info.board_id == BOARD_E1257))
458                                 debug_port_id = 1;
459         }
460
461         switch (debug_port_id) {
462         case 0:
463                 /* UARTA is the debug port. */
464                 pr_info("Selecting UARTA as the debug console\n");
465                 cardhu_uart_devices[0] = &debug_uarta_device;
466                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
467                 debug_uart_port_base = ((struct plat_serial8250_port *)(
468                         debug_uarta_device.dev.platform_data))->mapbase;
469                 break;
470
471         case 1:
472                 /* UARTB is the debug port. */
473                 pr_info("Selecting UARTB as the debug console\n");
474                 cardhu_uart_devices[1] = &debug_uartb_device;
475                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
476                 debug_uart_port_base = ((struct plat_serial8250_port *)(
477                         debug_uartb_device.dev.platform_data))->mapbase;
478                 break;
479
480         case 2:
481                 /* UARTC is the debug port. */
482                 pr_info("Selecting UARTC as the debug console\n");
483                 cardhu_uart_devices[2] = &debug_uartc_device;
484                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
485                 debug_uart_port_base = ((struct plat_serial8250_port *)(
486                         debug_uartc_device.dev.platform_data))->mapbase;
487                 break;
488
489         case 3:
490                 /* UARTD is the debug port. */
491                 pr_info("Selecting UARTD as the debug console\n");
492                 cardhu_uart_devices[3] = &debug_uartd_device;
493                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
494                 debug_uart_port_base = ((struct plat_serial8250_port *)(
495                         debug_uartd_device.dev.platform_data))->mapbase;
496                 break;
497
498         case 4:
499                 /* UARTE is the debug port. */
500                 pr_info("Selecting UARTE as the debug console\n");
501                 cardhu_uart_devices[4] = &debug_uarte_device;
502                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
503                 debug_uart_port_base = ((struct plat_serial8250_port *)(
504                         debug_uarte_device.dev.platform_data))->mapbase;
505                 break;
506
507         default:
508                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
509                 cardhu_uart_devices[0] = &debug_uarta_device;
510                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
511                 debug_uart_port_base = ((struct plat_serial8250_port *)(
512                         debug_uarta_device.dev.platform_data))->mapbase;
513                 break;
514         }
515         return;
516 }
517
518 static void __init cardhu_uart_init(void)
519 {
520         struct clk *c;
521         int i;
522
523         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
524                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
525                 if (IS_ERR_OR_NULL(c)) {
526                         pr_err("Not able to get the clock for %s\n",
527                                                 uart_parent_clk[i].name);
528                         continue;
529                 }
530                 uart_parent_clk[i].parent_clk = c;
531                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
532         }
533         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
534         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
535         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
536         cardhu_loopback_uart_pdata.parent_clk_count =
537                                                 ARRAY_SIZE(uart_parent_clk);
538         cardhu_loopback_uart_pdata.is_loopback = true;
539         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
540         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
541         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
542         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
543         /* UARTE is used for loopback test purpose */
544         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
545
546         /* Register low speed only if it is selected */
547         if (!is_tegra_debug_uartport_hs()) {
548                 uart_debug_init();
549                 /* Clock enable for the debug channel */
550                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
551                         pr_info("The debug console clock name is %s\n",
552                                                 debug_uart_clk->name);
553                         c = tegra_get_clock_by_name("pll_p");
554                         if (IS_ERR_OR_NULL(c))
555                                 pr_err("Not getting the parent clock pll_p\n");
556                         else
557                                 clk_set_parent(debug_uart_clk, c);
558
559                         clk_enable(debug_uart_clk);
560                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
561                 } else {
562                         pr_err("Not getting the clock %s for debug console\n",
563                                         debug_uart_clk->name);
564                 }
565         }
566
567         platform_add_devices(cardhu_uart_devices,
568                                 ARRAY_SIZE(cardhu_uart_devices));
569 }
570
571 static struct platform_device tegra_camera = {
572         .name = "tegra_camera",
573         .id = -1,
574 };
575
576 static struct platform_device *cardhu_spi_devices[] __initdata = {
577         &tegra_spi_device4,
578 };
579
580 struct spi_clk_parent spi_parent_clk[] = {
581         [0] = {.name = "pll_p"},
582 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
583         [1] = {.name = "pll_m"},
584         [2] = {.name = "clk_m"},
585 #else
586         [1] = {.name = "clk_m"},
587 #endif
588 };
589
590 static struct tegra_spi_platform_data cardhu_spi_pdata = {
591         .is_dma_based           = true,
592         .max_dma_buffer         = (16 * 1024),
593         .is_clkon_always        = false,
594         .max_rate               = 100000000,
595 };
596
597 static void __init cardhu_spi_init(void)
598 {
599         int i;
600         struct clk *c;
601         struct board_info board_info;
602
603         tegra_get_board_info(&board_info);
604
605         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
606                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
607                 if (IS_ERR_OR_NULL(c)) {
608                         pr_err("Not able to get the clock for %s\n",
609                                                 spi_parent_clk[i].name);
610                         continue;
611                 }
612                 spi_parent_clk[i].parent_clk = c;
613                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
614         }
615         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
616         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
617         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
618         platform_add_devices(cardhu_spi_devices,
619                                 ARRAY_SIZE(cardhu_spi_devices));
620
621         if (board_info.board_id == BOARD_E1198) {
622                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
623                 platform_device_register(&tegra_spi_device2);
624                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
625                 platform_device_register(&tegra_spi_slave_device1);
626         }
627 }
628
629 static void __init cardhu_dtv_init(void)
630 {
631         struct board_info board_info;
632
633         tegra_get_board_info(&board_info);
634
635         if (board_info.board_id == BOARD_E1186)
636                 platform_device_register(&tegra_dtv_device);
637 }
638
639 static struct resource tegra_rtc_resources[] = {
640         [0] = {
641                 .start = TEGRA_RTC_BASE,
642                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
643                 .flags = IORESOURCE_MEM,
644         },
645         [1] = {
646                 .start = INT_RTC,
647                 .end = INT_RTC,
648                 .flags = IORESOURCE_IRQ,
649         },
650 };
651
652 static struct platform_device tegra_rtc_device = {
653         .name = "tegra_rtc",
654         .id   = -1,
655         .resource = tegra_rtc_resources,
656         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
657 };
658
659 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
660         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
661         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
662         .gpio_hp_mute           = -1,
663         .gpio_int_mic_en        = -1,
664         .gpio_ext_mic_en        = -1,
665 };
666
667 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
668         .gpio_spkr_en           = -1,
669         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
670         .gpio_hp_mute           = -1,
671         .gpio_int_mic_en        = -1,
672         .gpio_ext_mic_en        = -1,
673 };
674
675 static struct platform_device cardhu_audio_wm8903_device = {
676         .name   = "tegra-snd-wm8903",
677         .id     = 0,
678         .dev    = {
679                 .platform_data = &cardhu_audio_wm8903_pdata,
680         },
681 };
682
683 static struct platform_device cardhu_audio_max98095_device = {
684         .name   = "tegra-snd-max98095",
685         .id     = 0,
686         .dev    = {
687                 .platform_data = &cardhu_audio_max98095_pdata,
688         },
689 };
690
691 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
692         .gpio_spkr_en           = -1,
693         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
694         .gpio_hp_mute           = -1,
695         .gpio_int_mic_en        = -1,
696         .gpio_ext_mic_en        = -1,
697 };
698
699 static struct platform_device cardhu_audio_aic326x_device = {
700         .name   = "tegra-snd-aic326x",
701         .id     = 0,
702         .dev    = {
703                 .platform_data  = &cardhu_audio_aic326x_pdata,
704         },
705 };
706
707 static struct platform_device *cardhu_devices[] __initdata = {
708         &tegra_pmu_device,
709         &tegra_rtc_device,
710         &tegra_udc_device,
711 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
712         &tegra_smmu_device,
713 #endif
714         &tegra_wdt_device,
715 #if defined(CONFIG_TEGRA_AVP)
716         &tegra_avp_device,
717 #endif
718         &tegra_camera,
719 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
720         &tegra_se_device,
721 #endif
722         &tegra_ahub_device,
723         &tegra_dam_device0,
724         &tegra_dam_device1,
725         &tegra_dam_device2,
726         &tegra_i2s_device0,
727         &tegra_i2s_device1,
728         &tegra_i2s_device3,
729         &tegra_spdif_device,
730         &spdif_dit_device,
731         &bluetooth_dit_device,
732         &baseband_dit_device,
733         &cardhu_bcm4329_rfkill_device,
734         &tegra_pcm_device,
735         &cardhu_audio_wm8903_device,
736         &cardhu_audio_max98095_device,
737         &cardhu_audio_aic326x_device,
738         &tegra_hda_device,
739 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
740         &tegra_aes_device,
741 #endif
742 };
743
744 #define MXT_CONFIG_CRC  0xD62DE8
745 static const u8 config[] = {
746         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
747         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
748         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
749         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
750         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
751         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
752         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
753         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
754         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
755         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
756         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
757         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
758         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
759         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
760         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
762         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
763         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
764         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
766 };
767
768 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
769 static const u8 config_sku2000[] = {
770         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
771         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
772         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
773         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
774         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
775         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
776         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
777         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
778         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
779         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
780         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
781         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
782         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
783         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
784         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
786         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
788         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
789         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
790 };
791
792 static struct mxt_platform_data atmel_mxt_info = {
793         .x_line         = 27,
794         .y_line         = 42,
795         .x_size         = 768,
796         .y_size         = 1366,
797         .blen           = 0x20,
798         .threshold      = 0x3C,
799         .voltage        = 3300000,              /* 3.3V */
800         .orient         = 5,
801         .config         = config,
802         .config_length  = 157,
803         .config_crc     = MXT_CONFIG_CRC,
804         .irqflags       = IRQF_TRIGGER_FALLING,
805 /*      .read_chg       = &read_chg, */
806         .read_chg       = NULL,
807 };
808
809 static struct i2c_board_info __initdata atmel_i2c_info[] = {
810         {
811                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
812                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
813                 .platform_data = &atmel_mxt_info,
814         }
815 };
816
817 static int __init cardhu_touch_init(void)
818 {
819         struct board_info BoardInfo;
820
821         tegra_gpio_enable(TEGRA_GPIO_PH4);
822         tegra_gpio_enable(TEGRA_GPIO_PH6);
823
824         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
825         gpio_direction_input(TEGRA_GPIO_PH4);
826
827         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
828         gpio_direction_output(TEGRA_GPIO_PH6, 0);
829         msleep(1);
830         gpio_set_value(TEGRA_GPIO_PH6, 1);
831         msleep(100);
832
833         tegra_get_board_info(&BoardInfo);
834         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
835                 atmel_mxt_info.config = config_sku2000;
836                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
837         }
838
839         i2c_register_board_info(1, atmel_i2c_info, 1);
840
841         return 0;
842 }
843
844 static struct tegra_uhsic_config uhsic_phy_config = {
845         .enable_gpio = EN_HSIC_GPIO,
846         .reset_gpio = -1,
847         .sync_start_delay = 9,
848         .idle_wait_delay = 17,
849         .term_range_adj = 0,
850         .elastic_underrun_limit = 16,
851         .elastic_overrun_limit = 16,
852 };
853
854 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
855         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
856         .phy_config = &uhsic_phy_config,
857         .operating_mode = TEGRA_USB_HOST,
858         .power_down_on_bus_suspend = 1,
859         .default_enable = true,
860 };
861
862 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
863         [0] = {
864                         .phy_config = &utmi_phy_config[0],
865                         .operating_mode = TEGRA_USB_HOST,
866                         .power_down_on_bus_suspend = 1,
867                         .default_enable = true,
868         },
869         [1] = {
870                         .phy_config = &utmi_phy_config[1],
871                         .operating_mode = TEGRA_USB_HOST,
872                         .power_down_on_bus_suspend = 1,
873                         .default_enable = true,
874         },
875         [2] = {
876                         .phy_config = &utmi_phy_config[2],
877                         .operating_mode = TEGRA_USB_HOST,
878                         .power_down_on_bus_suspend = 1,
879                         .hotplug = 1,
880                         .default_enable = true,
881         },
882 };
883
884 static struct tegra_otg_platform_data tegra_otg_pdata = {
885         .ehci_device = &tegra_ehci1_device,
886         .ehci_pdata = &tegra_ehci_pdata[0],
887 };
888
889 #ifdef CONFIG_USB_SUPPORT
890 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
891         [0] = {
892                         .instance = 0,
893                         .vbus_gpio = -1,
894                         .vbus_reg_supply = "vdd_vbus_micro_usb",
895         },
896         [1] = {
897                         .instance = 1,
898                         .vbus_gpio = -1,
899         },
900         [2] = {
901                         .instance = 2,
902                         .vbus_gpio = -1,
903                         .vbus_reg_supply = "vdd_vbus_typea_usb",
904         },
905 };
906
907 static int cardhu_usb_hsic_postsupend(void)
908 {
909 #ifdef CONFIG_TEGRA_BB_XMM_POWER
910         baseband_xmm_set_power_status(BBXMM_PS_L2);
911 #endif
912         return 0;
913 }
914
915 static int cardhu_usb_hsic_preresume(void)
916 {
917 #ifdef CONFIG_TEGRA_BB_XMM_POWER
918         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
919 #endif
920         return 0;
921 }
922
923 static int cardhu_usb_hsic_phy_ready(void)
924 {
925 #ifdef CONFIG_TEGRA_BB_XMM_POWER
926         baseband_xmm_set_power_status(BBXMM_PS_L0);
927 #endif
928         return 0;
929 }
930
931 static int cardhu_usb_hsic_phy_off(void)
932 {
933 #ifdef CONFIG_TEGRA_BB_XMM_POWER
934         baseband_xmm_set_power_status(BBXMM_PS_L3);
935 #endif
936         return 0;
937 }
938
939 static void cardhu_usb_init(void)
940 {
941         struct board_info bi;
942
943         tegra_get_board_info(&bi);
944
945         tegra_usb_phy_init(tegra_usb_phy_pdata,
946                         ARRAY_SIZE(tegra_usb_phy_pdata));
947
948         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
949         platform_device_register(&tegra_otg_device);
950         if (bi.board_id == BOARD_PM267) {
951                 uhsic_phy_config.reset_gpio =
952                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
953                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
954                 platform_device_register(&tegra_ehci2_device);
955         } else if (bi.board_id == BOARD_E1256) {
956                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
957                 platform_device_register(&tegra_ehci2_device);
958         } else if (bi.board_id == BOARD_E1186) {
959                 /* for baseband devices do not switch off phy during suspend */
960                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
961                 uhsic_phy_config.postsuspend = cardhu_usb_hsic_postsupend;
962                 uhsic_phy_config.preresume = cardhu_usb_hsic_preresume;
963                 uhsic_phy_config.usb_phy_ready = cardhu_usb_hsic_phy_ready;
964                 uhsic_phy_config.post_phy_off = cardhu_usb_hsic_phy_off;
965                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
966                 /* baseband registration happens in baseband-xmm-power  */
967         } else {
968                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
969                 platform_device_register(&tegra_ehci2_device);
970         }
971
972         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
973         platform_device_register(&tegra_ehci3_device);
974
975 }
976 #else
977 static void cardhu_usb_init(void) { }
978 #endif
979
980 static void cardhu_gps_init(void)
981 {
982         tegra_gpio_enable(TEGRA_GPIO_PU2);
983         tegra_gpio_enable(TEGRA_GPIO_PU3);
984 }
985
986 static void cardhu_nfc_init(void)
987 {
988         tegra_gpio_enable(TEGRA_GPIO_PX0);
989         tegra_gpio_enable(TEGRA_GPIO_PP3);
990         tegra_gpio_enable(TEGRA_GPIO_PO7);
991 }
992
993 static struct baseband_power_platform_data tegra_baseband_power_data = {
994         .baseband_type = BASEBAND_XMM,
995         .modem = {
996         .xmm = {
997                         .bb_rst = XMM_GPIO_BB_RST,
998                         .bb_on = XMM_GPIO_BB_ON,
999                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1000                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1001                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1002                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1003                         .hsic_device = &tegra_ehci2_device,
1004                 },
1005         },
1006 };
1007
1008 static struct platform_device tegra_baseband_power_device = {
1009         .name = "baseband_xmm_power",
1010         .id = -1,
1011         .dev = {
1012                 .platform_data = &tegra_baseband_power_data,
1013         },
1014 };
1015
1016 static struct platform_device tegra_baseband_power2_device = {
1017         .name = "baseband_xmm_power2",
1018         .id = -1,
1019         .dev = {
1020                 .platform_data = &tegra_baseband_power_data,
1021         },
1022 };
1023
1024
1025 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1026         .port_status[0] = 1,
1027         .port_status[1] = 1,
1028         .port_status[2] = 1,
1029         .use_dock_detect        = 0,
1030         .gpio           = 0,
1031 };
1032
1033 static void cardhu_pci_init(void)
1034 {
1035         struct board_info board_info;
1036
1037         tegra_get_board_info(&board_info);
1038         if (board_info.board_id == BOARD_E1291) {
1039                 cardhu_pci_platform_data.port_status[0] = 0;
1040                 cardhu_pci_platform_data.port_status[1] = 0;
1041                 cardhu_pci_platform_data.port_status[2] = 1;
1042                 cardhu_pci_platform_data.use_dock_detect = 1;
1043                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1044         }
1045         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1046         platform_device_register(&tegra_pci_device);
1047 }
1048
1049 static void cardhu_modem_init(void)
1050 {
1051         struct board_info board_info;
1052         int w_disable_gpio, ret;
1053
1054         tegra_get_board_info(&board_info);
1055         switch (board_info.board_id) {
1056         case BOARD_E1291:
1057         case BOARD_E1198:
1058                 if (((board_info.board_id == BOARD_E1291) &&
1059                                 (board_info.fab < BOARD_FAB_A03)) ||
1060                         ((board_info.board_id == BOARD_E1198) &&
1061                                         (board_info.fab < BOARD_FAB_A02))) {
1062                         w_disable_gpio = TEGRA_GPIO_PH5;
1063                 } else {
1064                         w_disable_gpio = TEGRA_GPIO_PDD5;
1065                 }
1066                 tegra_gpio_enable(w_disable_gpio);
1067                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1068                 if (ret < 0)
1069                         pr_err("%s: gpio_request failed for gpio %d\n",
1070                                 __func__, w_disable_gpio);
1071                 else
1072                         gpio_direction_input(w_disable_gpio);
1073
1074                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1075                 if (((board_info.board_id == BOARD_E1291) &&
1076                                 (board_info.fab >= BOARD_FAB_A04)) ||
1077                         ((board_info.board_id == BOARD_E1198) &&
1078                                         (board_info.fab >= BOARD_FAB_A02))) {
1079                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1080                         if (ret < 0) {
1081                                 pr_err("%s(): Error in allocating gpio "
1082                                         "TEGRA_GPIO_PH7\n", __func__);
1083                                 break;
1084                         }
1085                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1086                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1087                 }
1088                 break;
1089         case BOARD_E1186:
1090                 tegra_gpio_enable(
1091                         tegra_baseband_power_data.modem.xmm.bb_rst);
1092                 tegra_gpio_enable(
1093                         tegra_baseband_power_data.modem.xmm.bb_on);
1094                 tegra_gpio_enable(
1095                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1096                 tegra_gpio_enable(
1097                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1098                 tegra_gpio_enable(
1099                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1100                 tegra_gpio_enable(
1101                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1102                 platform_device_register(&tegra_baseband_power_device);
1103                 platform_device_register(&tegra_baseband_power2_device);
1104                 break;
1105         default:
1106                 break;
1107         }
1108
1109 }
1110
1111 #ifdef CONFIG_SATA_AHCI_TEGRA
1112 static void cardhu_sata_init(void)
1113 {
1114         platform_device_register(&tegra_sata_device);
1115 }
1116 #else
1117 static void cardhu_sata_init(void) { }
1118 #endif
1119
1120 static void __init tegra_cardhu_init(void)
1121 {
1122         tegra_thermal_init(&thermal_data);
1123         tegra_clk_init_from_table(cardhu_clk_init_table);
1124         tegra_enable_pinmux();
1125         cardhu_pinmux_init();
1126         cardhu_i2c_init();
1127         cardhu_spi_init();
1128         cardhu_usb_init();
1129 #ifdef CONFIG_TEGRA_EDP_LIMITS
1130         cardhu_edp_init();
1131 #endif
1132         cardhu_uart_init();
1133         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1134         tegra_ram_console_debug_init();
1135         cardhu_sdhci_init();
1136         cardhu_regulator_init();
1137         cardhu_dtv_init();
1138         cardhu_suspend_init();
1139         cardhu_touch_init();
1140         cardhu_gps_init();
1141         cardhu_modem_init();
1142         cardhu_kbc_init();
1143         cardhu_scroll_init();
1144         cardhu_keys_init();
1145         cardhu_panel_init();
1146         cardhu_pmon_init();
1147         cardhu_sensors_init();
1148         cardhu_setup_bluesleep();
1149         cardhu_sata_init();
1150         //audio_wired_jack_init();
1151         cardhu_pins_state_init();
1152         cardhu_emc_init();
1153         tegra_release_bootloader_fb();
1154         cardhu_nfc_init();
1155         cardhu_pci_init();
1156 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1157         tegra_wdt_recovery_init();
1158 #endif
1159 }
1160
1161 static void __init tegra_cardhu_reserve(void)
1162 {
1163 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1164         /* support 1920X1200 with 24bpp */
1165         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1166 #else
1167         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1168 #endif
1169         tegra_ram_console_debug_reserve(SZ_1M);
1170 }
1171
1172 MACHINE_START(CARDHU, "cardhu")
1173         .atag_offset    = 0x100,
1174         .map_io         = tegra_map_common_io,
1175         .reserve        = tegra_cardhu_reserve,
1176         .init_early     = tegra30_init_early,
1177         .init_irq       = tegra_init_irq,
1178         .handle_irq     = gic_handle_irq,
1179         .timer          = &tegra_timer,
1180         .init_machine   = tegra_cardhu_init,
1181         .restart        = tegra_assert_system_reset,
1182 MACHINE_END