ARM: tegra: thermal: Thermal Refactor
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  * Copyright (c) 2011-2012, NVIDIA Corporation.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/serial_8250.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/panjit_ts.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/gpio.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/spi/spi.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44
45
46 #include <sound/wm8903.h>
47 #include <sound/max98095.h>
48 #include <media/tegra_dtv.h>
49
50 #include <asm/hardware/gic.h>
51
52 #include <mach/edp.h>
53 #include <mach/clk.h>
54 #include <mach/iomap.h>
55 #include <mach/irqs.h>
56 #include <mach/pinmux.h>
57 #include <mach/iomap.h>
58 #include <mach/io_dpd.h>
59 #include <mach/io.h>
60 #include <mach/i2s.h>
61 #include <mach/tegra_asoc_pdata.h>
62 #include <mach/tegra_wm8903_pdata.h>
63 #include <mach/usb_phy.h>
64 #include <mach/thermal.h>
65 #include <mach/pci.h>
66 #include <mach/gpio-tegra.h>
67 #include <mach/tegra_fiq_debugger.h>
68 #include <linux/thermal.h>
69
70 #include <asm/hardware/gic.h>
71 #include <asm/mach-types.h>
72 #include <asm/mach/arch.h>
73
74 #include "board.h"
75 #include "clock.h"
76 #include "board-cardhu.h"
77 #include "board-touch.h"
78 #include "devices.h"
79 #include "gpio-names.h"
80 #include "fuse.h"
81 #include "pm.h"
82 #include "baseband-xmm-power.h"
83 #include "wdt-recovery.h"
84 #include "common.h"
85
86 static struct balanced_throttle throttle_list[] = {
87         {
88                 .tegra_cdev = {
89                         .id = CDEV_BTHROT_ID_TJ,
90                 },
91                 .throt_tab_size = 10,
92                 .throt_tab = {
93                         {      0, 1000 },
94                         { 640000, 1000 },
95                         { 640000, 1000 },
96                         { 640000, 1000 },
97                         { 640000, 1000 },
98                         { 640000, 1000 },
99                         { 760000, 1000 },
100                         { 760000, 1050 },
101                         {1000000, 1050 },
102                         {1000000, 1100 },
103                 },
104         },
105 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
106         {
107                 .tegra_cdev = {
108                         .id = CDEV_BTHROT_ID_SKIN,
109                 },
110                 .throt_tab_size = 6,
111                 .throt_tab = {
112                         { 640000, 1200 },
113                         { 640000, 1200 },
114                         { 760000, 1200 },
115                         { 760000, 1200 },
116                         {1000000, 1200 },
117                         {1000000, 1200 },
118                 },
119         },
120 #endif
121 };
122
123 static struct tegra_thermal_bind thermal_binds[] = {
124         /* Thermal Throttling */
125         {
126                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
127                 .cdev_id = CDEV_BTHROT_ID_TJ,
128                 .type = THERMAL_TRIP_PASSIVE,
129                 .passive = {
130                         .trip_temp = 85000,
131                         .tc1 = 0,
132                         .tc2 = 1,
133                         .passive_delay = 2000,
134                 }
135         },
136         /* EDP Capping */
137         {
138                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
139                 .cdev_id = CDEV_EDPTABLE_ID_EDP,
140                 .type = THERMAL_TRIP_ACTIVE,
141                 .get_trip_temp = tegra_edp_get_trip_temp,
142                 .get_trip_size = tegra_edp_get_trip_size,
143         },
144 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
145         /* Skin Thermal Throttling */
146         {
147                 .tdev_id = THERMAL_DEVICE_ID_SKIN,
148                 .cdev_id = CDEV_BTHROT_ID_SKIN,
149                 .type = THERMAL_TRIP_PASSIVE,
150                 .passive = {
151                         .trip_temp = 43000,
152                         .tc1 = 10,
153                         .tc2 = 1,
154                         .passive_delay = 15000,
155                 }
156         },
157 #endif
158         {
159                 .tdev_id = THERMAL_DEVICE_ID_NULL,
160         },
161 };
162
163 static struct tegra_skin_data skin_data = {
164 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
165         .skin_device_id = THERMAL_DEVICE_ID_THERM_EST_SKIN,
166         .skin_temp_offset = 9793,
167         .skin_period = 1100,
168         .skin_devs_size = 2,
169         .skin_devs = {
170                 {
171                         THERMAL_DEVICE_ID_NCT_EXT,
172                         {
173                                 2, 1, 1, 1,
174                                 1, 1, 1, 1,
175                                 1, 1, 1, 0,
176                                 1, 1, 0, 0,
177                                 0, 0, -1, -7
178                         }
179                 },
180                 {
181                         THERMAL_DEVICE_ID_NCT_INT,
182                         {
183                                 -11, -7, -5, -3,
184                                 -3, -2, -1, 0,
185                                 0, 0, 1, 1,
186                                 1, 2, 2, 3,
187                                 4, 6, 11, 18
188                         }
189                 },
190         },
191 #else
192         .skin_device_id = THERMAL_DEVICE_ID_NULL,
193 #endif
194 };
195
196
197 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
198         {
199                 .name           = "bt_rfkill",
200                 .shutdown_gpio  = TEGRA_GPIO_PU0,
201                 .reset_gpio     = TEGRA_GPIO_INVALID,
202                 .type           = RFKILL_TYPE_BLUETOOTH,
203         },
204 };
205
206 static struct platform_device cardhu_bt_rfkill_device = {
207         .name = "rfkill_gpio",
208         .id             = -1,
209         .dev = {
210                 .platform_data = &cardhu_bt_rfkill_pdata,
211         },
212 };
213
214 static struct resource cardhu_bluesleep_resources[] = {
215         [0] = {
216                 .name = "gpio_host_wake",
217                         .start  = TEGRA_GPIO_PU6,
218                         .end    = TEGRA_GPIO_PU6,
219                         .flags  = IORESOURCE_IO,
220         },
221         [1] = {
222                 .name = "gpio_ext_wake",
223                         .start  = TEGRA_GPIO_PU1,
224                         .end    = TEGRA_GPIO_PU1,
225                         .flags  = IORESOURCE_IO,
226         },
227         [2] = {
228                 .name = "host_wake",
229                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
230         },
231 };
232
233 static struct platform_device cardhu_bluesleep_device = {
234         .name           = "bluesleep",
235         .id             = -1,
236         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
237         .resource       = cardhu_bluesleep_resources,
238 };
239
240 static noinline void __init cardhu_setup_bluesleep(void)
241 {
242         cardhu_bluesleep_resources[2].start =
243                 cardhu_bluesleep_resources[2].end =
244                         gpio_to_irq(TEGRA_GPIO_PU6);
245         platform_device_register(&cardhu_bluesleep_device);
246         return;
247 }
248
249 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
250         /* name         parent          rate            enabled */
251         { "pll_m",      NULL,           0,              false},
252         { "hda",        "pll_p",        108000000,      false},
253         { "hda2codec_2x","pll_p",       48000000,       false},
254         { "pwm",        "pll_p",        3187500,        false},
255         { "blink",      "clk_32k",      32768,          true},
256         { "i2s0",       "pll_a_out0",   0,              false},
257         { "i2s1",       "pll_a_out0",   0,              false},
258         { "i2s3",       "pll_a_out0",   0,              false},
259         { "spdif_out",  "pll_a_out0",   0,              false},
260         { "d_audio",    "clk_m",        12000000,       false},
261         { "dam0",       "clk_m",        12000000,       false},
262         { "dam1",       "clk_m",        12000000,       false},
263         { "dam2",       "clk_m",        12000000,       false},
264         { "audio1",     "i2s1_sync",    0,              false},
265         { "audio3",     "i2s3_sync",    0,              false},
266         { "vi_sensor",  "pll_p",        150000000,      false},
267         { "i2c1",       "pll_p",        3200000,        false},
268         { "i2c2",       "pll_p",        3200000,        false},
269         { "i2c3",       "pll_p",        3200000,        false},
270         { "i2c4",       "pll_p",        3200000,        false},
271         { "i2c5",       "pll_p",        3200000,        false},
272         { "vi",         "pll_p",        0,              false},
273         { NULL,         NULL,           0,              0},
274 };
275
276 static struct pn544_i2c_platform_data nfc_pdata = {
277         .irq_gpio = TEGRA_GPIO_PX0,
278         .ven_gpio = TEGRA_GPIO_PP3,
279         .firm_gpio = TEGRA_GPIO_PO7,
280         };
281
282 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
283         {
284                 I2C_BOARD_INFO("pn544", 0x28),
285                 .platform_data = &nfc_pdata,
286         },
287 };
288 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
289         .adapter_nr     = 0,
290         .bus_count      = 1,
291         .bus_clk_rate   = { 100000, 0 },
292         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
293         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
294         .arb_recovery = arb_lost_recovery,
295 };
296
297 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
298         .adapter_nr     = 1,
299         .bus_count      = 1,
300         .bus_clk_rate   = { 400000, 0 },
301         .is_clkon_always = true,
302         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
303         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
304         .arb_recovery = arb_lost_recovery,
305 };
306
307 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
308         .adapter_nr     = 2,
309         .bus_count      = 1,
310         .bus_clk_rate   = { 100000, 0 },
311         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
312         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
313         .arb_recovery = arb_lost_recovery,
314 };
315
316 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
317         .adapter_nr     = 3,
318         .bus_count      = 1,
319         .bus_clk_rate   = { 10000, 0 },
320         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
321         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
322         .arb_recovery = arb_lost_recovery,
323 };
324
325 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
326         .adapter_nr     = 4,
327         .bus_count      = 1,
328         .bus_clk_rate   = { 400000, 0 },
329         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
330         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
331         .arb_recovery = arb_lost_recovery,
332 };
333
334
335 #if 0
336 struct tegra_wired_jack_conf audio_wr_jack_conf = {
337         .hp_det_n = TEGRA_GPIO_PW2,
338         .en_mic_ext = TEGRA_GPIO_PX1,
339         .en_mic_int = TEGRA_GPIO_PX0,
340 };
341 #endif
342
343 static struct wm8903_platform_data cardhu_wm8903_pdata = {
344         .irq_active_low = 0,
345         .micdet_cfg = 0,
346         .micdet_delay = 100,
347         .gpio_base = CARDHU_GPIO_WM8903(0),
348         .gpio_cfg = {
349                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
350                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
351                         WM8903_GP2_DIR,
352                 WM8903_GPIO_CONFIG_ZERO,
353                 0,
354                 0,
355         },
356 };
357
358 /* Equalizer filter coefs generated from the MAXIM MAX98095
359  * evkit software tool */
360 static struct max98095_eq_cfg max98095_eq_cfg[] = {
361         {
362                 .name = "FLAT",
363                 .rate = 44100,
364                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
365                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
366                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
367                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
368                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
369         },
370         {
371                 .name = "LOWPASS1K",
372                 .rate = 44100,
373                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
374                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
375                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
376                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
377                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
378         },
379         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
380                 .name = "HIBOOST",
381                 .rate = 44100,
382                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
383                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
384                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
385                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
386                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
387         },
388         { /* BASS=12dB, TREBLE=+12dB */
389                 .name = "LOUD12DB",
390                 .rate = 44100,
391                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
392                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
393                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
394                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
395                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
396         },
397         {
398                 .name = "FLAT",
399                 .rate = 16000,
400                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
401                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
402                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
403                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
404                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
405         },
406         {
407                 .name = "LOWPASS1K",
408                 .rate = 16000,
409                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
410                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
411                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
412                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
413                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
414         },
415         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
416                 .name = "HIBOOST",
417                 .rate = 16000,
418                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
419                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
420                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
421                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
422                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
423         },
424         { /* BASS=12dB, TREBLE=+12dB */
425                 .name = "LOUD12DB",
426                 .rate = 16000,
427                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
428                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
429                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
430                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
431                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
432         },
433 };
434
435 static struct max98095_pdata cardhu_max98095_pdata = {
436         /* equalizer configuration */
437         .eq_cfg = max98095_eq_cfg,
438         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
439
440         /* Biquad filter response configuration */
441         .bq_cfg = NULL,
442         .bq_cfgcnt = 0,
443
444         /* microphone configuration */
445         .digmic_left_mode = 1,
446         .digmic_right_mode = 1,
447 };
448
449 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
450         I2C_BOARD_INFO("wm8903", 0x1a),
451         .platform_data = &cardhu_wm8903_pdata,
452 };
453
454 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
455         I2C_BOARD_INFO("aic3262-codec", 0x18),
456 };
457
458 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
459         I2C_BOARD_INFO("max98095", 0x10),
460         .platform_data = &cardhu_max98095_pdata,
461 };
462
463 static void cardhu_i2c_init(void)
464 {
465         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
466         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
467         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
468         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
469         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
470
471         platform_device_register(&tegra_i2c_device5);
472         platform_device_register(&tegra_i2c_device4);
473         platform_device_register(&tegra_i2c_device3);
474         platform_device_register(&tegra_i2c_device2);
475         platform_device_register(&tegra_i2c_device1);
476
477         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
478                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
479         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
480         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
481         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
482
483         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
484         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
485 }
486
487 static struct platform_device *cardhu_uart_devices[] __initdata = {
488         &tegra_uarta_device,
489         &tegra_uartb_device,
490         &tegra_uartc_device,
491         &tegra_uartd_device,
492         &tegra_uarte_device,
493 };
494 static struct uart_clk_parent uart_parent_clk[] = {
495         [0] = {.name = "clk_m"},
496         [1] = {.name = "pll_p"},
497 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
498         [2] = {.name = "pll_m"},
499 #endif
500 };
501
502 static struct tegra_uart_platform_data cardhu_uart_pdata;
503 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
504
505 static void __init uart_debug_init(void)
506 {
507         struct board_info board_info;
508         int debug_port_id;
509
510         tegra_get_board_info(&board_info);
511
512         debug_port_id = get_tegra_uart_debug_port_id();
513         if (debug_port_id < 0) {
514                 debug_port_id = 0;
515                         /* UARTB is debug port
516                          *       for SLT - E1186/E1187/PM269
517                          *       for E1256/E1257
518                          */
519                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
520                         ((board_info.board_id == BOARD_E1186) ||
521                         (board_info.board_id == BOARD_E1187) ||
522                         (board_info.board_id == BOARD_PM269))) ||
523                         (board_info.board_id == BOARD_E1256) ||
524                         (board_info.board_id == BOARD_E1257))
525                                 debug_port_id = 1;
526         }
527
528 #ifdef CONFIG_TEGRA_IRDA
529         if ((board_info.board_id == BOARD_E1186) ||
530                 (board_info.board_id == BOARD_E1198)) {
531                 if (debug_port_id == 1) {
532                         cardhu_irda_pdata.is_irda = false;
533                         pr_err("UARTB is not available for IrDA\n");
534                 }
535         }
536 #endif
537
538         switch (debug_port_id) {
539         case 0:
540                 /* UARTA is the debug port. */
541                 pr_info("Selecting UARTA as the debug console\n");
542                 cardhu_uart_devices[0] = &debug_uarta_device;
543                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
544                 debug_uart_port_base = ((struct plat_serial8250_port *)(
545                         debug_uarta_device.dev.platform_data))->mapbase;
546                 break;
547
548         case 1:
549                 /* UARTB is the debug port. */
550                 pr_info("Selecting UARTB as the debug console\n");
551                 cardhu_uart_devices[1] = &debug_uartb_device;
552                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
553                 debug_uart_port_base = ((struct plat_serial8250_port *)(
554                         debug_uartb_device.dev.platform_data))->mapbase;
555                 break;
556
557         case 2:
558                 /* UARTC is the debug port. */
559                 pr_info("Selecting UARTC as the debug console\n");
560                 cardhu_uart_devices[2] = &debug_uartc_device;
561                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
562                 debug_uart_port_base = ((struct plat_serial8250_port *)(
563                         debug_uartc_device.dev.platform_data))->mapbase;
564                 break;
565
566         case 3:
567                 /* UARTD is the debug port. */
568                 pr_info("Selecting UARTD as the debug console\n");
569                 cardhu_uart_devices[3] = &debug_uartd_device;
570                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
571                 debug_uart_port_base = ((struct plat_serial8250_port *)(
572                         debug_uartd_device.dev.platform_data))->mapbase;
573                 break;
574
575         case 4:
576                 /* UARTE is the debug port. */
577                 pr_info("Selecting UARTE as the debug console\n");
578                 cardhu_uart_devices[4] = &debug_uarte_device;
579                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
580                 debug_uart_port_base = ((struct plat_serial8250_port *)(
581                         debug_uarte_device.dev.platform_data))->mapbase;
582                 break;
583
584         default:
585                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
586                 cardhu_uart_devices[0] = &debug_uarta_device;
587                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
588                 debug_uart_port_base = ((struct plat_serial8250_port *)(
589                         debug_uarta_device.dev.platform_data))->mapbase;
590                 break;
591         }
592         return;
593 }
594
595 static void __init cardhu_uart_init(void)
596 {
597         struct clk *c;
598         int i;
599         struct board_info board_info;
600
601         tegra_get_board_info(&board_info);
602
603         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
604                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
605                 if (IS_ERR_OR_NULL(c)) {
606                         pr_err("Not able to get the clock for %s\n",
607                                                 uart_parent_clk[i].name);
608                         continue;
609                 }
610                 uart_parent_clk[i].parent_clk = c;
611                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
612         }
613         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
614         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
615         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
616         cardhu_loopback_uart_pdata.parent_clk_count =
617                                                 ARRAY_SIZE(uart_parent_clk);
618         cardhu_loopback_uart_pdata.is_loopback = true;
619         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
620         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
621         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
622         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
623         /* UARTE is used for loopback test purpose */
624         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
625
626         /* Register low speed only if it is selected */
627         if (!is_tegra_debug_uartport_hs()) {
628                 uart_debug_init();
629                 /* Clock enable for the debug channel */
630                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
631                         pr_info("The debug console clock name is %s\n",
632                                                 debug_uart_clk->name);
633                         c = tegra_get_clock_by_name("pll_p");
634                         if (IS_ERR_OR_NULL(c))
635                                 pr_err("Not getting the parent clock pll_p\n");
636                         else
637                                 clk_set_parent(debug_uart_clk, c);
638
639                         clk_enable(debug_uart_clk);
640                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
641                 } else {
642                         pr_err("Not getting the clock %s for debug console\n",
643                                         debug_uart_clk->name);
644                 }
645         }
646
647 #ifdef CONFIG_TEGRA_IRDA
648         if (((board_info.board_id == BOARD_E1186) ||
649                 (board_info.board_id == BOARD_E1198)) &&
650                         cardhu_irda_pdata.is_irda) {
651                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
652                 cardhu_irda_pdata.parent_clk_count =
653                                         ARRAY_SIZE(uart_parent_clk);
654
655                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
656         }
657 #endif
658
659         platform_add_devices(cardhu_uart_devices,
660                                 ARRAY_SIZE(cardhu_uart_devices));
661 }
662
663 static struct platform_device tegra_camera = {
664         .name = "tegra_camera",
665         .id = -1,
666 };
667
668 static struct platform_device *cardhu_spi_devices[] __initdata = {
669         &tegra_spi_device4,
670 };
671
672 static struct platform_device *touch_spi_device[] __initdata = {
673         &tegra_spi_device1,
674 };
675
676 struct spi_clk_parent spi_parent_clk[] = {
677         [0] = {.name = "pll_p"},
678 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
679         [1] = {.name = "pll_m"},
680         [2] = {.name = "clk_m"},
681 #else
682         [1] = {.name = "clk_m"},
683 #endif
684 };
685
686 static struct tegra_spi_platform_data cardhu_spi_pdata = {
687         .is_dma_based           = true,
688         .max_dma_buffer         = (16 * 1024),
689         .is_clkon_always        = false,
690         .max_rate               = 100000000,
691 };
692
693 static void __init cardhu_spi_init(void)
694 {
695         int i;
696         struct clk *c;
697         struct board_info board_info, display_board_info;
698
699         tegra_get_board_info(&board_info);
700         tegra_get_display_board_info(&display_board_info);
701
702         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
703                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
704                 if (IS_ERR_OR_NULL(c)) {
705                         pr_err("Not able to get the clock for %s\n",
706                                                 spi_parent_clk[i].name);
707                         continue;
708                 }
709                 spi_parent_clk[i].parent_clk = c;
710                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
711         }
712         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
713         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
714         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
715         platform_add_devices(cardhu_spi_devices,
716                                 ARRAY_SIZE(cardhu_spi_devices));
717
718         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
719                 platform_add_devices(touch_spi_device,
720                                 ARRAY_SIZE(touch_spi_device));
721         }
722         if (board_info.board_id == BOARD_E1198) {
723                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
724                 platform_device_register(&tegra_spi_device2);
725                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
726                 platform_device_register(&tegra_spi_slave_device1);
727         }
728 }
729
730 static void __init cardhu_dtv_init(void)
731 {
732         struct board_info board_info;
733
734         tegra_get_board_info(&board_info);
735
736         if (board_info.board_id == BOARD_E1186)
737                 platform_device_register(&tegra_dtv_device);
738 }
739
740 static struct resource tegra_rtc_resources[] = {
741         [0] = {
742                 .start = TEGRA_RTC_BASE,
743                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
744                 .flags = IORESOURCE_MEM,
745         },
746         [1] = {
747                 .start = INT_RTC,
748                 .end = INT_RTC,
749                 .flags = IORESOURCE_IRQ,
750         },
751 };
752
753 static struct platform_device tegra_rtc_device = {
754         .name = "tegra_rtc",
755         .id   = -1,
756         .resource = tegra_rtc_resources,
757         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
758 };
759
760 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
761         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
762         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
763         .gpio_hp_mute           = -1,
764         .gpio_int_mic_en        = -1,
765         .gpio_ext_mic_en        = -1,
766         .i2s_param[HIFI_CODEC]  = {
767                 .audio_port_id  = 0,
768                 .is_i2s_master  = 1,
769                 .i2s_mode       = TEGRA_DAIFMT_I2S,
770         },
771         .i2s_param[BASEBAND]    = {
772                 .audio_port_id  = -1,
773         },
774         .i2s_param[BT_SCO]      = {
775                 .audio_port_id  = 3,
776                 .is_i2s_master  = 1,
777                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
778         },
779 };
780
781 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
782         .gpio_spkr_en           = -1,
783         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
784         .gpio_hp_mute           = -1,
785         .gpio_int_mic_en        = -1,
786         .gpio_ext_mic_en        = -1,
787         .i2s_param[HIFI_CODEC]  = {
788                 .audio_port_id  = 0,
789                 .is_i2s_master  = 1,
790                 .i2s_mode       = TEGRA_DAIFMT_I2S,
791         },
792         .i2s_param[BASEBAND]    = {
793                 .audio_port_id  = -1,
794         },
795         .i2s_param[BT_SCO]      = {
796                 .audio_port_id  = 3,
797                 .is_i2s_master  = 1,
798                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
799         },
800 };
801
802 static struct platform_device cardhu_audio_wm8903_device = {
803         .name   = "tegra-snd-wm8903",
804         .id     = 0,
805         .dev    = {
806                 .platform_data = &cardhu_audio_wm8903_pdata,
807         },
808 };
809
810 static struct platform_device cardhu_audio_max98095_device = {
811         .name   = "tegra-snd-max98095",
812         .id     = 0,
813         .dev    = {
814                 .platform_data = &cardhu_audio_max98095_pdata,
815         },
816 };
817
818 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
819         .gpio_spkr_en           = -1,
820         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
821         .gpio_hp_mute           = -1,
822         .gpio_int_mic_en        = -1,
823         .gpio_ext_mic_en        = -1,
824         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
825         .i2s_param[HIFI_CODEC]  = {
826                 .audio_port_id  = 0,
827                 .is_i2s_master  = 1,
828                 .i2s_mode       = TEGRA_DAIFMT_I2S,
829                 .sample_size    = 16,
830         },
831         .i2s_param[BT_SCO]      = {
832                 .sample_size    = 16,
833                 .audio_port_id  = 3,
834                 .is_i2s_master  = 1,
835                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
836         },
837 };
838
839 static struct platform_device cardhu_audio_aic326x_device = {
840         .name   = "tegra-snd-aic326x",
841         .id     = 0,
842         .dev    = {
843                 .platform_data  = &cardhu_audio_aic326x_pdata,
844         },
845 };
846
847 static struct platform_device *cardhu_devices[] __initdata = {
848         &tegra_pmu_device,
849         &tegra_rtc_device,
850         &tegra_udc_device,
851         &tegra_wdt0_device,
852         &tegra_wdt1_device,
853         &tegra_wdt2_device,
854 #if defined(CONFIG_TEGRA_AVP)
855         &tegra_avp_device,
856 #endif
857         &tegra_camera,
858 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
859         &tegra_se_device,
860 #endif
861         &tegra_ahub_device,
862         &tegra_dam_device0,
863         &tegra_dam_device1,
864         &tegra_dam_device2,
865         &tegra_i2s_device0,
866         &tegra_i2s_device1,
867         &tegra_i2s_device3,
868         &tegra_spdif_device,
869         &spdif_dit_device,
870         &bluetooth_dit_device,
871         &baseband_dit_device,
872         &cardhu_bt_rfkill_device,
873         &tegra_pcm_device,
874         &cardhu_audio_wm8903_device,
875         &cardhu_audio_max98095_device,
876         &cardhu_audio_aic326x_device,
877         &tegra_hda_device,
878         &tegra_cec_device,
879 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
880         &tegra_aes_device,
881 #endif
882 };
883
884 #define E1506_MXT_CONFIG_CRC 0x62F903
885 static const u8 e1506_config[] = {
886         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
887         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
888         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
889         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
890         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
891         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
892         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
893         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
894         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
895         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
896         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
897         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
898         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
899         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
900         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
901         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
903         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
904         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
906         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
907         0x00
908 };
909
910 #define MXT_CONFIG_CRC  0xD62DE8
911 static const u8 config[] = {
912         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
913         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
914         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
915         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
916         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
917         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
918         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
919         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
920         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
921         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
922         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
923         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
924         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
925         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
926         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
927         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
928         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
929         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
930         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
931         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
932 };
933
934 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
935 static const u8 config_sku2000[] = {
936         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
937         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
938         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
939         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
940         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
941         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
942         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
943         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
944         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
945         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
946         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
947         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
948         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
949         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
950         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
951         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
952         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
953         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
954         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
955         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
956 };
957
958 static struct mxt_platform_data atmel_mxt_info = {
959         .x_line         = 27,
960         .y_line         = 42,
961         .x_size         = 768,
962         .y_size         = 1366,
963         .blen           = 0x20,
964         .threshold      = 0x3C,
965         .voltage        = 3300000,              /* 3.3V */
966         .orient         = 5,
967         .config         = config,
968         .config_length  = 157,
969         .config_crc     = MXT_CONFIG_CRC,
970         .irqflags       = IRQF_TRIGGER_FALLING,
971 /*      .read_chg       = &read_chg, */
972         .read_chg       = NULL,
973 };
974
975 static struct mxt_platform_data e1506_atmel_mxt_info = {
976         .x_line         = 19,
977         .y_line         = 11,
978         .x_size         = 960,
979         .y_size         = 540,
980         .blen           = 0x10,
981         .threshold      = 0x32,
982         .voltage        = 3300000,              /* 3.3V */
983         .orient         = 3,
984         .config         = e1506_config,
985         .config_length  = 168,
986         .config_crc     = E1506_MXT_CONFIG_CRC,
987         .irqflags       = IRQF_TRIGGER_FALLING,
988 /*      .read_chg       = &read_chg, */
989         .read_chg       = NULL,
990 };
991
992 static struct i2c_board_info __initdata atmel_i2c_info[] = {
993         {
994                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
995                 .platform_data = &atmel_mxt_info,
996         }
997 };
998
999 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
1000         {
1001                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
1002                 .platform_data = &e1506_atmel_mxt_info,
1003         }
1004 };
1005
1006 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
1007         /* name         parent          rate            enabled */
1008         { "sbc1",       "pll_p",        52000000,       true},
1009         { NULL,         NULL,           0,              0},
1010 };
1011
1012 static int __init cardhu_touch_init(void)
1013 {
1014         struct board_info BoardInfo, DisplayBoardInfo;
1015
1016         tegra_get_board_info(&BoardInfo);
1017         tegra_get_display_board_info(&DisplayBoardInfo);
1018         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
1019                 tegra_clk_init_from_table(spi_clk_init_table);
1020
1021                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
1022         } else {
1023                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1024                 gpio_direction_input(TEGRA_GPIO_PH4);
1025
1026                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1027                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1028                 msleep(1);
1029                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1030                 msleep(100);
1031
1032                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1033                         atmel_mxt_info.config = config_sku2000;
1034                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1035                 }
1036
1037                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1038                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1039                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1040                 } else {
1041                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1042                         i2c_register_board_info(1, atmel_i2c_info, 1);
1043                 }
1044         }
1045
1046         return 0;
1047 }
1048
1049 #if defined(CONFIG_USB_SUPPORT)
1050
1051 static void cardu_usb_hsic_postsupend(void)
1052 {
1053 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1054         baseband_xmm_set_power_status(BBXMM_PS_L2);
1055 #endif
1056 }
1057
1058 static void cardu_usb_hsic_preresume(void)
1059 {
1060 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1061         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1062 #endif
1063 }
1064
1065 static void cardu_usb_hsic_phy_ready(void)
1066 {
1067 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1068         baseband_xmm_set_power_status(BBXMM_PS_L0);
1069 #endif
1070 }
1071
1072 static void cardu_usb_hsic_phy_off(void)
1073 {
1074 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1075         baseband_xmm_set_power_status(BBXMM_PS_L3);
1076 #endif
1077 }
1078
1079 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1080         .post_suspend = cardu_usb_hsic_postsupend,
1081         .pre_resume = cardu_usb_hsic_preresume,
1082         .port_power = cardu_usb_hsic_phy_ready,
1083         .post_phy_off = cardu_usb_hsic_phy_off,
1084 };
1085
1086 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1087         .port_otg = false,
1088         .has_hostpc = true,
1089         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1090         .op_mode        = TEGRA_USB_OPMODE_HOST,
1091         .u_data.host = {
1092                 .vbus_gpio = -1,
1093                 .hot_plug = false,
1094                 .remote_wakeup_supported = false,
1095                 .power_off_on_suspend = false,
1096         },
1097         .ops = &hsic_xmm_plat_ops,
1098 };
1099 #endif
1100
1101 static int hsic_enable_gpio = -1;
1102 static int hsic_reset_gpio = -1;
1103
1104 void hsic_platform_open(void)
1105 {
1106         int reset_gpio = 0, enable_gpio = 0;
1107
1108         if (hsic_enable_gpio != -1)
1109                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1110         if (hsic_reset_gpio != -1)
1111                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1112         /* hsic enable signal deasserted, hsic reset asserted */
1113         if (!enable_gpio)
1114                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1115         if (!reset_gpio)
1116                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1117         /* keep hsic reset asserted for 1 ms */
1118         udelay(1000);
1119         /* enable (power on) hsic */
1120         if (!enable_gpio)
1121                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1122         udelay(1000);
1123         /* deassert reset */
1124         if (!reset_gpio)
1125                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1126
1127 }
1128
1129 void hsic_platform_close(void)
1130 {
1131         if (hsic_enable_gpio != -1) {
1132                 gpio_set_value(hsic_enable_gpio, 0);
1133                 gpio_free(hsic_enable_gpio);
1134         }
1135         if (hsic_reset_gpio != -1) {
1136                 gpio_set_value(hsic_reset_gpio, 0);
1137                 gpio_free(hsic_reset_gpio);
1138         }
1139 }
1140
1141 void hsic_power_on(void)
1142 {
1143         if (hsic_enable_gpio != -1) {
1144                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1145                 udelay(1000);
1146         }
1147 }
1148
1149 void hsic_power_off(void)
1150 {
1151         if (hsic_enable_gpio != -1) {
1152                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1153                 udelay(1000);
1154         }
1155 }
1156
1157 #if defined(CONFIG_USB_SUPPORT)
1158 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1159         .open = hsic_platform_open,
1160         .close = hsic_platform_close,
1161         .pre_phy_on = hsic_power_on,
1162         .post_phy_off = hsic_power_off,
1163 };
1164
1165 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1166         .port_otg = false,
1167         .has_hostpc = true,
1168         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1169         .op_mode        = TEGRA_USB_OPMODE_HOST,
1170         .u_data.host = {
1171                 .vbus_gpio = -1,
1172                 .hot_plug = false,
1173                 .remote_wakeup_supported = false,
1174                 .power_off_on_suspend = false,
1175         },
1176         .ops = &hsic_plat_ops,
1177 };
1178
1179 static struct tegra_usb_platform_data tegra_udc_pdata = {
1180         .port_otg = true,
1181         .has_hostpc = true,
1182         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1183         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1184         .u_data.dev = {
1185                 .vbus_pmu_irq = 0,
1186                 .vbus_gpio = -1,
1187                 .charging_supported = false,
1188                 .remote_wakeup_supported = false,
1189         },
1190         .u_cfg.utmi = {
1191                 .hssync_start_delay = 0,
1192                 .elastic_limit = 16,
1193                 .idle_wait_delay = 17,
1194                 .term_range_adj = 6,
1195                 .xcvr_setup = 8,
1196                 .xcvr_lsfslew = 2,
1197                 .xcvr_lsrslew = 2,
1198                 .xcvr_setup_offset = 0,
1199                 .xcvr_use_fuses = 1,
1200         },
1201 };
1202
1203 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1204         .port_otg = false,
1205         .has_hostpc = true,
1206         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1207         .op_mode        = TEGRA_USB_OPMODE_HOST,
1208         .u_data.host = {
1209                 .vbus_gpio = -1,
1210                 .hot_plug = false,
1211                 .remote_wakeup_supported = true,
1212                 .power_off_on_suspend = true,
1213         },
1214         .u_cfg.utmi = {
1215                 .hssync_start_delay = 0,
1216                 .elastic_limit = 16,
1217                 .idle_wait_delay = 17,
1218                 .term_range_adj = 6,
1219                 .xcvr_setup = 15,
1220                 .xcvr_lsfslew = 2,
1221                 .xcvr_lsrslew = 2,
1222                 .xcvr_setup_offset = 0,
1223                 .xcvr_use_fuses = 1,
1224         },
1225 };
1226
1227 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1228         .port_otg = false,
1229         .has_hostpc = true,
1230         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1231         .op_mode = TEGRA_USB_OPMODE_HOST,
1232         .u_data.host = {
1233                 .vbus_gpio = -1,
1234                 .vbus_reg = "vdd_vbus_typea_usb",
1235                 .hot_plug = true,
1236                 .remote_wakeup_supported = true,
1237                 .power_off_on_suspend = true,
1238         },
1239         .u_cfg.utmi = {
1240                 .hssync_start_delay = 0,
1241                 .elastic_limit = 16,
1242                 .idle_wait_delay = 17,
1243                 .term_range_adj = 6,
1244                 .xcvr_setup = 8,
1245                 .xcvr_lsfslew = 2,
1246                 .xcvr_lsrslew = 2,
1247                 .xcvr_setup_offset = 0,
1248                 .xcvr_use_fuses = 1,
1249         },
1250 };
1251
1252 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1253         .port_otg = true,
1254         .has_hostpc = true,
1255         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1256         .op_mode = TEGRA_USB_OPMODE_HOST,
1257         .u_data.host = {
1258                 .vbus_gpio = -1,
1259                 .vbus_reg = "vdd_vbus_micro_usb",
1260                 .hot_plug = true,
1261                 .remote_wakeup_supported = true,
1262                 .power_off_on_suspend = true,
1263         },
1264         .u_cfg.utmi = {
1265                 .hssync_start_delay = 0,
1266                 .elastic_limit = 16,
1267                 .idle_wait_delay = 17,
1268                 .term_range_adj = 6,
1269                 .xcvr_setup = 15,
1270                 .xcvr_lsfslew = 2,
1271                 .xcvr_lsrslew = 2,
1272                 .xcvr_setup_offset = 0,
1273                 .xcvr_use_fuses = 1,
1274         },
1275 };
1276
1277 static struct tegra_usb_otg_data tegra_otg_pdata = {
1278         .ehci_device = &tegra_ehci1_device,
1279         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1280 };
1281 #endif
1282
1283 #if defined(CONFIG_USB_SUPPORT)
1284 static void cardhu_usb_init(void)
1285 {
1286         struct board_info bi;
1287
1288         tegra_get_board_info(&bi);
1289
1290         /* OTG should be the first to be registered */
1291         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1292         platform_device_register(&tegra_otg_device);
1293
1294         /* setup the udc platform data */
1295         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1296
1297         if (bi.board_id == BOARD_PM267) {
1298                 hsic_enable_gpio = EN_HSIC_GPIO;
1299                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1300                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1301                 platform_device_register(&tegra_ehci2_device);
1302         } else if (bi.board_id == BOARD_E1256) {
1303                 hsic_enable_gpio = EN_HSIC_GPIO;
1304                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1305                 platform_device_register(&tegra_ehci2_device);
1306         } else if (bi.board_id == BOARD_E1186) {
1307                 tegra_ehci2_device.dev.platform_data =
1308                                                 &tegra_ehci2_hsic_xmm_pdata;
1309                 /* ehci2 registration happens in baseband-xmm-power  */
1310         } else {
1311                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1312                 platform_device_register(&tegra_ehci2_device);
1313         }
1314
1315         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1316         platform_device_register(&tegra_ehci3_device);
1317
1318 }
1319 #else
1320 static void cardhu_usb_init(void) { }
1321 #endif
1322
1323 static struct baseband_power_platform_data tegra_baseband_power_data = {
1324         .baseband_type = BASEBAND_XMM,
1325         .modem = {
1326         .xmm = {
1327                         .bb_rst = XMM_GPIO_BB_RST,
1328                         .bb_on = XMM_GPIO_BB_ON,
1329                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1330                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1331                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1332                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1333                         .hsic_device = &tegra_ehci2_device,
1334                 },
1335         },
1336 };
1337
1338 static struct platform_device tegra_baseband_power_device = {
1339         .name = "baseband_xmm_power",
1340         .id = -1,
1341         .dev = {
1342                 .platform_data = &tegra_baseband_power_data,
1343         },
1344 };
1345
1346 static struct platform_device tegra_baseband_power2_device = {
1347         .name = "baseband_xmm_power2",
1348         .id = -1,
1349         .dev = {
1350                 .platform_data = &tegra_baseband_power_data,
1351         },
1352 };
1353
1354
1355 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1356         .port_status[0] = 1,
1357         .port_status[1] = 1,
1358         .port_status[2] = 1,
1359         .use_dock_detect        = 0,
1360         .gpio           = 0,
1361 };
1362
1363 static void cardhu_pci_init(void)
1364 {
1365         struct board_info board_info;
1366
1367         tegra_get_board_info(&board_info);
1368         if (board_info.board_id == BOARD_E1291) {
1369                 cardhu_pci_platform_data.port_status[0] = 0;
1370                 cardhu_pci_platform_data.port_status[1] = 0;
1371                 cardhu_pci_platform_data.port_status[2] = 1;
1372                 cardhu_pci_platform_data.use_dock_detect = 1;
1373                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1374         }
1375         if ((board_info.board_id == BOARD_E1186) ||
1376                 (board_info.board_id == BOARD_E1187) ||
1377                 (board_info.board_id == BOARD_E1291)) {
1378                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1379                 platform_device_register(&tegra_pci_device);
1380         }
1381 }
1382
1383 static void cardhu_modem_init(void)
1384 {
1385         struct board_info board_info;
1386         int w_disable_gpio, ret;
1387
1388         tegra_get_board_info(&board_info);
1389         switch (board_info.board_id) {
1390         case BOARD_E1291:
1391         case BOARD_E1198:
1392                 if (((board_info.board_id == BOARD_E1291) &&
1393                                 (board_info.fab < BOARD_FAB_A03)) ||
1394                         ((board_info.board_id == BOARD_E1198) &&
1395                                         (board_info.fab < BOARD_FAB_A02))) {
1396                         w_disable_gpio = TEGRA_GPIO_PH5;
1397                 } else {
1398                         w_disable_gpio = TEGRA_GPIO_PDD5;
1399                 }
1400
1401                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1402                 if (ret < 0)
1403                         pr_err("%s: gpio_request failed for gpio %d\n",
1404                                 __func__, w_disable_gpio);
1405                 else
1406                         gpio_direction_input(w_disable_gpio);
1407
1408                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1409                 if (((board_info.board_id == BOARD_E1291) &&
1410                                 (board_info.fab >= BOARD_FAB_A04)) ||
1411                         ((board_info.board_id == BOARD_E1198) &&
1412                                         (board_info.fab >= BOARD_FAB_A02))) {
1413                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1414                         if (ret < 0) {
1415                                 pr_err("%s(): Error in allocating gpio "
1416                                         "TEGRA_GPIO_PH7\n", __func__);
1417                                 break;
1418                         }
1419                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1420                 }
1421                 break;
1422         case BOARD_E1186:
1423                 platform_device_register(&tegra_baseband_power_device);
1424                 platform_device_register(&tegra_baseband_power2_device);
1425                 break;
1426         default:
1427                 break;
1428         }
1429
1430 }
1431
1432 #ifdef CONFIG_SATA_AHCI_TEGRA
1433 static void cardhu_sata_init(void)
1434 {
1435         platform_device_register(&tegra_sata_device);
1436 }
1437 #else
1438 static void cardhu_sata_init(void) { }
1439 #endif
1440
1441 static void __init tegra_cardhu_init(void)
1442 {
1443         tegra_thermal_init(thermal_binds,
1444                                 &skin_data,
1445                                 throttle_list,
1446                                 ARRAY_SIZE(throttle_list));
1447         tegra_clk_init_from_table(cardhu_clk_init_table);
1448         tegra_enable_pinmux();
1449         tegra_smmu_init();
1450         cardhu_pinmux_init();
1451         cardhu_i2c_init();
1452         cardhu_spi_init();
1453         cardhu_usb_init();
1454 #ifdef CONFIG_TEGRA_EDP_LIMITS
1455         cardhu_edp_init();
1456 #endif
1457         cardhu_uart_init();
1458         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1459         tegra_ram_console_debug_init();
1460         tegra_io_dpd_init();
1461         cardhu_sdhci_init();
1462         cardhu_regulator_init();
1463         cardhu_dtv_init();
1464         cardhu_suspend_init();
1465         cardhu_touch_init();
1466         cardhu_modem_init();
1467         cardhu_kbc_init();
1468         cardhu_scroll_init();
1469         cardhu_keys_init();
1470         cardhu_panel_init();
1471         cardhu_pmon_init();
1472         cardhu_sensors_init();
1473         cardhu_setup_bluesleep();
1474         cardhu_sata_init();
1475         //audio_wired_jack_init();
1476         cardhu_pins_state_init();
1477         cardhu_emc_init();
1478         tegra_release_bootloader_fb();
1479         cardhu_pci_init();
1480 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1481         tegra_wdt_recovery_init();
1482 #endif
1483         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1484 }
1485
1486 static void __init tegra_cardhu_reserve(void)
1487 {
1488 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1489         /* support 1920X1200 with 24bpp */
1490         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1491 #else
1492         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1493 #endif
1494         tegra_ram_console_debug_reserve(SZ_1M);
1495 }
1496
1497 static const char *cardhu_dt_board_compat[] = {
1498         "nvidia,cardhu",
1499         NULL
1500 };
1501
1502 MACHINE_START(CARDHU, "cardhu")
1503         .atag_offset    = 0x100,
1504         .soc            = &tegra_soc_desc,
1505         .map_io         = tegra_map_common_io,
1506         .reserve        = tegra_cardhu_reserve,
1507         .init_early     = tegra30_init_early,
1508         .init_irq       = tegra_init_irq,
1509         .handle_irq     = gic_handle_irq,
1510         .timer          = &tegra_timer,
1511         .init_machine   = tegra_cardhu_init,
1512         .restart        = tegra_assert_system_reset,
1513         .dt_compat      = cardhu_dt_board_compat,
1514 MACHINE_END