ARM: tegra: Create IOMMU map at board_init w/ PLATFORM_IOMMUABLE
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/clk.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/iomap.h>
55 #include <mach/io_dpd.h>
56 #include <mach/io.h>
57 #include <mach/i2s.h>
58 #include <mach/tegra_asoc_pdata.h>
59 #include <mach/tegra_wm8903_pdata.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/gpio-tegra.h>
64 #include <mach/tegra_fiq_debugger.h>
65
66 #include <asm/hardware/gic.h>
67 #include <asm/mach-types.h>
68 #include <asm/mach/arch.h>
69
70 #include "board.h"
71 #include "clock.h"
72 #include "board-cardhu.h"
73 #include "board-touch.h"
74 #include "devices.h"
75 #include "gpio-names.h"
76 #include "fuse.h"
77 #include "pm.h"
78 #include "baseband-xmm-power.h"
79 #include "wdt-recovery.h"
80 #include "common.h"
81
82 static struct balanced_throttle throttle_list[] = {
83 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
84         {
85                 .id = BALANCED_THROTTLE_ID_TJ,
86                 .throt_tab_size = 10,
87                 .throt_tab = {
88                         {      0, 1000 },
89                         { 640000, 1000 },
90                         { 640000, 1000 },
91                         { 640000, 1000 },
92                         { 640000, 1000 },
93                         { 640000, 1000 },
94                         { 760000, 1000 },
95                         { 760000, 1050 },
96                         {1000000, 1050 },
97                         {1000000, 1100 },
98                 },
99         },
100 #endif
101 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
102         {
103                 .id = BALANCED_THROTTLE_ID_SKIN,
104                 .throt_tab_size = 6,
105                 .throt_tab = {
106                         { 640000, 1200 },
107                         { 640000, 1200 },
108                         { 760000, 1200 },
109                         { 760000, 1200 },
110                         {1000000, 1200 },
111                         {1000000, 1200 },
112                 },
113         },
114 #endif
115 };
116
117 /* All units are in millicelsius */
118 static struct tegra_thermal_data thermal_data = {
119         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
120         .temp_shutdown = 90000,
121
122 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
123         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
124 #endif
125 #ifdef CONFIG_TEGRA_EDP_LIMITS
126         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
127         .hysteresis_edp = 3000,
128 #endif
129 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
130         .temp_throttle = 85000,
131         .tc1 = 0,
132         .tc2 = 1,
133         .passive_delay = 2000,
134 #endif
135 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
136         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
137         .temp_throttle_skin = 43000,
138         .tc1_skin = 0,
139         .tc2_skin = 1,
140         .passive_delay_skin = 5000,
141
142         .skin_temp_offset = 9793,
143         .skin_period = 1100,
144         .skin_devs_size = 2,
145         .skin_devs = {
146                 {
147                         THERMAL_DEVICE_ID_NCT_EXT,
148                         {
149                                 2, 1, 1, 1,
150                                 1, 1, 1, 1,
151                                 1, 1, 1, 0,
152                                 1, 1, 0, 0,
153                                 0, 0, -1, -7
154                         }
155                 },
156                 {
157                         THERMAL_DEVICE_ID_NCT_INT,
158                         {
159                                 -11, -7, -5, -3,
160                                 -3, -2, -1, 0,
161                                 0, 0, 1, 1,
162                                 1, 2, 2, 3,
163                                 4, 6, 11, 18
164                         }
165                 },
166         },
167 #endif
168 };
169
170 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
171         {
172                 .name           = "bt_rfkill",
173                 .shutdown_gpio  = TEGRA_GPIO_PU0,
174                 .reset_gpio     = TEGRA_GPIO_INVALID,
175                 .type           = RFKILL_TYPE_BLUETOOTH,
176         },
177 };
178
179 static struct platform_device cardhu_bt_rfkill_device = {
180         .name = "rfkill_gpio",
181         .id             = -1,
182         .dev = {
183                 .platform_data = &cardhu_bt_rfkill_pdata,
184         },
185 };
186
187 static struct resource cardhu_bluesleep_resources[] = {
188         [0] = {
189                 .name = "gpio_host_wake",
190                         .start  = TEGRA_GPIO_PU6,
191                         .end    = TEGRA_GPIO_PU6,
192                         .flags  = IORESOURCE_IO,
193         },
194         [1] = {
195                 .name = "gpio_ext_wake",
196                         .start  = TEGRA_GPIO_PU1,
197                         .end    = TEGRA_GPIO_PU1,
198                         .flags  = IORESOURCE_IO,
199         },
200         [2] = {
201                 .name = "host_wake",
202                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
203         },
204 };
205
206 static struct platform_device cardhu_bluesleep_device = {
207         .name           = "bluesleep",
208         .id             = -1,
209         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
210         .resource       = cardhu_bluesleep_resources,
211 };
212
213 static noinline void __init cardhu_setup_bluesleep(void)
214 {
215         cardhu_bluesleep_resources[2].start =
216                 cardhu_bluesleep_resources[2].end =
217                         gpio_to_irq(TEGRA_GPIO_PU6);
218         platform_device_register(&cardhu_bluesleep_device);
219         return;
220 }
221
222 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
223         /* name         parent          rate            enabled */
224         { "pll_m",      NULL,           0,              false},
225         { "hda",        "pll_p",        108000000,      false},
226         { "hda2codec_2x","pll_p",       48000000,       false},
227         { "pwm",        "pll_p",        3187500,        false},
228         { "blink",      "clk_32k",      32768,          true},
229         { "i2s0",       "pll_a_out0",   0,              false},
230         { "i2s1",       "pll_a_out0",   0,              false},
231         { "i2s3",       "pll_a_out0",   0,              false},
232         { "spdif_out",  "pll_a_out0",   0,              false},
233         { "d_audio",    "clk_m",        12000000,       false},
234         { "dam0",       "clk_m",        12000000,       false},
235         { "dam1",       "clk_m",        12000000,       false},
236         { "dam2",       "clk_m",        12000000,       false},
237         { "audio1",     "i2s1_sync",    0,              false},
238         { "audio3",     "i2s3_sync",    0,              false},
239         { "vi_sensor",  "pll_p",        150000000,      false},
240         { "i2c1",       "pll_p",        3200000,        false},
241         { "i2c2",       "pll_p",        3200000,        false},
242         { "i2c3",       "pll_p",        3200000,        false},
243         { "i2c4",       "pll_p",        3200000,        false},
244         { "i2c5",       "pll_p",        3200000,        false},
245         { "vi",         "pll_p",        0,              false},
246         { NULL,         NULL,           0,              0},
247 };
248
249 static struct pn544_i2c_platform_data nfc_pdata = {
250         .irq_gpio = TEGRA_GPIO_PX0,
251         .ven_gpio = TEGRA_GPIO_PP3,
252         .firm_gpio = TEGRA_GPIO_PO7,
253         };
254
255 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
256         {
257                 I2C_BOARD_INFO("pn544", 0x28),
258                 .platform_data = &nfc_pdata,
259         },
260 };
261 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
262         .adapter_nr     = 0,
263         .bus_count      = 1,
264         .bus_clk_rate   = { 100000, 0 },
265         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
266         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
267         .arb_recovery = arb_lost_recovery,
268 };
269
270 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
271         .adapter_nr     = 1,
272         .bus_count      = 1,
273         .bus_clk_rate   = { 400000, 0 },
274         .is_clkon_always = true,
275         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
276         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
277         .arb_recovery = arb_lost_recovery,
278 };
279
280 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
281         .adapter_nr     = 2,
282         .bus_count      = 1,
283         .bus_clk_rate   = { 100000, 0 },
284         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
285         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
286         .arb_recovery = arb_lost_recovery,
287 };
288
289 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
290         .adapter_nr     = 3,
291         .bus_count      = 1,
292         .bus_clk_rate   = { 10000, 0 },
293         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
294         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
295         .arb_recovery = arb_lost_recovery,
296 };
297
298 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
299         .adapter_nr     = 4,
300         .bus_count      = 1,
301         .bus_clk_rate   = { 400000, 0 },
302         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
303         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
304         .arb_recovery = arb_lost_recovery,
305 };
306
307
308 #if 0
309 struct tegra_wired_jack_conf audio_wr_jack_conf = {
310         .hp_det_n = TEGRA_GPIO_PW2,
311         .en_mic_ext = TEGRA_GPIO_PX1,
312         .en_mic_int = TEGRA_GPIO_PX0,
313 };
314 #endif
315
316 static struct wm8903_platform_data cardhu_wm8903_pdata = {
317         .irq_active_low = 0,
318         .micdet_cfg = 0,
319         .micdet_delay = 100,
320         .gpio_base = CARDHU_GPIO_WM8903(0),
321         .gpio_cfg = {
322                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
323                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
324                         WM8903_GP2_DIR,
325                 WM8903_GPIO_CONFIG_ZERO,
326                 0,
327                 0,
328         },
329 };
330
331 /* Equalizer filter coefs generated from the MAXIM MAX98095
332  * evkit software tool */
333 static struct max98095_eq_cfg max98095_eq_cfg[] = {
334         {
335                 .name = "FLAT",
336                 .rate = 44100,
337                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
338                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
339                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
340                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
341                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
342         },
343         {
344                 .name = "LOWPASS1K",
345                 .rate = 44100,
346                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
347                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
348                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
349                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
350                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
351         },
352         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
353                 .name = "HIBOOST",
354                 .rate = 44100,
355                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
356                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
357                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
358                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
359                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
360         },
361         { /* BASS=12dB, TREBLE=+12dB */
362                 .name = "LOUD12DB",
363                 .rate = 44100,
364                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
365                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
366                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
367                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
368                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
369         },
370         {
371                 .name = "FLAT",
372                 .rate = 16000,
373                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
374                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
375                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
376                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
377                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
378         },
379         {
380                 .name = "LOWPASS1K",
381                 .rate = 16000,
382                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
383                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
384                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
385                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
386                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
387         },
388         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
389                 .name = "HIBOOST",
390                 .rate = 16000,
391                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
392                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
393                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
394                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
395                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
396         },
397         { /* BASS=12dB, TREBLE=+12dB */
398                 .name = "LOUD12DB",
399                 .rate = 16000,
400                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
401                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
402                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
403                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
404                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
405         },
406 };
407
408 static struct max98095_pdata cardhu_max98095_pdata = {
409         /* equalizer configuration */
410         .eq_cfg = max98095_eq_cfg,
411         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
412
413         /* Biquad filter response configuration */
414         .bq_cfg = NULL,
415         .bq_cfgcnt = 0,
416
417         /* microphone configuration */
418         .digmic_left_mode = 1,
419         .digmic_right_mode = 1,
420 };
421
422 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
423         I2C_BOARD_INFO("wm8903", 0x1a),
424         .platform_data = &cardhu_wm8903_pdata,
425 };
426
427 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
428         I2C_BOARD_INFO("aic3262-codec", 0x18),
429 };
430
431 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
432         I2C_BOARD_INFO("max98095", 0x10),
433         .platform_data = &cardhu_max98095_pdata,
434 };
435
436 static void cardhu_i2c_init(void)
437 {
438         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
439         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
440         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
441         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
442         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
443
444         platform_device_register(&tegra_i2c_device5);
445         platform_device_register(&tegra_i2c_device4);
446         platform_device_register(&tegra_i2c_device3);
447         platform_device_register(&tegra_i2c_device2);
448         platform_device_register(&tegra_i2c_device1);
449
450         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
451                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
452         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
453         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
454         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
455
456         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
457         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
458 }
459
460 static struct platform_device *cardhu_uart_devices[] __initdata = {
461         &tegra_uarta_device,
462         &tegra_uartb_device,
463         &tegra_uartc_device,
464         &tegra_uartd_device,
465         &tegra_uarte_device,
466 };
467 static struct uart_clk_parent uart_parent_clk[] = {
468         [0] = {.name = "clk_m"},
469         [1] = {.name = "pll_p"},
470 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
471         [2] = {.name = "pll_m"},
472 #endif
473 };
474
475 static struct tegra_uart_platform_data cardhu_uart_pdata;
476 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
477
478 static void __init uart_debug_init(void)
479 {
480         struct board_info board_info;
481         int debug_port_id;
482
483         tegra_get_board_info(&board_info);
484
485         debug_port_id = get_tegra_uart_debug_port_id();
486         if (debug_port_id < 0) {
487                 debug_port_id = 0;
488                         /* UARTB is debug port
489                          *       for SLT - E1186/E1187/PM269
490                          *       for E1256/E1257
491                          */
492                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
493                         ((board_info.board_id == BOARD_E1186) ||
494                         (board_info.board_id == BOARD_E1187) ||
495                         (board_info.board_id == BOARD_PM269))) ||
496                         (board_info.board_id == BOARD_E1256) ||
497                         (board_info.board_id == BOARD_E1257))
498                                 debug_port_id = 1;
499         }
500
501 #ifdef CONFIG_TEGRA_IRDA
502         if ((board_info.board_id == BOARD_E1186) ||
503                 (board_info.board_id == BOARD_E1198)) {
504                 if (debug_port_id == 1) {
505                         cardhu_irda_pdata.is_irda = false;
506                         pr_err("UARTB is not available for IrDA\n");
507                 }
508         }
509 #endif
510
511         switch (debug_port_id) {
512         case 0:
513                 /* UARTA is the debug port. */
514                 pr_info("Selecting UARTA as the debug console\n");
515                 cardhu_uart_devices[0] = &debug_uarta_device;
516                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
517                 debug_uart_port_base = ((struct plat_serial8250_port *)(
518                         debug_uarta_device.dev.platform_data))->mapbase;
519                 break;
520
521         case 1:
522                 /* UARTB is the debug port. */
523                 pr_info("Selecting UARTB as the debug console\n");
524                 cardhu_uart_devices[1] = &debug_uartb_device;
525                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
526                 debug_uart_port_base = ((struct plat_serial8250_port *)(
527                         debug_uartb_device.dev.platform_data))->mapbase;
528                 break;
529
530         case 2:
531                 /* UARTC is the debug port. */
532                 pr_info("Selecting UARTC as the debug console\n");
533                 cardhu_uart_devices[2] = &debug_uartc_device;
534                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
535                 debug_uart_port_base = ((struct plat_serial8250_port *)(
536                         debug_uartc_device.dev.platform_data))->mapbase;
537                 break;
538
539         case 3:
540                 /* UARTD is the debug port. */
541                 pr_info("Selecting UARTD as the debug console\n");
542                 cardhu_uart_devices[3] = &debug_uartd_device;
543                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
544                 debug_uart_port_base = ((struct plat_serial8250_port *)(
545                         debug_uartd_device.dev.platform_data))->mapbase;
546                 break;
547
548         case 4:
549                 /* UARTE is the debug port. */
550                 pr_info("Selecting UARTE as the debug console\n");
551                 cardhu_uart_devices[4] = &debug_uarte_device;
552                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
553                 debug_uart_port_base = ((struct plat_serial8250_port *)(
554                         debug_uarte_device.dev.platform_data))->mapbase;
555                 break;
556
557         default:
558                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
559                 cardhu_uart_devices[0] = &debug_uarta_device;
560                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
561                 debug_uart_port_base = ((struct plat_serial8250_port *)(
562                         debug_uarta_device.dev.platform_data))->mapbase;
563                 break;
564         }
565         return;
566 }
567
568 static void __init cardhu_uart_init(void)
569 {
570         struct clk *c;
571         int i;
572         struct board_info board_info;
573
574         tegra_get_board_info(&board_info);
575
576         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
577                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
578                 if (IS_ERR_OR_NULL(c)) {
579                         pr_err("Not able to get the clock for %s\n",
580                                                 uart_parent_clk[i].name);
581                         continue;
582                 }
583                 uart_parent_clk[i].parent_clk = c;
584                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
585         }
586         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
587         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
588         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
589         cardhu_loopback_uart_pdata.parent_clk_count =
590                                                 ARRAY_SIZE(uart_parent_clk);
591         cardhu_loopback_uart_pdata.is_loopback = true;
592         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
593         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
594         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
595         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
596         /* UARTE is used for loopback test purpose */
597         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
598
599         /* Register low speed only if it is selected */
600         if (!is_tegra_debug_uartport_hs()) {
601                 uart_debug_init();
602                 /* Clock enable for the debug channel */
603                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
604                         pr_info("The debug console clock name is %s\n",
605                                                 debug_uart_clk->name);
606                         c = tegra_get_clock_by_name("pll_p");
607                         if (IS_ERR_OR_NULL(c))
608                                 pr_err("Not getting the parent clock pll_p\n");
609                         else
610                                 clk_set_parent(debug_uart_clk, c);
611
612                         clk_enable(debug_uart_clk);
613                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
614                 } else {
615                         pr_err("Not getting the clock %s for debug console\n",
616                                         debug_uart_clk->name);
617                 }
618         }
619
620 #ifdef CONFIG_TEGRA_IRDA
621         if (((board_info.board_id == BOARD_E1186) ||
622                 (board_info.board_id == BOARD_E1198)) &&
623                         cardhu_irda_pdata.is_irda) {
624                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
625                 cardhu_irda_pdata.parent_clk_count =
626                                         ARRAY_SIZE(uart_parent_clk);
627
628                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
629         }
630 #endif
631
632         platform_add_devices(cardhu_uart_devices,
633                                 ARRAY_SIZE(cardhu_uart_devices));
634 }
635
636 static struct platform_device tegra_camera = {
637         .name = "tegra_camera",
638         .id = -1,
639 };
640
641 static struct platform_device *cardhu_spi_devices[] __initdata = {
642         &tegra_spi_device4,
643 };
644
645 static struct platform_device *touch_spi_device[] __initdata = {
646         &tegra_spi_device1,
647 };
648
649 struct spi_clk_parent spi_parent_clk[] = {
650         [0] = {.name = "pll_p"},
651 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
652         [1] = {.name = "pll_m"},
653         [2] = {.name = "clk_m"},
654 #else
655         [1] = {.name = "clk_m"},
656 #endif
657 };
658
659 static struct tegra_spi_platform_data cardhu_spi_pdata = {
660         .is_dma_based           = true,
661         .max_dma_buffer         = (16 * 1024),
662         .is_clkon_always        = false,
663         .max_rate               = 100000000,
664 };
665
666 static void __init cardhu_spi_init(void)
667 {
668         int i;
669         struct clk *c;
670         struct board_info board_info, display_board_info;
671
672         tegra_get_board_info(&board_info);
673         tegra_get_display_board_info(&display_board_info);
674
675         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
676                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
677                 if (IS_ERR_OR_NULL(c)) {
678                         pr_err("Not able to get the clock for %s\n",
679                                                 spi_parent_clk[i].name);
680                         continue;
681                 }
682                 spi_parent_clk[i].parent_clk = c;
683                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
684         }
685         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
686         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
687         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
688         platform_add_devices(cardhu_spi_devices,
689                                 ARRAY_SIZE(cardhu_spi_devices));
690
691         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
692                 platform_add_devices(touch_spi_device,
693                                 ARRAY_SIZE(touch_spi_device));
694         }
695         if (board_info.board_id == BOARD_E1198) {
696                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
697                 platform_device_register(&tegra_spi_device2);
698                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
699                 platform_device_register(&tegra_spi_slave_device1);
700         }
701 }
702
703 static void __init cardhu_dtv_init(void)
704 {
705         struct board_info board_info;
706
707         tegra_get_board_info(&board_info);
708
709         if (board_info.board_id == BOARD_E1186)
710                 platform_device_register(&tegra_dtv_device);
711 }
712
713 static struct resource tegra_rtc_resources[] = {
714         [0] = {
715                 .start = TEGRA_RTC_BASE,
716                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
717                 .flags = IORESOURCE_MEM,
718         },
719         [1] = {
720                 .start = INT_RTC,
721                 .end = INT_RTC,
722                 .flags = IORESOURCE_IRQ,
723         },
724 };
725
726 static struct platform_device tegra_rtc_device = {
727         .name = "tegra_rtc",
728         .id   = -1,
729         .resource = tegra_rtc_resources,
730         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
731 };
732
733 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
734         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
735         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
736         .gpio_hp_mute           = -1,
737         .gpio_int_mic_en        = -1,
738         .gpio_ext_mic_en        = -1,
739 };
740
741 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
742         .gpio_spkr_en           = -1,
743         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
744         .gpio_hp_mute           = -1,
745         .gpio_int_mic_en        = -1,
746         .gpio_ext_mic_en        = -1,
747 };
748
749 static struct platform_device cardhu_audio_wm8903_device = {
750         .name   = "tegra-snd-wm8903",
751         .id     = 0,
752         .dev    = {
753                 .platform_data = &cardhu_audio_wm8903_pdata,
754         },
755 };
756
757 static struct platform_device cardhu_audio_max98095_device = {
758         .name   = "tegra-snd-max98095",
759         .id     = 0,
760         .dev    = {
761                 .platform_data = &cardhu_audio_max98095_pdata,
762         },
763 };
764
765 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
766         .gpio_spkr_en           = -1,
767         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
768         .gpio_hp_mute           = -1,
769         .gpio_int_mic_en        = -1,
770         .gpio_ext_mic_en        = -1,
771         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
772         .audio_port_id          = {
773                 [HIFI_CODEC] = 0,
774                 [BASEBAND] = -1,
775                 [BT_SCO] = 3,
776         },
777         .baseband_param         = {
778                 .rate = -1,
779                 .channels = -1,
780         },
781 };
782
783 static struct platform_device cardhu_audio_aic326x_device = {
784         .name   = "tegra-snd-aic326x",
785         .id     = 0,
786         .dev    = {
787                 .platform_data  = &cardhu_audio_aic326x_pdata,
788         },
789 };
790
791 static struct platform_device *cardhu_devices[] __initdata = {
792         &tegra_pmu_device,
793         &tegra_rtc_device,
794         &tegra_udc_device,
795         &tegra_wdt0_device,
796         &tegra_wdt1_device,
797         &tegra_wdt2_device,
798 #if defined(CONFIG_TEGRA_AVP)
799         &tegra_avp_device,
800 #endif
801         &tegra_camera,
802 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
803         &tegra_se_device,
804 #endif
805         &tegra_ahub_device,
806         &tegra_dam_device0,
807         &tegra_dam_device1,
808         &tegra_dam_device2,
809         &tegra_i2s_device0,
810         &tegra_i2s_device1,
811         &tegra_i2s_device3,
812         &tegra_spdif_device,
813         &spdif_dit_device,
814         &bluetooth_dit_device,
815         &baseband_dit_device,
816         &cardhu_bt_rfkill_device,
817         &tegra_pcm_device,
818         &cardhu_audio_wm8903_device,
819         &cardhu_audio_max98095_device,
820         &cardhu_audio_aic326x_device,
821         &tegra_hda_device,
822         &tegra_cec_device,
823 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
824         &tegra_aes_device,
825 #endif
826 };
827
828 #define E1506_MXT_CONFIG_CRC 0x62F903
829 static const u8 e1506_config[] = {
830         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
832         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
833         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
834         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
835         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
836         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
837         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
838         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
839         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
843         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
844         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
845         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
846         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
847         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
851         0x00
852 };
853
854 #define MXT_CONFIG_CRC  0xD62DE8
855 static const u8 config[] = {
856         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
857         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
858         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
859         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
860         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
861         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
862         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
863         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
867         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
868         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
869         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
870         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
871         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
876 };
877
878 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
879 static const u8 config_sku2000[] = {
880         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
881         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
882         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
883         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
884         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
885         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
886         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
887         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
888         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
889         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
890         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
891         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
892         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
893         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
894         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
895         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
896         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
897         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
898         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
899         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
900 };
901
902 static struct mxt_platform_data atmel_mxt_info = {
903         .x_line         = 27,
904         .y_line         = 42,
905         .x_size         = 768,
906         .y_size         = 1366,
907         .blen           = 0x20,
908         .threshold      = 0x3C,
909         .voltage        = 3300000,              /* 3.3V */
910         .orient         = 5,
911         .config         = config,
912         .config_length  = 157,
913         .config_crc     = MXT_CONFIG_CRC,
914         .irqflags       = IRQF_TRIGGER_FALLING,
915 /*      .read_chg       = &read_chg, */
916         .read_chg       = NULL,
917 };
918
919 static struct mxt_platform_data e1506_atmel_mxt_info = {
920         .x_line         = 19,
921         .y_line         = 11,
922         .x_size         = 960,
923         .y_size         = 540,
924         .blen           = 0x10,
925         .threshold      = 0x32,
926         .voltage        = 3300000,              /* 3.3V */
927         .orient         = 3,
928         .config         = e1506_config,
929         .config_length  = 168,
930         .config_crc     = E1506_MXT_CONFIG_CRC,
931         .irqflags       = IRQF_TRIGGER_FALLING,
932 /*      .read_chg       = &read_chg, */
933         .read_chg       = NULL,
934 };
935
936 static struct i2c_board_info __initdata atmel_i2c_info[] = {
937         {
938                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
939                 .platform_data = &atmel_mxt_info,
940         }
941 };
942
943 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
944         {
945                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
946                 .platform_data = &e1506_atmel_mxt_info,
947         }
948 };
949
950 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
951         /* name         parent          rate            enabled */
952         { "sbc1",       "pll_p",        52000000,       true},
953         { NULL,         NULL,           0,              0},
954 };
955
956 static int __init cardhu_touch_init(void)
957 {
958         struct board_info BoardInfo, DisplayBoardInfo;
959
960         tegra_get_board_info(&BoardInfo);
961         tegra_get_display_board_info(&DisplayBoardInfo);
962         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
963                 tegra_clk_init_from_table(spi_clk_init_table);
964
965                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
966         } else {
967                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
968                 gpio_direction_input(TEGRA_GPIO_PH4);
969
970                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
971                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
972                 msleep(1);
973                 gpio_set_value(TEGRA_GPIO_PH6, 1);
974                 msleep(100);
975
976                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
977                         atmel_mxt_info.config = config_sku2000;
978                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
979                 }
980
981                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
982                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
983                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
984                 } else {
985                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
986                         i2c_register_board_info(1, atmel_i2c_info, 1);
987                 }
988         }
989
990         return 0;
991 }
992
993 #if defined(CONFIG_USB_SUPPORT)
994
995 static void cardu_usb_hsic_postsupend(void)
996 {
997 #ifdef CONFIG_TEGRA_BB_XMM_POWER
998         baseband_xmm_set_power_status(BBXMM_PS_L2);
999 #endif
1000 }
1001
1002 static void cardu_usb_hsic_preresume(void)
1003 {
1004 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1005         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1006 #endif
1007 }
1008
1009 static void cardu_usb_hsic_phy_ready(void)
1010 {
1011 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1012         baseband_xmm_set_power_status(BBXMM_PS_L0);
1013 #endif
1014 }
1015
1016 static void cardu_usb_hsic_phy_off(void)
1017 {
1018 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1019         baseband_xmm_set_power_status(BBXMM_PS_L3);
1020 #endif
1021 }
1022
1023 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1024         .post_suspend = cardu_usb_hsic_postsupend,
1025         .pre_resume = cardu_usb_hsic_preresume,
1026         .port_power = cardu_usb_hsic_phy_ready,
1027         .post_phy_off = cardu_usb_hsic_phy_off,
1028 };
1029
1030 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1031         .port_otg = false,
1032         .has_hostpc = true,
1033         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1034         .op_mode        = TEGRA_USB_OPMODE_HOST,
1035         .u_data.host = {
1036                 .vbus_gpio = -1,
1037                 .hot_plug = false,
1038                 .remote_wakeup_supported = false,
1039                 .power_off_on_suspend = false,
1040         },
1041         .ops = &hsic_xmm_plat_ops,
1042 };
1043 #endif
1044
1045 static int hsic_enable_gpio = -1;
1046 static int hsic_reset_gpio = -1;
1047
1048 void hsic_platform_open(void)
1049 {
1050         int reset_gpio = 0, enable_gpio = 0;
1051
1052         if (hsic_enable_gpio != -1)
1053                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1054         if (hsic_reset_gpio != -1)
1055                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1056         /* hsic enable signal deasserted, hsic reset asserted */
1057         if (!enable_gpio)
1058                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1059         if (!reset_gpio)
1060                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1061         /* keep hsic reset asserted for 1 ms */
1062         udelay(1000);
1063         /* enable (power on) hsic */
1064         if (!enable_gpio)
1065                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1066         udelay(1000);
1067         /* deassert reset */
1068         if (!reset_gpio)
1069                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1070
1071 }
1072
1073 void hsic_platform_close(void)
1074 {
1075         if (hsic_enable_gpio != -1) {
1076                 gpio_set_value(hsic_enable_gpio, 0);
1077                 gpio_free(hsic_enable_gpio);
1078         }
1079         if (hsic_reset_gpio != -1) {
1080                 gpio_set_value(hsic_reset_gpio, 0);
1081                 gpio_free(hsic_reset_gpio);
1082         }
1083 }
1084
1085 void hsic_power_on(void)
1086 {
1087         if (hsic_enable_gpio != -1) {
1088                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1089                 udelay(1000);
1090         }
1091 }
1092
1093 void hsic_power_off(void)
1094 {
1095         if (hsic_enable_gpio != -1) {
1096                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1097                 udelay(1000);
1098         }
1099 }
1100
1101 #if defined(CONFIG_USB_SUPPORT)
1102 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1103         .open = hsic_platform_open,
1104         .close = hsic_platform_close,
1105         .pre_phy_on = hsic_power_on,
1106         .post_phy_off = hsic_power_off,
1107 };
1108
1109 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1110         .port_otg = false,
1111         .has_hostpc = true,
1112         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1113         .op_mode        = TEGRA_USB_OPMODE_HOST,
1114         .u_data.host = {
1115                 .vbus_gpio = -1,
1116                 .hot_plug = false,
1117                 .remote_wakeup_supported = false,
1118                 .power_off_on_suspend = false,
1119         },
1120         .ops = &hsic_plat_ops,
1121 };
1122
1123 static struct tegra_usb_platform_data tegra_udc_pdata = {
1124         .port_otg = true,
1125         .has_hostpc = true,
1126         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1127         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1128         .u_data.dev = {
1129                 .vbus_pmu_irq = 0,
1130                 .vbus_gpio = -1,
1131                 .charging_supported = false,
1132                 .remote_wakeup_supported = false,
1133         },
1134         .u_cfg.utmi = {
1135                 .hssync_start_delay = 0,
1136                 .elastic_limit = 16,
1137                 .idle_wait_delay = 17,
1138                 .term_range_adj = 6,
1139                 .xcvr_setup = 8,
1140                 .xcvr_lsfslew = 2,
1141                 .xcvr_lsrslew = 2,
1142                 .xcvr_setup_offset = 0,
1143                 .xcvr_use_fuses = 1,
1144         },
1145 };
1146
1147 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1148         .port_otg = false,
1149         .has_hostpc = true,
1150         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1151         .op_mode        = TEGRA_USB_OPMODE_HOST,
1152         .u_data.host = {
1153                 .vbus_gpio = -1,
1154                 .hot_plug = false,
1155                 .remote_wakeup_supported = true,
1156                 .power_off_on_suspend = true,
1157         },
1158         .u_cfg.utmi = {
1159                 .hssync_start_delay = 0,
1160                 .elastic_limit = 16,
1161                 .idle_wait_delay = 17,
1162                 .term_range_adj = 6,
1163                 .xcvr_setup = 15,
1164                 .xcvr_lsfslew = 2,
1165                 .xcvr_lsrslew = 2,
1166                 .xcvr_setup_offset = 0,
1167                 .xcvr_use_fuses = 1,
1168         },
1169 };
1170
1171 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1172         .port_otg = false,
1173         .has_hostpc = true,
1174         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1175         .op_mode = TEGRA_USB_OPMODE_HOST,
1176         .u_data.host = {
1177                 .vbus_gpio = -1,
1178                 .vbus_reg = "vdd_vbus_typea_usb",
1179                 .hot_plug = true,
1180                 .remote_wakeup_supported = true,
1181                 .power_off_on_suspend = true,
1182         },
1183         .u_cfg.utmi = {
1184                 .hssync_start_delay = 0,
1185                 .elastic_limit = 16,
1186                 .idle_wait_delay = 17,
1187                 .term_range_adj = 6,
1188                 .xcvr_setup = 8,
1189                 .xcvr_lsfslew = 2,
1190                 .xcvr_lsrslew = 2,
1191                 .xcvr_setup_offset = 0,
1192                 .xcvr_use_fuses = 1,
1193         },
1194 };
1195
1196 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1197         .port_otg = true,
1198         .has_hostpc = true,
1199         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1200         .op_mode = TEGRA_USB_OPMODE_HOST,
1201         .u_data.host = {
1202                 .vbus_gpio = -1,
1203                 .vbus_reg = "vdd_vbus_micro_usb",
1204                 .hot_plug = true,
1205                 .remote_wakeup_supported = true,
1206                 .power_off_on_suspend = true,
1207         },
1208         .u_cfg.utmi = {
1209                 .hssync_start_delay = 0,
1210                 .elastic_limit = 16,
1211                 .idle_wait_delay = 17,
1212                 .term_range_adj = 6,
1213                 .xcvr_setup = 15,
1214                 .xcvr_lsfslew = 2,
1215                 .xcvr_lsrslew = 2,
1216                 .xcvr_setup_offset = 0,
1217                 .xcvr_use_fuses = 1,
1218         },
1219 };
1220
1221 static struct tegra_usb_otg_data tegra_otg_pdata = {
1222         .ehci_device = &tegra_ehci1_device,
1223         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1224 };
1225 #endif
1226
1227 #if defined(CONFIG_USB_SUPPORT)
1228 static void cardhu_usb_init(void)
1229 {
1230         struct board_info bi;
1231
1232         tegra_get_board_info(&bi);
1233
1234         /* OTG should be the first to be registered */
1235         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1236         platform_device_register(&tegra_otg_device);
1237
1238         /* setup the udc platform data */
1239         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1240
1241         if (bi.board_id == BOARD_PM267) {
1242                 hsic_enable_gpio = EN_HSIC_GPIO;
1243                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1244                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1245                 platform_device_register(&tegra_ehci2_device);
1246         } else if (bi.board_id == BOARD_E1256) {
1247                 hsic_enable_gpio = EN_HSIC_GPIO;
1248                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1249                 platform_device_register(&tegra_ehci2_device);
1250         } else if (bi.board_id == BOARD_E1186) {
1251                 tegra_ehci2_device.dev.platform_data =
1252                                                 &tegra_ehci2_hsic_xmm_pdata;
1253                 /* ehci2 registration happens in baseband-xmm-power  */
1254         } else {
1255                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1256                 platform_device_register(&tegra_ehci2_device);
1257         }
1258
1259         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1260         platform_device_register(&tegra_ehci3_device);
1261
1262 }
1263 #else
1264 static void cardhu_usb_init(void) { }
1265 #endif
1266
1267 static struct baseband_power_platform_data tegra_baseband_power_data = {
1268         .baseband_type = BASEBAND_XMM,
1269         .modem = {
1270         .xmm = {
1271                         .bb_rst = XMM_GPIO_BB_RST,
1272                         .bb_on = XMM_GPIO_BB_ON,
1273                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1274                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1275                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1276                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1277                         .hsic_device = &tegra_ehci2_device,
1278                 },
1279         },
1280 };
1281
1282 static struct platform_device tegra_baseband_power_device = {
1283         .name = "baseband_xmm_power",
1284         .id = -1,
1285         .dev = {
1286                 .platform_data = &tegra_baseband_power_data,
1287         },
1288 };
1289
1290 static struct platform_device tegra_baseband_power2_device = {
1291         .name = "baseband_xmm_power2",
1292         .id = -1,
1293         .dev = {
1294                 .platform_data = &tegra_baseband_power_data,
1295         },
1296 };
1297
1298
1299 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1300         .port_status[0] = 1,
1301         .port_status[1] = 1,
1302         .port_status[2] = 1,
1303         .use_dock_detect        = 0,
1304         .gpio           = 0,
1305 };
1306
1307 static void cardhu_pci_init(void)
1308 {
1309         struct board_info board_info;
1310
1311         tegra_get_board_info(&board_info);
1312         if (board_info.board_id == BOARD_E1291) {
1313                 cardhu_pci_platform_data.port_status[0] = 0;
1314                 cardhu_pci_platform_data.port_status[1] = 0;
1315                 cardhu_pci_platform_data.port_status[2] = 1;
1316                 cardhu_pci_platform_data.use_dock_detect = 1;
1317                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1318         }
1319         if ((board_info.board_id == BOARD_E1186) ||
1320                 (board_info.board_id == BOARD_E1187) ||
1321                 (board_info.board_id == BOARD_E1291)) {
1322                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1323                 platform_device_register(&tegra_pci_device);
1324         }
1325 }
1326
1327 static void cardhu_modem_init(void)
1328 {
1329         struct board_info board_info;
1330         int w_disable_gpio, ret;
1331
1332         tegra_get_board_info(&board_info);
1333         switch (board_info.board_id) {
1334         case BOARD_E1291:
1335         case BOARD_E1198:
1336                 if (((board_info.board_id == BOARD_E1291) &&
1337                                 (board_info.fab < BOARD_FAB_A03)) ||
1338                         ((board_info.board_id == BOARD_E1198) &&
1339                                         (board_info.fab < BOARD_FAB_A02))) {
1340                         w_disable_gpio = TEGRA_GPIO_PH5;
1341                 } else {
1342                         w_disable_gpio = TEGRA_GPIO_PDD5;
1343                 }
1344
1345                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1346                 if (ret < 0)
1347                         pr_err("%s: gpio_request failed for gpio %d\n",
1348                                 __func__, w_disable_gpio);
1349                 else
1350                         gpio_direction_input(w_disable_gpio);
1351
1352                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1353                 if (((board_info.board_id == BOARD_E1291) &&
1354                                 (board_info.fab >= BOARD_FAB_A04)) ||
1355                         ((board_info.board_id == BOARD_E1198) &&
1356                                         (board_info.fab >= BOARD_FAB_A02))) {
1357                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1358                         if (ret < 0) {
1359                                 pr_err("%s(): Error in allocating gpio "
1360                                         "TEGRA_GPIO_PH7\n", __func__);
1361                                 break;
1362                         }
1363                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1364                 }
1365                 break;
1366         case BOARD_E1186:
1367                 platform_device_register(&tegra_baseband_power_device);
1368                 platform_device_register(&tegra_baseband_power2_device);
1369                 break;
1370         default:
1371                 break;
1372         }
1373
1374 }
1375
1376 #ifdef CONFIG_SATA_AHCI_TEGRA
1377 static void cardhu_sata_init(void)
1378 {
1379         platform_device_register(&tegra_sata_device);
1380 }
1381 #else
1382 static void cardhu_sata_init(void) { }
1383 #endif
1384
1385 static void __init tegra_cardhu_init(void)
1386 {
1387         tegra_thermal_init(&thermal_data,
1388                                 throttle_list,
1389                                 ARRAY_SIZE(throttle_list));
1390         tegra_clk_init_from_table(cardhu_clk_init_table);
1391         tegra_enable_pinmux();
1392         tegra_smmu_init();
1393         cardhu_pinmux_init();
1394         cardhu_i2c_init();
1395         cardhu_spi_init();
1396         cardhu_usb_init();
1397 #ifdef CONFIG_TEGRA_EDP_LIMITS
1398         cardhu_edp_init();
1399 #endif
1400         cardhu_uart_init();
1401         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1402         tegra_ram_console_debug_init();
1403         tegra_io_dpd_init();
1404         cardhu_sdhci_init();
1405         cardhu_regulator_init();
1406         cardhu_dtv_init();
1407         cardhu_suspend_init();
1408         cardhu_touch_init();
1409         cardhu_modem_init();
1410         cardhu_kbc_init();
1411         cardhu_scroll_init();
1412         cardhu_keys_init();
1413         cardhu_panel_init();
1414         cardhu_pmon_init();
1415         cardhu_sensors_init();
1416         cardhu_setup_bluesleep();
1417         cardhu_sata_init();
1418         //audio_wired_jack_init();
1419         cardhu_pins_state_init();
1420         cardhu_emc_init();
1421         tegra_release_bootloader_fb();
1422         cardhu_pci_init();
1423 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1424         tegra_wdt_recovery_init();
1425 #endif
1426         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1427 }
1428
1429 static void __init tegra_cardhu_reserve(void)
1430 {
1431 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1432         /* support 1920X1200 with 24bpp */
1433         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1434 #else
1435         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1436 #endif
1437         tegra_ram_console_debug_reserve(SZ_1M);
1438 }
1439
1440 static const char *cardhu_dt_board_compat[] = {
1441         "nvidia,cardhu",
1442         NULL
1443 };
1444
1445 MACHINE_START(CARDHU, "cardhu")
1446         .atag_offset    = 0x100,
1447         .soc            = &tegra_soc_desc,
1448         .map_io         = tegra_map_common_io,
1449         .reserve        = tegra_cardhu_reserve,
1450         .init_early     = tegra30_init_early,
1451         .init_irq       = tegra_init_irq,
1452         .handle_irq     = gic_handle_irq,
1453         .timer          = &tegra_timer,
1454         .init_machine   = tegra_cardhu_init,
1455         .restart        = tegra_assert_system_reset,
1456         .dt_compat      = cardhu_dt_board_compat,
1457 MACHINE_END