arm: tegra: sd: enable sd dpd
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/clk.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/iomap.h>
55 #include <mach/io_dpd.h>
56 #include <mach/io.h>
57 #include <mach/i2s.h>
58 #include <mach/tegra_asoc_pdata.h>
59 #include <mach/tegra_wm8903_pdata.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/gpio-tegra.h>
64 #include <mach/tegra_fiq_debugger.h>
65
66 #include <asm/hardware/gic.h>
67 #include <asm/mach-types.h>
68 #include <asm/mach/arch.h>
69
70 #include "board.h"
71 #include "clock.h"
72 #include "board-cardhu.h"
73 #include "board-touch.h"
74 #include "devices.h"
75 #include "gpio-names.h"
76 #include "fuse.h"
77 #include "pm.h"
78 #include "baseband-xmm-power.h"
79 #include "wdt-recovery.h"
80 #include "common.h"
81
82 static struct balanced_throttle throttle_list[] = {
83 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
84         {
85                 .id = BALANCED_THROTTLE_ID_TJ,
86                 .throt_tab_size = 10,
87                 .throt_tab = {
88                         {      0, 1000 },
89                         { 640000, 1000 },
90                         { 640000, 1000 },
91                         { 640000, 1000 },
92                         { 640000, 1000 },
93                         { 640000, 1000 },
94                         { 760000, 1000 },
95                         { 760000, 1050 },
96                         {1000000, 1050 },
97                         {1000000, 1100 },
98                 },
99         },
100 #endif
101 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
102         {
103                 .id = BALANCED_THROTTLE_ID_SKIN,
104                 .throt_tab_size = 6,
105                 .throt_tab = {
106                         { 640000, 1200 },
107                         { 640000, 1200 },
108                         { 760000, 1200 },
109                         { 760000, 1200 },
110                         {1000000, 1200 },
111                         {1000000, 1200 },
112                 },
113         },
114 #endif
115 };
116
117 /* All units are in millicelsius */
118 static struct tegra_thermal_data thermal_data = {
119         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
120         .temp_shutdown = 90000,
121
122 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
123         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
124 #endif
125 #ifdef CONFIG_TEGRA_EDP_LIMITS
126         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
127         .hysteresis_edp = 3000,
128 #endif
129 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
130         .temp_throttle = 85000,
131         .tc1 = 0,
132         .tc2 = 1,
133         .passive_delay = 2000,
134 #endif
135 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
136         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
137         .temp_throttle_skin = 43000,
138         .tc1_skin = 0,
139         .tc2_skin = 1,
140         .passive_delay_skin = 5000,
141
142         .skin_temp_offset = 9793,
143         .skin_period = 1100,
144         .skin_devs_size = 2,
145         .skin_devs = {
146                 {
147                         THERMAL_DEVICE_ID_NCT_EXT,
148                         {
149                                 2, 1, 1, 1,
150                                 1, 1, 1, 1,
151                                 1, 1, 1, 0,
152                                 1, 1, 0, 0,
153                                 0, 0, -1, -7
154                         }
155                 },
156                 {
157                         THERMAL_DEVICE_ID_NCT_INT,
158                         {
159                                 -11, -7, -5, -3,
160                                 -3, -2, -1, 0,
161                                 0, 0, 1, 1,
162                                 1, 2, 2, 3,
163                                 4, 6, 11, 18
164                         }
165                 },
166         },
167 #endif
168 };
169
170 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
171         {
172                 .name           = "bt_rfkill",
173                 .shutdown_gpio  = TEGRA_GPIO_PU0,
174                 .reset_gpio     = TEGRA_GPIO_INVALID,
175                 .type           = RFKILL_TYPE_BLUETOOTH,
176         },
177 };
178
179 static struct platform_device cardhu_bt_rfkill_device = {
180         .name = "rfkill_gpio",
181         .id             = -1,
182         .dev = {
183                 .platform_data = &cardhu_bt_rfkill_pdata,
184         },
185 };
186
187 static struct resource cardhu_bluesleep_resources[] = {
188         [0] = {
189                 .name = "gpio_host_wake",
190                         .start  = TEGRA_GPIO_PU6,
191                         .end    = TEGRA_GPIO_PU6,
192                         .flags  = IORESOURCE_IO,
193         },
194         [1] = {
195                 .name = "gpio_ext_wake",
196                         .start  = TEGRA_GPIO_PU1,
197                         .end    = TEGRA_GPIO_PU1,
198                         .flags  = IORESOURCE_IO,
199         },
200         [2] = {
201                 .name = "host_wake",
202                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
203         },
204 };
205
206 static struct platform_device cardhu_bluesleep_device = {
207         .name           = "bluesleep",
208         .id             = -1,
209         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
210         .resource       = cardhu_bluesleep_resources,
211 };
212
213 static noinline void __init cardhu_setup_bluesleep(void)
214 {
215         cardhu_bluesleep_resources[2].start =
216                 cardhu_bluesleep_resources[2].end =
217                         gpio_to_irq(TEGRA_GPIO_PU6);
218         platform_device_register(&cardhu_bluesleep_device);
219         return;
220 }
221
222 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
223         /* name         parent          rate            enabled */
224         { "pll_m",      NULL,           0,              false},
225         { "hda",        "pll_p",        108000000,      false},
226         { "hda2codec_2x","pll_p",       48000000,       false},
227         { "pwm",        "pll_p",        3187500,        false},
228         { "blink",      "clk_32k",      32768,          true},
229         { "i2s0",       "pll_a_out0",   0,              false},
230         { "i2s1",       "pll_a_out0",   0,              false},
231         { "i2s3",       "pll_a_out0",   0,              false},
232         { "spdif_out",  "pll_a_out0",   0,              false},
233         { "d_audio",    "clk_m",        12000000,       false},
234         { "dam0",       "clk_m",        12000000,       false},
235         { "dam1",       "clk_m",        12000000,       false},
236         { "dam2",       "clk_m",        12000000,       false},
237         { "audio1",     "i2s1_sync",    0,              false},
238         { "audio3",     "i2s3_sync",    0,              false},
239         { "vi_sensor",  "pll_p",        150000000,      false},
240         { "i2c1",       "pll_p",        3200000,        false},
241         { "i2c2",       "pll_p",        3200000,        false},
242         { "i2c3",       "pll_p",        3200000,        false},
243         { "i2c4",       "pll_p",        3200000,        false},
244         { "i2c5",       "pll_p",        3200000,        false},
245         { "vi",         "pll_p",        0,              false},
246         { NULL,         NULL,           0,              0},
247 };
248
249 static struct pn544_i2c_platform_data nfc_pdata = {
250         .irq_gpio = TEGRA_GPIO_PX0,
251         .ven_gpio = TEGRA_GPIO_PP3,
252         .firm_gpio = TEGRA_GPIO_PO7,
253         };
254
255 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
256         {
257                 I2C_BOARD_INFO("pn544", 0x28),
258                 .platform_data = &nfc_pdata,
259         },
260 };
261 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
262         .adapter_nr     = 0,
263         .bus_count      = 1,
264         .bus_clk_rate   = { 100000, 0 },
265         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
266         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
267         .arb_recovery = arb_lost_recovery,
268 };
269
270 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
271         .adapter_nr     = 1,
272         .bus_count      = 1,
273         .bus_clk_rate   = { 400000, 0 },
274         .is_clkon_always = true,
275         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
276         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
277         .arb_recovery = arb_lost_recovery,
278 };
279
280 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
281         .adapter_nr     = 2,
282         .bus_count      = 1,
283         .bus_clk_rate   = { 100000, 0 },
284         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
285         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
286         .arb_recovery = arb_lost_recovery,
287 };
288
289 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
290         .adapter_nr     = 3,
291         .bus_count      = 1,
292         .bus_clk_rate   = { 10000, 0 },
293         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
294         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
295         .arb_recovery = arb_lost_recovery,
296 };
297
298 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
299         .adapter_nr     = 4,
300         .bus_count      = 1,
301         .bus_clk_rate   = { 400000, 0 },
302         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
303         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
304         .arb_recovery = arb_lost_recovery,
305 };
306
307
308 #if 0
309 struct tegra_wired_jack_conf audio_wr_jack_conf = {
310         .hp_det_n = TEGRA_GPIO_PW2,
311         .en_mic_ext = TEGRA_GPIO_PX1,
312         .en_mic_int = TEGRA_GPIO_PX0,
313 };
314 #endif
315
316 static struct wm8903_platform_data cardhu_wm8903_pdata = {
317         .irq_active_low = 0,
318         .micdet_cfg = 0,
319         .micdet_delay = 100,
320         .gpio_base = CARDHU_GPIO_WM8903(0),
321         .gpio_cfg = {
322                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
323                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
324                         WM8903_GP2_DIR,
325                 WM8903_GPIO_CONFIG_ZERO,
326                 0,
327                 0,
328         },
329 };
330
331 /* Equalizer filter coefs generated from the MAXIM MAX98095
332  * evkit software tool */
333 static struct max98095_eq_cfg max98095_eq_cfg[] = {
334         {
335                 .name = "FLAT",
336                 .rate = 44100,
337                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
338                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
339                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
340                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
341                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
342         },
343         {
344                 .name = "LOWPASS1K",
345                 .rate = 44100,
346                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
347                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
348                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
349                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
350                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
351         },
352         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
353                 .name = "HIBOOST",
354                 .rate = 44100,
355                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
356                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
357                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
358                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
359                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
360         },
361         { /* BASS=12dB, TREBLE=+12dB */
362                 .name = "LOUD12DB",
363                 .rate = 44100,
364                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
365                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
366                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
367                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
368                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
369         },
370         {
371                 .name = "FLAT",
372                 .rate = 16000,
373                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
374                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
375                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
376                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
377                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
378         },
379         {
380                 .name = "LOWPASS1K",
381                 .rate = 16000,
382                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
383                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
384                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
385                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
386                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
387         },
388         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
389                 .name = "HIBOOST",
390                 .rate = 16000,
391                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
392                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
393                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
394                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
395                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
396         },
397         { /* BASS=12dB, TREBLE=+12dB */
398                 .name = "LOUD12DB",
399                 .rate = 16000,
400                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
401                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
402                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
403                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
404                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
405         },
406 };
407
408 static struct max98095_pdata cardhu_max98095_pdata = {
409         /* equalizer configuration */
410         .eq_cfg = max98095_eq_cfg,
411         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
412
413         /* Biquad filter response configuration */
414         .bq_cfg = NULL,
415         .bq_cfgcnt = 0,
416
417         /* microphone configuration */
418         .digmic_left_mode = 1,
419         .digmic_right_mode = 1,
420 };
421
422 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
423         I2C_BOARD_INFO("wm8903", 0x1a),
424         .platform_data = &cardhu_wm8903_pdata,
425 };
426
427 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
428         I2C_BOARD_INFO("aic3262-codec", 0x18),
429 };
430
431 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
432         I2C_BOARD_INFO("max98095", 0x10),
433         .platform_data = &cardhu_max98095_pdata,
434 };
435
436 static void cardhu_i2c_init(void)
437 {
438         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
439         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
440         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
441         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
442         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
443
444         platform_device_register(&tegra_i2c_device5);
445         platform_device_register(&tegra_i2c_device4);
446         platform_device_register(&tegra_i2c_device3);
447         platform_device_register(&tegra_i2c_device2);
448         platform_device_register(&tegra_i2c_device1);
449
450         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
451                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
452         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
453         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
454         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
455
456         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
457         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
458 }
459
460 static struct platform_device *cardhu_uart_devices[] __initdata = {
461         &tegra_uarta_device,
462         &tegra_uartb_device,
463         &tegra_uartc_device,
464         &tegra_uartd_device,
465         &tegra_uarte_device,
466 };
467 static struct uart_clk_parent uart_parent_clk[] = {
468         [0] = {.name = "clk_m"},
469         [1] = {.name = "pll_p"},
470 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
471         [2] = {.name = "pll_m"},
472 #endif
473 };
474
475 static struct tegra_uart_platform_data cardhu_uart_pdata;
476 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
477
478 static void __init uart_debug_init(void)
479 {
480         struct board_info board_info;
481         int debug_port_id;
482
483         tegra_get_board_info(&board_info);
484
485         debug_port_id = get_tegra_uart_debug_port_id();
486         if (debug_port_id < 0) {
487                 debug_port_id = 0;
488                         /* UARTB is debug port
489                          *       for SLT - E1186/E1187/PM269
490                          *       for E1256/E1257
491                          */
492                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
493                         ((board_info.board_id == BOARD_E1186) ||
494                         (board_info.board_id == BOARD_E1187) ||
495                         (board_info.board_id == BOARD_PM269))) ||
496                         (board_info.board_id == BOARD_E1256) ||
497                         (board_info.board_id == BOARD_E1257))
498                                 debug_port_id = 1;
499         }
500
501         switch (debug_port_id) {
502         case 0:
503                 /* UARTA is the debug port. */
504                 pr_info("Selecting UARTA as the debug console\n");
505                 cardhu_uart_devices[0] = &debug_uarta_device;
506                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
507                 debug_uart_port_base = ((struct plat_serial8250_port *)(
508                         debug_uarta_device.dev.platform_data))->mapbase;
509                 break;
510
511         case 1:
512                 /* UARTB is the debug port. */
513                 pr_info("Selecting UARTB as the debug console\n");
514                 cardhu_uart_devices[1] = &debug_uartb_device;
515                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
516                 debug_uart_port_base = ((struct plat_serial8250_port *)(
517                         debug_uartb_device.dev.platform_data))->mapbase;
518                 break;
519
520         case 2:
521                 /* UARTC is the debug port. */
522                 pr_info("Selecting UARTC as the debug console\n");
523                 cardhu_uart_devices[2] = &debug_uartc_device;
524                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
525                 debug_uart_port_base = ((struct plat_serial8250_port *)(
526                         debug_uartc_device.dev.platform_data))->mapbase;
527                 break;
528
529         case 3:
530                 /* UARTD is the debug port. */
531                 pr_info("Selecting UARTD as the debug console\n");
532                 cardhu_uart_devices[3] = &debug_uartd_device;
533                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
534                 debug_uart_port_base = ((struct plat_serial8250_port *)(
535                         debug_uartd_device.dev.platform_data))->mapbase;
536                 break;
537
538         case 4:
539                 /* UARTE is the debug port. */
540                 pr_info("Selecting UARTE as the debug console\n");
541                 cardhu_uart_devices[4] = &debug_uarte_device;
542                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
543                 debug_uart_port_base = ((struct plat_serial8250_port *)(
544                         debug_uarte_device.dev.platform_data))->mapbase;
545                 break;
546
547         default:
548                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
549                 cardhu_uart_devices[0] = &debug_uarta_device;
550                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
551                 debug_uart_port_base = ((struct plat_serial8250_port *)(
552                         debug_uarta_device.dev.platform_data))->mapbase;
553                 break;
554         }
555         return;
556 }
557
558 static void __init cardhu_uart_init(void)
559 {
560         struct clk *c;
561         int i;
562
563         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
564                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
565                 if (IS_ERR_OR_NULL(c)) {
566                         pr_err("Not able to get the clock for %s\n",
567                                                 uart_parent_clk[i].name);
568                         continue;
569                 }
570                 uart_parent_clk[i].parent_clk = c;
571                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
572         }
573         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
574         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
575         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
576         cardhu_loopback_uart_pdata.parent_clk_count =
577                                                 ARRAY_SIZE(uart_parent_clk);
578         cardhu_loopback_uart_pdata.is_loopback = true;
579         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
580         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
581         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
582         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
583         /* UARTE is used for loopback test purpose */
584         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
585
586         /* Register low speed only if it is selected */
587         if (!is_tegra_debug_uartport_hs()) {
588                 uart_debug_init();
589                 /* Clock enable for the debug channel */
590                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
591                         pr_info("The debug console clock name is %s\n",
592                                                 debug_uart_clk->name);
593                         c = tegra_get_clock_by_name("pll_p");
594                         if (IS_ERR_OR_NULL(c))
595                                 pr_err("Not getting the parent clock pll_p\n");
596                         else
597                                 clk_set_parent(debug_uart_clk, c);
598
599                         clk_enable(debug_uart_clk);
600                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
601                 } else {
602                         pr_err("Not getting the clock %s for debug console\n",
603                                         debug_uart_clk->name);
604                 }
605         }
606
607         platform_add_devices(cardhu_uart_devices,
608                                 ARRAY_SIZE(cardhu_uart_devices));
609 }
610
611 static struct platform_device tegra_camera = {
612         .name = "tegra_camera",
613         .id = -1,
614 };
615
616 static struct platform_device *cardhu_spi_devices[] __initdata = {
617         &tegra_spi_device4,
618 };
619
620 static struct platform_device *touch_spi_device[] __initdata = {
621         &tegra_spi_device1,
622 };
623
624 struct spi_clk_parent spi_parent_clk[] = {
625         [0] = {.name = "pll_p"},
626 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
627         [1] = {.name = "pll_m"},
628         [2] = {.name = "clk_m"},
629 #else
630         [1] = {.name = "clk_m"},
631 #endif
632 };
633
634 static struct tegra_spi_platform_data cardhu_spi_pdata = {
635         .is_dma_based           = true,
636         .max_dma_buffer         = (16 * 1024),
637         .is_clkon_always        = false,
638         .max_rate               = 100000000,
639 };
640
641 static void __init cardhu_spi_init(void)
642 {
643         int i;
644         struct clk *c;
645         struct board_info board_info, display_board_info;
646
647         tegra_get_board_info(&board_info);
648         tegra_get_display_board_info(&display_board_info);
649
650         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
651                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
652                 if (IS_ERR_OR_NULL(c)) {
653                         pr_err("Not able to get the clock for %s\n",
654                                                 spi_parent_clk[i].name);
655                         continue;
656                 }
657                 spi_parent_clk[i].parent_clk = c;
658                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
659         }
660         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
661         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
662         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
663         platform_add_devices(cardhu_spi_devices,
664                                 ARRAY_SIZE(cardhu_spi_devices));
665
666         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
667                 platform_add_devices(touch_spi_device,
668                                 ARRAY_SIZE(touch_spi_device));
669         }
670         if (board_info.board_id == BOARD_E1198) {
671                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
672                 platform_device_register(&tegra_spi_device2);
673                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
674                 platform_device_register(&tegra_spi_slave_device1);
675         }
676 }
677
678 static void __init cardhu_dtv_init(void)
679 {
680         struct board_info board_info;
681
682         tegra_get_board_info(&board_info);
683
684         if (board_info.board_id == BOARD_E1186)
685                 platform_device_register(&tegra_dtv_device);
686 }
687
688 static struct resource tegra_rtc_resources[] = {
689         [0] = {
690                 .start = TEGRA_RTC_BASE,
691                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
692                 .flags = IORESOURCE_MEM,
693         },
694         [1] = {
695                 .start = INT_RTC,
696                 .end = INT_RTC,
697                 .flags = IORESOURCE_IRQ,
698         },
699 };
700
701 static struct platform_device tegra_rtc_device = {
702         .name = "tegra_rtc",
703         .id   = -1,
704         .resource = tegra_rtc_resources,
705         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
706 };
707
708 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
709         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
710         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
711         .gpio_hp_mute           = -1,
712         .gpio_int_mic_en        = -1,
713         .gpio_ext_mic_en        = -1,
714 };
715
716 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
717         .gpio_spkr_en           = -1,
718         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
719         .gpio_hp_mute           = -1,
720         .gpio_int_mic_en        = -1,
721         .gpio_ext_mic_en        = -1,
722 };
723
724 static struct platform_device cardhu_audio_wm8903_device = {
725         .name   = "tegra-snd-wm8903",
726         .id     = 0,
727         .dev    = {
728                 .platform_data = &cardhu_audio_wm8903_pdata,
729         },
730 };
731
732 static struct platform_device cardhu_audio_max98095_device = {
733         .name   = "tegra-snd-max98095",
734         .id     = 0,
735         .dev    = {
736                 .platform_data = &cardhu_audio_max98095_pdata,
737         },
738 };
739
740 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
741         .gpio_spkr_en           = -1,
742         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
743         .gpio_hp_mute           = -1,
744         .gpio_int_mic_en        = -1,
745         .gpio_ext_mic_en        = -1,
746         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
747         .audio_port_id          = {
748                 [HIFI_CODEC] = 0,
749                 [BASEBAND] = -1,
750                 [BT_SCO] = 3,
751         },
752         .baseband_param         = {
753                 .rate = -1,
754                 .channels = -1,
755         },
756 };
757
758 static struct platform_device cardhu_audio_aic326x_device = {
759         .name   = "tegra-snd-aic326x",
760         .id     = 0,
761         .dev    = {
762                 .platform_data  = &cardhu_audio_aic326x_pdata,
763         },
764 };
765
766 static struct platform_device *cardhu_devices[] __initdata = {
767         &tegra_pmu_device,
768         &tegra_rtc_device,
769         &tegra_udc_device,
770 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
771         &tegra_smmu_device,
772 #endif
773         &tegra_wdt0_device,
774         &tegra_wdt1_device,
775         &tegra_wdt2_device,
776 #if defined(CONFIG_TEGRA_AVP)
777         &tegra_avp_device,
778 #endif
779         &tegra_camera,
780 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
781         &tegra_se_device,
782 #endif
783         &tegra_ahub_device,
784         &tegra_dam_device0,
785         &tegra_dam_device1,
786         &tegra_dam_device2,
787         &tegra_i2s_device0,
788         &tegra_i2s_device1,
789         &tegra_i2s_device3,
790         &tegra_spdif_device,
791         &spdif_dit_device,
792         &bluetooth_dit_device,
793         &baseband_dit_device,
794         &cardhu_bt_rfkill_device,
795         &tegra_pcm_device,
796         &cardhu_audio_wm8903_device,
797         &cardhu_audio_max98095_device,
798         &cardhu_audio_aic326x_device,
799         &tegra_hda_device,
800         &tegra_cec_device,
801 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
802         &tegra_aes_device,
803 #endif
804 };
805
806 #define E1506_MXT_CONFIG_CRC 0x62F903
807 static const u8 e1506_config[] = {
808         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
810         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
811         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
812         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
813         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
814         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
815         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
816         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
817         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
818         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
819         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
820         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
821         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
824         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
825         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
826         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
827         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
829         0x00
830 };
831
832 #define MXT_CONFIG_CRC  0xD62DE8
833 static const u8 config[] = {
834         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
835         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
836         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
837         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
838         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
839         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
843         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
844         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
845         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
846         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
847         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
848         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
852         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
853         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
854 };
855
856 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
857 static const u8 config_sku2000[] = {
858         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
859         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
860         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
861         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
862         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
863         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
869         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
870         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
871         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
872         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
876         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
877         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
878 };
879
880 static struct mxt_platform_data atmel_mxt_info = {
881         .x_line         = 27,
882         .y_line         = 42,
883         .x_size         = 768,
884         .y_size         = 1366,
885         .blen           = 0x20,
886         .threshold      = 0x3C,
887         .voltage        = 3300000,              /* 3.3V */
888         .orient         = 5,
889         .config         = config,
890         .config_length  = 157,
891         .config_crc     = MXT_CONFIG_CRC,
892         .irqflags       = IRQF_TRIGGER_FALLING,
893 /*      .read_chg       = &read_chg, */
894         .read_chg       = NULL,
895 };
896
897 static struct mxt_platform_data e1506_atmel_mxt_info = {
898         .x_line         = 19,
899         .y_line         = 11,
900         .x_size         = 960,
901         .y_size         = 540,
902         .blen           = 0x10,
903         .threshold      = 0x32,
904         .voltage        = 3300000,              /* 3.3V */
905         .orient         = 3,
906         .config         = e1506_config,
907         .config_length  = 168,
908         .config_crc     = E1506_MXT_CONFIG_CRC,
909         .irqflags       = IRQF_TRIGGER_FALLING,
910 /*      .read_chg       = &read_chg, */
911         .read_chg       = NULL,
912 };
913
914 static struct i2c_board_info __initdata atmel_i2c_info[] = {
915         {
916                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
917                 .platform_data = &atmel_mxt_info,
918         }
919 };
920
921 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
922         {
923                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
924                 .platform_data = &e1506_atmel_mxt_info,
925         }
926 };
927
928 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
929         /* name         parent          rate            enabled */
930         { "sbc1",       "pll_p",        52000000,       true},
931         { NULL,         NULL,           0,              0},
932 };
933
934 static int __init cardhu_touch_init(void)
935 {
936         struct board_info BoardInfo, DisplayBoardInfo;
937
938         tegra_get_board_info(&BoardInfo);
939         tegra_get_display_board_info(&DisplayBoardInfo);
940         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
941                 tegra_clk_init_from_table(spi_clk_init_table);
942
943                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
944         } else {
945                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
946                 gpio_direction_input(TEGRA_GPIO_PH4);
947
948                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
949                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
950                 msleep(1);
951                 gpio_set_value(TEGRA_GPIO_PH6, 1);
952                 msleep(100);
953
954                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
955                         atmel_mxt_info.config = config_sku2000;
956                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
957                 }
958
959                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
960                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
961                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
962                 } else {
963                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
964                         i2c_register_board_info(1, atmel_i2c_info, 1);
965                 }
966         }
967
968         return 0;
969 }
970
971 #if defined(CONFIG_USB_SUPPORT)
972
973 static void cardu_usb_hsic_postsupend(void)
974 {
975 #ifdef CONFIG_TEGRA_BB_XMM_POWER
976         baseband_xmm_set_power_status(BBXMM_PS_L2);
977 #endif
978 }
979
980 static void cardu_usb_hsic_preresume(void)
981 {
982 #ifdef CONFIG_TEGRA_BB_XMM_POWER
983         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
984 #endif
985 }
986
987 static void cardu_usb_hsic_phy_ready(void)
988 {
989 #ifdef CONFIG_TEGRA_BB_XMM_POWER
990         baseband_xmm_set_power_status(BBXMM_PS_L0);
991 #endif
992 }
993
994 static void cardu_usb_hsic_phy_off(void)
995 {
996 #ifdef CONFIG_TEGRA_BB_XMM_POWER
997         baseband_xmm_set_power_status(BBXMM_PS_L3);
998 #endif
999 }
1000
1001 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1002         .post_suspend = cardu_usb_hsic_postsupend,
1003         .pre_resume = cardu_usb_hsic_preresume,
1004         .port_power = cardu_usb_hsic_phy_ready,
1005         .post_phy_off = cardu_usb_hsic_phy_off,
1006 };
1007
1008 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1009         .port_otg = false,
1010         .has_hostpc = true,
1011         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1012         .op_mode        = TEGRA_USB_OPMODE_HOST,
1013         .u_data.host = {
1014                 .vbus_gpio = -1,
1015                 .hot_plug = false,
1016                 .remote_wakeup_supported = false,
1017                 .power_off_on_suspend = false,
1018         },
1019         .u_cfg.hsic = {
1020                 .sync_start_delay = 9,
1021                 .idle_wait_delay = 17,
1022                 .term_range_adj = 0,
1023                 .elastic_underrun_limit = 16,
1024                 .elastic_overrun_limit = 16,
1025         },
1026         .ops = &hsic_xmm_plat_ops,
1027 };
1028 #endif
1029
1030 static int hsic_enable_gpio = -1;
1031 static int hsic_reset_gpio = -1;
1032
1033 void hsic_platform_open(void)
1034 {
1035         int reset_gpio = 0, enable_gpio = 0;
1036
1037         if (hsic_enable_gpio != -1)
1038                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1039         if (hsic_reset_gpio != -1)
1040                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1041         /* hsic enable signal deasserted, hsic reset asserted */
1042         if (!enable_gpio)
1043                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1044         if (!reset_gpio)
1045                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1046         if (!enable_gpio)
1047                 tegra_gpio_enable(hsic_enable_gpio);
1048         if (!reset_gpio)
1049                 tegra_gpio_enable(hsic_reset_gpio);
1050         /* keep hsic reset asserted for 1 ms */
1051         udelay(1000);
1052         /* enable (power on) hsic */
1053         if (!enable_gpio)
1054                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1055         udelay(1000);
1056         /* deassert reset */
1057         if (!reset_gpio)
1058                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1059
1060 }
1061
1062 void hsic_platform_close(void)
1063 {
1064         if (hsic_enable_gpio != -1) {
1065                 gpio_set_value(hsic_enable_gpio, 0);
1066                 gpio_free(hsic_enable_gpio);
1067         }
1068         if (hsic_reset_gpio != -1) {
1069                 gpio_set_value(hsic_reset_gpio, 0);
1070                 gpio_free(hsic_reset_gpio);
1071         }
1072 }
1073
1074 void hsic_power_on(void)
1075 {
1076         if (hsic_enable_gpio != -1) {
1077                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1078                 udelay(1000);
1079         }
1080 }
1081
1082 void hsic_power_off(void)
1083 {
1084         if (hsic_enable_gpio != -1) {
1085                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1086                 udelay(1000);
1087         }
1088 }
1089
1090 #if defined(CONFIG_USB_SUPPORT)
1091 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1092         .open = hsic_platform_open,
1093         .close = hsic_platform_close,
1094         .pre_phy_on = hsic_power_on,
1095         .post_phy_off = hsic_power_off,
1096 };
1097
1098 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1099         .port_otg = false,
1100         .has_hostpc = true,
1101         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1102         .op_mode        = TEGRA_USB_OPMODE_HOST,
1103         .u_data.host = {
1104                 .vbus_gpio = -1,
1105                 .hot_plug = false,
1106                 .remote_wakeup_supported = false,
1107                 .power_off_on_suspend = false,
1108         },
1109         .u_cfg.hsic = {
1110                 .sync_start_delay = 9,
1111                 .idle_wait_delay = 17,
1112                 .term_range_adj = 0,
1113                 .elastic_underrun_limit = 16,
1114                 .elastic_overrun_limit = 16,
1115         },
1116         .ops = &hsic_plat_ops,
1117 };
1118
1119 static struct tegra_usb_platform_data tegra_udc_pdata = {
1120         .port_otg = true,
1121         .has_hostpc = true,
1122         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1123         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1124         .u_data.dev = {
1125                 .vbus_pmu_irq = 0,
1126                 .vbus_gpio = -1,
1127                 .charging_supported = false,
1128                 .remote_wakeup_supported = false,
1129         },
1130         .u_cfg.utmi = {
1131                 .hssync_start_delay = 0,
1132                 .elastic_limit = 16,
1133                 .idle_wait_delay = 17,
1134                 .term_range_adj = 6,
1135                 .xcvr_setup = 8,
1136                 .xcvr_lsfslew = 2,
1137                 .xcvr_lsrslew = 2,
1138                 .xcvr_setup_offset = 0,
1139                 .xcvr_use_fuses = 1,
1140         },
1141 };
1142
1143 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1144         .port_otg = false,
1145         .has_hostpc = true,
1146         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1147         .op_mode        = TEGRA_USB_OPMODE_HOST,
1148         .u_data.host = {
1149                 .vbus_gpio = -1,
1150                 .hot_plug = false,
1151                 .remote_wakeup_supported = true,
1152                 .power_off_on_suspend = true,
1153         },
1154         .u_cfg.utmi = {
1155                 .hssync_start_delay = 0,
1156                 .elastic_limit = 16,
1157                 .idle_wait_delay = 17,
1158                 .term_range_adj = 6,
1159                 .xcvr_setup = 15,
1160                 .xcvr_lsfslew = 2,
1161                 .xcvr_lsrslew = 2,
1162                 .xcvr_setup_offset = 0,
1163                 .xcvr_use_fuses = 1,
1164         },
1165 };
1166
1167 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1168         .port_otg = false,
1169         .has_hostpc = true,
1170         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1171         .op_mode = TEGRA_USB_OPMODE_HOST,
1172         .u_data.host = {
1173                 .vbus_gpio = -1,
1174                 .vbus_reg = "vdd_vbus_typea_usb",
1175                 .hot_plug = true,
1176                 .remote_wakeup_supported = true,
1177                 .power_off_on_suspend = true,
1178         },
1179         .u_cfg.utmi = {
1180                 .hssync_start_delay = 0,
1181                 .elastic_limit = 16,
1182                 .idle_wait_delay = 17,
1183                 .term_range_adj = 6,
1184                 .xcvr_setup = 8,
1185                 .xcvr_lsfslew = 2,
1186                 .xcvr_lsrslew = 2,
1187                 .xcvr_setup_offset = 0,
1188                 .xcvr_use_fuses = 1,
1189         },
1190 };
1191
1192 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1193         .port_otg = true,
1194         .has_hostpc = true,
1195         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1196         .op_mode = TEGRA_USB_OPMODE_HOST,
1197         .u_data.host = {
1198                 .vbus_gpio = -1,
1199                 .vbus_reg = "vdd_vbus_micro_usb",
1200                 .hot_plug = true,
1201                 .remote_wakeup_supported = true,
1202                 .power_off_on_suspend = true,
1203         },
1204         .u_cfg.utmi = {
1205                 .hssync_start_delay = 0,
1206                 .elastic_limit = 16,
1207                 .idle_wait_delay = 17,
1208                 .term_range_adj = 6,
1209                 .xcvr_setup = 15,
1210                 .xcvr_lsfslew = 2,
1211                 .xcvr_lsrslew = 2,
1212                 .xcvr_setup_offset = 0,
1213                 .xcvr_use_fuses = 1,
1214         },
1215 };
1216
1217 static struct tegra_usb_otg_data tegra_otg_pdata = {
1218         .ehci_device = &tegra_ehci1_device,
1219         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1220 };
1221 #endif
1222
1223 #if defined(CONFIG_USB_SUPPORT)
1224 static void cardhu_usb_init(void)
1225 {
1226         struct board_info bi;
1227
1228         tegra_get_board_info(&bi);
1229
1230         /* OTG should be the first to be registered */
1231         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1232         platform_device_register(&tegra_otg_device);
1233
1234         /* setup the udc platform data */
1235         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1236
1237         if (bi.board_id == BOARD_PM267) {
1238                 hsic_enable_gpio = EN_HSIC_GPIO;
1239                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1240                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1241                 platform_device_register(&tegra_ehci2_device);
1242         } else if (bi.board_id == BOARD_E1256) {
1243                 hsic_enable_gpio = EN_HSIC_GPIO;
1244                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1245                 platform_device_register(&tegra_ehci2_device);
1246         } else if (bi.board_id == BOARD_E1186) {
1247                 tegra_ehci2_device.dev.platform_data =
1248                                                 &tegra_ehci2_hsic_xmm_pdata;
1249                 /* ehci2 registration happens in baseband-xmm-power  */
1250         } else {
1251                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1252                 platform_device_register(&tegra_ehci2_device);
1253         }
1254
1255         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1256         platform_device_register(&tegra_ehci3_device);
1257
1258 }
1259 #else
1260 static void cardhu_usb_init(void) { }
1261 #endif
1262
1263 static struct baseband_power_platform_data tegra_baseband_power_data = {
1264         .baseband_type = BASEBAND_XMM,
1265         .modem = {
1266         .xmm = {
1267                         .bb_rst = XMM_GPIO_BB_RST,
1268                         .bb_on = XMM_GPIO_BB_ON,
1269                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1270                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1271                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1272                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1273                         .hsic_device = &tegra_ehci2_device,
1274                 },
1275         },
1276 };
1277
1278 static struct platform_device tegra_baseband_power_device = {
1279         .name = "baseband_xmm_power",
1280         .id = -1,
1281         .dev = {
1282                 .platform_data = &tegra_baseband_power_data,
1283         },
1284 };
1285
1286 static struct platform_device tegra_baseband_power2_device = {
1287         .name = "baseband_xmm_power2",
1288         .id = -1,
1289         .dev = {
1290                 .platform_data = &tegra_baseband_power_data,
1291         },
1292 };
1293
1294
1295 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1296         .port_status[0] = 1,
1297         .port_status[1] = 1,
1298         .port_status[2] = 1,
1299         .use_dock_detect        = 0,
1300         .gpio           = 0,
1301 };
1302
1303 static void cardhu_pci_init(void)
1304 {
1305         struct board_info board_info;
1306
1307         tegra_get_board_info(&board_info);
1308         if (board_info.board_id == BOARD_E1291) {
1309                 cardhu_pci_platform_data.port_status[0] = 0;
1310                 cardhu_pci_platform_data.port_status[1] = 0;
1311                 cardhu_pci_platform_data.port_status[2] = 1;
1312                 cardhu_pci_platform_data.use_dock_detect = 1;
1313                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1314         }
1315         if ((board_info.board_id == BOARD_E1186) ||
1316                 (board_info.board_id == BOARD_E1187) ||
1317                 (board_info.board_id == BOARD_E1291)) {
1318                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1319                 platform_device_register(&tegra_pci_device);
1320         }
1321 }
1322
1323 static void cardhu_modem_init(void)
1324 {
1325         struct board_info board_info;
1326         int w_disable_gpio, ret;
1327
1328         tegra_get_board_info(&board_info);
1329         switch (board_info.board_id) {
1330         case BOARD_E1291:
1331         case BOARD_E1198:
1332                 if (((board_info.board_id == BOARD_E1291) &&
1333                                 (board_info.fab < BOARD_FAB_A03)) ||
1334                         ((board_info.board_id == BOARD_E1198) &&
1335                                         (board_info.fab < BOARD_FAB_A02))) {
1336                         w_disable_gpio = TEGRA_GPIO_PH5;
1337                 } else {
1338                         w_disable_gpio = TEGRA_GPIO_PDD5;
1339                 }
1340
1341                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1342                 if (ret < 0)
1343                         pr_err("%s: gpio_request failed for gpio %d\n",
1344                                 __func__, w_disable_gpio);
1345                 else
1346                         gpio_direction_input(w_disable_gpio);
1347
1348                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1349                 if (((board_info.board_id == BOARD_E1291) &&
1350                                 (board_info.fab >= BOARD_FAB_A04)) ||
1351                         ((board_info.board_id == BOARD_E1198) &&
1352                                         (board_info.fab >= BOARD_FAB_A02))) {
1353                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1354                         if (ret < 0) {
1355                                 pr_err("%s(): Error in allocating gpio "
1356                                         "TEGRA_GPIO_PH7\n", __func__);
1357                                 break;
1358                         }
1359                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1360                 }
1361                 break;
1362         case BOARD_E1186:
1363                 platform_device_register(&tegra_baseband_power_device);
1364                 platform_device_register(&tegra_baseband_power2_device);
1365                 break;
1366         default:
1367                 break;
1368         }
1369
1370 }
1371
1372 #ifdef CONFIG_SATA_AHCI_TEGRA
1373 static void cardhu_sata_init(void)
1374 {
1375         platform_device_register(&tegra_sata_device);
1376 }
1377 #else
1378 static void cardhu_sata_init(void) { }
1379 #endif
1380
1381 static void __init tegra_cardhu_init(void)
1382 {
1383         tegra_thermal_init(&thermal_data,
1384                                 throttle_list,
1385                                 ARRAY_SIZE(throttle_list));
1386         tegra_clk_init_from_table(cardhu_clk_init_table);
1387         tegra_enable_pinmux();
1388         cardhu_pinmux_init();
1389         cardhu_i2c_init();
1390         cardhu_spi_init();
1391         cardhu_usb_init();
1392 #ifdef CONFIG_TEGRA_EDP_LIMITS
1393         cardhu_edp_init();
1394 #endif
1395         cardhu_uart_init();
1396         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1397         tegra_ram_console_debug_init();
1398         tegra_io_dpd_init();
1399         cardhu_sdhci_init();
1400         cardhu_regulator_init();
1401         cardhu_dtv_init();
1402         cardhu_suspend_init();
1403         cardhu_touch_init();
1404         cardhu_modem_init();
1405         cardhu_kbc_init();
1406         cardhu_scroll_init();
1407         cardhu_keys_init();
1408         cardhu_panel_init();
1409         cardhu_pmon_init();
1410         cardhu_sensors_init();
1411         cardhu_setup_bluesleep();
1412         cardhu_sata_init();
1413         //audio_wired_jack_init();
1414         cardhu_pins_state_init();
1415         cardhu_emc_init();
1416         tegra_release_bootloader_fb();
1417         cardhu_pci_init();
1418 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1419         tegra_wdt_recovery_init();
1420 #endif
1421         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1422 }
1423
1424 static void __init tegra_cardhu_reserve(void)
1425 {
1426 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1427         /* support 1920X1200 with 24bpp */
1428         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1429 #else
1430         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1431 #endif
1432         tegra_ram_console_debug_reserve(SZ_1M);
1433 }
1434
1435 MACHINE_START(CARDHU, "cardhu")
1436         .atag_offset    = 0x100,
1437         .soc            = &tegra_soc_desc,
1438         .map_io         = tegra_map_common_io,
1439         .reserve        = tegra_cardhu_reserve,
1440         .init_early     = tegra30_init_early,
1441         .init_irq       = tegra_init_irq,
1442         .handle_irq     = gic_handle_irq,
1443         .timer          = &tegra_timer,
1444         .init_machine   = tegra_cardhu_init,
1445         .restart        = tegra_assert_system_reset,
1446 MACHINE_END