arch/arm/mach-tegra/board-cardhu.c

   1 /*
   2  * arch/arm/mach-tegra/board-cardhu.c
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
   5  * Copyright (c) 2011-2012, NVIDIA Corporation.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/slab.h>
  25 #include <linux/ctype.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/clk.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/i2c.h>
  30 #include <linux/i2c/panjit_ts.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c-tegra.h>
  34 #include <linux/gpio.h>
  35 #include <linux/input.h>
  36 #include <linux/platform_data/tegra_usb.h>
  37 #include <linux/spi/spi.h>
  38 #include <linux/i2c/atmel_mxt_ts.h>
  39 #include <linux/tegra_uart.h>
  40 #include <linux/memblock.h>
  41 #include <linux/spi-tegra.h>
  42 #include <linux/nfc/pn544.h>
  43 #include <linux/rfkill-gpio.h>
  44
  45 #include <sound/wm8903.h>
  46 #include <sound/max98095.h>
  47 #include <media/tegra_dtv.h>
  48 #include <media/tegra_camera.h>
  49
  50 #include <mach/clk.h>
  51 #include <mach/iomap.h>
  52 #include <mach/irqs.h>
  53 #include <mach/pinmux.h>
  54 #include <mach/iomap.h>
  55 #include <mach/io_dpd.h>
  56 #include <mach/io.h>
  57 #include <mach/i2s.h>
  58 #include <mach/tegra_asoc_pdata.h>
  59 #include <mach/tegra_wm8903_pdata.h>
  60 #include <asm/mach-types.h>
  61 #include <asm/mach/arch.h>
  62 #include <mach/usb_phy.h>
  63 #include <mach/thermal.h>
  64 #include <mach/pci.h>
  65 #include <mach/tegra_fiq_debugger.h>
  66
  67 #include "board.h"
  68 #include "clock.h"
  69 #include "board-cardhu.h"
  70 #include "board-touch.h"
  71 #include "devices.h"
  72 #include "gpio-names.h"
  73 #include "fuse.h"
  74 #include "pm.h"
  75 #include "baseband-xmm-power.h"
  76 #include "wdt-recovery.h"
  77
  78 static struct balanced_throttle throttle_list[] = {
  79 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
  80         {
  81                 .id = BALANCED_THROTTLE_ID_TJ,
  82                 .throt_tab_size = 10,
  83                 .throt_tab = {
  84                         {      0, 1000 },
  85                         { 640000, 1000 },
  86                         { 640000, 1000 },
  87                         { 640000, 1000 },
  88                         { 640000, 1000 },
  89                         { 640000, 1000 },
  90                         { 760000, 1000 },
  91                         { 760000, 1050 },
  92                         {1000000, 1050 },
  93                         {1000000, 1100 },
  94                 },
  95         },
  96 #endif
  97 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
  98         {
  99                 .id = BALANCED_THROTTLE_ID_SKIN,
 100                 .throt_tab_size = 6,
 101                 .throt_tab = {
 102                         { 640000, 1200 },
 103                         { 640000, 1200 },
 104                         { 760000, 1200 },
 105                         { 760000, 1200 },
 106                         {1000000, 1200 },
 107                         {1000000, 1200 },
 108                 },
 109         },
 110 #endif
 111 };
 112
 113 /* All units are in millicelsius */
 114 static struct tegra_thermal_data thermal_data = {
 115         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
 116         .temp_shutdown = 90000,
 117
 118 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
 119         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
 120 #endif
 121 #ifdef CONFIG_TEGRA_EDP_LIMITS
 122         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
 123         .hysteresis_edp = 3000,
 124 #endif
 125 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
 126         .temp_throttle = 85000,
 127         .tc1 = 0,
 128         .tc2 = 1,
 129         .passive_delay = 2000,
 130 #endif
 131 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
 132         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
 133         .temp_throttle_skin = 43000,
 134         .tc1_skin = 0,
 135         .tc2_skin = 1,
 136         .passive_delay_skin = 5000,
 137
 138         .skin_temp_offset = 9793,
 139         .skin_period = 1100,
 140         .skin_devs_size = 2,
 141         .skin_devs = {
 142                 {
 143                         THERMAL_DEVICE_ID_NCT_EXT,
 144                         {
 145                                 2, 1, 1, 1,
 146                                 1, 1, 1, 1,
 147                                 1, 1, 1, 0,
 148                                 1, 1, 0, 0,
 149                                 0, 0, -1, -7
 150                         }
 151                 },
 152                 {
 153                         THERMAL_DEVICE_ID_NCT_INT,
 154                         {
 155                                 -11, -7, -5, -3,
 156                                 -3, -2, -1, 0,
 157                                 0, 0, 1, 1,
 158                                 1, 2, 2, 3,
 159                                 4, 6, 11, 18
 160                         }
 161                 },
 162         },
 163 #endif
 164 };
 165
 166 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
 167         {
 168                 .name           = "bt_rfkill",
 169                 .shutdown_gpio  = TEGRA_GPIO_PU0,
 170                 .reset_gpio     = TEGRA_GPIO_INVALID,
 171                 .type           = RFKILL_TYPE_BLUETOOTH,
 172         },
 173 };
 174
 175 static struct platform_device cardhu_bt_rfkill_device = {
 176         .name = "rfkill_gpio",
 177         .id             = -1,
 178         .dev = {
 179                 .platform_data = &cardhu_bt_rfkill_pdata,
 180         },
 181 };
 182
 183 static struct resource cardhu_bluesleep_resources[] = {
 184         [0] = {
 185                 .name = "gpio_host_wake",
 186                         .start  = TEGRA_GPIO_PU6,
 187                         .end    = TEGRA_GPIO_PU6,
 188                         .flags  = IORESOURCE_IO,
 189         },
 190         [1] = {
 191                 .name = "gpio_ext_wake",
 192                         .start  = TEGRA_GPIO_PU1,
 193                         .end    = TEGRA_GPIO_PU1,
 194                         .flags  = IORESOURCE_IO,
 195         },
 196         [2] = {
 197                 .name = "host_wake",
 198                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
 199                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
 200                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 201         },
 202 };
 203
 204 static struct platform_device cardhu_bluesleep_device = {
 205         .name           = "bluesleep",
 206         .id             = -1,
 207         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
 208         .resource       = cardhu_bluesleep_resources,
 209 };
 210
 211 static noinline void __init cardhu_setup_bluesleep(void)
 212 {
 213         platform_device_register(&cardhu_bluesleep_device);
 214         return;
 215 }
 216
 217 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
 218         /* name         parent          rate            enabled */
 219         { "pll_m",      NULL,           0,              false},
 220         { "hda",        "pll_p",        108000000,      false},
 221         { "hda2codec_2x","pll_p",       48000000,       false},
 222         { "pwm",        "pll_p",        3187500,        false},
 223         { "blink",      "clk_32k",      32768,          true},
 224         { "i2s0",       "pll_a_out0",   0,              false},
 225         { "i2s1",       "pll_a_out0",   0,              false},
 226         { "i2s3",       "pll_a_out0",   0,              false},
 227         { "spdif_out",  "pll_a_out0",   0,              false},
 228         { "d_audio",    "clk_m",        12000000,       false},
 229         { "dam0",       "clk_m",        12000000,       false},
 230         { "dam1",       "clk_m",        12000000,       false},
 231         { "dam2",       "clk_m",        12000000,       false},
 232         { "audio1",     "i2s1_sync",    0,              false},
 233         { "audio3",     "i2s3_sync",    0,              false},
 234         { "vi_sensor",  "pll_p",        150000000,      false},
 235         { "i2c1",       "pll_p",        3200000,        false},
 236         { "i2c2",       "pll_p",        3200000,        false},
 237         { "i2c3",       "pll_p",        3200000,        false},
 238         { "i2c4",       "pll_p",        3200000,        false},
 239         { "i2c5",       "pll_p",        3200000,        false},
 240         { "vi",         "pll_p",        0,              false},
 241         { NULL,         NULL,           0,              0},
 242 };
 243
 244 static struct pn544_i2c_platform_data nfc_pdata = {
 245         .irq_gpio = TEGRA_GPIO_PX0,
 246         .ven_gpio = TEGRA_GPIO_PP3,
 247         .firm_gpio = TEGRA_GPIO_PO7,
 248         };
 249
 250 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
 251         {
 252                 I2C_BOARD_INFO("pn544", 0x28),
 253                 .platform_data = &nfc_pdata,
 254                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
 255         },
 256 };
 257 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
 258         .adapter_nr     = 0,
 259         .bus_count      = 1,
 260         .bus_clk_rate   = { 100000, 0 },
 261         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
 262         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
 263         .arb_recovery = arb_lost_recovery,
 264 };
 265
 266 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
 267         .adapter_nr     = 1,
 268         .bus_count      = 1,
 269         .bus_clk_rate   = { 400000, 0 },
 270         .is_clkon_always = true,
 271         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
 272         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
 273         .arb_recovery = arb_lost_recovery,
 274 };
 275
 276 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
 277         .adapter_nr     = 2,
 278         .bus_count      = 1,
 279         .bus_clk_rate   = { 100000, 0 },
 280         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
 281         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
 282         .arb_recovery = arb_lost_recovery,
 283 };
 284
 285 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
 286         .adapter_nr     = 3,
 287         .bus_count      = 1,
 288         .bus_clk_rate   = { 10000, 0 },
 289         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
 290         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
 291         .arb_recovery = arb_lost_recovery,
 292 };
 293
 294 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
 295         .adapter_nr     = 4,
 296         .bus_count      = 1,
 297         .bus_clk_rate   = { 400000, 0 },
 298         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
 299         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
 300         .arb_recovery = arb_lost_recovery,
 301 };
 302
 303
 304 #if 0
 305 struct tegra_wired_jack_conf audio_wr_jack_conf = {
 306         .hp_det_n = TEGRA_GPIO_PW2,
 307         .en_mic_ext = TEGRA_GPIO_PX1,
 308         .en_mic_int = TEGRA_GPIO_PX0,
 309 };
 310 #endif
 311
 312 static struct wm8903_platform_data cardhu_wm8903_pdata = {
 313         .irq_active_low = 0,
 314         .micdet_cfg = 0,
 315         .micdet_delay = 100,
 316         .gpio_base = CARDHU_GPIO_WM8903(0),
 317         .gpio_cfg = {
 318                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
 319                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
 320                         WM8903_GP2_DIR,
 321                 0,
 322                 WM8903_GPIO_NO_CONFIG,
 323                 WM8903_GPIO_NO_CONFIG,
 324         },
 325 };
 326
 327 /* Equalizer filter coefs generated from the MAXIM MAX98095
 328  * evkit software tool */
 329 static struct max98095_eq_cfg max98095_eq_cfg[] = {
 330         {
 331                 .name = "FLAT",
 332                 .rate = 44100,
 333                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
 334                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
 335                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
 336                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
 337                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
 338         },
 339         {
 340                 .name = "LOWPASS1K",
 341                 .rate = 44100,
 342                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
 343                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
 344                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
 345                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
 346                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
 347         },
 348         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
 349                 .name = "HIBOOST",
 350                 .rate = 44100,
 351                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
 352                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
 353                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
 354                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
 355                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
 356         },
 357         { /* BASS=12dB, TREBLE=+12dB */
 358                 .name = "LOUD12DB",
 359                 .rate = 44100,
 360                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
 361                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
 362                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
 363                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
 364                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
 365         },
 366         {
 367                 .name = "FLAT",
 368                 .rate = 16000,
 369                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
 370                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
 371                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
 372                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
 373                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
 374         },
 375         {
 376                 .name = "LOWPASS1K",
 377                 .rate = 16000,
 378                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
 379                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
 380                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
 381                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
 382                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
 383         },
 384         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
 385                 .name = "HIBOOST",
 386                 .rate = 16000,
 387                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
 388                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
 389                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
 390                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
 391                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
 392         },
 393         { /* BASS=12dB, TREBLE=+12dB */
 394                 .name = "LOUD12DB",
 395                 .rate = 16000,
 396                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
 397                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
 398                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
 399                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
 400                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
 401         },
 402 };
 403
 404 static struct max98095_pdata cardhu_max98095_pdata = {
 405         /* equalizer configuration */
 406         .eq_cfg = max98095_eq_cfg,
 407         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
 408
 409         /* Biquad filter response configuration */
 410         .bq_cfg = NULL,
 411         .bq_cfgcnt = 0,
 412
 413         /* microphone configuration */
 414         .digmic_left_mode = 1,
 415         .digmic_right_mode = 1,
 416 };
 417
 418 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
 419         I2C_BOARD_INFO("wm8903", 0x1a),
 420         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
 421         .platform_data = &cardhu_wm8903_pdata,
 422 };
 423
 424 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
 425         I2C_BOARD_INFO("aic3262-codec", 0x18),
 426         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
 427 };
 428
 429 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
 430         I2C_BOARD_INFO("max98095", 0x10),
 431         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
 432         .platform_data = &cardhu_max98095_pdata,
 433 };
 434
 435 static void cardhu_i2c_init(void)
 436 {
 437         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
 438         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
 439         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
 440         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
 441         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
 442
 443         platform_device_register(&tegra_i2c_device5);
 444         platform_device_register(&tegra_i2c_device4);
 445         platform_device_register(&tegra_i2c_device3);
 446         platform_device_register(&tegra_i2c_device2);
 447         platform_device_register(&tegra_i2c_device1);
 448
 449         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
 450         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
 451         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
 452
 453         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
 454 }
 455
 456 static struct platform_device *cardhu_uart_devices[] __initdata = {
 457         &tegra_uarta_device,
 458         &tegra_uartb_device,
 459         &tegra_uartc_device,
 460         &tegra_uartd_device,
 461         &tegra_uarte_device,
 462 };
 463 static struct uart_clk_parent uart_parent_clk[] = {
 464         [0] = {.name = "clk_m"},
 465         [1] = {.name = "pll_p"},
 466 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
 467         [2] = {.name = "pll_m"},
 468 #endif
 469 };
 470
 471 static struct tegra_uart_platform_data cardhu_uart_pdata;
 472 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
 473
 474 static void __init uart_debug_init(void)
 475 {
 476         struct board_info board_info;
 477         int debug_port_id;
 478
 479         tegra_get_board_info(&board_info);
 480
 481         debug_port_id = get_tegra_uart_debug_port_id();
 482         if (debug_port_id < 0) {
 483                 debug_port_id = 0;
 484                         /* UARTB is debug port
 485                          *       for SLT - E1186/E1187/PM269
 486                          *       for E1256/E1257
 487                          */
 488                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
 489                         ((board_info.board_id == BOARD_E1186) ||
 490                         (board_info.board_id == BOARD_E1187) ||
 491                         (board_info.board_id == BOARD_PM269))) ||
 492                         (board_info.board_id == BOARD_E1256) ||
 493                         (board_info.board_id == BOARD_E1257))
 494                                 debug_port_id = 1;
 495         }
 496
 497 #ifdef CONFIG_TEGRA_IRDA
 498         if ((board_info.board_id == BOARD_E1186) ||
 499                 (board_info.board_id == BOARD_E1198)) {
 500                 if (debug_port_id == 1) {
 501                         cardhu_irda_pdata.is_irda = false;
 502                         pr_err("UARTB is not available for IrDA\n");
 503                 }
 504         }
 505 #endif
 506
 507         switch (debug_port_id) {
 508         case 0:
 509                 /* UARTA is the debug port. */
 510                 pr_info("Selecting UARTA as the debug console\n");
 511                 cardhu_uart_devices[0] = &debug_uarta_device;
 512                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
 513                 debug_uart_port_base = ((struct plat_serial8250_port *)(
 514                         debug_uarta_device.dev.platform_data))->mapbase;
 515                 break;
 516
 517         case 1:
 518                 /* UARTB is the debug port. */
 519                 pr_info("Selecting UARTB as the debug console\n");
 520                 cardhu_uart_devices[1] = &debug_uartb_device;
 521                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
 522                 debug_uart_port_base = ((struct plat_serial8250_port *)(
 523                         debug_uartb_device.dev.platform_data))->mapbase;
 524                 break;
 525
 526         case 2:
 527                 /* UARTC is the debug port. */
 528                 pr_info("Selecting UARTC as the debug console\n");
 529                 cardhu_uart_devices[2] = &debug_uartc_device;
 530                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
 531                 debug_uart_port_base = ((struct plat_serial8250_port *)(
 532                         debug_uartc_device.dev.platform_data))->mapbase;
 533                 break;
 534
 535         case 3:
 536                 /* UARTD is the debug port. */
 537                 pr_info("Selecting UARTD as the debug console\n");
 538                 cardhu_uart_devices[3] = &debug_uartd_device;
 539                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
 540                 debug_uart_port_base = ((struct plat_serial8250_port *)(
 541                         debug_uartd_device.dev.platform_data))->mapbase;
 542                 break;
 543
 544         case 4:
 545                 /* UARTE is the debug port. */
 546                 pr_info("Selecting UARTE as the debug console\n");
 547                 cardhu_uart_devices[4] = &debug_uarte_device;
 548                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
 549                 debug_uart_port_base = ((struct plat_serial8250_port *)(
 550                         debug_uarte_device.dev.platform_data))->mapbase;
 551                 break;
 552
 553         default:
 554                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
 555                 cardhu_uart_devices[0] = &debug_uarta_device;
 556                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
 557                 debug_uart_port_base = ((struct plat_serial8250_port *)(
 558                         debug_uarta_device.dev.platform_data))->mapbase;
 559                 break;
 560         }
 561         return;
 562 }
 563
 564 static void __init cardhu_uart_init(void)
 565 {
 566         struct clk *c;
 567         int i;
 568         struct board_info board_info;
 569
 570         tegra_get_board_info(&board_info);
 571
 572         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
 573                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
 574                 if (IS_ERR_OR_NULL(c)) {
 575                         pr_err("Not able to get the clock for %s\n",
 576                                                 uart_parent_clk[i].name);
 577                         continue;
 578                 }
 579                 uart_parent_clk[i].parent_clk = c;
 580                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
 581         }
 582         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
 583         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
 584         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
 585         cardhu_loopback_uart_pdata.parent_clk_count =
 586                                                 ARRAY_SIZE(uart_parent_clk);
 587         cardhu_loopback_uart_pdata.is_loopback = true;
 588         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
 589         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
 590         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
 591         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
 592         /* UARTE is used for loopback test purpose */
 593         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
 594
 595         /* Register low speed only if it is selected */
 596         if (!is_tegra_debug_uartport_hs()) {
 597                 uart_debug_init();
 598                 /* Clock enable for the debug channel */
 599                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
 600                         pr_info("The debug console clock name is %s\n",
 601                                                 debug_uart_clk->name);
 602                         c = tegra_get_clock_by_name("pll_p");
 603                         if (IS_ERR_OR_NULL(c))
 604                                 pr_err("Not getting the parent clock pll_p\n");
 605                         else
 606                                 clk_set_parent(debug_uart_clk, c);
 607
 608                         clk_enable(debug_uart_clk);
 609                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
 610                 } else {
 611                         pr_err("Not getting the clock %s for debug console\n",
 612                                         debug_uart_clk->name);
 613                 }
 614         }
 615
 616 #ifdef CONFIG_TEGRA_IRDA
 617         if (((board_info.board_id == BOARD_E1186) ||
 618                 (board_info.board_id == BOARD_E1198)) &&
 619                         cardhu_irda_pdata.is_irda) {
 620                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
 621                 cardhu_irda_pdata.parent_clk_count =
 622                                         ARRAY_SIZE(uart_parent_clk);
 623
 624                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
 625         }
 626 #endif
 627
 628         platform_add_devices(cardhu_uart_devices,
 629                                 ARRAY_SIZE(cardhu_uart_devices));
 630 }
 631
 632 static struct tegra_camera_platform_data tegra_camera_pdata = {
 633         .limit_3d_emc_clk = false,
 634 };
 635
 636 static struct platform_device tegra_camera = {
 637         .name = "tegra_camera",
 638         .dev = {
 639                 .platform_data = &tegra_camera_pdata,
 640         },
 641         .id = -1,
 642 };
 643
 644 static void tegra_camera_init(void)
 645 {
 646         /* For AP37 platform, limit 3d and emc freq when camera is ON */
 647         if (TEGRA_REVISION_A03 == tegra_get_revision() &&
 648                 0xA0 == tegra_sku_id())
 649                 tegra_camera_pdata.limit_3d_emc_clk = true;
 650         else
 651                 tegra_camera_pdata.limit_3d_emc_clk = false;
 652 }
 653
 654 static struct platform_device *cardhu_spi_devices[] __initdata = {
 655         &tegra_spi_device4,
 656 };
 657
 658 static struct platform_device *touch_spi_device[] __initdata = {
 659         &tegra_spi_device1,
 660 };
 661
 662 struct spi_clk_parent spi_parent_clk[] = {
 663         [0] = {.name = "pll_p"},
 664 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
 665         [1] = {.name = "pll_m"},
 666         [2] = {.name = "clk_m"},
 667 #else
 668         [1] = {.name = "clk_m"},
 669 #endif
 670 };
 671
 672 static struct tegra_spi_platform_data cardhu_spi_pdata = {
 673         .is_dma_based           = true,
 674         .max_dma_buffer         = (16 * 1024),
 675         .is_clkon_always        = false,
 676         .max_rate               = 100000000,
 677 };
 678
 679 static void __init cardhu_spi_init(void)
 680 {
 681         int i;
 682         struct clk *c;
 683         struct board_info board_info, display_board_info;
 684
 685         tegra_get_board_info(&board_info);
 686         tegra_get_display_board_info(&display_board_info);
 687
 688         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
 689                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
 690                 if (IS_ERR_OR_NULL(c)) {
 691                         pr_err("Not able to get the clock for %s\n",
 692                                                 spi_parent_clk[i].name);
 693                         continue;
 694                 }
 695                 spi_parent_clk[i].parent_clk = c;
 696                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
 697         }
 698         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
 699         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
 700         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
 701         platform_add_devices(cardhu_spi_devices,
 702                                 ARRAY_SIZE(cardhu_spi_devices));
 703
 704         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
 705                 platform_add_devices(touch_spi_device,
 706                                 ARRAY_SIZE(touch_spi_device));
 707         }
 708         if (board_info.board_id == BOARD_E1198) {
 709                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
 710                 platform_device_register(&tegra_spi_device2);
 711                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
 712                 platform_device_register(&tegra_spi_slave_device1);
 713         }
 714 }
 715
 716 static void __init cardhu_dtv_init(void)
 717 {
 718         struct board_info board_info;
 719
 720         tegra_get_board_info(&board_info);
 721
 722         if (board_info.board_id == BOARD_E1186)
 723                 platform_device_register(&tegra_dtv_device);
 724 }
 725
 726 static struct resource tegra_rtc_resources[] = {
 727         [0] = {
 728                 .start = TEGRA_RTC_BASE,
 729                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
 730                 .flags = IORESOURCE_MEM,
 731         },
 732         [1] = {
 733                 .start = INT_RTC,
 734                 .end = INT_RTC,
 735                 .flags = IORESOURCE_IRQ,
 736         },
 737 };
 738
 739 static struct platform_device tegra_rtc_device = {
 740         .name = "tegra_rtc",
 741         .id   = -1,
 742         .resource = tegra_rtc_resources,
 743         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
 744 };
 745
 746 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
 747         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
 748         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
 749         .gpio_hp_mute           = -1,
 750         .gpio_int_mic_en        = -1,
 751         .gpio_ext_mic_en        = -1,
 752         .i2s_param[HIFI_CODEC]  = {
 753                 .audio_port_id  = 0,
 754                 .is_i2s_master  = 1,
 755                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 756         },
 757         .i2s_param[BASEBAND]    = {
 758                 .audio_port_id  = -1,
 759         },
 760         .i2s_param[BT_SCO]      = {
 761                 .audio_port_id  = 3,
 762                 .is_i2s_master  = 1,
 763                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
 764         },
 765 };
 766
 767 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
 768         .gpio_spkr_en           = -1,
 769         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
 770         .gpio_hp_mute           = -1,
 771         .gpio_int_mic_en        = -1,
 772         .gpio_ext_mic_en        = -1,
 773         .i2s_param[HIFI_CODEC]  = {
 774                 .audio_port_id  = 0,
 775                 .is_i2s_master  = 1,
 776                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 777         },
 778         .i2s_param[BASEBAND]    = {
 779                 .audio_port_id  = -1,
 780         },
 781         .i2s_param[BT_SCO]      = {
 782                 .audio_port_id  = 3,
 783                 .is_i2s_master  = 1,
 784                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
 785         },
 786 };
 787
 788 static struct platform_device cardhu_audio_wm8903_device = {
 789         .name   = "tegra-snd-wm8903",
 790         .id     = 0,
 791         .dev    = {
 792                 .platform_data = &cardhu_audio_wm8903_pdata,
 793         },
 794 };
 795
 796 static struct platform_device cardhu_audio_max98095_device = {
 797         .name   = "tegra-snd-max98095",
 798         .id     = 0,
 799         .dev    = {
 800                 .platform_data = &cardhu_audio_max98095_pdata,
 801         },
 802 };
 803
 804 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
 805         .gpio_spkr_en           = -1,
 806         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
 807         .gpio_hp_mute           = -1,
 808         .gpio_int_mic_en        = -1,
 809         .gpio_ext_mic_en        = -1,
 810         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
 811         .i2s_param[HIFI_CODEC]  = {
 812                 .audio_port_id  = 0,
 813                 .is_i2s_master  = 1,
 814                 .i2s_mode       = TEGRA_DAIFMT_I2S,
 815                 .sample_size    = 16,
 816         },
 817         .i2s_param[BT_SCO]      = {
 818                 .sample_size    = 16,
 819                 .audio_port_id  = 3,
 820                 .is_i2s_master  = 1,
 821                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
 822         },
 823 };
 824
 825 static struct platform_device cardhu_audio_aic326x_device = {
 826         .name   = "tegra-snd-aic326x",
 827         .id     = 0,
 828         .dev    = {
 829                 .platform_data  = &cardhu_audio_aic326x_pdata,
 830         },
 831 };
 832
 833 static struct platform_device *cardhu_devices[] __initdata = {
 834         &tegra_pmu_device,
 835         &tegra_rtc_device,
 836         &tegra_udc_device,
 837 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
 838         &tegra_smmu_device,
 839 #endif
 840         &tegra_wdt0_device,
 841         &tegra_wdt1_device,
 842         &tegra_wdt2_device,
 843 #if defined(CONFIG_TEGRA_AVP)
 844         &tegra_avp_device,
 845 #endif
 846         &tegra_camera,
 847 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
 848         &tegra_se_device,
 849 #endif
 850         &tegra_ahub_device,
 851         &tegra_dam_device0,
 852         &tegra_dam_device1,
 853         &tegra_dam_device2,
 854         &tegra_i2s_device0,
 855         &tegra_i2s_device1,
 856         &tegra_i2s_device3,
 857         &tegra_spdif_device,
 858         &spdif_dit_device,
 859         &bluetooth_dit_device,
 860         &baseband_dit_device,
 861         &cardhu_bt_rfkill_device,
 862         &tegra_pcm_device,
 863         &cardhu_audio_wm8903_device,
 864         &cardhu_audio_max98095_device,
 865         &cardhu_audio_aic326x_device,
 866         &tegra_hda_device,
 867         &tegra_cec_device,
 868 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
 869         &tegra_aes_device,
 870 #endif
 871 };
 872
 873 #define E1506_MXT_CONFIG_CRC 0x62F903
 874 static const u8 e1506_config[] = {
 875         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 876         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
 877         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
 878         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
 879         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
 880         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
 881         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 882         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
 883         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 884         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
 885         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 886         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
 887         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
 888         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
 889         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 890         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 891         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 892         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 893         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 894         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 895         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
 896         0x00
 897 };
 898
 899 #define MXT_CONFIG_CRC  0xD62DE8
 900 static const u8 config[] = {
 901         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 902         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
 903         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
 904         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
 905         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
 906         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
 907         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
 908         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 909         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 910         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
 911         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
 912         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
 913         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
 914         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
 915         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 916         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 917         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 918         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
 919         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 920         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 921 };
 922
 923 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
 924 static const u8 config_sku2000[] = {
 925         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 926         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
 927         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
 928         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
 929         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
 930         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
 931         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
 932         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 933         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 934         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 935         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
 936         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
 937         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
 938         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
 939         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 940         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 941         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 942         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
 943         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 944         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 945 };
 946
 947 static struct mxt_platform_data atmel_mxt_info = {
 948         .x_line         = 27,
 949         .y_line         = 42,
 950         .x_size         = 768,
 951         .y_size         = 1366,
 952         .blen           = 0x20,
 953         .threshold      = 0x3C,
 954         .voltage        = 3300000,              /* 3.3V */
 955         .orient         = 5,
 956         .config         = config,
 957         .config_length  = 157,
 958         .config_crc     = MXT_CONFIG_CRC,
 959         .irqflags       = IRQF_TRIGGER_FALLING,
 960 /*      .read_chg       = &read_chg, */
 961         .read_chg       = NULL,
 962 };
 963
 964 static struct mxt_platform_data e1506_atmel_mxt_info = {
 965         .x_line         = 19,
 966         .y_line         = 11,
 967         .x_size         = 960,
 968         .y_size         = 540,
 969         .blen           = 0x10,
 970         .threshold      = 0x32,
 971         .voltage        = 3300000,              /* 3.3V */
 972         .orient         = 3,
 973         .config         = e1506_config,
 974         .config_length  = 168,
 975         .config_crc     = E1506_MXT_CONFIG_CRC,
 976         .irqflags       = IRQF_TRIGGER_FALLING,
 977 /*      .read_chg       = &read_chg, */
 978         .read_chg       = NULL,
 979 };
 980
 981 static struct i2c_board_info __initdata atmel_i2c_info[] = {
 982         {
 983                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
 984                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
 985                 .platform_data = &atmel_mxt_info,
 986         }
 987 };
 988
 989 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
 990         {
 991                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
 992                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
 993                 .platform_data = &e1506_atmel_mxt_info,
 994         }
 995 };
 996
 997 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
 998         /* name         parent          rate            enabled */
 999         { "sbc1",       "pll_p",        52000000,       true},
1000         { NULL,         NULL,           0,              0},
1001 };
1002
1003 static int __init cardhu_touch_init(void)
1004 {
1005         struct board_info BoardInfo, DisplayBoardInfo;
1006
1007         tegra_get_board_info(&BoardInfo);
1008         tegra_get_display_board_info(&DisplayBoardInfo);
1009         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
1010                 tegra_clk_init_from_table(spi_clk_init_table);
1011
1012                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
1013         } else {
1014                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1015                 gpio_direction_input(TEGRA_GPIO_PH4);
1016
1017                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1018                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1019                 msleep(1);
1020                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1021                 msleep(100);
1022
1023                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1024                         atmel_mxt_info.config = config_sku2000;
1025                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1026                 }
1027
1028                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506)
1029                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1030                 else
1031                         i2c_register_board_info(1, atmel_i2c_info, 1);
1032         }
1033
1034         return 0;
1035 }
1036
1037 #if defined(CONFIG_USB_SUPPORT)
1038
1039 static void cardu_usb_hsic_postsupend(void)
1040 {
1041 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1042         baseband_xmm_set_power_status(BBXMM_PS_L2);
1043 #endif
1044 }
1045
1046 static void cardu_usb_hsic_preresume(void)
1047 {
1048 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1049         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1050 #endif
1051 }
1052
1053 static void cardu_usb_hsic_phy_ready(void)
1054 {
1055 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1056         baseband_xmm_set_power_status(BBXMM_PS_L0);
1057 #endif
1058 }
1059
1060 static void cardu_usb_hsic_phy_off(void)
1061 {
1062 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1063         baseband_xmm_set_power_status(BBXMM_PS_L3);
1064 #endif
1065 }
1066
1067 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1068         .post_suspend = cardu_usb_hsic_postsupend,
1069         .pre_resume = cardu_usb_hsic_preresume,
1070         .port_power = cardu_usb_hsic_phy_ready,
1071         .post_phy_off = cardu_usb_hsic_phy_off,
1072 };
1073
1074 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1075         .port_otg = false,
1076         .has_hostpc = true,
1077         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1078         .op_mode        = TEGRA_USB_OPMODE_HOST,
1079         .u_data.host = {
1080                 .vbus_gpio = -1,
1081                 .hot_plug = false,
1082                 .remote_wakeup_supported = false,
1083                 .power_off_on_suspend = false,
1084         },
1085         .ops = &hsic_xmm_plat_ops,
1086 };
1087 #endif
1088
1089 static int hsic_enable_gpio = -1;
1090 static int hsic_reset_gpio = -1;
1091
1092 void hsic_platform_open(void)
1093 {
1094         int reset_gpio = 0, enable_gpio = 0;
1095
1096         if (hsic_enable_gpio != -1)
1097                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1098         if (hsic_reset_gpio != -1)
1099                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1100         /* hsic enable signal deasserted, hsic reset asserted */
1101         if (!enable_gpio)
1102                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1103         if (!reset_gpio)
1104                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1105         /* keep hsic reset asserted for 1 ms */
1106         udelay(1000);
1107         /* enable (power on) hsic */
1108         if (!enable_gpio)
1109                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1110         udelay(1000);
1111         /* deassert reset */
1112         if (!reset_gpio)
1113                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1114
1115 }
1116
1117 void hsic_platform_close(void)
1118 {
1119         if (hsic_enable_gpio != -1) {
1120                 gpio_set_value(hsic_enable_gpio, 0);
1121                 gpio_free(hsic_enable_gpio);
1122         }
1123         if (hsic_reset_gpio != -1) {
1124                 gpio_set_value(hsic_reset_gpio, 0);
1125                 gpio_free(hsic_reset_gpio);
1126         }
1127 }
1128
1129 void hsic_power_on(void)
1130 {
1131         if (hsic_enable_gpio != -1) {
1132                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1133                 udelay(1000);
1134         }
1135 }
1136
1137 void hsic_power_off(void)
1138 {
1139         if (hsic_enable_gpio != -1) {
1140                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1141                 udelay(1000);
1142         }
1143 }
1144
1145 #if defined(CONFIG_USB_SUPPORT)
1146 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1147         .open = hsic_platform_open,
1148         .close = hsic_platform_close,
1149         .pre_phy_on = hsic_power_on,
1150         .post_phy_off = hsic_power_off,
1151 };
1152
1153 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1154         .port_otg = false,
1155         .has_hostpc = true,
1156         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1157         .op_mode        = TEGRA_USB_OPMODE_HOST,
1158         .u_data.host = {
1159                 .vbus_gpio = -1,
1160                 .hot_plug = false,
1161                 .remote_wakeup_supported = false,
1162                 .power_off_on_suspend = false,
1163         },
1164         .ops = &hsic_plat_ops,
1165 };
1166
1167 static struct tegra_usb_platform_data tegra_udc_pdata = {
1168         .port_otg = true,
1169         .has_hostpc = true,
1170         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1171         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1172         .u_data.dev = {
1173                 .vbus_pmu_irq = 0,
1174                 .vbus_gpio = -1,
1175                 .charging_supported = false,
1176                 .remote_wakeup_supported = false,
1177         },
1178         .u_cfg.utmi = {
1179                 .hssync_start_delay = 0,
1180                 .elastic_limit = 16,
1181                 .idle_wait_delay = 17,
1182                 .term_range_adj = 6,
1183                 .xcvr_setup = 8,
1184                 .xcvr_lsfslew = 2,
1185                 .xcvr_lsrslew = 2,
1186                 .xcvr_setup_offset = 0,
1187                 .xcvr_use_fuses = 1,
1188         },
1189 };
1190
1191 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1192         .port_otg = false,
1193         .has_hostpc = true,
1194         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1195         .op_mode        = TEGRA_USB_OPMODE_HOST,
1196         .u_data.host = {
1197                 .vbus_gpio = -1,
1198                 .hot_plug = false,
1199                 .remote_wakeup_supported = true,
1200                 .power_off_on_suspend = true,
1201         },
1202         .u_cfg.utmi = {
1203                 .hssync_start_delay = 0,
1204                 .elastic_limit = 16,
1205                 .idle_wait_delay = 17,
1206                 .term_range_adj = 6,
1207                 .xcvr_setup = 15,
1208                 .xcvr_lsfslew = 2,
1209                 .xcvr_lsrslew = 2,
1210                 .xcvr_setup_offset = 0,
1211                 .xcvr_use_fuses = 1,
1212         },
1213 };
1214
1215 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1216         .port_otg = false,
1217         .has_hostpc = true,
1218         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1219         .op_mode = TEGRA_USB_OPMODE_HOST,
1220         .u_data.host = {
1221                 .vbus_gpio = -1,
1222                 .vbus_reg = "vdd_vbus_typea_usb",
1223                 .hot_plug = true,
1224                 .remote_wakeup_supported = true,
1225                 .power_off_on_suspend = true,
1226         },
1227         .u_cfg.utmi = {
1228                 .hssync_start_delay = 0,
1229                 .elastic_limit = 16,
1230                 .idle_wait_delay = 17,
1231                 .term_range_adj = 6,
1232                 .xcvr_setup = 8,
1233                 .xcvr_lsfslew = 2,
1234                 .xcvr_lsrslew = 2,
1235                 .xcvr_setup_offset = 0,
1236                 .xcvr_use_fuses = 1,
1237         },
1238 };
1239
1240 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1241         .port_otg = true,
1242         .has_hostpc = true,
1243         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1244         .op_mode = TEGRA_USB_OPMODE_HOST,
1245         .u_data.host = {
1246                 .vbus_gpio = -1,
1247                 .vbus_reg = "vdd_vbus_micro_usb",
1248                 .hot_plug = true,
1249                 .remote_wakeup_supported = true,
1250                 .power_off_on_suspend = true,
1251         },
1252         .u_cfg.utmi = {
1253                 .hssync_start_delay = 0,
1254                 .elastic_limit = 16,
1255                 .idle_wait_delay = 17,
1256                 .term_range_adj = 6,
1257                 .xcvr_setup = 15,
1258                 .xcvr_lsfslew = 2,
1259                 .xcvr_lsrslew = 2,
1260                 .xcvr_setup_offset = 0,
1261                 .xcvr_use_fuses = 1,
1262         },
1263 };
1264
1265 static struct tegra_usb_otg_data tegra_otg_pdata = {
1266         .ehci_device = &tegra_ehci1_device,
1267         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1268 };
1269 #endif
1270
1271 #if defined(CONFIG_USB_SUPPORT)
1272 static void cardhu_usb_init(void)
1273 {
1274         struct board_info bi;
1275
1276         tegra_get_board_info(&bi);
1277
1278         /* OTG should be the first to be registered */
1279         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1280         platform_device_register(&tegra_otg_device);
1281
1282         /* setup the udc platform data */
1283         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1284
1285         if (bi.board_id == BOARD_PM267) {
1286                 hsic_enable_gpio = EN_HSIC_GPIO;
1287                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1288                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1289                 platform_device_register(&tegra_ehci2_device);
1290         } else if (bi.board_id == BOARD_E1256) {
1291                 hsic_enable_gpio = EN_HSIC_GPIO;
1292                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1293                 platform_device_register(&tegra_ehci2_device);
1294         } else if (bi.board_id == BOARD_E1186) {
1295                 tegra_ehci2_device.dev.platform_data =
1296                                                 &tegra_ehci2_hsic_xmm_pdata;
1297                 /* ehci2 registration happens in baseband-xmm-power  */
1298         } else {
1299                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1300                 platform_device_register(&tegra_ehci2_device);
1301         }
1302
1303         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1304         platform_device_register(&tegra_ehci3_device);
1305
1306 }
1307 #else
1308 static void cardhu_usb_init(void) { }
1309 #endif
1310
1311 static struct baseband_power_platform_data tegra_baseband_power_data = {
1312         .baseband_type = BASEBAND_XMM,
1313         .modem = {
1314         .xmm = {
1315                         .bb_rst = XMM_GPIO_BB_RST,
1316                         .bb_on = XMM_GPIO_BB_ON,
1317                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1318                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1319                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1320                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1321                         .hsic_device = &tegra_ehci2_device,
1322                 },
1323         },
1324 };
1325
1326 static struct platform_device tegra_baseband_power_device = {
1327         .name = "baseband_xmm_power",
1328         .id = -1,
1329         .dev = {
1330                 .platform_data = &tegra_baseband_power_data,
1331         },
1332 };
1333
1334 static struct platform_device tegra_baseband_power2_device = {
1335         .name = "baseband_xmm_power2",
1336         .id = -1,
1337         .dev = {
1338                 .platform_data = &tegra_baseband_power_data,
1339         },
1340 };
1341
1342
1343 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1344         .port_status[0] = 1,
1345         .port_status[1] = 1,
1346         .port_status[2] = 1,
1347         .use_dock_detect        = 0,
1348         .gpio           = 0,
1349 };
1350
1351 static void cardhu_pci_init(void)
1352 {
1353         struct board_info board_info;
1354
1355         tegra_get_board_info(&board_info);
1356         if (board_info.board_id == BOARD_E1291) {
1357                 cardhu_pci_platform_data.port_status[0] = 0;
1358                 cardhu_pci_platform_data.port_status[1] = 0;
1359                 cardhu_pci_platform_data.port_status[2] = 1;
1360                 cardhu_pci_platform_data.use_dock_detect = 1;
1361                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1362         }
1363         if ((board_info.board_id == BOARD_E1186) ||
1364                 (board_info.board_id == BOARD_E1187) ||
1365                 (board_info.board_id == BOARD_E1291)) {
1366                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1367                 platform_device_register(&tegra_pci_device);
1368         }
1369 }
1370
1371 static void cardhu_modem_init(void)
1372 {
1373         struct board_info board_info;
1374         int w_disable_gpio, ret;
1375
1376         tegra_get_board_info(&board_info);
1377         switch (board_info.board_id) {
1378         case BOARD_E1291:
1379         case BOARD_E1198:
1380                 if (((board_info.board_id == BOARD_E1291) &&
1381                                 (board_info.fab < BOARD_FAB_A03)) ||
1382                         ((board_info.board_id == BOARD_E1198) &&
1383                                         (board_info.fab < BOARD_FAB_A02))) {
1384                         w_disable_gpio = TEGRA_GPIO_PH5;
1385                 } else {
1386                         w_disable_gpio = TEGRA_GPIO_PDD5;
1387                 }
1388
1389                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1390                 if (ret < 0)
1391                         pr_err("%s: gpio_request failed for gpio %d\n",
1392                                 __func__, w_disable_gpio);
1393                 else
1394                         gpio_direction_input(w_disable_gpio);
1395
1396                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1397                 if (((board_info.board_id == BOARD_E1291) &&
1398                                 (board_info.fab >= BOARD_FAB_A04)) ||
1399                         ((board_info.board_id == BOARD_E1198) &&
1400                                         (board_info.fab >= BOARD_FAB_A02))) {
1401                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1402                         if (ret < 0) {
1403                                 pr_err("%s(): Error in allocating gpio "
1404                                         "TEGRA_GPIO_PH7\n", __func__);
1405                                 break;
1406                         }
1407                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1408                 }
1409                 break;
1410         case BOARD_E1186:
1411                 platform_device_register(&tegra_baseband_power_device);
1412                 platform_device_register(&tegra_baseband_power2_device);
1413                 break;
1414         default:
1415                 break;
1416         }
1417
1418 }
1419
1420 #ifdef CONFIG_SATA_AHCI_TEGRA
1421 static void cardhu_sata_init(void)
1422 {
1423         platform_device_register(&tegra_sata_device);
1424 }
1425 #else
1426 static void cardhu_sata_init(void) { }
1427 #endif
1428
1429 static void __init tegra_cardhu_init(void)
1430 {
1431         tegra_thermal_init(&thermal_data,
1432                                 throttle_list,
1433                                 ARRAY_SIZE(throttle_list));
1434         tegra_clk_init_from_table(cardhu_clk_init_table);
1435         cardhu_pinmux_init();
1436         cardhu_i2c_init();
1437         cardhu_spi_init();
1438         cardhu_usb_init();
1439 #ifdef CONFIG_TEGRA_EDP_LIMITS
1440         cardhu_edp_init();
1441 #endif
1442         cardhu_uart_init();
1443         tegra_camera_init();
1444         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1445         tegra_ram_console_debug_init();
1446         tegra_io_dpd_init();
1447         cardhu_sdhci_init();
1448         cardhu_regulator_init();
1449         cardhu_dtv_init();
1450         cardhu_suspend_init();
1451         cardhu_touch_init();
1452         cardhu_modem_init();
1453         cardhu_kbc_init();
1454         cardhu_scroll_init();
1455         cardhu_keys_init();
1456         cardhu_panel_init();
1457         cardhu_pmon_init();
1458         cardhu_sensors_init();
1459         cardhu_setup_bluesleep();
1460         cardhu_sata_init();
1461         //audio_wired_jack_init();
1462         cardhu_pins_state_init();
1463         cardhu_emc_init();
1464         tegra_release_bootloader_fb();
1465         cardhu_pci_init();
1466 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1467         tegra_wdt_recovery_init();
1468 #endif
1469         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1470 }
1471
1472 static void __init tegra_cardhu_reserve(void)
1473 {
1474 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1475         /* Support 1920X1080 32bpp,double buffered on HDMI*/
1476         tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M);
1477 #else
1478         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1479 #endif
1480         tegra_ram_console_debug_reserve(SZ_1M);
1481 }
1482
1483 static const char *cardhu_dt_board_compat[] = {
1484         "nvidia,cardhu",
1485         NULL
1486 };
1487
1488 MACHINE_START(CARDHU, "cardhu")
1489         .boot_params    = 0x80000100,
1490         .map_io         = tegra_map_common_io,
1491         .reserve        = tegra_cardhu_reserve,
1492         .init_early     = tegra_init_early,
1493         .init_irq       = tegra_init_irq,
1494         .timer          = &tegra_timer,
1495         .init_machine   = tegra_cardhu_init,
1496         .dt_compat      = cardhu_dt_board_compat,
1497 MACHINE_END