ARM: tegra: integration of slave mode support.
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  * Copyright (c) 2011-2012, NVIDIA Corporation.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/serial_8250.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/panjit_ts.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/gpio.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/spi/spi.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44
45 #include <sound/wm8903.h>
46 #include <sound/max98095.h>
47 #include <media/tegra_dtv.h>
48
49 #include <asm/hardware/gic.h>
50
51 #include <mach/clk.h>
52 #include <mach/iomap.h>
53 #include <mach/irqs.h>
54 #include <mach/pinmux.h>
55 #include <mach/iomap.h>
56 #include <mach/io_dpd.h>
57 #include <mach/io.h>
58 #include <mach/i2s.h>
59 #include <mach/tegra_asoc_pdata.h>
60 #include <mach/tegra_wm8903_pdata.h>
61 #include <mach/usb_phy.h>
62 #include <mach/thermal.h>
63 #include <mach/pci.h>
64 #include <mach/gpio-tegra.h>
65 #include <mach/tegra_fiq_debugger.h>
66
67 #include <asm/hardware/gic.h>
68 #include <asm/mach-types.h>
69 #include <asm/mach/arch.h>
70
71 #include "board.h"
72 #include "clock.h"
73 #include "board-cardhu.h"
74 #include "board-touch.h"
75 #include "devices.h"
76 #include "gpio-names.h"
77 #include "fuse.h"
78 #include "pm.h"
79 #include "baseband-xmm-power.h"
80 #include "wdt-recovery.h"
81 #include "common.h"
82
83 static struct balanced_throttle throttle_list[] = {
84 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
85         {
86                 .id = BALANCED_THROTTLE_ID_TJ,
87                 .throt_tab_size = 10,
88                 .throt_tab = {
89                         {      0, 1000 },
90                         { 640000, 1000 },
91                         { 640000, 1000 },
92                         { 640000, 1000 },
93                         { 640000, 1000 },
94                         { 640000, 1000 },
95                         { 760000, 1000 },
96                         { 760000, 1050 },
97                         {1000000, 1050 },
98                         {1000000, 1100 },
99                 },
100         },
101 #endif
102 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
103         {
104                 .id = BALANCED_THROTTLE_ID_SKIN,
105                 .throt_tab_size = 6,
106                 .throt_tab = {
107                         { 640000, 1200 },
108                         { 640000, 1200 },
109                         { 760000, 1200 },
110                         { 760000, 1200 },
111                         {1000000, 1200 },
112                         {1000000, 1200 },
113                 },
114         },
115 #endif
116 };
117
118 /* All units are in millicelsius */
119 static struct tegra_thermal_data thermal_data = {
120         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
121         .temp_shutdown = 90000,
122
123 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
124         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
125 #endif
126 #ifdef CONFIG_TEGRA_EDP_LIMITS
127         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
128         .hysteresis_edp = 3000,
129 #endif
130 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
131         .temp_throttle = 85000,
132         .tc1 = 0,
133         .tc2 = 1,
134         .passive_delay = 2000,
135 #endif
136 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
137         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
138         .temp_throttle_skin = 43000,
139         .tc1_skin = 0,
140         .tc2_skin = 1,
141         .passive_delay_skin = 5000,
142
143         .skin_temp_offset = 9793,
144         .skin_period = 1100,
145         .skin_devs_size = 2,
146         .skin_devs = {
147                 {
148                         THERMAL_DEVICE_ID_NCT_EXT,
149                         {
150                                 2, 1, 1, 1,
151                                 1, 1, 1, 1,
152                                 1, 1, 1, 0,
153                                 1, 1, 0, 0,
154                                 0, 0, -1, -7
155                         }
156                 },
157                 {
158                         THERMAL_DEVICE_ID_NCT_INT,
159                         {
160                                 -11, -7, -5, -3,
161                                 -3, -2, -1, 0,
162                                 0, 0, 1, 1,
163                                 1, 2, 2, 3,
164                                 4, 6, 11, 18
165                         }
166                 },
167         },
168 #endif
169 };
170
171 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
172         {
173                 .name           = "bt_rfkill",
174                 .shutdown_gpio  = TEGRA_GPIO_PU0,
175                 .reset_gpio     = TEGRA_GPIO_INVALID,
176                 .type           = RFKILL_TYPE_BLUETOOTH,
177         },
178 };
179
180 static struct platform_device cardhu_bt_rfkill_device = {
181         .name = "rfkill_gpio",
182         .id             = -1,
183         .dev = {
184                 .platform_data = &cardhu_bt_rfkill_pdata,
185         },
186 };
187
188 static struct resource cardhu_bluesleep_resources[] = {
189         [0] = {
190                 .name = "gpio_host_wake",
191                         .start  = TEGRA_GPIO_PU6,
192                         .end    = TEGRA_GPIO_PU6,
193                         .flags  = IORESOURCE_IO,
194         },
195         [1] = {
196                 .name = "gpio_ext_wake",
197                         .start  = TEGRA_GPIO_PU1,
198                         .end    = TEGRA_GPIO_PU1,
199                         .flags  = IORESOURCE_IO,
200         },
201         [2] = {
202                 .name = "host_wake",
203                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
204         },
205 };
206
207 static struct platform_device cardhu_bluesleep_device = {
208         .name           = "bluesleep",
209         .id             = -1,
210         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
211         .resource       = cardhu_bluesleep_resources,
212 };
213
214 static noinline void __init cardhu_setup_bluesleep(void)
215 {
216         cardhu_bluesleep_resources[2].start =
217                 cardhu_bluesleep_resources[2].end =
218                         gpio_to_irq(TEGRA_GPIO_PU6);
219         platform_device_register(&cardhu_bluesleep_device);
220         return;
221 }
222
223 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
224         /* name         parent          rate            enabled */
225         { "pll_m",      NULL,           0,              false},
226         { "hda",        "pll_p",        108000000,      false},
227         { "hda2codec_2x","pll_p",       48000000,       false},
228         { "pwm",        "pll_p",        3187500,        false},
229         { "blink",      "clk_32k",      32768,          true},
230         { "i2s0",       "pll_a_out0",   0,              false},
231         { "i2s1",       "pll_a_out0",   0,              false},
232         { "i2s3",       "pll_a_out0",   0,              false},
233         { "spdif_out",  "pll_a_out0",   0,              false},
234         { "d_audio",    "clk_m",        12000000,       false},
235         { "dam0",       "clk_m",        12000000,       false},
236         { "dam1",       "clk_m",        12000000,       false},
237         { "dam2",       "clk_m",        12000000,       false},
238         { "audio1",     "i2s1_sync",    0,              false},
239         { "audio3",     "i2s3_sync",    0,              false},
240         { "vi_sensor",  "pll_p",        150000000,      false},
241         { "i2c1",       "pll_p",        3200000,        false},
242         { "i2c2",       "pll_p",        3200000,        false},
243         { "i2c3",       "pll_p",        3200000,        false},
244         { "i2c4",       "pll_p",        3200000,        false},
245         { "i2c5",       "pll_p",        3200000,        false},
246         { "vi",         "pll_p",        0,              false},
247         { NULL,         NULL,           0,              0},
248 };
249
250 static struct pn544_i2c_platform_data nfc_pdata = {
251         .irq_gpio = TEGRA_GPIO_PX0,
252         .ven_gpio = TEGRA_GPIO_PP3,
253         .firm_gpio = TEGRA_GPIO_PO7,
254         };
255
256 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
257         {
258                 I2C_BOARD_INFO("pn544", 0x28),
259                 .platform_data = &nfc_pdata,
260         },
261 };
262 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
263         .adapter_nr     = 0,
264         .bus_count      = 1,
265         .bus_clk_rate   = { 100000, 0 },
266         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
267         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
268         .arb_recovery = arb_lost_recovery,
269 };
270
271 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
272         .adapter_nr     = 1,
273         .bus_count      = 1,
274         .bus_clk_rate   = { 400000, 0 },
275         .is_clkon_always = true,
276         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
277         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
278         .arb_recovery = arb_lost_recovery,
279 };
280
281 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
282         .adapter_nr     = 2,
283         .bus_count      = 1,
284         .bus_clk_rate   = { 100000, 0 },
285         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
286         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
287         .arb_recovery = arb_lost_recovery,
288 };
289
290 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
291         .adapter_nr     = 3,
292         .bus_count      = 1,
293         .bus_clk_rate   = { 10000, 0 },
294         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
295         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
296         .arb_recovery = arb_lost_recovery,
297 };
298
299 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
300         .adapter_nr     = 4,
301         .bus_count      = 1,
302         .bus_clk_rate   = { 400000, 0 },
303         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
304         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
305         .arb_recovery = arb_lost_recovery,
306 };
307
308
309 #if 0
310 struct tegra_wired_jack_conf audio_wr_jack_conf = {
311         .hp_det_n = TEGRA_GPIO_PW2,
312         .en_mic_ext = TEGRA_GPIO_PX1,
313         .en_mic_int = TEGRA_GPIO_PX0,
314 };
315 #endif
316
317 static struct wm8903_platform_data cardhu_wm8903_pdata = {
318         .irq_active_low = 0,
319         .micdet_cfg = 0,
320         .micdet_delay = 100,
321         .gpio_base = CARDHU_GPIO_WM8903(0),
322         .gpio_cfg = {
323                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
324                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
325                         WM8903_GP2_DIR,
326                 WM8903_GPIO_CONFIG_ZERO,
327                 0,
328                 0,
329         },
330 };
331
332 /* Equalizer filter coefs generated from the MAXIM MAX98095
333  * evkit software tool */
334 static struct max98095_eq_cfg max98095_eq_cfg[] = {
335         {
336                 .name = "FLAT",
337                 .rate = 44100,
338                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
339                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
340                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
341                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
342                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
343         },
344         {
345                 .name = "LOWPASS1K",
346                 .rate = 44100,
347                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
348                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
349                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
350                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
351                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
352         },
353         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
354                 .name = "HIBOOST",
355                 .rate = 44100,
356                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
357                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
358                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
359                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
360                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
361         },
362         { /* BASS=12dB, TREBLE=+12dB */
363                 .name = "LOUD12DB",
364                 .rate = 44100,
365                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
366                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
367                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
368                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
369                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
370         },
371         {
372                 .name = "FLAT",
373                 .rate = 16000,
374                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
375                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
376                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
377                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
378                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
379         },
380         {
381                 .name = "LOWPASS1K",
382                 .rate = 16000,
383                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
384                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
385                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
386                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
387                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
388         },
389         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
390                 .name = "HIBOOST",
391                 .rate = 16000,
392                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
393                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
394                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
395                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
396                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
397         },
398         { /* BASS=12dB, TREBLE=+12dB */
399                 .name = "LOUD12DB",
400                 .rate = 16000,
401                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
402                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
403                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
404                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
405                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
406         },
407 };
408
409 static struct max98095_pdata cardhu_max98095_pdata = {
410         /* equalizer configuration */
411         .eq_cfg = max98095_eq_cfg,
412         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
413
414         /* Biquad filter response configuration */
415         .bq_cfg = NULL,
416         .bq_cfgcnt = 0,
417
418         /* microphone configuration */
419         .digmic_left_mode = 1,
420         .digmic_right_mode = 1,
421 };
422
423 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
424         I2C_BOARD_INFO("wm8903", 0x1a),
425         .platform_data = &cardhu_wm8903_pdata,
426 };
427
428 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
429         I2C_BOARD_INFO("aic3262-codec", 0x18),
430 };
431
432 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
433         I2C_BOARD_INFO("max98095", 0x10),
434         .platform_data = &cardhu_max98095_pdata,
435 };
436
437 static void cardhu_i2c_init(void)
438 {
439         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
440         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
441         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
442         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
443         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
444
445         platform_device_register(&tegra_i2c_device5);
446         platform_device_register(&tegra_i2c_device4);
447         platform_device_register(&tegra_i2c_device3);
448         platform_device_register(&tegra_i2c_device2);
449         platform_device_register(&tegra_i2c_device1);
450
451         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
452                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
453         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
454         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
455         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
456
457         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
458         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
459 }
460
461 static struct platform_device *cardhu_uart_devices[] __initdata = {
462         &tegra_uarta_device,
463         &tegra_uartb_device,
464         &tegra_uartc_device,
465         &tegra_uartd_device,
466         &tegra_uarte_device,
467 };
468 static struct uart_clk_parent uart_parent_clk[] = {
469         [0] = {.name = "clk_m"},
470         [1] = {.name = "pll_p"},
471 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
472         [2] = {.name = "pll_m"},
473 #endif
474 };
475
476 static struct tegra_uart_platform_data cardhu_uart_pdata;
477 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
478
479 static void __init uart_debug_init(void)
480 {
481         struct board_info board_info;
482         int debug_port_id;
483
484         tegra_get_board_info(&board_info);
485
486         debug_port_id = get_tegra_uart_debug_port_id();
487         if (debug_port_id < 0) {
488                 debug_port_id = 0;
489                         /* UARTB is debug port
490                          *       for SLT - E1186/E1187/PM269
491                          *       for E1256/E1257
492                          */
493                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
494                         ((board_info.board_id == BOARD_E1186) ||
495                         (board_info.board_id == BOARD_E1187) ||
496                         (board_info.board_id == BOARD_PM269))) ||
497                         (board_info.board_id == BOARD_E1256) ||
498                         (board_info.board_id == BOARD_E1257))
499                                 debug_port_id = 1;
500         }
501
502 #ifdef CONFIG_TEGRA_IRDA
503         if ((board_info.board_id == BOARD_E1186) ||
504                 (board_info.board_id == BOARD_E1198)) {
505                 if (debug_port_id == 1) {
506                         cardhu_irda_pdata.is_irda = false;
507                         pr_err("UARTB is not available for IrDA\n");
508                 }
509         }
510 #endif
511
512         switch (debug_port_id) {
513         case 0:
514                 /* UARTA is the debug port. */
515                 pr_info("Selecting UARTA as the debug console\n");
516                 cardhu_uart_devices[0] = &debug_uarta_device;
517                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
518                 debug_uart_port_base = ((struct plat_serial8250_port *)(
519                         debug_uarta_device.dev.platform_data))->mapbase;
520                 break;
521
522         case 1:
523                 /* UARTB is the debug port. */
524                 pr_info("Selecting UARTB as the debug console\n");
525                 cardhu_uart_devices[1] = &debug_uartb_device;
526                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
527                 debug_uart_port_base = ((struct plat_serial8250_port *)(
528                         debug_uartb_device.dev.platform_data))->mapbase;
529                 break;
530
531         case 2:
532                 /* UARTC is the debug port. */
533                 pr_info("Selecting UARTC as the debug console\n");
534                 cardhu_uart_devices[2] = &debug_uartc_device;
535                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
536                 debug_uart_port_base = ((struct plat_serial8250_port *)(
537                         debug_uartc_device.dev.platform_data))->mapbase;
538                 break;
539
540         case 3:
541                 /* UARTD is the debug port. */
542                 pr_info("Selecting UARTD as the debug console\n");
543                 cardhu_uart_devices[3] = &debug_uartd_device;
544                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
545                 debug_uart_port_base = ((struct plat_serial8250_port *)(
546                         debug_uartd_device.dev.platform_data))->mapbase;
547                 break;
548
549         case 4:
550                 /* UARTE is the debug port. */
551                 pr_info("Selecting UARTE as the debug console\n");
552                 cardhu_uart_devices[4] = &debug_uarte_device;
553                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
554                 debug_uart_port_base = ((struct plat_serial8250_port *)(
555                         debug_uarte_device.dev.platform_data))->mapbase;
556                 break;
557
558         default:
559                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
560                 cardhu_uart_devices[0] = &debug_uarta_device;
561                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
562                 debug_uart_port_base = ((struct plat_serial8250_port *)(
563                         debug_uarta_device.dev.platform_data))->mapbase;
564                 break;
565         }
566         return;
567 }
568
569 static void __init cardhu_uart_init(void)
570 {
571         struct clk *c;
572         int i;
573         struct board_info board_info;
574
575         tegra_get_board_info(&board_info);
576
577         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
578                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
579                 if (IS_ERR_OR_NULL(c)) {
580                         pr_err("Not able to get the clock for %s\n",
581                                                 uart_parent_clk[i].name);
582                         continue;
583                 }
584                 uart_parent_clk[i].parent_clk = c;
585                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
586         }
587         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
588         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
589         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
590         cardhu_loopback_uart_pdata.parent_clk_count =
591                                                 ARRAY_SIZE(uart_parent_clk);
592         cardhu_loopback_uart_pdata.is_loopback = true;
593         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
594         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
595         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
596         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
597         /* UARTE is used for loopback test purpose */
598         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
599
600         /* Register low speed only if it is selected */
601         if (!is_tegra_debug_uartport_hs()) {
602                 uart_debug_init();
603                 /* Clock enable for the debug channel */
604                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
605                         pr_info("The debug console clock name is %s\n",
606                                                 debug_uart_clk->name);
607                         c = tegra_get_clock_by_name("pll_p");
608                         if (IS_ERR_OR_NULL(c))
609                                 pr_err("Not getting the parent clock pll_p\n");
610                         else
611                                 clk_set_parent(debug_uart_clk, c);
612
613                         clk_enable(debug_uart_clk);
614                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
615                 } else {
616                         pr_err("Not getting the clock %s for debug console\n",
617                                         debug_uart_clk->name);
618                 }
619         }
620
621 #ifdef CONFIG_TEGRA_IRDA
622         if (((board_info.board_id == BOARD_E1186) ||
623                 (board_info.board_id == BOARD_E1198)) &&
624                         cardhu_irda_pdata.is_irda) {
625                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
626                 cardhu_irda_pdata.parent_clk_count =
627                                         ARRAY_SIZE(uart_parent_clk);
628
629                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
630         }
631 #endif
632
633         platform_add_devices(cardhu_uart_devices,
634                                 ARRAY_SIZE(cardhu_uart_devices));
635 }
636
637 static struct platform_device tegra_camera = {
638         .name = "tegra_camera",
639         .id = -1,
640 };
641
642 static struct platform_device *cardhu_spi_devices[] __initdata = {
643         &tegra_spi_device4,
644 };
645
646 static struct platform_device *touch_spi_device[] __initdata = {
647         &tegra_spi_device1,
648 };
649
650 struct spi_clk_parent spi_parent_clk[] = {
651         [0] = {.name = "pll_p"},
652 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
653         [1] = {.name = "pll_m"},
654         [2] = {.name = "clk_m"},
655 #else
656         [1] = {.name = "clk_m"},
657 #endif
658 };
659
660 static struct tegra_spi_platform_data cardhu_spi_pdata = {
661         .is_dma_based           = true,
662         .max_dma_buffer         = (16 * 1024),
663         .is_clkon_always        = false,
664         .max_rate               = 100000000,
665 };
666
667 static void __init cardhu_spi_init(void)
668 {
669         int i;
670         struct clk *c;
671         struct board_info board_info, display_board_info;
672
673         tegra_get_board_info(&board_info);
674         tegra_get_display_board_info(&display_board_info);
675
676         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
677                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
678                 if (IS_ERR_OR_NULL(c)) {
679                         pr_err("Not able to get the clock for %s\n",
680                                                 spi_parent_clk[i].name);
681                         continue;
682                 }
683                 spi_parent_clk[i].parent_clk = c;
684                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
685         }
686         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
687         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
688         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
689         platform_add_devices(cardhu_spi_devices,
690                                 ARRAY_SIZE(cardhu_spi_devices));
691
692         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
693                 platform_add_devices(touch_spi_device,
694                                 ARRAY_SIZE(touch_spi_device));
695         }
696         if (board_info.board_id == BOARD_E1198) {
697                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
698                 platform_device_register(&tegra_spi_device2);
699                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
700                 platform_device_register(&tegra_spi_slave_device1);
701         }
702 }
703
704 static void __init cardhu_dtv_init(void)
705 {
706         struct board_info board_info;
707
708         tegra_get_board_info(&board_info);
709
710         if (board_info.board_id == BOARD_E1186)
711                 platform_device_register(&tegra_dtv_device);
712 }
713
714 static struct resource tegra_rtc_resources[] = {
715         [0] = {
716                 .start = TEGRA_RTC_BASE,
717                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
718                 .flags = IORESOURCE_MEM,
719         },
720         [1] = {
721                 .start = INT_RTC,
722                 .end = INT_RTC,
723                 .flags = IORESOURCE_IRQ,
724         },
725 };
726
727 static struct platform_device tegra_rtc_device = {
728         .name = "tegra_rtc",
729         .id   = -1,
730         .resource = tegra_rtc_resources,
731         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
732 };
733
734 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
735         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
736         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
737         .gpio_hp_mute           = -1,
738         .gpio_int_mic_en        = -1,
739         .gpio_ext_mic_en        = -1,
740         .i2s_param[HIFI_CODEC]  = {
741                 .audio_port_id  = 0,
742                 .is_i2s_master  = 1,
743                 .i2s_mode       = TEGRA_DAIFMT_I2S,
744         },
745         .i2s_param[BASEBAND]    = {
746                 .audio_port_id  = -1,
747         },
748         .i2s_param[BT_SCO]      = {
749                 .audio_port_id  = 3,
750                 .is_i2s_master  = 1,
751                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
752         },
753 };
754
755 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
756         .gpio_spkr_en           = -1,
757         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
758         .gpio_hp_mute           = -1,
759         .gpio_int_mic_en        = -1,
760         .gpio_ext_mic_en        = -1,
761         .i2s_param[HIFI_CODEC]  = {
762                 .audio_port_id  = 0,
763                 .is_i2s_master  = 1,
764                 .i2s_mode       = TEGRA_DAIFMT_I2S,
765         },
766         .i2s_param[BASEBAND]    = {
767                 .audio_port_id  = -1,
768         },
769         .i2s_param[BT_SCO]      = {
770                 .audio_port_id  = 3,
771                 .is_i2s_master  = 1,
772                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
773         },
774 };
775
776 static struct platform_device cardhu_audio_wm8903_device = {
777         .name   = "tegra-snd-wm8903",
778         .id     = 0,
779         .dev    = {
780                 .platform_data = &cardhu_audio_wm8903_pdata,
781         },
782 };
783
784 static struct platform_device cardhu_audio_max98095_device = {
785         .name   = "tegra-snd-max98095",
786         .id     = 0,
787         .dev    = {
788                 .platform_data = &cardhu_audio_max98095_pdata,
789         },
790 };
791
792 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
793         .gpio_spkr_en           = -1,
794         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
795         .gpio_hp_mute           = -1,
796         .gpio_int_mic_en        = -1,
797         .gpio_ext_mic_en        = -1,
798         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
799         .i2s_param[HIFI_CODEC]  = {
800                 .audio_port_id  = 0,
801                 .is_i2s_master  = 1,
802                 .i2s_mode       = TEGRA_DAIFMT_I2S,
803                 .sample_size    = 16,
804         },
805         .i2s_param[BT_SCO]      = {
806                 .sample_size    = 16,
807                 .audio_port_id  = 3,
808                 .is_i2s_master  = 1,
809                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
810         },
811 };
812
813 static struct platform_device cardhu_audio_aic326x_device = {
814         .name   = "tegra-snd-aic326x",
815         .id     = 0,
816         .dev    = {
817                 .platform_data  = &cardhu_audio_aic326x_pdata,
818         },
819 };
820
821 static struct platform_device *cardhu_devices[] __initdata = {
822         &tegra_pmu_device,
823         &tegra_rtc_device,
824         &tegra_udc_device,
825 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
826         &tegra_smmu_device,
827 #endif
828         &tegra_wdt0_device,
829         &tegra_wdt1_device,
830         &tegra_wdt2_device,
831 #if defined(CONFIG_TEGRA_AVP)
832         &tegra_avp_device,
833 #endif
834         &tegra_camera,
835 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
836         &tegra_se_device,
837 #endif
838         &tegra_ahub_device,
839         &tegra_dam_device0,
840         &tegra_dam_device1,
841         &tegra_dam_device2,
842         &tegra_i2s_device0,
843         &tegra_i2s_device1,
844         &tegra_i2s_device3,
845         &tegra_spdif_device,
846         &spdif_dit_device,
847         &bluetooth_dit_device,
848         &baseband_dit_device,
849         &cardhu_bt_rfkill_device,
850         &tegra_pcm_device,
851         &cardhu_audio_wm8903_device,
852         &cardhu_audio_max98095_device,
853         &cardhu_audio_aic326x_device,
854         &tegra_hda_device,
855         &tegra_cec_device,
856 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
857         &tegra_aes_device,
858 #endif
859 };
860
861 #define E1506_MXT_CONFIG_CRC 0x62F903
862 static const u8 e1506_config[] = {
863         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
865         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
866         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
867         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
868         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
869         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
870         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
871         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
873         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
875         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
876         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
877         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
878         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
879         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
880         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
881         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
882         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
883         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
884         0x00
885 };
886
887 #define MXT_CONFIG_CRC  0xD62DE8
888 static const u8 config[] = {
889         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
890         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
891         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
892         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
893         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
894         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
895         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
896         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
897         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
899         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
900         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
901         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
902         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
903         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
904         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
906         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
907         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
908         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
909 };
910
911 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
912 static const u8 config_sku2000[] = {
913         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
914         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
915         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
916         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
917         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
918         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
919         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
920         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
921         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
922         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
923         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
924         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
925         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
926         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
927         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
928         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
929         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
930         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
931         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
932         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
933 };
934
935 static struct mxt_platform_data atmel_mxt_info = {
936         .x_line         = 27,
937         .y_line         = 42,
938         .x_size         = 768,
939         .y_size         = 1366,
940         .blen           = 0x20,
941         .threshold      = 0x3C,
942         .voltage        = 3300000,              /* 3.3V */
943         .orient         = 5,
944         .config         = config,
945         .config_length  = 157,
946         .config_crc     = MXT_CONFIG_CRC,
947         .irqflags       = IRQF_TRIGGER_FALLING,
948 /*      .read_chg       = &read_chg, */
949         .read_chg       = NULL,
950 };
951
952 static struct mxt_platform_data e1506_atmel_mxt_info = {
953         .x_line         = 19,
954         .y_line         = 11,
955         .x_size         = 960,
956         .y_size         = 540,
957         .blen           = 0x10,
958         .threshold      = 0x32,
959         .voltage        = 3300000,              /* 3.3V */
960         .orient         = 3,
961         .config         = e1506_config,
962         .config_length  = 168,
963         .config_crc     = E1506_MXT_CONFIG_CRC,
964         .irqflags       = IRQF_TRIGGER_FALLING,
965 /*      .read_chg       = &read_chg, */
966         .read_chg       = NULL,
967 };
968
969 static struct i2c_board_info __initdata atmel_i2c_info[] = {
970         {
971                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
972                 .platform_data = &atmel_mxt_info,
973         }
974 };
975
976 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
977         {
978                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
979                 .platform_data = &e1506_atmel_mxt_info,
980         }
981 };
982
983 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
984         /* name         parent          rate            enabled */
985         { "sbc1",       "pll_p",        52000000,       true},
986         { NULL,         NULL,           0,              0},
987 };
988
989 static int __init cardhu_touch_init(void)
990 {
991         struct board_info BoardInfo, DisplayBoardInfo;
992
993         tegra_get_board_info(&BoardInfo);
994         tegra_get_display_board_info(&DisplayBoardInfo);
995         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
996                 tegra_clk_init_from_table(spi_clk_init_table);
997
998                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
999         } else {
1000                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1001                 gpio_direction_input(TEGRA_GPIO_PH4);
1002
1003                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1004                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1005                 msleep(1);
1006                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1007                 msleep(100);
1008
1009                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1010                         atmel_mxt_info.config = config_sku2000;
1011                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1012                 }
1013
1014                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1015                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1016                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1017                 } else {
1018                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1019                         i2c_register_board_info(1, atmel_i2c_info, 1);
1020                 }
1021         }
1022
1023         return 0;
1024 }
1025
1026 #if defined(CONFIG_USB_SUPPORT)
1027
1028 static void cardu_usb_hsic_postsupend(void)
1029 {
1030 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1031         baseband_xmm_set_power_status(BBXMM_PS_L2);
1032 #endif
1033 }
1034
1035 static void cardu_usb_hsic_preresume(void)
1036 {
1037 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1038         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1039 #endif
1040 }
1041
1042 static void cardu_usb_hsic_phy_ready(void)
1043 {
1044 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1045         baseband_xmm_set_power_status(BBXMM_PS_L0);
1046 #endif
1047 }
1048
1049 static void cardu_usb_hsic_phy_off(void)
1050 {
1051 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1052         baseband_xmm_set_power_status(BBXMM_PS_L3);
1053 #endif
1054 }
1055
1056 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1057         .post_suspend = cardu_usb_hsic_postsupend,
1058         .pre_resume = cardu_usb_hsic_preresume,
1059         .port_power = cardu_usb_hsic_phy_ready,
1060         .post_phy_off = cardu_usb_hsic_phy_off,
1061 };
1062
1063 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1064         .port_otg = false,
1065         .has_hostpc = true,
1066         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1067         .op_mode        = TEGRA_USB_OPMODE_HOST,
1068         .u_data.host = {
1069                 .vbus_gpio = -1,
1070                 .hot_plug = false,
1071                 .remote_wakeup_supported = false,
1072                 .power_off_on_suspend = false,
1073         },
1074         .u_cfg.hsic = {
1075                 .sync_start_delay = 9,
1076                 .idle_wait_delay = 17,
1077                 .term_range_adj = 0,
1078                 .elastic_underrun_limit = 16,
1079                 .elastic_overrun_limit = 16,
1080         },
1081         .ops = &hsic_xmm_plat_ops,
1082 };
1083 #endif
1084
1085 static int hsic_enable_gpio = -1;
1086 static int hsic_reset_gpio = -1;
1087
1088 void hsic_platform_open(void)
1089 {
1090         int reset_gpio = 0, enable_gpio = 0;
1091
1092         if (hsic_enable_gpio != -1)
1093                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1094         if (hsic_reset_gpio != -1)
1095                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1096         /* hsic enable signal deasserted, hsic reset asserted */
1097         if (!enable_gpio)
1098                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1099         if (!reset_gpio)
1100                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1101         if (!enable_gpio)
1102                 tegra_gpio_enable(hsic_enable_gpio);
1103         if (!reset_gpio)
1104                 tegra_gpio_enable(hsic_reset_gpio);
1105         /* keep hsic reset asserted for 1 ms */
1106         udelay(1000);
1107         /* enable (power on) hsic */
1108         if (!enable_gpio)
1109                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1110         udelay(1000);
1111         /* deassert reset */
1112         if (!reset_gpio)
1113                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1114
1115 }
1116
1117 void hsic_platform_close(void)
1118 {
1119         if (hsic_enable_gpio != -1) {
1120                 gpio_set_value(hsic_enable_gpio, 0);
1121                 gpio_free(hsic_enable_gpio);
1122         }
1123         if (hsic_reset_gpio != -1) {
1124                 gpio_set_value(hsic_reset_gpio, 0);
1125                 gpio_free(hsic_reset_gpio);
1126         }
1127 }
1128
1129 void hsic_power_on(void)
1130 {
1131         if (hsic_enable_gpio != -1) {
1132                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1133                 udelay(1000);
1134         }
1135 }
1136
1137 void hsic_power_off(void)
1138 {
1139         if (hsic_enable_gpio != -1) {
1140                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1141                 udelay(1000);
1142         }
1143 }
1144
1145 #if defined(CONFIG_USB_SUPPORT)
1146 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1147         .open = hsic_platform_open,
1148         .close = hsic_platform_close,
1149         .pre_phy_on = hsic_power_on,
1150         .post_phy_off = hsic_power_off,
1151 };
1152
1153 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1154         .port_otg = false,
1155         .has_hostpc = true,
1156         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1157         .op_mode        = TEGRA_USB_OPMODE_HOST,
1158         .u_data.host = {
1159                 .vbus_gpio = -1,
1160                 .hot_plug = false,
1161                 .remote_wakeup_supported = false,
1162                 .power_off_on_suspend = false,
1163         },
1164         .u_cfg.hsic = {
1165                 .sync_start_delay = 9,
1166                 .idle_wait_delay = 17,
1167                 .term_range_adj = 0,
1168                 .elastic_underrun_limit = 16,
1169                 .elastic_overrun_limit = 16,
1170         },
1171         .ops = &hsic_plat_ops,
1172 };
1173
1174 static struct tegra_usb_platform_data tegra_udc_pdata = {
1175         .port_otg = true,
1176         .has_hostpc = true,
1177         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1178         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1179         .u_data.dev = {
1180                 .vbus_pmu_irq = 0,
1181                 .vbus_gpio = -1,
1182                 .charging_supported = false,
1183                 .remote_wakeup_supported = false,
1184         },
1185         .u_cfg.utmi = {
1186                 .hssync_start_delay = 0,
1187                 .elastic_limit = 16,
1188                 .idle_wait_delay = 17,
1189                 .term_range_adj = 6,
1190                 .xcvr_setup = 8,
1191                 .xcvr_lsfslew = 2,
1192                 .xcvr_lsrslew = 2,
1193                 .xcvr_setup_offset = 0,
1194                 .xcvr_use_fuses = 1,
1195         },
1196 };
1197
1198 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1199         .port_otg = false,
1200         .has_hostpc = true,
1201         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1202         .op_mode        = TEGRA_USB_OPMODE_HOST,
1203         .u_data.host = {
1204                 .vbus_gpio = -1,
1205                 .hot_plug = false,
1206                 .remote_wakeup_supported = true,
1207                 .power_off_on_suspend = true,
1208         },
1209         .u_cfg.utmi = {
1210                 .hssync_start_delay = 0,
1211                 .elastic_limit = 16,
1212                 .idle_wait_delay = 17,
1213                 .term_range_adj = 6,
1214                 .xcvr_setup = 15,
1215                 .xcvr_lsfslew = 2,
1216                 .xcvr_lsrslew = 2,
1217                 .xcvr_setup_offset = 0,
1218                 .xcvr_use_fuses = 1,
1219         },
1220 };
1221
1222 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1223         .port_otg = false,
1224         .has_hostpc = true,
1225         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1226         .op_mode = TEGRA_USB_OPMODE_HOST,
1227         .u_data.host = {
1228                 .vbus_gpio = -1,
1229                 .vbus_reg = "vdd_vbus_typea_usb",
1230                 .hot_plug = true,
1231                 .remote_wakeup_supported = true,
1232                 .power_off_on_suspend = true,
1233         },
1234         .u_cfg.utmi = {
1235                 .hssync_start_delay = 0,
1236                 .elastic_limit = 16,
1237                 .idle_wait_delay = 17,
1238                 .term_range_adj = 6,
1239                 .xcvr_setup = 8,
1240                 .xcvr_lsfslew = 2,
1241                 .xcvr_lsrslew = 2,
1242                 .xcvr_setup_offset = 0,
1243                 .xcvr_use_fuses = 1,
1244         },
1245 };
1246
1247 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1248         .port_otg = true,
1249         .has_hostpc = true,
1250         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1251         .op_mode = TEGRA_USB_OPMODE_HOST,
1252         .u_data.host = {
1253                 .vbus_gpio = -1,
1254                 .vbus_reg = "vdd_vbus_micro_usb",
1255                 .hot_plug = true,
1256                 .remote_wakeup_supported = true,
1257                 .power_off_on_suspend = true,
1258         },
1259         .u_cfg.utmi = {
1260                 .hssync_start_delay = 0,
1261                 .elastic_limit = 16,
1262                 .idle_wait_delay = 17,
1263                 .term_range_adj = 6,
1264                 .xcvr_setup = 15,
1265                 .xcvr_lsfslew = 2,
1266                 .xcvr_lsrslew = 2,
1267                 .xcvr_setup_offset = 0,
1268                 .xcvr_use_fuses = 1,
1269         },
1270 };
1271
1272 static struct tegra_usb_otg_data tegra_otg_pdata = {
1273         .ehci_device = &tegra_ehci1_device,
1274         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1275 };
1276 #endif
1277
1278 #if defined(CONFIG_USB_SUPPORT)
1279 static void cardhu_usb_init(void)
1280 {
1281         struct board_info bi;
1282
1283         tegra_get_board_info(&bi);
1284
1285         /* OTG should be the first to be registered */
1286         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1287         platform_device_register(&tegra_otg_device);
1288
1289         /* setup the udc platform data */
1290         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1291
1292         if (bi.board_id == BOARD_PM267) {
1293                 hsic_enable_gpio = EN_HSIC_GPIO;
1294                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1295                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1296                 platform_device_register(&tegra_ehci2_device);
1297         } else if (bi.board_id == BOARD_E1256) {
1298                 hsic_enable_gpio = EN_HSIC_GPIO;
1299                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1300                 platform_device_register(&tegra_ehci2_device);
1301         } else if (bi.board_id == BOARD_E1186) {
1302                 tegra_ehci2_device.dev.platform_data =
1303                                                 &tegra_ehci2_hsic_xmm_pdata;
1304                 /* ehci2 registration happens in baseband-xmm-power  */
1305         } else {
1306                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1307                 platform_device_register(&tegra_ehci2_device);
1308         }
1309
1310         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1311         platform_device_register(&tegra_ehci3_device);
1312
1313 }
1314 #else
1315 static void cardhu_usb_init(void) { }
1316 #endif
1317
1318 static struct baseband_power_platform_data tegra_baseband_power_data = {
1319         .baseband_type = BASEBAND_XMM,
1320         .modem = {
1321         .xmm = {
1322                         .bb_rst = XMM_GPIO_BB_RST,
1323                         .bb_on = XMM_GPIO_BB_ON,
1324                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1325                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1326                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1327                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1328                         .hsic_device = &tegra_ehci2_device,
1329                 },
1330         },
1331 };
1332
1333 static struct platform_device tegra_baseband_power_device = {
1334         .name = "baseband_xmm_power",
1335         .id = -1,
1336         .dev = {
1337                 .platform_data = &tegra_baseband_power_data,
1338         },
1339 };
1340
1341 static struct platform_device tegra_baseband_power2_device = {
1342         .name = "baseband_xmm_power2",
1343         .id = -1,
1344         .dev = {
1345                 .platform_data = &tegra_baseband_power_data,
1346         },
1347 };
1348
1349
1350 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1351         .port_status[0] = 1,
1352         .port_status[1] = 1,
1353         .port_status[2] = 1,
1354         .use_dock_detect        = 0,
1355         .gpio           = 0,
1356 };
1357
1358 static void cardhu_pci_init(void)
1359 {
1360         struct board_info board_info;
1361
1362         tegra_get_board_info(&board_info);
1363         if (board_info.board_id == BOARD_E1291) {
1364                 cardhu_pci_platform_data.port_status[0] = 0;
1365                 cardhu_pci_platform_data.port_status[1] = 0;
1366                 cardhu_pci_platform_data.port_status[2] = 1;
1367                 cardhu_pci_platform_data.use_dock_detect = 1;
1368                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1369         }
1370         if ((board_info.board_id == BOARD_E1186) ||
1371                 (board_info.board_id == BOARD_E1187) ||
1372                 (board_info.board_id == BOARD_E1291)) {
1373                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1374                 platform_device_register(&tegra_pci_device);
1375         }
1376 }
1377
1378 static void cardhu_modem_init(void)
1379 {
1380         struct board_info board_info;
1381         int w_disable_gpio, ret;
1382
1383         tegra_get_board_info(&board_info);
1384         switch (board_info.board_id) {
1385         case BOARD_E1291:
1386         case BOARD_E1198:
1387                 if (((board_info.board_id == BOARD_E1291) &&
1388                                 (board_info.fab < BOARD_FAB_A03)) ||
1389                         ((board_info.board_id == BOARD_E1198) &&
1390                                         (board_info.fab < BOARD_FAB_A02))) {
1391                         w_disable_gpio = TEGRA_GPIO_PH5;
1392                 } else {
1393                         w_disable_gpio = TEGRA_GPIO_PDD5;
1394                 }
1395
1396                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1397                 if (ret < 0)
1398                         pr_err("%s: gpio_request failed for gpio %d\n",
1399                                 __func__, w_disable_gpio);
1400                 else
1401                         gpio_direction_input(w_disable_gpio);
1402
1403                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1404                 if (((board_info.board_id == BOARD_E1291) &&
1405                                 (board_info.fab >= BOARD_FAB_A04)) ||
1406                         ((board_info.board_id == BOARD_E1198) &&
1407                                         (board_info.fab >= BOARD_FAB_A02))) {
1408                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1409                         if (ret < 0) {
1410                                 pr_err("%s(): Error in allocating gpio "
1411                                         "TEGRA_GPIO_PH7\n", __func__);
1412                                 break;
1413                         }
1414                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1415                 }
1416                 break;
1417         case BOARD_E1186:
1418                 platform_device_register(&tegra_baseband_power_device);
1419                 platform_device_register(&tegra_baseband_power2_device);
1420                 break;
1421         default:
1422                 break;
1423         }
1424
1425 }
1426
1427 #ifdef CONFIG_SATA_AHCI_TEGRA
1428 static void cardhu_sata_init(void)
1429 {
1430         platform_device_register(&tegra_sata_device);
1431 }
1432 #else
1433 static void cardhu_sata_init(void) { }
1434 #endif
1435
1436 static void __init tegra_cardhu_init(void)
1437 {
1438         tegra_thermal_init(&thermal_data,
1439                                 throttle_list,
1440                                 ARRAY_SIZE(throttle_list));
1441         tegra_clk_init_from_table(cardhu_clk_init_table);
1442         tegra_enable_pinmux();
1443         cardhu_pinmux_init();
1444         cardhu_i2c_init();
1445         cardhu_spi_init();
1446         cardhu_usb_init();
1447 #ifdef CONFIG_TEGRA_EDP_LIMITS
1448         cardhu_edp_init();
1449 #endif
1450         cardhu_uart_init();
1451         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1452         tegra_ram_console_debug_init();
1453         tegra_io_dpd_init();
1454         cardhu_sdhci_init();
1455         cardhu_regulator_init();
1456         cardhu_dtv_init();
1457         cardhu_suspend_init();
1458         cardhu_touch_init();
1459         cardhu_modem_init();
1460         cardhu_kbc_init();
1461         cardhu_scroll_init();
1462         cardhu_keys_init();
1463         cardhu_panel_init();
1464         cardhu_pmon_init();
1465         cardhu_sensors_init();
1466         cardhu_setup_bluesleep();
1467         cardhu_sata_init();
1468         //audio_wired_jack_init();
1469         cardhu_pins_state_init();
1470         cardhu_emc_init();
1471         tegra_release_bootloader_fb();
1472         cardhu_pci_init();
1473 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1474         tegra_wdt_recovery_init();
1475 #endif
1476         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1477 }
1478
1479 static void __init tegra_cardhu_reserve(void)
1480 {
1481 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1482         /* support 1920X1200 with 24bpp */
1483         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1484 #else
1485         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1486 #endif
1487         tegra_ram_console_debug_reserve(SZ_1M);
1488 }
1489
1490 MACHINE_START(CARDHU, "cardhu")
1491         .atag_offset    = 0x100,
1492         .soc            = &tegra_soc_desc,
1493         .map_io         = tegra_map_common_io,
1494         .reserve        = tegra_cardhu_reserve,
1495         .init_early     = tegra30_init_early,
1496         .init_irq       = tegra_init_irq,
1497         .handle_irq     = gic_handle_irq,
1498         .timer          = &tegra_timer,
1499         .init_machine   = tegra_cardhu_init,
1500         .restart        = tegra_assert_system_reset,
1501 MACHINE_END