Arm: Tegra: clocks: Don't enable sdmmc clocks by default
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "devices.h"
66 #include "gpio-names.h"
67 #include "fuse.h"
68 #include "pm.h"
69 #include "baseband-xmm-power.h"
70 #include "wdt-recovery.h"
71
72 /* All units are in millicelsius */
73 static struct tegra_thermal_data thermal_data = {
74         .temp_throttle = 85000,
75         .temp_shutdown = 90000,
76         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
77 #ifdef CONFIG_TEGRA_EDP_LIMITS
78         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
79         .hysteresis_edp = 3000,
80 #endif
81 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
82         .tc1 = 0,
83         .tc2 = 1,
84         .passive_delay = 2000,
85 #else
86         .hysteresis_throttle = 1000,
87 #endif
88 };
89
90 /* !!!TODO: Change for cardhu (Taken from Ventana) */
91 static struct tegra_utmip_config utmi_phy_config[] = {
92         [0] = {
93                         .hssync_start_delay = 0,
94                         .idle_wait_delay = 17,
95                         .elastic_limit = 16,
96                         .term_range_adj = 6,
97                         .xcvr_setup = 15,
98                         .xcvr_setup_offset = 0,
99                         .xcvr_use_fuses = 1,
100                         .xcvr_lsfslew = 2,
101                         .xcvr_lsrslew = 2,
102         },
103         [1] = {
104                         .hssync_start_delay = 0,
105                         .idle_wait_delay = 17,
106                         .elastic_limit = 16,
107                         .term_range_adj = 6,
108                         .xcvr_setup = 15,
109                         .xcvr_setup_offset = 0,
110                         .xcvr_use_fuses = 1,
111                         .xcvr_lsfslew = 2,
112                         .xcvr_lsrslew = 2,
113         },
114         [2] = {
115                         .hssync_start_delay = 0,
116                         .idle_wait_delay = 17,
117                         .elastic_limit = 16,
118                         .term_range_adj = 6,
119                         .xcvr_setup = 8,
120                         .xcvr_setup_offset = 0,
121                         .xcvr_use_fuses = 1,
122                         .xcvr_lsfslew = 2,
123                         .xcvr_lsrslew = 2,
124         },
125 };
126
127 #ifdef CONFIG_BCM4329_RFKILL
128 static struct resource cardhu_bcm4329_rfkill_resources[] = {
129         {
130                 .name   = "bcm4329_nshutdown_gpio",
131                 .start  = TEGRA_GPIO_PU0,
132                 .end    = TEGRA_GPIO_PU0,
133                 .flags  = IORESOURCE_IO,
134         },
135 };
136
137 static struct platform_device cardhu_bcm4329_rfkill_device = {
138         .name = "bcm4329_rfkill",
139         .id             = -1,
140         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
141         .resource       = cardhu_bcm4329_rfkill_resources,
142 };
143
144 static noinline void __init cardhu_bt_rfkill(void)
145 {
146         platform_device_register(&cardhu_bcm4329_rfkill_device);
147
148         return;
149 }
150 #else
151 static inline void cardhu_bt_rfkill(void) { }
152 #endif
153
154 #ifdef CONFIG_BT_BLUESLEEP
155 static noinline void __init tegra_setup_bluesleep(void)
156 {
157         struct platform_device *pdev = NULL;
158         struct resource *res;
159
160         pdev = platform_device_alloc("bluesleep", 0);
161         if (!pdev) {
162                 pr_err("unable to allocate platform device for bluesleep");
163                 return;
164         }
165
166         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
167         if (!res) {
168                 pr_err("unable to allocate resource for bluesleep\n");
169                 goto err_free_dev;
170         }
171
172         res[0].name   = "gpio_host_wake";
173         res[0].start  = TEGRA_GPIO_PU6;
174         res[0].end    = TEGRA_GPIO_PU6;
175         res[0].flags  = IORESOURCE_IO;
176
177         res[1].name   = "gpio_ext_wake";
178         res[1].start  = TEGRA_GPIO_PU1;
179         res[1].end    = TEGRA_GPIO_PU1;
180         res[1].flags  = IORESOURCE_IO;
181
182         res[2].name   = "host_wake";
183         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
184         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
185         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
186
187         if (platform_device_add_resources(pdev, res, 3)) {
188                 pr_err("unable to add resources to bluesleep device\n");
189                 goto err_free_res;
190         }
191
192         if (platform_device_add(pdev)) {
193                 pr_err("unable to add bluesleep device\n");
194                 goto err_free_res;
195         }
196         tegra_gpio_enable(TEGRA_GPIO_PU6);
197         tegra_gpio_enable(TEGRA_GPIO_PU1);
198
199 return;
200
201 err_free_res:
202         kfree(res);
203 err_free_dev:
204         platform_device_put(pdev);
205         return;
206 }
207 #else
208 static inline void tegra_setup_bluesleep(void) { }
209 #endif
210
211 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
212         /* name         parent          rate            enabled */
213         { "pll_m",      NULL,           0,              false},
214         { "hda",        "pll_p",        108000000,      false},
215         { "hda2codec_2x","pll_p",       48000000,       false},
216         { "pwm",        "pll_p",        3187500,        false},
217         { "blink",      "clk_32k",      32768,          true},
218         { "i2s0",       "pll_a_out0",   0,              false},
219         { "i2s1",       "pll_a_out0",   0,              false},
220         { "i2s3",       "pll_a_out0",   0,              false},
221         { "spdif_out",  "pll_a_out0",   0,              false},
222         { "d_audio",    "clk_m",        12000000,       false},
223         { "dam0",       "clk_m",        12000000,       false},
224         { "dam1",       "clk_m",        12000000,       false},
225         { "dam2",       "clk_m",        12000000,       false},
226         { "audio1",     "i2s1_sync",    0,              false},
227         { "audio3",     "i2s3_sync",    0,              false},
228         { "vi_sensor",  "pll_p",        150000000,      false},
229         { "i2c1",       "pll_p",        3200000,        false},
230         { "i2c2",       "pll_p",        3200000,        false},
231         { "i2c3",       "pll_p",        3200000,        false},
232         { "i2c4",       "pll_p",        3200000,        false},
233         { "i2c5",       "pll_p",        3200000,        false},
234         { NULL,         NULL,           0,              0},
235 };
236
237 static struct pn544_i2c_platform_data nfc_pdata = {
238         .irq_gpio = TEGRA_GPIO_PX0,
239         .ven_gpio = TEGRA_GPIO_PP3,
240         .firm_gpio = TEGRA_GPIO_PO7,
241         };
242
243 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
244         {
245                 I2C_BOARD_INFO("pn544", 0x28),
246                 .platform_data = &nfc_pdata,
247                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
248         },
249 };
250 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
251         .adapter_nr     = 0,
252         .bus_count      = 1,
253         .bus_clk_rate   = { 100000, 0 },
254         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
255         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
256         .arb_recovery = arb_lost_recovery,
257 };
258
259 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
260         .adapter_nr     = 1,
261         .bus_count      = 1,
262         .bus_clk_rate   = { 100000, 0 },
263         .is_clkon_always = true,
264         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
265         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
266         .arb_recovery = arb_lost_recovery,
267 };
268
269 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
270         .adapter_nr     = 2,
271         .bus_count      = 1,
272         .bus_clk_rate   = { 100000, 0 },
273         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
274         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
275         .arb_recovery = arb_lost_recovery,
276 };
277
278 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
279         .adapter_nr     = 3,
280         .bus_count      = 1,
281         .bus_clk_rate   = { 100000, 0 },
282         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
283         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
284         .arb_recovery = arb_lost_recovery,
285 };
286
287 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
288         .adapter_nr     = 4,
289         .bus_count      = 1,
290         .bus_clk_rate   = { 400000, 0 },
291         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
292         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
293         .arb_recovery = arb_lost_recovery,
294 };
295
296
297 #if 0
298 struct tegra_wired_jack_conf audio_wr_jack_conf = {
299         .hp_det_n = TEGRA_GPIO_PW2,
300         .en_mic_ext = TEGRA_GPIO_PX1,
301         .en_mic_int = TEGRA_GPIO_PX0,
302 };
303 #endif
304
305 static struct wm8903_platform_data cardhu_wm8903_pdata = {
306         .irq_active_low = 0,
307         .micdet_cfg = 0,
308         .micdet_delay = 100,
309         .gpio_base = CARDHU_GPIO_WM8903(0),
310         .gpio_cfg = {
311                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
312                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
313                         WM8903_GP2_DIR,
314                 0,
315                 WM8903_GPIO_NO_CONFIG,
316                 WM8903_GPIO_NO_CONFIG,
317         },
318 };
319
320 /* Equalizer filter coefs generated from the MAXIM MAX98095
321  * evkit software tool */
322 static struct max98095_eq_cfg max98095_eq_cfg[] = {
323         {
324                 .name = "FLAT",
325                 .rate = 44100,
326                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
327                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
328                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
329                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
330                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
331         },
332         {
333                 .name = "LOWPASS1K",
334                 .rate = 44100,
335                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
336                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
337                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
338                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
339                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
340         },
341         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
342                 .name = "HIBOOST",
343                 .rate = 44100,
344                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
345                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
346                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
347                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
348                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
349         },
350         { /* BASS=12dB, TREBLE=+12dB */
351                 .name = "LOUD12DB",
352                 .rate = 44100,
353                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
354                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
355                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
356                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
357                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
358         },
359         {
360                 .name = "FLAT",
361                 .rate = 16000,
362                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
363                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
364                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
365                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
366                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
367         },
368         {
369                 .name = "LOWPASS1K",
370                 .rate = 16000,
371                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
372                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
373                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
374                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
375                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
376         },
377         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
378                 .name = "HIBOOST",
379                 .rate = 16000,
380                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
381                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
382                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
383                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
384                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
385         },
386         { /* BASS=12dB, TREBLE=+12dB */
387                 .name = "LOUD12DB",
388                 .rate = 16000,
389                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
390                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
391                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
392                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
393                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
394         },
395 };
396
397 static struct max98095_pdata cardhu_max98095_pdata = {
398         /* equalizer configuration */
399         .eq_cfg = max98095_eq_cfg,
400         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
401
402         /* Biquad filter response configuration */
403         .bq_cfg = NULL,
404         .bq_cfgcnt = 0,
405
406         /* microphone configuration */
407         .digmic_left_mode = 1,
408         .digmic_right_mode = 1,
409 };
410
411 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
412         I2C_BOARD_INFO("wm8903", 0x1a),
413         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
414         .platform_data = &cardhu_wm8903_pdata,
415 };
416
417 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
418         I2C_BOARD_INFO("aic3262-codec", 0x18),
419         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
420 };
421
422 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
423         I2C_BOARD_INFO("max98095", 0x10),
424         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
425         .platform_data = &cardhu_max98095_pdata,
426 };
427
428 static void cardhu_i2c_init(void)
429 {
430         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
431         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
432         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
433         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
434         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
435
436         platform_device_register(&tegra_i2c_device5);
437         platform_device_register(&tegra_i2c_device4);
438         platform_device_register(&tegra_i2c_device3);
439         platform_device_register(&tegra_i2c_device2);
440         platform_device_register(&tegra_i2c_device1);
441
442         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
443         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
444         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
445
446         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
447 }
448
449 static struct platform_device *cardhu_uart_devices[] __initdata = {
450         &tegra_uarta_device,
451         &tegra_uartb_device,
452         &tegra_uartc_device,
453         &tegra_uartd_device,
454         &tegra_uarte_device,
455 };
456 static struct uart_clk_parent uart_parent_clk[] = {
457         [0] = {.name = "clk_m"},
458         [1] = {.name = "pll_p"},
459 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
460         [2] = {.name = "pll_m"},
461 #endif
462 };
463
464 static struct tegra_uart_platform_data cardhu_uart_pdata;
465 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
466
467 static void __init uart_debug_init(void)
468 {
469         struct board_info board_info;
470         int debug_port_id;
471
472         tegra_get_board_info(&board_info);
473
474         debug_port_id = get_tegra_uart_debug_port_id();
475         if (debug_port_id < 0) {
476                 debug_port_id = 0;
477                         /* UARTB is debug port
478                          *       for SLT - E1186/E1187/PM269
479                          *       for E1256/E1257
480                          */
481                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
482                         ((board_info.board_id == BOARD_E1186) ||
483                         (board_info.board_id == BOARD_E1187) ||
484                         (board_info.board_id == BOARD_PM269))) ||
485                         (board_info.board_id == BOARD_E1256) ||
486                         (board_info.board_id == BOARD_E1257))
487                                 debug_port_id = 1;
488         }
489
490         switch (debug_port_id) {
491         case 0:
492                 /* UARTA is the debug port. */
493                 pr_info("Selecting UARTA as the debug console\n");
494                 cardhu_uart_devices[0] = &debug_uarta_device;
495                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
496                 debug_uart_port_base = ((struct plat_serial8250_port *)(
497                         debug_uarta_device.dev.platform_data))->mapbase;
498                 break;
499
500         case 1:
501                 /* UARTB is the debug port. */
502                 pr_info("Selecting UARTB as the debug console\n");
503                 cardhu_uart_devices[1] = &debug_uartb_device;
504                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
505                 debug_uart_port_base = ((struct plat_serial8250_port *)(
506                         debug_uartb_device.dev.platform_data))->mapbase;
507                 break;
508
509         case 2:
510                 /* UARTC is the debug port. */
511                 pr_info("Selecting UARTC as the debug console\n");
512                 cardhu_uart_devices[2] = &debug_uartc_device;
513                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
514                 debug_uart_port_base = ((struct plat_serial8250_port *)(
515                         debug_uartc_device.dev.platform_data))->mapbase;
516                 break;
517
518         case 3:
519                 /* UARTD is the debug port. */
520                 pr_info("Selecting UARTD as the debug console\n");
521                 cardhu_uart_devices[3] = &debug_uartd_device;
522                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
523                 debug_uart_port_base = ((struct plat_serial8250_port *)(
524                         debug_uartd_device.dev.platform_data))->mapbase;
525                 break;
526
527         case 4:
528                 /* UARTE is the debug port. */
529                 pr_info("Selecting UARTE as the debug console\n");
530                 cardhu_uart_devices[4] = &debug_uarte_device;
531                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
532                 debug_uart_port_base = ((struct plat_serial8250_port *)(
533                         debug_uarte_device.dev.platform_data))->mapbase;
534                 break;
535
536         default:
537                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
538                 cardhu_uart_devices[0] = &debug_uarta_device;
539                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
540                 debug_uart_port_base = ((struct plat_serial8250_port *)(
541                         debug_uarta_device.dev.platform_data))->mapbase;
542                 break;
543         }
544         return;
545 }
546
547 static void __init cardhu_uart_init(void)
548 {
549         struct clk *c;
550         int i;
551
552         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
553                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
554                 if (IS_ERR_OR_NULL(c)) {
555                         pr_err("Not able to get the clock for %s\n",
556                                                 uart_parent_clk[i].name);
557                         continue;
558                 }
559                 uart_parent_clk[i].parent_clk = c;
560                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
561         }
562         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
563         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
564         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
565         cardhu_loopback_uart_pdata.parent_clk_count =
566                                                 ARRAY_SIZE(uart_parent_clk);
567         cardhu_loopback_uart_pdata.is_loopback = true;
568         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
569         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
570         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
571         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
572         /* UARTE is used for loopback test purpose */
573         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
574
575         /* Register low speed only if it is selected */
576         if (!is_tegra_debug_uartport_hs()) {
577                 uart_debug_init();
578                 /* Clock enable for the debug channel */
579                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
580                         pr_info("The debug console clock name is %s\n",
581                                                 debug_uart_clk->name);
582                         c = tegra_get_clock_by_name("pll_p");
583                         if (IS_ERR_OR_NULL(c))
584                                 pr_err("Not getting the parent clock pll_p\n");
585                         else
586                                 clk_set_parent(debug_uart_clk, c);
587
588                         clk_enable(debug_uart_clk);
589                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
590                 } else {
591                         pr_err("Not getting the clock %s for debug console\n",
592                                         debug_uart_clk->name);
593                 }
594         }
595
596         platform_add_devices(cardhu_uart_devices,
597                                 ARRAY_SIZE(cardhu_uart_devices));
598 }
599
600 static struct platform_device tegra_camera = {
601         .name = "tegra_camera",
602         .id = -1,
603 };
604
605 static struct platform_device *cardhu_spi_devices[] __initdata = {
606         &tegra_spi_device4,
607 };
608
609 struct spi_clk_parent spi_parent_clk[] = {
610         [0] = {.name = "pll_p"},
611 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
612         [1] = {.name = "pll_m"},
613         [2] = {.name = "clk_m"},
614 #else
615         [1] = {.name = "clk_m"},
616 #endif
617 };
618
619 static struct tegra_spi_platform_data cardhu_spi_pdata = {
620         .is_dma_based           = true,
621         .max_dma_buffer         = (16 * 1024),
622         .is_clkon_always        = false,
623         .max_rate               = 100000000,
624 };
625
626 static void __init cardhu_spi_init(void)
627 {
628         int i;
629         struct clk *c;
630         struct board_info board_info;
631
632         tegra_get_board_info(&board_info);
633
634         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
635                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
636                 if (IS_ERR_OR_NULL(c)) {
637                         pr_err("Not able to get the clock for %s\n",
638                                                 spi_parent_clk[i].name);
639                         continue;
640                 }
641                 spi_parent_clk[i].parent_clk = c;
642                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
643         }
644         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
645         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
646         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
647         platform_add_devices(cardhu_spi_devices,
648                                 ARRAY_SIZE(cardhu_spi_devices));
649
650         if (board_info.board_id == BOARD_E1198) {
651                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
652                 platform_device_register(&tegra_spi_device2);
653                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
654                 platform_device_register(&tegra_spi_slave_device1);
655         }
656 }
657
658 static void __init cardhu_dtv_init(void)
659 {
660         struct board_info board_info;
661
662         tegra_get_board_info(&board_info);
663
664         if (board_info.board_id == BOARD_E1186)
665                 platform_device_register(&tegra_dtv_device);
666 }
667
668 static struct resource tegra_rtc_resources[] = {
669         [0] = {
670                 .start = TEGRA_RTC_BASE,
671                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
672                 .flags = IORESOURCE_MEM,
673         },
674         [1] = {
675                 .start = INT_RTC,
676                 .end = INT_RTC,
677                 .flags = IORESOURCE_IRQ,
678         },
679 };
680
681 static struct platform_device tegra_rtc_device = {
682         .name = "tegra_rtc",
683         .id   = -1,
684         .resource = tegra_rtc_resources,
685         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
686 };
687
688 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
689         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
690         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
691         .gpio_hp_mute           = -1,
692         .gpio_int_mic_en        = -1,
693         .gpio_ext_mic_en        = -1,
694 };
695
696 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
697         .gpio_spkr_en           = -1,
698         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
699         .gpio_hp_mute           = -1,
700         .gpio_int_mic_en        = -1,
701         .gpio_ext_mic_en        = -1,
702 };
703
704 static struct platform_device cardhu_audio_wm8903_device = {
705         .name   = "tegra-snd-wm8903",
706         .id     = 0,
707         .dev    = {
708                 .platform_data = &cardhu_audio_wm8903_pdata,
709         },
710 };
711
712 static struct platform_device cardhu_audio_max98095_device = {
713         .name   = "tegra-snd-max98095",
714         .id     = 0,
715         .dev    = {
716                 .platform_data = &cardhu_audio_max98095_pdata,
717         },
718 };
719
720 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
721         .gpio_spkr_en           = -1,
722         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
723         .gpio_hp_mute           = -1,
724         .gpio_int_mic_en        = -1,
725         .gpio_ext_mic_en        = -1,
726 };
727
728 static struct platform_device cardhu_audio_aic326x_device = {
729         .name   = "tegra-snd-aic326x",
730         .id     = 0,
731         .dev    = {
732                 .platform_data  = &cardhu_audio_aic326x_pdata,
733         },
734 };
735
736 static struct resource ram_console_resources[] = {
737         {
738                 .flags = IORESOURCE_MEM,
739         },
740 };
741
742 static struct platform_device ram_console_device = {
743         .name           = "ram_console",
744         .id             = -1,
745         .num_resources  = ARRAY_SIZE(ram_console_resources),
746         .resource       = ram_console_resources,
747 };
748
749 static struct platform_device *cardhu_devices[] __initdata = {
750         &tegra_pmu_device,
751         &tegra_rtc_device,
752         &tegra_udc_device,
753 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
754         &tegra_smmu_device,
755 #endif
756         &tegra_wdt_device,
757 #if defined(CONFIG_TEGRA_AVP)
758         &tegra_avp_device,
759 #endif
760         &tegra_camera,
761 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
762         &tegra_se_device,
763 #endif
764         &tegra_ahub_device,
765         &tegra_dam_device0,
766         &tegra_dam_device1,
767         &tegra_dam_device2,
768         &tegra_i2s_device0,
769         &tegra_i2s_device1,
770         &tegra_i2s_device3,
771         &tegra_spdif_device,
772         &spdif_dit_device,
773         &bluetooth_dit_device,
774         &baseband_dit_device,
775         &tegra_pcm_device,
776         &cardhu_audio_wm8903_device,
777         &cardhu_audio_max98095_device,
778         &cardhu_audio_aic326x_device,
779         &tegra_hda_device,
780 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
781         &tegra_aes_device,
782 #endif
783         &ram_console_device,
784 };
785
786 #define MXT_CONFIG_CRC  0xD62DE8
787 static const u8 config[] = {
788         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
789         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
790         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
791         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
792         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
793         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
794         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
795         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
796         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
797         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
798         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
799         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
800         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
801         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
802         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
803         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
804         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
806         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
808 };
809
810 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
811 static const u8 config_sku2000[] = {
812         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
813         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
814         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
815         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
816         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
817         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
818         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
819         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
820         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
821         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
823         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
824         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
825         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
826         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
827         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
829         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
830         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
832 };
833
834 static struct mxt_platform_data atmel_mxt_info = {
835         .x_line         = 27,
836         .y_line         = 42,
837         .x_size         = 768,
838         .y_size         = 1366,
839         .blen           = 0x20,
840         .threshold      = 0x3C,
841         .voltage        = 3300000,              /* 3.3V */
842         .orient         = 5,
843         .config         = config,
844         .config_length  = 157,
845         .config_crc     = MXT_CONFIG_CRC,
846         .irqflags       = IRQF_TRIGGER_FALLING,
847 /*      .read_chg       = &read_chg, */
848         .read_chg       = NULL,
849 };
850
851 static struct i2c_board_info __initdata atmel_i2c_info[] = {
852         {
853                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
854                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
855                 .platform_data = &atmel_mxt_info,
856         }
857 };
858
859 static int __init cardhu_touch_init(void)
860 {
861         struct board_info BoardInfo;
862
863         tegra_gpio_enable(TEGRA_GPIO_PH4);
864         tegra_gpio_enable(TEGRA_GPIO_PH6);
865
866         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
867         gpio_direction_input(TEGRA_GPIO_PH4);
868
869         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
870         gpio_direction_output(TEGRA_GPIO_PH6, 0);
871         msleep(1);
872         gpio_set_value(TEGRA_GPIO_PH6, 1);
873         msleep(100);
874
875         tegra_get_board_info(&BoardInfo);
876         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
877                 atmel_mxt_info.config = config_sku2000;
878                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
879         }
880
881         i2c_register_board_info(1, atmel_i2c_info, 1);
882
883         return 0;
884 }
885
886 static struct tegra_uhsic_config uhsic_phy_config = {
887         .enable_gpio = EN_HSIC_GPIO,
888         .reset_gpio = -1,
889         .sync_start_delay = 9,
890         .idle_wait_delay = 17,
891         .term_range_adj = 0,
892         .elastic_underrun_limit = 16,
893         .elastic_overrun_limit = 16,
894 };
895
896 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
897         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
898         .phy_config = &uhsic_phy_config,
899         .operating_mode = TEGRA_USB_HOST,
900         .power_down_on_bus_suspend = 1,
901         .default_enable = true,
902 };
903
904 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
905         [0] = {
906                         .phy_config = &utmi_phy_config[0],
907                         .operating_mode = TEGRA_USB_HOST,
908                         .power_down_on_bus_suspend = 1,
909                         .default_enable = true,
910         },
911         [1] = {
912                         .phy_config = &utmi_phy_config[1],
913                         .operating_mode = TEGRA_USB_HOST,
914                         .power_down_on_bus_suspend = 1,
915                         .default_enable = true,
916         },
917         [2] = {
918                         .phy_config = &utmi_phy_config[2],
919                         .operating_mode = TEGRA_USB_HOST,
920                         .power_down_on_bus_suspend = 1,
921                         .hotplug = 1,
922                         .default_enable = true,
923         },
924 };
925
926 static struct tegra_otg_platform_data tegra_otg_pdata = {
927         .ehci_device = &tegra_ehci1_device,
928         .ehci_pdata = &tegra_ehci_pdata[0],
929 };
930
931 #ifdef CONFIG_USB_SUPPORT
932 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
933         [0] = {
934                         .instance = 0,
935                         .vbus_gpio = -1,
936                         .vbus_reg_supply = "vdd_vbus_micro_usb",
937         },
938         [1] = {
939                         .instance = 1,
940                         .vbus_gpio = -1,
941         },
942         [2] = {
943                         .instance = 2,
944                         .vbus_gpio = -1,
945                         .vbus_reg_supply = "vdd_vbus_typea_usb",
946         },
947 };
948
949 static int cardu_usb_hsic_postsupend(void)
950 {
951         baseband_xmm_set_power_status(BBXMM_PS_L2);
952         return 0;
953 }
954
955 static int cardu_usb_hsic_preresume(void)
956 {
957         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
958         return 0;
959 }
960
961 static int cardu_usb_hsic_phy_ready(void)
962 {
963 #ifdef CONFIG_TEGRA_BB_XMM_POWER
964         baseband_xmm_set_power_status(BBXMM_PS_L0);
965 #endif
966         return 0;
967 }
968
969 static int cardu_usb_hsic_phy_off(void)
970 {
971 #ifdef CONFIG_TEGRA_BB_XMM_POWER
972         baseband_xmm_set_power_status(BBXMM_PS_L3);
973 #endif
974         return 0;
975 }
976
977 static void cardhu_usb_init(void)
978 {
979         struct board_info bi;
980
981         tegra_get_board_info(&bi);
982
983         tegra_usb_phy_init(tegra_usb_phy_pdata,
984                         ARRAY_SIZE(tegra_usb_phy_pdata));
985
986         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
987         platform_device_register(&tegra_otg_device);
988         if (bi.board_id == BOARD_PM267) {
989                 uhsic_phy_config.reset_gpio =
990                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
991                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
992                 platform_device_register(&tegra_ehci2_device);
993         } else if (bi.board_id == BOARD_E1256) {
994                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
995                 platform_device_register(&tegra_ehci2_device);
996         } else if (bi.board_id == BOARD_E1186) {
997                 /* for baseband devices do not switch off phy during suspend */
998                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
999                 uhsic_phy_config.postsuspend = cardu_usb_hsic_postsupend;
1000                 uhsic_phy_config.preresume = cardu_usb_hsic_preresume;
1001                 uhsic_phy_config.usb_phy_ready = cardu_usb_hsic_phy_ready;
1002                 uhsic_phy_config.post_phy_off = cardu_usb_hsic_phy_off;
1003                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
1004                 /* baseband registration happens in baseband-xmm-power  */
1005         } else {
1006                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
1007                 platform_device_register(&tegra_ehci2_device);
1008         }
1009
1010         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
1011         platform_device_register(&tegra_ehci3_device);
1012
1013 }
1014 #else
1015 static void cardhu_usb_init(void) { }
1016 #endif
1017
1018 static void cardhu_gps_init(void)
1019 {
1020         tegra_gpio_enable(TEGRA_GPIO_PU2);
1021         tegra_gpio_enable(TEGRA_GPIO_PU3);
1022 }
1023
1024 static void cardhu_nfc_init(void)
1025 {
1026         tegra_gpio_enable(TEGRA_GPIO_PX0);
1027         tegra_gpio_enable(TEGRA_GPIO_PP3);
1028         tegra_gpio_enable(TEGRA_GPIO_PO7);
1029 }
1030
1031 static struct baseband_power_platform_data tegra_baseband_power_data = {
1032         .baseband_type = BASEBAND_XMM,
1033         .modem = {
1034         .xmm = {
1035                         .bb_rst = XMM_GPIO_BB_RST,
1036                         .bb_on = XMM_GPIO_BB_ON,
1037                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1038                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1039                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1040                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1041                         .hsic_device = &tegra_ehci2_device,
1042                 },
1043         },
1044 };
1045
1046 static struct platform_device tegra_baseband_power_device = {
1047         .name = "baseband_xmm_power",
1048         .id = -1,
1049         .dev = {
1050                 .platform_data = &tegra_baseband_power_data,
1051         },
1052 };
1053
1054 static struct platform_device tegra_baseband_power2_device = {
1055         .name = "baseband_xmm_power2",
1056         .id = -1,
1057         .dev = {
1058                 .platform_data = &tegra_baseband_power_data,
1059         },
1060 };
1061
1062
1063 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1064         .port_status[0] = 1,
1065         .port_status[1] = 1,
1066         .port_status[2] = 1,
1067         .use_dock_detect        = 0,
1068         .gpio           = 0,
1069 };
1070
1071 static void cardhu_pci_init(void)
1072 {
1073         struct board_info board_info;
1074
1075         tegra_get_board_info(&board_info);
1076         if (board_info.board_id == BOARD_E1291) {
1077                 cardhu_pci_platform_data.port_status[0] = 0;
1078                 cardhu_pci_platform_data.port_status[1] = 0;
1079                 cardhu_pci_platform_data.port_status[2] = 1;
1080                 cardhu_pci_platform_data.use_dock_detect = 1;
1081                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1082         }
1083         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1084         platform_device_register(&tegra_pci_device);
1085 }
1086
1087 static void cardhu_modem_init(void)
1088 {
1089         struct board_info board_info;
1090         int w_disable_gpio, ret;
1091
1092         tegra_get_board_info(&board_info);
1093         switch (board_info.board_id) {
1094         case BOARD_E1291:
1095         case BOARD_E1198:
1096                 if (((board_info.board_id == BOARD_E1291) &&
1097                                 (board_info.fab < BOARD_FAB_A03)) ||
1098                         ((board_info.board_id == BOARD_E1198) &&
1099                                         (board_info.fab < BOARD_FAB_A02))) {
1100                         w_disable_gpio = TEGRA_GPIO_PH5;
1101                 } else {
1102                         w_disable_gpio = TEGRA_GPIO_PDD5;
1103                 }
1104                 tegra_gpio_enable(w_disable_gpio);
1105                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1106                 if (ret < 0)
1107                         pr_err("%s: gpio_request failed for gpio %d\n",
1108                                 __func__, w_disable_gpio);
1109                 else
1110                         gpio_direction_input(w_disable_gpio);
1111
1112                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1113                 if (((board_info.board_id == BOARD_E1291) &&
1114                                 (board_info.fab >= BOARD_FAB_A04)) ||
1115                         ((board_info.board_id == BOARD_E1198) &&
1116                                         (board_info.fab >= BOARD_FAB_A02))) {
1117                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1118                         if (ret < 0) {
1119                                 pr_err("%s(): Error in allocating gpio "
1120                                         "TEGRA_GPIO_PH7\n", __func__);
1121                                 break;
1122                         }
1123                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1124                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1125                 }
1126                 break;
1127         case BOARD_E1186:
1128                 tegra_gpio_enable(
1129                         tegra_baseband_power_data.modem.xmm.bb_rst);
1130                 tegra_gpio_enable(
1131                         tegra_baseband_power_data.modem.xmm.bb_on);
1132                 tegra_gpio_enable(
1133                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1134                 tegra_gpio_enable(
1135                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1136                 tegra_gpio_enable(
1137                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1138                 tegra_gpio_enable(
1139                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1140                 platform_device_register(&tegra_baseband_power_device);
1141                 platform_device_register(&tegra_baseband_power2_device);
1142                 break;
1143         default:
1144                 break;
1145         }
1146
1147 }
1148
1149 #ifdef CONFIG_SATA_AHCI_TEGRA
1150 static void cardhu_sata_init(void)
1151 {
1152         platform_device_register(&tegra_sata_device);
1153 }
1154 #else
1155 static void cardhu_sata_init(void) { }
1156 #endif
1157
1158 static void __init tegra_cardhu_init(void)
1159 {
1160         tegra_thermal_init(&thermal_data);
1161         tegra_clk_init_from_table(cardhu_clk_init_table);
1162         cardhu_pinmux_init();
1163         cardhu_i2c_init();
1164         cardhu_spi_init();
1165         cardhu_usb_init();
1166 #ifdef CONFIG_TEGRA_EDP_LIMITS
1167         cardhu_edp_init();
1168 #endif
1169         cardhu_uart_init();
1170         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1171         cardhu_sdhci_init();
1172         cardhu_regulator_init();
1173         cardhu_dtv_init();
1174         cardhu_suspend_init();
1175         cardhu_touch_init();
1176         cardhu_gps_init();
1177         cardhu_modem_init();
1178         cardhu_kbc_init();
1179         cardhu_scroll_init();
1180         cardhu_keys_init();
1181         cardhu_panel_init();
1182         cardhu_pmon_init();
1183         cardhu_sensors_init();
1184         cardhu_bt_rfkill();
1185         tegra_setup_bluesleep();
1186         cardhu_sata_init();
1187         //audio_wired_jack_init();
1188         cardhu_pins_state_init();
1189         cardhu_emc_init();
1190         tegra_release_bootloader_fb();
1191         cardhu_nfc_init();
1192         cardhu_pci_init();
1193 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1194         tegra_wdt_recovery_init();
1195 #endif
1196 }
1197
1198 static void __init cardhu_ramconsole_reserve(unsigned long size)
1199 {
1200         struct resource *res;
1201         long ret;
1202
1203         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
1204         if (!res) {
1205                 pr_err("Failed to find memory resource for ram console\n");
1206                 return;
1207         }
1208         res->start = memblock_end_of_DRAM() - size;
1209         res->end = res->start + size - 1;
1210         ret = memblock_remove(res->start, size);
1211         if (ret) {
1212                 ram_console_device.resource = NULL;
1213                 ram_console_device.num_resources = 0;
1214                 pr_err("Failed to reserve memory block for ram console\n");
1215         }
1216 }
1217
1218 static void __init tegra_cardhu_reserve(void)
1219 {
1220 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1221         /* support 1920X1200 with 24bpp */
1222         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1223 #else
1224         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1225 #endif
1226         cardhu_ramconsole_reserve(SZ_1M);
1227 }
1228
1229 MACHINE_START(CARDHU, "cardhu")
1230         .boot_params    = 0x80000100,
1231         .map_io         = tegra_map_common_io,
1232         .reserve        = tegra_cardhu_reserve,
1233         .init_early     = tegra_init_early,
1234         .init_irq       = tegra_init_irq,
1235         .timer          = &tegra_timer,
1236         .init_machine   = tegra_cardhu_init,
1237 MACHINE_END