ARM: tegra3: convert to CONFIG_MULTI_IRQ_HANDLER
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <asm/hardware/gic.h>
48
49 #include <mach/clk.h>
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/pinmux.h>
53 #include <mach/iomap.h>
54 #include <mach/io.h>
55 #include <mach/i2s.h>
56 #include <mach/tegra_asoc_pdata.h>
57 #include <mach/tegra_wm8903_pdata.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61 #include <mach/gpio-tegra.h>
62
63 #include <asm/hardware/gic.h>
64 #include <asm/mach-types.h>
65 #include <asm/mach/arch.h>
66
67 #include "board.h"
68 #include "clock.h"
69 #include "board-cardhu.h"
70 #include "board-touch.h"
71 #include "devices.h"
72 #include "gpio-names.h"
73 #include "fuse.h"
74 #include "pm.h"
75 #include "baseband-xmm-power.h"
76 #include "wdt-recovery.h"
77
78 /* All units are in millicelsius */
79 static struct tegra_thermal_data thermal_data = {
80         .temp_shutdown = 90000,
81         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
82 #ifdef CONFIG_TEGRA_EDP_LIMITS
83         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
84         .hysteresis_edp = 3000,
85 #endif
86 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
87         .temp_throttle = 85000,
88         .tc1 = 0,
89         .tc2 = 1,
90         .passive_delay = 2000,
91 #endif
92 };
93
94 static struct resource cardhu_bcm4329_rfkill_resources[] = {
95         {
96                 .name   = "bcm4329_nshutdown_gpio",
97                 .start  = TEGRA_GPIO_PU0,
98                 .end    = TEGRA_GPIO_PU0,
99                 .flags  = IORESOURCE_IO,
100         },
101 };
102
103 static struct platform_device cardhu_bcm4329_rfkill_device = {
104         .name = "bcm4329_rfkill",
105         .id             = -1,
106         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
107         .resource       = cardhu_bcm4329_rfkill_resources,
108 };
109
110 static struct resource cardhu_bluesleep_resources[] = {
111         [0] = {
112                 .name = "gpio_host_wake",
113                         .start  = TEGRA_GPIO_PU6,
114                         .end    = TEGRA_GPIO_PU6,
115                         .flags  = IORESOURCE_IO,
116         },
117         [1] = {
118                 .name = "gpio_ext_wake",
119                         .start  = TEGRA_GPIO_PU1,
120                         .end    = TEGRA_GPIO_PU1,
121                         .flags  = IORESOURCE_IO,
122         },
123         [2] = {
124                 .name = "host_wake",
125                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
126         },
127 };
128
129 static struct platform_device cardhu_bluesleep_device = {
130         .name           = "bluesleep",
131         .id             = -1,
132         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
133         .resource       = cardhu_bluesleep_resources,
134 };
135
136 static noinline void __init cardhu_setup_bluesleep(void)
137 {
138         cardhu_bluesleep_resources[2].start =
139                 cardhu_bluesleep_resources[2].end =
140                         gpio_to_irq(TEGRA_GPIO_PU6);
141         platform_device_register(&cardhu_bluesleep_device);
142         return;
143 }
144
145 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
146         /* name         parent          rate            enabled */
147         { "pll_m",      NULL,           0,              false},
148         { "hda",        "pll_p",        108000000,      false},
149         { "hda2codec_2x","pll_p",       48000000,       false},
150         { "pwm",        "pll_p",        3187500,        false},
151         { "blink",      "clk_32k",      32768,          true},
152         { "i2s0",       "pll_a_out0",   0,              false},
153         { "i2s1",       "pll_a_out0",   0,              false},
154         { "i2s3",       "pll_a_out0",   0,              false},
155         { "spdif_out",  "pll_a_out0",   0,              false},
156         { "d_audio",    "clk_m",        12000000,       false},
157         { "dam0",       "clk_m",        12000000,       false},
158         { "dam1",       "clk_m",        12000000,       false},
159         { "dam2",       "clk_m",        12000000,       false},
160         { "audio1",     "i2s1_sync",    0,              false},
161         { "audio3",     "i2s3_sync",    0,              false},
162         { "vi_sensor",  "pll_p",        150000000,      false},
163         { "i2c1",       "pll_p",        3200000,        false},
164         { "i2c2",       "pll_p",        3200000,        false},
165         { "i2c3",       "pll_p",        3200000,        false},
166         { "i2c4",       "pll_p",        3200000,        false},
167         { "i2c5",       "pll_p",        3200000,        false},
168         { NULL,         NULL,           0,              0},
169 };
170
171 static struct pn544_i2c_platform_data nfc_pdata = {
172         .irq_gpio = TEGRA_GPIO_PX0,
173         .ven_gpio = TEGRA_GPIO_PP3,
174         .firm_gpio = TEGRA_GPIO_PO7,
175         };
176
177 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
178         {
179                 I2C_BOARD_INFO("pn544", 0x28),
180                 .platform_data = &nfc_pdata,
181         },
182 };
183 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
184         .adapter_nr     = 0,
185         .bus_count      = 1,
186         .bus_clk_rate   = { 100000, 0 },
187         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
188         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
189         .arb_recovery = arb_lost_recovery,
190 };
191
192 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
193         .adapter_nr     = 1,
194         .bus_count      = 1,
195         .bus_clk_rate   = { 400000, 0 },
196         .is_clkon_always = true,
197         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
198         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
199         .arb_recovery = arb_lost_recovery,
200 };
201
202 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
203         .adapter_nr     = 2,
204         .bus_count      = 1,
205         .bus_clk_rate   = { 100000, 0 },
206         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
207         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
208         .arb_recovery = arb_lost_recovery,
209 };
210
211 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
212         .adapter_nr     = 3,
213         .bus_count      = 1,
214         .bus_clk_rate   = { 10000, 0 },
215         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
216         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
217         .arb_recovery = arb_lost_recovery,
218 };
219
220 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
221         .adapter_nr     = 4,
222         .bus_count      = 1,
223         .bus_clk_rate   = { 400000, 0 },
224         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
225         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
226         .arb_recovery = arb_lost_recovery,
227 };
228
229
230 #if 0
231 struct tegra_wired_jack_conf audio_wr_jack_conf = {
232         .hp_det_n = TEGRA_GPIO_PW2,
233         .en_mic_ext = TEGRA_GPIO_PX1,
234         .en_mic_int = TEGRA_GPIO_PX0,
235 };
236 #endif
237
238 static struct wm8903_platform_data cardhu_wm8903_pdata = {
239         .irq_active_low = 0,
240         .micdet_cfg = 0,
241         .micdet_delay = 100,
242         .gpio_base = CARDHU_GPIO_WM8903(0),
243         .gpio_cfg = {
244                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
245                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
246                         WM8903_GP2_DIR,
247                 WM8903_GPIO_CONFIG_ZERO,
248                 0,
249                 0,
250         },
251 };
252
253 /* Equalizer filter coefs generated from the MAXIM MAX98095
254  * evkit software tool */
255 static struct max98095_eq_cfg max98095_eq_cfg[] = {
256         {
257                 .name = "FLAT",
258                 .rate = 44100,
259                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
260                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
261                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
262                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
263                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
264         },
265         {
266                 .name = "LOWPASS1K",
267                 .rate = 44100,
268                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
269                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
270                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
271                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
272                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
273         },
274         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
275                 .name = "HIBOOST",
276                 .rate = 44100,
277                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
278                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
279                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
280                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
281                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
282         },
283         { /* BASS=12dB, TREBLE=+12dB */
284                 .name = "LOUD12DB",
285                 .rate = 44100,
286                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
287                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
288                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
289                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
290                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
291         },
292         {
293                 .name = "FLAT",
294                 .rate = 16000,
295                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
296                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
297                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
298                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
299                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
300         },
301         {
302                 .name = "LOWPASS1K",
303                 .rate = 16000,
304                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
305                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
306                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
307                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
308                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
309         },
310         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
311                 .name = "HIBOOST",
312                 .rate = 16000,
313                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
314                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
315                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
316                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
317                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
318         },
319         { /* BASS=12dB, TREBLE=+12dB */
320                 .name = "LOUD12DB",
321                 .rate = 16000,
322                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
323                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
324                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
325                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
326                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
327         },
328 };
329
330 static struct max98095_pdata cardhu_max98095_pdata = {
331         /* equalizer configuration */
332         .eq_cfg = max98095_eq_cfg,
333         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
334
335         /* Biquad filter response configuration */
336         .bq_cfg = NULL,
337         .bq_cfgcnt = 0,
338
339         /* microphone configuration */
340         .digmic_left_mode = 1,
341         .digmic_right_mode = 1,
342 };
343
344 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
345         I2C_BOARD_INFO("wm8903", 0x1a),
346         .platform_data = &cardhu_wm8903_pdata,
347 };
348
349 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
350         I2C_BOARD_INFO("aic3262-codec", 0x18),
351 };
352
353 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
354         I2C_BOARD_INFO("max98095", 0x10),
355         .platform_data = &cardhu_max98095_pdata,
356 };
357
358 static void cardhu_i2c_init(void)
359 {
360         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
361         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
362         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
363         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
364         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
365
366         platform_device_register(&tegra_i2c_device5);
367         platform_device_register(&tegra_i2c_device4);
368         platform_device_register(&tegra_i2c_device3);
369         platform_device_register(&tegra_i2c_device2);
370         platform_device_register(&tegra_i2c_device1);
371
372         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
373                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
374         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
375         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
376         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
377
378         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
379         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
380 }
381
382 static struct platform_device *cardhu_uart_devices[] __initdata = {
383         &tegra_uarta_device,
384         &tegra_uartb_device,
385         &tegra_uartc_device,
386         &tegra_uartd_device,
387         &tegra_uarte_device,
388 };
389 static struct uart_clk_parent uart_parent_clk[] = {
390         [0] = {.name = "clk_m"},
391         [1] = {.name = "pll_p"},
392 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
393         [2] = {.name = "pll_m"},
394 #endif
395 };
396
397 static struct tegra_uart_platform_data cardhu_uart_pdata;
398 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
399
400 static void __init uart_debug_init(void)
401 {
402         struct board_info board_info;
403         int debug_port_id;
404
405         tegra_get_board_info(&board_info);
406
407         debug_port_id = get_tegra_uart_debug_port_id();
408         if (debug_port_id < 0) {
409                 debug_port_id = 0;
410                         /* UARTB is debug port
411                          *       for SLT - E1186/E1187/PM269
412                          *       for E1256/E1257
413                          */
414                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
415                         ((board_info.board_id == BOARD_E1186) ||
416                         (board_info.board_id == BOARD_E1187) ||
417                         (board_info.board_id == BOARD_PM269))) ||
418                         (board_info.board_id == BOARD_E1256) ||
419                         (board_info.board_id == BOARD_E1257))
420                                 debug_port_id = 1;
421         }
422
423         switch (debug_port_id) {
424         case 0:
425                 /* UARTA is the debug port. */
426                 pr_info("Selecting UARTA as the debug console\n");
427                 cardhu_uart_devices[0] = &debug_uarta_device;
428                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
429                 debug_uart_port_base = ((struct plat_serial8250_port *)(
430                         debug_uarta_device.dev.platform_data))->mapbase;
431                 break;
432
433         case 1:
434                 /* UARTB is the debug port. */
435                 pr_info("Selecting UARTB as the debug console\n");
436                 cardhu_uart_devices[1] = &debug_uartb_device;
437                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
438                 debug_uart_port_base = ((struct plat_serial8250_port *)(
439                         debug_uartb_device.dev.platform_data))->mapbase;
440                 break;
441
442         case 2:
443                 /* UARTC is the debug port. */
444                 pr_info("Selecting UARTC as the debug console\n");
445                 cardhu_uart_devices[2] = &debug_uartc_device;
446                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
447                 debug_uart_port_base = ((struct plat_serial8250_port *)(
448                         debug_uartc_device.dev.platform_data))->mapbase;
449                 break;
450
451         case 3:
452                 /* UARTD is the debug port. */
453                 pr_info("Selecting UARTD as the debug console\n");
454                 cardhu_uart_devices[3] = &debug_uartd_device;
455                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
456                 debug_uart_port_base = ((struct plat_serial8250_port *)(
457                         debug_uartd_device.dev.platform_data))->mapbase;
458                 break;
459
460         case 4:
461                 /* UARTE is the debug port. */
462                 pr_info("Selecting UARTE as the debug console\n");
463                 cardhu_uart_devices[4] = &debug_uarte_device;
464                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
465                 debug_uart_port_base = ((struct plat_serial8250_port *)(
466                         debug_uarte_device.dev.platform_data))->mapbase;
467                 break;
468
469         default:
470                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
471                 cardhu_uart_devices[0] = &debug_uarta_device;
472                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
473                 debug_uart_port_base = ((struct plat_serial8250_port *)(
474                         debug_uarta_device.dev.platform_data))->mapbase;
475                 break;
476         }
477         return;
478 }
479
480 static void __init cardhu_uart_init(void)
481 {
482         struct clk *c;
483         int i;
484
485         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
486                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
487                 if (IS_ERR_OR_NULL(c)) {
488                         pr_err("Not able to get the clock for %s\n",
489                                                 uart_parent_clk[i].name);
490                         continue;
491                 }
492                 uart_parent_clk[i].parent_clk = c;
493                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
494         }
495         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
496         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
497         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
498         cardhu_loopback_uart_pdata.parent_clk_count =
499                                                 ARRAY_SIZE(uart_parent_clk);
500         cardhu_loopback_uart_pdata.is_loopback = true;
501         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
502         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
503         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
504         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
505         /* UARTE is used for loopback test purpose */
506         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
507
508         /* Register low speed only if it is selected */
509         if (!is_tegra_debug_uartport_hs()) {
510                 uart_debug_init();
511                 /* Clock enable for the debug channel */
512                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
513                         pr_info("The debug console clock name is %s\n",
514                                                 debug_uart_clk->name);
515                         c = tegra_get_clock_by_name("pll_p");
516                         if (IS_ERR_OR_NULL(c))
517                                 pr_err("Not getting the parent clock pll_p\n");
518                         else
519                                 clk_set_parent(debug_uart_clk, c);
520
521                         clk_enable(debug_uart_clk);
522                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
523                 } else {
524                         pr_err("Not getting the clock %s for debug console\n",
525                                         debug_uart_clk->name);
526                 }
527         }
528
529         platform_add_devices(cardhu_uart_devices,
530                                 ARRAY_SIZE(cardhu_uart_devices));
531 }
532
533 static struct platform_device tegra_camera = {
534         .name = "tegra_camera",
535         .id = -1,
536 };
537
538 static struct platform_device *cardhu_spi_devices[] __initdata = {
539         &tegra_spi_device4,
540 };
541
542 static struct platform_device *touch_spi_device[] __initdata = {
543         &tegra_spi_device1,
544 };
545
546 struct spi_clk_parent spi_parent_clk[] = {
547         [0] = {.name = "pll_p"},
548 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
549         [1] = {.name = "pll_m"},
550         [2] = {.name = "clk_m"},
551 #else
552         [1] = {.name = "clk_m"},
553 #endif
554 };
555
556 static struct tegra_spi_platform_data cardhu_spi_pdata = {
557         .is_dma_based           = true,
558         .max_dma_buffer         = (16 * 1024),
559         .is_clkon_always        = false,
560         .max_rate               = 100000000,
561 };
562
563 static void __init cardhu_spi_init(void)
564 {
565         int i;
566         struct clk *c;
567         struct board_info board_info, display_board_info;
568
569         tegra_get_board_info(&board_info);
570         tegra_get_display_board_info(&display_board_info);
571
572         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
573                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
574                 if (IS_ERR_OR_NULL(c)) {
575                         pr_err("Not able to get the clock for %s\n",
576                                                 spi_parent_clk[i].name);
577                         continue;
578                 }
579                 spi_parent_clk[i].parent_clk = c;
580                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
581         }
582         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
583         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
584         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
585         platform_add_devices(cardhu_spi_devices,
586                                 ARRAY_SIZE(cardhu_spi_devices));
587
588         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
589                 platform_add_devices(touch_spi_device,
590                                 ARRAY_SIZE(touch_spi_device));
591         }
592         if (board_info.board_id == BOARD_E1198) {
593                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
594                 platform_device_register(&tegra_spi_device2);
595                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
596                 platform_device_register(&tegra_spi_slave_device1);
597         }
598 }
599
600 static void __init cardhu_dtv_init(void)
601 {
602         struct board_info board_info;
603
604         tegra_get_board_info(&board_info);
605
606         if (board_info.board_id == BOARD_E1186)
607                 platform_device_register(&tegra_dtv_device);
608 }
609
610 static struct resource tegra_rtc_resources[] = {
611         [0] = {
612                 .start = TEGRA_RTC_BASE,
613                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
614                 .flags = IORESOURCE_MEM,
615         },
616         [1] = {
617                 .start = INT_RTC,
618                 .end = INT_RTC,
619                 .flags = IORESOURCE_IRQ,
620         },
621 };
622
623 static struct platform_device tegra_rtc_device = {
624         .name = "tegra_rtc",
625         .id   = -1,
626         .resource = tegra_rtc_resources,
627         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
628 };
629
630 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
631         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
632         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
633         .gpio_hp_mute           = -1,
634         .gpio_int_mic_en        = -1,
635         .gpio_ext_mic_en        = -1,
636 };
637
638 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
639         .gpio_spkr_en           = -1,
640         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
641         .gpio_hp_mute           = -1,
642         .gpio_int_mic_en        = -1,
643         .gpio_ext_mic_en        = -1,
644 };
645
646 static struct platform_device cardhu_audio_wm8903_device = {
647         .name   = "tegra-snd-wm8903",
648         .id     = 0,
649         .dev    = {
650                 .platform_data = &cardhu_audio_wm8903_pdata,
651         },
652 };
653
654 static struct platform_device cardhu_audio_max98095_device = {
655         .name   = "tegra-snd-max98095",
656         .id     = 0,
657         .dev    = {
658                 .platform_data = &cardhu_audio_max98095_pdata,
659         },
660 };
661
662 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
663         .gpio_spkr_en           = -1,
664         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
665         .gpio_hp_mute           = -1,
666         .gpio_int_mic_en        = -1,
667         .gpio_ext_mic_en        = -1,
668         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
669         .audio_port_id          = {
670                 [HIFI_CODEC] = 0,
671                 [BASEBAND] = -1,
672                 [BT_SCO] = 3,
673         },
674         .baseband_param         = {
675                 .rate = -1,
676                 .channels = -1,
677         },
678 };
679
680 static struct platform_device cardhu_audio_aic326x_device = {
681         .name   = "tegra-snd-aic326x",
682         .id     = 0,
683         .dev    = {
684                 .platform_data  = &cardhu_audio_aic326x_pdata,
685         },
686 };
687
688 static struct platform_device *cardhu_devices[] __initdata = {
689         &tegra_pmu_device,
690         &tegra_rtc_device,
691         &tegra_udc_device,
692 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
693         &tegra_smmu_device,
694 #endif
695         &tegra_wdt_device,
696 #if defined(CONFIG_TEGRA_AVP)
697         &tegra_avp_device,
698 #endif
699         &tegra_camera,
700 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
701         &tegra_se_device,
702 #endif
703         &tegra_ahub_device,
704         &tegra_dam_device0,
705         &tegra_dam_device1,
706         &tegra_dam_device2,
707         &tegra_i2s_device0,
708         &tegra_i2s_device1,
709         &tegra_i2s_device3,
710         &tegra_spdif_device,
711         &spdif_dit_device,
712         &bluetooth_dit_device,
713         &baseband_dit_device,
714         &cardhu_bcm4329_rfkill_device,
715         &tegra_pcm_device,
716         &cardhu_audio_wm8903_device,
717         &cardhu_audio_max98095_device,
718         &cardhu_audio_aic326x_device,
719         &tegra_hda_device,
720 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
721         &tegra_aes_device,
722 #endif
723 };
724
725 #define E1506_MXT_CONFIG_CRC 0x62F903
726 static const u8 e1506_config[] = {
727         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
728         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
729         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
730         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
731         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
732         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
733         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
734         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
735         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
736         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
737         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
738         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
739         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
740         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
741         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
742         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
743         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
744         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
745         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
746         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
747         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
748         0x00
749 };
750
751 #define MXT_CONFIG_CRC  0xD62DE8
752 static const u8 config[] = {
753         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
754         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
755         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
756         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
757         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
758         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
759         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
760         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
762         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
763         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
764         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
765         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
766         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
767         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
768         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
769         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
770         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
771         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
772         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
773 };
774
775 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
776 static const u8 config_sku2000[] = {
777         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
778         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
779         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
780         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
781         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
782         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
783         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
784         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
786         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
788         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
789         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
790         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
791         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
792         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
793         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
794         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
795         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
796         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
797 };
798
799 static struct mxt_platform_data atmel_mxt_info = {
800         .x_line         = 27,
801         .y_line         = 42,
802         .x_size         = 768,
803         .y_size         = 1366,
804         .blen           = 0x20,
805         .threshold      = 0x3C,
806         .voltage        = 3300000,              /* 3.3V */
807         .orient         = 5,
808         .config         = config,
809         .config_length  = 157,
810         .config_crc     = MXT_CONFIG_CRC,
811         .irqflags       = IRQF_TRIGGER_FALLING,
812 /*      .read_chg       = &read_chg, */
813         .read_chg       = NULL,
814 };
815
816 static struct mxt_platform_data e1506_atmel_mxt_info = {
817         .x_line         = 19,
818         .y_line         = 11,
819         .x_size         = 960,
820         .y_size         = 540,
821         .blen           = 0x10,
822         .threshold      = 0x32,
823         .voltage        = 3300000,              /* 3.3V */
824         .orient         = 3,
825         .config         = e1506_config,
826         .config_length  = 168,
827         .config_crc     = E1506_MXT_CONFIG_CRC,
828         .irqflags       = IRQF_TRIGGER_FALLING,
829 /*      .read_chg       = &read_chg, */
830         .read_chg       = NULL,
831 };
832
833 static struct i2c_board_info __initdata atmel_i2c_info[] = {
834         {
835                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
836                 .platform_data = &atmel_mxt_info,
837         }
838 };
839
840 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
841         {
842                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
843                 .platform_data = &e1506_atmel_mxt_info,
844         }
845 };
846
847 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
848         /* name         parent          rate            enabled */
849         { "sbc1",       "pll_p",        52000000,       true},
850         { NULL,         NULL,           0,              0},
851 };
852
853 static int __init cardhu_touch_init(void)
854 {
855         struct board_info BoardInfo, DisplayBoardInfo;
856
857         tegra_get_board_info(&BoardInfo);
858         tegra_get_display_board_info(&DisplayBoardInfo);
859         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
860                 tegra_clk_init_from_table(spi_clk_init_table);
861
862                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
863         } else {
864                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
865                 gpio_direction_input(TEGRA_GPIO_PH4);
866
867                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
868                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
869                 msleep(1);
870                 gpio_set_value(TEGRA_GPIO_PH6, 1);
871                 msleep(100);
872
873                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
874                         atmel_mxt_info.config = config_sku2000;
875                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
876                 }
877
878                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
879                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
880                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
881                 } else {
882                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
883                         i2c_register_board_info(1, atmel_i2c_info, 1);
884                 }
885         }
886
887         return 0;
888 }
889
890 static void cardu_usb_hsic_postsupend(void)
891 {
892 #ifdef CONFIG_TEGRA_BB_XMM_POWER
893         baseband_xmm_set_power_status(BBXMM_PS_L2);
894 #endif
895 }
896
897 static void cardu_usb_hsic_preresume(void)
898 {
899 #ifdef CONFIG_TEGRA_BB_XMM_POWER
900         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
901 #endif
902 }
903
904 static void cardu_usb_hsic_phy_ready(void)
905 {
906 #ifdef CONFIG_TEGRA_BB_XMM_POWER
907         baseband_xmm_set_power_status(BBXMM_PS_L0);
908 #endif
909 }
910
911 static void cardu_usb_hsic_phy_off(void)
912 {
913 #ifdef CONFIG_TEGRA_BB_XMM_POWER
914         baseband_xmm_set_power_status(BBXMM_PS_L3);
915 #endif
916 }
917
918 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
919         .post_suspend = cardu_usb_hsic_postsupend,
920         .pre_resume = cardu_usb_hsic_preresume,
921         .port_power = cardu_usb_hsic_phy_ready,
922         .post_phy_off = cardu_usb_hsic_phy_off,
923 };
924
925 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
926         .port_otg = false,
927         .has_hostpc = true,
928         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
929         .op_mode        = TEGRA_USB_OPMODE_HOST,
930         .u_data.host = {
931                 .vbus_gpio = -1,
932                 .hot_plug = false,
933                 .remote_wakeup_supported = false,
934                 .power_off_on_suspend = false,
935         },
936         .u_cfg.hsic = {
937                 .sync_start_delay = 9,
938                 .idle_wait_delay = 17,
939                 .term_range_adj = 0,
940                 .elastic_underrun_limit = 16,
941                 .elastic_overrun_limit = 16,
942         },
943         .ops = &hsic_xmm_plat_ops,
944 };
945
946
947 static int hsic_enable_gpio = -1;
948 static int hsic_reset_gpio = -1;
949
950 void hsic_platform_open(void)
951 {
952         int reset_gpio = 0, enable_gpio = 0;
953
954         if (hsic_enable_gpio != -1)
955                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
956         if (hsic_reset_gpio != -1)
957                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
958         /* hsic enable signal deasserted, hsic reset asserted */
959         if (!enable_gpio)
960                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
961         if (!reset_gpio)
962                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
963         if (!enable_gpio)
964                 tegra_gpio_enable(hsic_enable_gpio);
965         if (!reset_gpio)
966                 tegra_gpio_enable(hsic_reset_gpio);
967         /* keep hsic reset asserted for 1 ms */
968         udelay(1000);
969         /* enable (power on) hsic */
970         if (!enable_gpio)
971                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
972         udelay(1000);
973         /* deassert reset */
974         if (!reset_gpio)
975                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
976
977 }
978
979 void hsic_platform_close(void)
980 {
981         if (hsic_enable_gpio != -1) {
982                 gpio_set_value(hsic_enable_gpio, 0);
983                 gpio_free(hsic_enable_gpio);
984         }
985         if (hsic_reset_gpio != -1) {
986                 gpio_set_value(hsic_reset_gpio, 0);
987                 gpio_free(hsic_reset_gpio);
988         }
989 }
990
991 void hsic_power_on(void)
992 {
993         if (hsic_enable_gpio != -1) {
994                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
995                 udelay(1000);
996         }
997 }
998
999 void hsic_power_off(void)
1000 {
1001         if (hsic_enable_gpio != -1) {
1002                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1003                 udelay(1000);
1004         }
1005 }
1006
1007 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1008         .open = hsic_platform_open,
1009         .close = hsic_platform_close,
1010         .pre_phy_on = hsic_power_on,
1011         .post_phy_off = hsic_power_off,
1012 };
1013
1014 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1015         .port_otg = false,
1016         .has_hostpc = true,
1017         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1018         .op_mode        = TEGRA_USB_OPMODE_HOST,
1019         .u_data.host = {
1020                 .vbus_gpio = -1,
1021                 .hot_plug = false,
1022                 .remote_wakeup_supported = false,
1023                 .power_off_on_suspend = false,
1024         },
1025         .u_cfg.hsic = {
1026                 .sync_start_delay = 9,
1027                 .idle_wait_delay = 17,
1028                 .term_range_adj = 0,
1029                 .elastic_underrun_limit = 16,
1030                 .elastic_overrun_limit = 16,
1031         },
1032         .ops = &hsic_plat_ops,
1033 };
1034
1035 static struct tegra_usb_platform_data tegra_udc_pdata = {
1036         .port_otg = true,
1037         .has_hostpc = true,
1038         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1039         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1040         .u_data.dev = {
1041                 .vbus_pmu_irq = 0,
1042                 .vbus_gpio = -1,
1043                 .charging_supported = false,
1044                 .remote_wakeup_supported = false,
1045         },
1046         .u_cfg.utmi = {
1047                 .hssync_start_delay = 0,
1048                 .elastic_limit = 16,
1049                 .idle_wait_delay = 17,
1050                 .term_range_adj = 6,
1051                 .xcvr_setup = 8,
1052                 .xcvr_lsfslew = 2,
1053                 .xcvr_lsrslew = 2,
1054                 .xcvr_setup_offset = 0,
1055                 .xcvr_use_fuses = 1,
1056         },
1057 };
1058
1059 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1060         .port_otg = true,
1061         .has_hostpc = true,
1062         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1063         .op_mode = TEGRA_USB_OPMODE_HOST,
1064         .u_data.host = {
1065                 .vbus_gpio = -1,
1066                 .vbus_reg = "vdd_vbus_micro_usb",
1067                 .hot_plug = true,
1068                 .remote_wakeup_supported = true,
1069                 .power_off_on_suspend = true,
1070         },
1071         .u_cfg.utmi = {
1072                 .hssync_start_delay = 0,
1073                 .elastic_limit = 16,
1074                 .idle_wait_delay = 17,
1075                 .term_range_adj = 6,
1076                 .xcvr_setup = 15,
1077                 .xcvr_lsfslew = 2,
1078                 .xcvr_lsrslew = 2,
1079                 .xcvr_setup_offset = 0,
1080                 .xcvr_use_fuses = 1,
1081         },
1082 };
1083
1084 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1085         .port_otg = false,
1086         .has_hostpc = true,
1087         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1088         .op_mode        = TEGRA_USB_OPMODE_HOST,
1089         .u_data.host = {
1090                 .vbus_gpio = -1,
1091                 .hot_plug = false,
1092                 .remote_wakeup_supported = true,
1093                 .power_off_on_suspend = true,
1094         },
1095         .u_cfg.utmi = {
1096                 .hssync_start_delay = 0,
1097                 .elastic_limit = 16,
1098                 .idle_wait_delay = 17,
1099                 .term_range_adj = 6,
1100                 .xcvr_setup = 15,
1101                 .xcvr_lsfslew = 2,
1102                 .xcvr_lsrslew = 2,
1103                 .xcvr_setup_offset = 0,
1104                 .xcvr_use_fuses = 1,
1105         },
1106 };
1107
1108 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1109         .port_otg = false,
1110         .has_hostpc = true,
1111         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1112         .op_mode        = TEGRA_USB_OPMODE_HOST,
1113         .u_data.host = {
1114                 .vbus_gpio = -1,
1115                 .vbus_reg = "vdd_vbus_typea_usb",
1116                 .hot_plug = true,
1117                 .remote_wakeup_supported = true,
1118                 .power_off_on_suspend = true,
1119         },
1120         .u_cfg.utmi = {
1121                 .hssync_start_delay = 0,
1122                 .elastic_limit = 16,
1123                 .idle_wait_delay = 17,
1124                 .term_range_adj = 6,
1125                 .xcvr_setup = 8,
1126                 .xcvr_lsfslew = 2,
1127                 .xcvr_lsrslew = 2,
1128                 .xcvr_setup_offset = 0,
1129                 .xcvr_use_fuses = 1,
1130         },
1131 };
1132
1133 static struct tegra_usb_otg_data tegra_otg_pdata = {
1134         .ehci_device = &tegra_ehci1_device,
1135         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1136 };
1137
1138 #if CONFIG_USB_SUPPORT
1139 static void cardhu_usb_init(void)
1140 {
1141         struct board_info bi;
1142
1143         tegra_get_board_info(&bi);
1144
1145         /* OTG should be the first to be registered */
1146         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1147         platform_device_register(&tegra_otg_device);
1148
1149         /* setup the udc platform data */
1150         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1151
1152         if (bi.board_id == BOARD_PM267) {
1153                 hsic_enable_gpio = EN_HSIC_GPIO;
1154                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1155                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1156                 platform_device_register(&tegra_ehci2_device);
1157         } else if (bi.board_id == BOARD_E1256) {
1158                 hsic_enable_gpio = EN_HSIC_GPIO;
1159                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1160                 platform_device_register(&tegra_ehci2_device);
1161         } else if (bi.board_id == BOARD_E1186) {
1162                 tegra_ehci2_device.dev.platform_data =
1163                                                 &tegra_ehci2_hsic_xmm_pdata;
1164                 /* ehci2 registration happens in baseband-xmm-power  */
1165         } else {
1166                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1167                 platform_device_register(&tegra_ehci2_device);
1168         }
1169
1170         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1171         platform_device_register(&tegra_ehci3_device);
1172
1173 }
1174 #else
1175 static void cardhu_usb_init(void) { }
1176 #endif
1177
1178 static struct baseband_power_platform_data tegra_baseband_power_data = {
1179         .baseband_type = BASEBAND_XMM,
1180         .modem = {
1181         .xmm = {
1182                         .bb_rst = XMM_GPIO_BB_RST,
1183                         .bb_on = XMM_GPIO_BB_ON,
1184                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1185                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1186                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1187                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1188                         .hsic_device = &tegra_ehci2_device,
1189                 },
1190         },
1191 };
1192
1193 static struct platform_device tegra_baseband_power_device = {
1194         .name = "baseband_xmm_power",
1195         .id = -1,
1196         .dev = {
1197                 .platform_data = &tegra_baseband_power_data,
1198         },
1199 };
1200
1201 static struct platform_device tegra_baseband_power2_device = {
1202         .name = "baseband_xmm_power2",
1203         .id = -1,
1204         .dev = {
1205                 .platform_data = &tegra_baseband_power_data,
1206         },
1207 };
1208
1209
1210 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1211         .port_status[0] = 1,
1212         .port_status[1] = 1,
1213         .port_status[2] = 1,
1214         .use_dock_detect        = 0,
1215         .gpio           = 0,
1216 };
1217
1218 static void cardhu_pci_init(void)
1219 {
1220         struct board_info board_info;
1221
1222         tegra_get_board_info(&board_info);
1223         if (board_info.board_id == BOARD_E1291) {
1224                 cardhu_pci_platform_data.port_status[0] = 0;
1225                 cardhu_pci_platform_data.port_status[1] = 0;
1226                 cardhu_pci_platform_data.port_status[2] = 1;
1227                 cardhu_pci_platform_data.use_dock_detect = 1;
1228                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1229         }
1230         if ((board_info.board_id == BOARD_E1186) ||
1231                 (board_info.board_id == BOARD_E1187) ||
1232                 (board_info.board_id == BOARD_E1291)) {
1233                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1234                 platform_device_register(&tegra_pci_device);
1235         }
1236 }
1237
1238 static void cardhu_modem_init(void)
1239 {
1240         struct board_info board_info;
1241         int w_disable_gpio, ret;
1242
1243         tegra_get_board_info(&board_info);
1244         switch (board_info.board_id) {
1245         case BOARD_E1291:
1246         case BOARD_E1198:
1247                 if (((board_info.board_id == BOARD_E1291) &&
1248                                 (board_info.fab < BOARD_FAB_A03)) ||
1249                         ((board_info.board_id == BOARD_E1198) &&
1250                                         (board_info.fab < BOARD_FAB_A02))) {
1251                         w_disable_gpio = TEGRA_GPIO_PH5;
1252                 } else {
1253                         w_disable_gpio = TEGRA_GPIO_PDD5;
1254                 }
1255
1256                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1257                 if (ret < 0)
1258                         pr_err("%s: gpio_request failed for gpio %d\n",
1259                                 __func__, w_disable_gpio);
1260                 else
1261                         gpio_direction_input(w_disable_gpio);
1262
1263                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1264                 if (((board_info.board_id == BOARD_E1291) &&
1265                                 (board_info.fab >= BOARD_FAB_A04)) ||
1266                         ((board_info.board_id == BOARD_E1198) &&
1267                                         (board_info.fab >= BOARD_FAB_A02))) {
1268                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1269                         if (ret < 0) {
1270                                 pr_err("%s(): Error in allocating gpio "
1271                                         "TEGRA_GPIO_PH7\n", __func__);
1272                                 break;
1273                         }
1274                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1275                 }
1276                 break;
1277         case BOARD_E1186:
1278                 platform_device_register(&tegra_baseband_power_device);
1279                 platform_device_register(&tegra_baseband_power2_device);
1280                 break;
1281         default:
1282                 break;
1283         }
1284
1285 }
1286
1287 #ifdef CONFIG_SATA_AHCI_TEGRA
1288 static void cardhu_sata_init(void)
1289 {
1290         platform_device_register(&tegra_sata_device);
1291 }
1292 #else
1293 static void cardhu_sata_init(void) { }
1294 #endif
1295
1296 static void __init tegra_cardhu_init(void)
1297 {
1298         tegra_thermal_init(&thermal_data);
1299         tegra_clk_init_from_table(cardhu_clk_init_table);
1300         tegra_enable_pinmux();
1301         cardhu_pinmux_init();
1302         cardhu_i2c_init();
1303         cardhu_spi_init();
1304         cardhu_usb_init();
1305 #ifdef CONFIG_TEGRA_EDP_LIMITS
1306         cardhu_edp_init();
1307 #endif
1308         cardhu_uart_init();
1309         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1310         tegra_ram_console_debug_init();
1311         cardhu_sdhci_init();
1312         cardhu_regulator_init();
1313         cardhu_dtv_init();
1314         cardhu_suspend_init();
1315         cardhu_touch_init();
1316         cardhu_modem_init();
1317         cardhu_kbc_init();
1318         cardhu_scroll_init();
1319         cardhu_keys_init();
1320         cardhu_panel_init();
1321         cardhu_pmon_init();
1322         cardhu_sensors_init();
1323         cardhu_setup_bluesleep();
1324         cardhu_sata_init();
1325         //audio_wired_jack_init();
1326         cardhu_pins_state_init();
1327         cardhu_emc_init();
1328         tegra_release_bootloader_fb();
1329         cardhu_pci_init();
1330 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1331         tegra_wdt_recovery_init();
1332 #endif
1333 }
1334
1335 static void __init tegra_cardhu_reserve(void)
1336 {
1337 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1338         /* support 1920X1200 with 24bpp */
1339         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1340 #else
1341         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1342 #endif
1343         tegra_ram_console_debug_reserve(SZ_1M);
1344 }
1345
1346 MACHINE_START(CARDHU, "cardhu")
1347         .atag_offset    = 0x100,
1348         .map_io         = tegra_map_common_io,
1349         .reserve        = tegra_cardhu_reserve,
1350         .init_early     = tegra30_init_early,
1351         .init_irq       = tegra_init_irq,
1352         .handle_irq     = gic_handle_irq,
1353         .timer          = &tegra_timer,
1354         .init_machine   = tegra_cardhu_init,
1355         .restart        = tegra_assert_system_reset,
1356 MACHINE_END