ARM: Tegra: Set i2s_sync as parent of audio clock for Tegra30
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41
42 #include <sound/wm8903.h>
43
44 #include <mach/clk.h>
45 #include <mach/iomap.h>
46 #include <mach/irqs.h>
47 #include <mach/pinmux.h>
48 #include <mach/iomap.h>
49 #include <mach/io.h>
50 #include <mach/i2s.h>
51 #include <mach/tegra_wm8903_pdata.h>
52 #include <asm/mach-types.h>
53 #include <asm/mach/arch.h>
54 #include <mach/usb_phy.h>
55 #include <mach/thermal.h>
56 #include <mach/pci.h>
57
58 #include "board.h"
59 #include "clock.h"
60 #include "board-cardhu.h"
61 #include "devices.h"
62 #include "gpio-names.h"
63 #include "fuse.h"
64 #include "pm.h"
65 #include "baseband-xmm-power.h"
66
67 /* All units are in millicelsius */
68 static struct tegra_thermal_data thermal_data = {
69         .temp_throttle = 85000,
70         .temp_shutdown = 90000,
71         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
72 #ifdef CONFIG_TEGRA_EDP_LIMITS
73         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
74         .hysteresis_edp = 3000,
75 #endif
76 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
77         .tc1 = 0,
78         .tc2 = 1,
79         .passive_delay = 2000,
80 #else
81         .hysteresis_throttle = 1000,
82 #endif
83 };
84
85 /* !!!TODO: Change for cardhu (Taken from Ventana) */
86 static struct tegra_utmip_config utmi_phy_config[] = {
87         [0] = {
88                         .hssync_start_delay = 0,
89                         .idle_wait_delay = 17,
90                         .elastic_limit = 16,
91                         .term_range_adj = 6,
92                         .xcvr_setup = 15,
93                         .xcvr_setup_offset = 0,
94                         .xcvr_use_fuses = 1,
95                         .xcvr_lsfslew = 2,
96                         .xcvr_lsrslew = 2,
97         },
98         [1] = {
99                         .hssync_start_delay = 0,
100                         .idle_wait_delay = 17,
101                         .elastic_limit = 16,
102                         .term_range_adj = 6,
103                         .xcvr_setup = 15,
104                         .xcvr_setup_offset = 0,
105                         .xcvr_use_fuses = 1,
106                         .xcvr_lsfslew = 2,
107                         .xcvr_lsrslew = 2,
108         },
109         [2] = {
110                         .hssync_start_delay = 0,
111                         .idle_wait_delay = 17,
112                         .elastic_limit = 16,
113                         .term_range_adj = 6,
114                         .xcvr_setup = 8,
115                         .xcvr_setup_offset = 0,
116                         .xcvr_use_fuses = 1,
117                         .xcvr_lsfslew = 2,
118                         .xcvr_lsrslew = 2,
119         },
120 };
121
122 #ifdef CONFIG_BCM4329_RFKILL
123 static struct resource cardhu_bcm4329_rfkill_resources[] = {
124         {
125                 .name   = "bcm4329_nshutdown_gpio",
126                 .start  = TEGRA_GPIO_PU0,
127                 .end    = TEGRA_GPIO_PU0,
128                 .flags  = IORESOURCE_IO,
129         },
130 };
131
132 static struct platform_device cardhu_bcm4329_rfkill_device = {
133         .name = "bcm4329_rfkill",
134         .id             = -1,
135         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
136         .resource       = cardhu_bcm4329_rfkill_resources,
137 };
138
139 static noinline void __init cardhu_bt_rfkill(void)
140 {
141         platform_device_register(&cardhu_bcm4329_rfkill_device);
142
143         return;
144 }
145 #else
146 static inline void cardhu_bt_rfkill(void) { }
147 #endif
148
149 #ifdef CONFIG_BT_BLUESLEEP
150 static noinline void __init tegra_setup_bluesleep(void)
151 {
152         struct platform_device *pdev = NULL;
153         struct resource *res;
154
155         pdev = platform_device_alloc("bluesleep", 0);
156         if (!pdev) {
157                 pr_err("unable to allocate platform device for bluesleep");
158                 return;
159         }
160
161         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
162         if (!res) {
163                 pr_err("unable to allocate resource for bluesleep\n");
164                 goto err_free_dev;
165         }
166
167         res[0].name   = "gpio_host_wake";
168         res[0].start  = TEGRA_GPIO_PU6;
169         res[0].end    = TEGRA_GPIO_PU6;
170         res[0].flags  = IORESOURCE_IO;
171
172         res[1].name   = "gpio_ext_wake";
173         res[1].start  = TEGRA_GPIO_PU1;
174         res[1].end    = TEGRA_GPIO_PU1;
175         res[1].flags  = IORESOURCE_IO;
176
177         res[2].name   = "host_wake";
178         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
179         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
180         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
181
182         if (platform_device_add_resources(pdev, res, 3)) {
183                 pr_err("unable to add resources to bluesleep device\n");
184                 goto err_free_res;
185         }
186
187         if (platform_device_add(pdev)) {
188                 pr_err("unable to add bluesleep device\n");
189                 goto err_free_res;
190         }
191         tegra_gpio_enable(TEGRA_GPIO_PU6);
192         tegra_gpio_enable(TEGRA_GPIO_PU1);
193
194 return;
195
196 err_free_res:
197         kfree(res);
198 err_free_dev:
199         platform_device_put(pdev);
200         return;
201 }
202 #else
203 static inline void tegra_setup_bluesleep(void) { }
204 #endif
205
206 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
207         /* name         parent          rate            enabled */
208         { "pll_m",      NULL,           0,              false},
209         { "hda",        "pll_p",        108000000,      false},
210         { "hda2codec_2x","pll_p",       48000000,       false},
211         { "pwm",        "pll_p",        3187500,        false},
212         { "blink",      "clk_32k",      32768,          true},
213         { "i2s1",       "pll_a_out0",   0,              false},
214         { "i2s3",       "pll_a_out0",   0,              false},
215         { "spdif_out",  "pll_a_out0",   0,              false},
216         { "d_audio",    "pll_a_out0",   0,              false},
217         { "dam0",       "pll_a_out0",   0,              false},
218         { "dam1",       "pll_a_out0",   0,              false},
219         { "dam2",       "pll_a_out0",   0,              false},
220         { "audio1",     "i2s1_sync",    0,              false},
221         { "audio3",     "i2s3_sync",    0,              false},
222         { "vi_sensor",  "pll_p",        150000000,      false},
223         { "i2c1",       "pll_p",        3200000,        false},
224         { "i2c2",       "pll_p",        3200000,        false},
225         { "i2c3",       "pll_p",        3200000,        false},
226         { "i2c4",       "pll_p",        3200000,        false},
227         { "i2c5",       "pll_p",        3200000,        false},
228         { NULL,         NULL,           0,              0},
229 };
230
231 static struct pn544_i2c_platform_data nfc_pdata = {
232         .irq_gpio = TEGRA_GPIO_PX0,
233         .ven_gpio = TEGRA_GPIO_PP3,
234         .firm_gpio = TEGRA_GPIO_PO7,
235         };
236
237 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
238         {
239                 I2C_BOARD_INFO("pn544", 0x28),
240                 .platform_data = &nfc_pdata,
241                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
242         },
243 };
244 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
245         .adapter_nr     = 0,
246         .bus_count      = 1,
247         .bus_clk_rate   = { 100000, 0 },
248         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
249         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
250         .arb_recovery = arb_lost_recovery,
251 };
252
253 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
254         .adapter_nr     = 1,
255         .bus_count      = 1,
256         .bus_clk_rate   = { 100000, 0 },
257         .is_clkon_always = true,
258         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
259         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
260         .arb_recovery = arb_lost_recovery,
261 };
262
263 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
264         .adapter_nr     = 2,
265         .bus_count      = 1,
266         .bus_clk_rate   = { 100000, 0 },
267         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
268         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
269         .arb_recovery = arb_lost_recovery,
270 };
271
272 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
273         .adapter_nr     = 3,
274         .bus_count      = 1,
275         .bus_clk_rate   = { 100000, 0 },
276         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
277         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
278         .arb_recovery = arb_lost_recovery,
279 };
280
281 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
282         .adapter_nr     = 4,
283         .bus_count      = 1,
284         .bus_clk_rate   = { 400000, 0 },
285         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
286         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
287         .arb_recovery = arb_lost_recovery,
288 };
289
290
291 #if 0
292 struct tegra_wired_jack_conf audio_wr_jack_conf = {
293         .hp_det_n = TEGRA_GPIO_PW2,
294         .en_mic_ext = TEGRA_GPIO_PX1,
295         .en_mic_int = TEGRA_GPIO_PX0,
296 };
297 #endif
298
299 static struct wm8903_platform_data cardhu_wm8903_pdata = {
300         .irq_active_low = 0,
301         .micdet_cfg = 0,
302         .micdet_delay = 100,
303         .gpio_base = CARDHU_GPIO_WM8903(0),
304         .gpio_cfg = {
305                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
306                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
307                         WM8903_GP2_DIR,
308                 0,
309                 WM8903_GPIO_NO_CONFIG,
310                 WM8903_GPIO_NO_CONFIG,
311         },
312 };
313
314 static struct i2c_board_info __initdata wm8903_board_info = {
315         I2C_BOARD_INFO("wm8903", 0x1a),
316         .platform_data = &cardhu_wm8903_pdata,
317         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
318 };
319
320 static void cardhu_i2c_init(void)
321 {
322         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
323         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
324         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
325         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
326         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
327
328         platform_device_register(&tegra_i2c_device5);
329         platform_device_register(&tegra_i2c_device4);
330         platform_device_register(&tegra_i2c_device3);
331         platform_device_register(&tegra_i2c_device2);
332         platform_device_register(&tegra_i2c_device1);
333
334         i2c_register_board_info(4, &wm8903_board_info, 1);
335         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
336 }
337
338 static struct platform_device *cardhu_uart_devices[] __initdata = {
339         &tegra_uarta_device,
340         &tegra_uartb_device,
341         &tegra_uartc_device,
342         &tegra_uartd_device,
343         &tegra_uarte_device,
344 };
345 static struct uart_clk_parent uart_parent_clk[] = {
346         [0] = {.name = "clk_m"},
347         [1] = {.name = "pll_p"},
348 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
349         [2] = {.name = "pll_m"},
350 #endif
351 };
352
353 static struct tegra_uart_platform_data cardhu_uart_pdata;
354
355 static void __init uart_debug_init(void)
356 {
357         struct board_info board_info;
358         int debug_port_id;
359
360         tegra_get_board_info(&board_info);
361
362         debug_port_id = get_tegra_uart_debug_port_id();
363         if (debug_port_id < 0) {
364                 debug_port_id = 0;
365                         /* UARTB is debug port
366                          *       for SLT - E1186/E1187/PM269
367                          *       for E1256/E1257
368                          */
369                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
370                         ((board_info.board_id == BOARD_E1186) ||
371                         (board_info.board_id == BOARD_E1187) ||
372                         (board_info.board_id == BOARD_PM269))) ||
373                         (board_info.board_id == BOARD_E1256) ||
374                         (board_info.board_id == BOARD_E1257))
375                                 debug_port_id = 1;
376         }
377         switch (debug_port_id) {
378         case 0:
379                 /* UARTA is the debug port. */
380                 pr_info("Selecting UARTA as the debug console\n");
381                 cardhu_uart_devices[0] = &debug_uarta_device;
382                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
383                 debug_uart_port_base = ((struct plat_serial8250_port *)(
384                         debug_uarta_device.dev.platform_data))->mapbase;
385                 break;
386
387         case 1:
388                 /* UARTB is the debug port. */
389                 pr_info("Selecting UARTB as the debug console\n");
390                 cardhu_uart_devices[1] = &debug_uartb_device;
391                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
392                 debug_uart_port_base = ((struct plat_serial8250_port *)(
393                         debug_uartb_device.dev.platform_data))->mapbase;
394                 break;
395
396         case 2:
397                 /* UARTC is the debug port. */
398                 pr_info("Selecting UARTC as the debug console\n");
399                 cardhu_uart_devices[2] = &debug_uartc_device;
400                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
401                 debug_uart_port_base = ((struct plat_serial8250_port *)(
402                         debug_uartc_device.dev.platform_data))->mapbase;
403                 break;
404
405         case 3:
406                 /* UARTD is the debug port. */
407                 pr_info("Selecting UARTD as the debug console\n");
408                 cardhu_uart_devices[3] = &debug_uartd_device;
409                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
410                 debug_uart_port_base = ((struct plat_serial8250_port *)(
411                         debug_uartd_device.dev.platform_data))->mapbase;
412                 break;
413
414         case 4:
415                 /* UARTE is the debug port. */
416                 pr_info("Selecting UARTE as the debug console\n");
417                 cardhu_uart_devices[4] = &debug_uarte_device;
418                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
419                 debug_uart_port_base = ((struct plat_serial8250_port *)(
420                         debug_uarte_device.dev.platform_data))->mapbase;
421                 break;
422
423         default:
424                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
425                 cardhu_uart_devices[0] = &debug_uarta_device;
426                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
427                 debug_uart_port_base = ((struct plat_serial8250_port *)(
428                         debug_uarta_device.dev.platform_data))->mapbase;
429                 break;
430         }
431         return;
432 }
433
434 static void __init cardhu_uart_init(void)
435 {
436         struct clk *c;
437         int i;
438
439         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
440                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
441                 if (IS_ERR_OR_NULL(c)) {
442                         pr_err("Not able to get the clock for %s\n",
443                                                 uart_parent_clk[i].name);
444                         continue;
445                 }
446                 uart_parent_clk[i].parent_clk = c;
447                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
448         }
449         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
450         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
451         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
452         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
453         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
454         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
455         tegra_uarte_device.dev.platform_data = &cardhu_uart_pdata;
456
457         /* Register low speed only if it is selected */
458         if (!is_tegra_debug_uartport_hs()) {
459                 uart_debug_init();
460                 /* Clock enable for the debug channel */
461                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
462                         pr_info("The debug console clock name is %s\n",
463                                                 debug_uart_clk->name);
464                         c = tegra_get_clock_by_name("pll_p");
465                         if (IS_ERR_OR_NULL(c))
466                                 pr_err("Not getting the parent clock pll_p\n");
467                         else
468                                 clk_set_parent(debug_uart_clk, c);
469
470                         clk_enable(debug_uart_clk);
471                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
472                 } else {
473                         pr_err("Not getting the clock %s for debug console\n",
474                                         debug_uart_clk->name);
475                 }
476         }
477
478         platform_add_devices(cardhu_uart_devices,
479                                 ARRAY_SIZE(cardhu_uart_devices));
480 }
481
482 static struct platform_device tegra_camera = {
483         .name = "tegra_camera",
484         .id = -1,
485 };
486
487 static struct platform_device *cardhu_spi_devices[] __initdata = {
488         &tegra_spi_device4,
489 };
490
491 struct spi_clk_parent spi_parent_clk[] = {
492         [0] = {.name = "pll_p"},
493 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
494         [1] = {.name = "pll_m"},
495         [2] = {.name = "clk_m"},
496 #else
497         [1] = {.name = "clk_m"},
498 #endif
499 };
500
501 static struct tegra_spi_platform_data cardhu_spi_pdata = {
502         .is_dma_based           = true,
503         .max_dma_buffer         = (16 * 1024),
504         .is_clkon_always        = false,
505         .max_rate               = 100000000,
506 };
507
508 static void __init cardhu_spi_init(void)
509 {
510         int i;
511         struct clk *c;
512         struct board_info board_info;
513
514         tegra_get_board_info(&board_info);
515
516         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
517                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
518                 if (IS_ERR_OR_NULL(c)) {
519                         pr_err("Not able to get the clock for %s\n",
520                                                 spi_parent_clk[i].name);
521                         continue;
522                 }
523                 spi_parent_clk[i].parent_clk = c;
524                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
525         }
526         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
527         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
528         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
529         platform_add_devices(cardhu_spi_devices,
530                                 ARRAY_SIZE(cardhu_spi_devices));
531
532         if (board_info.board_id == BOARD_E1198) {
533                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
534                 platform_device_register(&tegra_spi_device2);
535         }
536 }
537
538 static struct resource tegra_rtc_resources[] = {
539         [0] = {
540                 .start = TEGRA_RTC_BASE,
541                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
542                 .flags = IORESOURCE_MEM,
543         },
544         [1] = {
545                 .start = INT_RTC,
546                 .end = INT_RTC,
547                 .flags = IORESOURCE_IRQ,
548         },
549 };
550
551 static struct platform_device tegra_rtc_device = {
552         .name = "tegra_rtc",
553         .id   = -1,
554         .resource = tegra_rtc_resources,
555         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
556 };
557
558 static struct tegra_wm8903_platform_data cardhu_audio_pdata = {
559         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
560         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
561         .gpio_hp_mute           = -1,
562         .gpio_int_mic_en        = -1,
563         .gpio_ext_mic_en        = -1,
564 };
565
566 static struct platform_device cardhu_audio_device = {
567         .name   = "tegra-snd-wm8903",
568         .id     = 0,
569         .dev    = {
570                 .platform_data  = &cardhu_audio_pdata,
571         },
572 };
573
574 static struct platform_device *cardhu_devices[] __initdata = {
575         &tegra_pmu_device,
576         &tegra_rtc_device,
577         &tegra_udc_device,
578 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
579         &tegra_smmu_device,
580 #endif
581         &tegra_wdt_device,
582 #if defined(CONFIG_TEGRA_AVP)
583         &tegra_avp_device,
584 #endif
585         &tegra_camera,
586 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
587         &tegra_se_device,
588 #endif
589         &tegra_ahub_device,
590         &tegra_dam_device0,
591         &tegra_dam_device1,
592         &tegra_dam_device2,
593         &tegra_i2s_device1,
594         &tegra_i2s_device3,
595         &tegra_spdif_device,
596         &spdif_dit_device,
597         &bluetooth_dit_device,
598         &tegra_pcm_device,
599         &cardhu_audio_device,
600         &tegra_hda_device,
601 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
602         &tegra_aes_device,
603 #endif
604 };
605
606 #define MXT_CONFIG_CRC  0xD62DE8
607 static const u8 config[] = {
608         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
609         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
610         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
611         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
612         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
613         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
614         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
615         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
616         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
617         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
618         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
619         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
620         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
621         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
622         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
623         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
624         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
625         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
626         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
627         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
628 };
629
630 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
631 static const u8 config_sku2000[] = {
632         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
633         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
634         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
635         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
636         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
637         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
638         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
639         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
640         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
641         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
642         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
643         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
644         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
645         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
646         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
647         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
648         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
649         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
650         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
651         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
652 };
653
654 static struct mxt_platform_data atmel_mxt_info = {
655         .x_line         = 27,
656         .y_line         = 42,
657         .x_size         = 768,
658         .y_size         = 1366,
659         .blen           = 0x20,
660         .threshold      = 0x3C,
661         .voltage        = 3300000,              /* 3.3V */
662         .orient         = 5,
663         .config         = config,
664         .config_length  = 157,
665         .config_crc     = MXT_CONFIG_CRC,
666         .irqflags       = IRQF_TRIGGER_FALLING,
667 /*      .read_chg       = &read_chg, */
668         .read_chg       = NULL,
669 };
670
671 static struct i2c_board_info __initdata atmel_i2c_info[] = {
672         {
673                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
674                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
675                 .platform_data = &atmel_mxt_info,
676         }
677 };
678
679 static int __init cardhu_touch_init(void)
680 {
681         struct board_info BoardInfo;
682
683         tegra_gpio_enable(TEGRA_GPIO_PH4);
684         tegra_gpio_enable(TEGRA_GPIO_PH6);
685
686         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
687         gpio_direction_input(TEGRA_GPIO_PH4);
688
689         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
690         gpio_direction_output(TEGRA_GPIO_PH6, 0);
691         msleep(1);
692         gpio_set_value(TEGRA_GPIO_PH6, 1);
693         msleep(100);
694
695         tegra_get_board_info(&BoardInfo);
696         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
697                 atmel_mxt_info.config = config_sku2000;
698                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
699         }
700
701         i2c_register_board_info(1, atmel_i2c_info, 1);
702
703         return 0;
704 }
705
706 static struct tegra_uhsic_config uhsic_phy_config = {
707         .enable_gpio = EN_HSIC_GPIO,
708         .reset_gpio = -1,
709         .sync_start_delay = 9,
710         .idle_wait_delay = 17,
711         .term_range_adj = 0,
712         .elastic_underrun_limit = 16,
713         .elastic_overrun_limit = 16,
714 };
715
716 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
717         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
718         .phy_config = &uhsic_phy_config,
719         .operating_mode = TEGRA_USB_HOST,
720         .power_down_on_bus_suspend = 1,
721 };
722
723 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
724         [0] = {
725                         .phy_config = &utmi_phy_config[0],
726                         .operating_mode = TEGRA_USB_HOST,
727                         .power_down_on_bus_suspend = 1,
728         },
729         [1] = {
730                         .phy_config = &utmi_phy_config[1],
731                         .operating_mode = TEGRA_USB_HOST,
732                         .power_down_on_bus_suspend = 1,
733         },
734         [2] = {
735                         .phy_config = &utmi_phy_config[2],
736                         .operating_mode = TEGRA_USB_HOST,
737                         .power_down_on_bus_suspend = 1,
738                         .hotplug = 1,
739         },
740 };
741
742 static struct tegra_otg_platform_data tegra_otg_pdata = {
743         .ehci_device = &tegra_ehci1_device,
744         .ehci_pdata = &tegra_ehci_pdata[0],
745 };
746
747 #ifdef CONFIG_USB_SUPPORT
748 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
749         [0] = {
750                         .instance = 0,
751                         .vbus_gpio = -1,
752                         .vbus_reg_supply = "vdd_vbus_micro_usb",
753         },
754         [1] = {
755                         .instance = 1,
756                         .vbus_gpio = -1,
757         },
758         [2] = {
759                         .instance = 2,
760                         .vbus_gpio = -1,
761                         .vbus_reg_supply = "vdd_vbus_typea_usb",
762         },
763 };
764
765 static void cardhu_usb_init(void)
766 {
767         struct board_info bi;
768
769         tegra_get_board_info(&bi);
770
771         tegra_usb_phy_init(tegra_usb_phy_pdata,
772                         ARRAY_SIZE(tegra_usb_phy_pdata));
773
774         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
775         platform_device_register(&tegra_otg_device);
776         if (bi.board_id == BOARD_PM267) {
777                 uhsic_phy_config.reset_gpio =
778                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
779                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
780                 platform_device_register(&tegra_ehci2_device);
781         } else if (bi.board_id == BOARD_E1256) {
782                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
783                 platform_device_register(&tegra_ehci2_device);
784         } else if (bi.board_id == BOARD_E1186) {
785                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
786                 /* baseband registration happens in baseband-xmm-power  */
787         } else {
788                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
789                 platform_device_register(&tegra_ehci2_device);
790         }
791
792         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
793         platform_device_register(&tegra_ehci3_device);
794
795 }
796 #else
797 static void cardhu_usb_init(void) { }
798 #endif
799
800 static void cardhu_gps_init(void)
801 {
802         tegra_gpio_enable(TEGRA_GPIO_PU2);
803         tegra_gpio_enable(TEGRA_GPIO_PU3);
804 }
805
806 static void cardhu_nfc_init(void)
807 {
808         tegra_gpio_enable(TEGRA_GPIO_PX0);
809         tegra_gpio_enable(TEGRA_GPIO_PP3);
810         tegra_gpio_enable(TEGRA_GPIO_PO7);
811 }
812
813 static struct baseband_power_platform_data tegra_baseband_power_data = {
814         .baseband_type = BASEBAND_XMM,
815         .modem = {
816         .xmm = {
817                         .bb_rst = XMM_GPIO_BB_RST,
818                         .bb_on = XMM_GPIO_BB_ON,
819                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
820                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
821                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
822                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
823                         .hsic_device = &tegra_ehci2_device,
824                 },
825         },
826 };
827
828 static struct platform_device tegra_baseband_power_device = {
829         .name = "baseband_xmm_power",
830         .id = -1,
831         .dev = {
832                 .platform_data = &tegra_baseband_power_data,
833         },
834 };
835
836 static struct platform_device tegra_baseband_power2_device = {
837         .name = "baseband_xmm_power2",
838         .id = -1,
839         .dev = {
840                 .platform_data = &tegra_baseband_power_data,
841         },
842 };
843
844
845 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
846         .port_status[0] = 1,
847         .port_status[1] = 1,
848         .port_status[2] = 1,
849         .use_dock_detect        = 0,
850         .gpio           = 0,
851 };
852
853 static void cardhu_pci_init(void)
854 {
855         struct board_info board_info;
856
857         tegra_get_board_info(&board_info);
858         if (board_info.board_id == BOARD_E1291) {
859                 cardhu_pci_platform_data.port_status[0] = 0;
860                 cardhu_pci_platform_data.port_status[1] = 0;
861                 cardhu_pci_platform_data.port_status[2] = 1;
862                 cardhu_pci_platform_data.use_dock_detect = 1;
863                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
864         }
865         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
866         platform_device_register(&tegra_pci_device);
867 }
868
869 static void cardhu_modem_init(void)
870 {
871         struct board_info board_info;
872         int w_disable_gpio, ret;
873
874         tegra_get_board_info(&board_info);
875         switch (board_info.board_id) {
876         case BOARD_E1291:
877         case BOARD_E1198:
878                 if (((board_info.board_id == BOARD_E1291) &&
879                                 (board_info.fab < BOARD_FAB_A03)) ||
880                         ((board_info.board_id == BOARD_E1198) &&
881                                         (board_info.fab < BOARD_FAB_A02))) {
882                         w_disable_gpio = TEGRA_GPIO_PH5;
883                 } else {
884                         w_disable_gpio = TEGRA_GPIO_PDD5;
885                 }
886                 tegra_gpio_enable(w_disable_gpio);
887                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
888                 if (ret < 0)
889                         pr_err("%s: gpio_request failed for gpio %d\n",
890                                 __func__, w_disable_gpio);
891                 else
892                         gpio_direction_input(w_disable_gpio);
893
894                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
895                 if (((board_info.board_id == BOARD_E1291) &&
896                                 (board_info.fab >= BOARD_FAB_A04)) ||
897                         ((board_info.board_id == BOARD_E1198) &&
898                                         (board_info.fab >= BOARD_FAB_A02))) {
899                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
900                         if (ret < 0) {
901                                 pr_err("%s(): Error in allocating gpio "
902                                         "TEGRA_GPIO_PH7\n", __func__);
903                                 break;
904                         }
905                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
906                         tegra_gpio_enable(TEGRA_GPIO_PH7);
907                 }
908                 break;
909         case BOARD_E1186:
910                 tegra_gpio_enable(
911                         tegra_baseband_power_data.modem.xmm.bb_rst);
912                 tegra_gpio_enable(
913                         tegra_baseband_power_data.modem.xmm.bb_on);
914                 tegra_gpio_enable(
915                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
916                 tegra_gpio_enable(
917                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
918                 tegra_gpio_enable(
919                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
920                 tegra_gpio_enable(
921                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
922                 platform_device_register(&tegra_baseband_power_device);
923                 platform_device_register(&tegra_baseband_power2_device);
924                 break;
925         default:
926                 break;
927         }
928
929 }
930
931 #ifdef CONFIG_SATA_AHCI_TEGRA
932 static void cardhu_sata_init(void)
933 {
934         platform_device_register(&tegra_sata_device);
935 }
936 #else
937 static void cardhu_sata_init(void) { }
938 #endif
939
940 static void __init tegra_cardhu_init(void)
941 {
942         tegra_thermal_init(&thermal_data);
943         tegra_clk_init_from_table(cardhu_clk_init_table);
944         cardhu_pinmux_init();
945         cardhu_i2c_init();
946         cardhu_spi_init();
947         cardhu_usb_init();
948 #ifdef CONFIG_TEGRA_EDP_LIMITS
949         cardhu_edp_init();
950 #endif
951         cardhu_uart_init();
952         cardhu_tsensor_init();
953         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
954         cardhu_sdhci_init();
955         cardhu_regulator_init();
956         cardhu_gpio_switch_regulator_init();
957         cardhu_suspend_init();
958         cardhu_power_off_init();
959         cardhu_touch_init();
960         cardhu_gps_init();
961         cardhu_modem_init();
962         cardhu_kbc_init();
963         cardhu_scroll_init();
964         cardhu_keys_init();
965         cardhu_panel_init();
966         cardhu_pmon_init();
967         cardhu_sensors_init();
968         cardhu_bt_rfkill();
969         tegra_setup_bluesleep();
970         cardhu_sata_init();
971         //audio_wired_jack_init();
972         cardhu_pins_state_init();
973         cardhu_emc_init();
974         tegra_release_bootloader_fb();
975         cardhu_nfc_init();
976         cardhu_pci_init();
977 }
978
979 static void __init tegra_cardhu_reserve(void)
980 {
981 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
982         /* support 1920X1200 with 24bpp */
983         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
984 #else
985         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
986 #endif
987 }
988
989 MACHINE_START(CARDHU, "cardhu")
990         .boot_params    = 0x80000100,
991         .map_io         = tegra_map_common_io,
992         .reserve        = tegra_cardhu_reserve,
993         .init_early     = tegra_init_early,
994         .init_irq       = tegra_init_irq,
995         .timer          = &tegra_timer,
996         .init_machine   = tegra_cardhu_init,
997 MACHINE_END