ARM:tegra:cardhu: Enable PCIe for cardhu, E1186 & E1187
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "devices.h"
66 #include "gpio-names.h"
67 #include "fuse.h"
68 #include "pm.h"
69 #include "baseband-xmm-power.h"
70 #include "wdt-recovery.h"
71
72 /* All units are in millicelsius */
73 static struct tegra_thermal_data thermal_data = {
74         .temp_throttle = 85000,
75         .temp_shutdown = 90000,
76         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
77 #ifdef CONFIG_TEGRA_EDP_LIMITS
78         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
79         .hysteresis_edp = 3000,
80 #endif
81 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
82         .tc1 = 0,
83         .tc2 = 1,
84         .passive_delay = 2000,
85 #else
86         .hysteresis_throttle = 1000,
87 #endif
88 };
89
90 /* !!!TODO: Change for cardhu (Taken from Ventana) */
91 static struct tegra_utmip_config utmi_phy_config[] = {
92         [0] = {
93                         .hssync_start_delay = 0,
94                         .idle_wait_delay = 17,
95                         .elastic_limit = 16,
96                         .term_range_adj = 6,
97                         .xcvr_setup = 15,
98                         .xcvr_setup_offset = 0,
99                         .xcvr_use_fuses = 1,
100                         .xcvr_lsfslew = 2,
101                         .xcvr_lsrslew = 2,
102         },
103         [1] = {
104                         .hssync_start_delay = 0,
105                         .idle_wait_delay = 17,
106                         .elastic_limit = 16,
107                         .term_range_adj = 6,
108                         .xcvr_setup = 15,
109                         .xcvr_setup_offset = 0,
110                         .xcvr_use_fuses = 1,
111                         .xcvr_lsfslew = 2,
112                         .xcvr_lsrslew = 2,
113         },
114         [2] = {
115                         .hssync_start_delay = 0,
116                         .idle_wait_delay = 17,
117                         .elastic_limit = 16,
118                         .term_range_adj = 6,
119                         .xcvr_setup = 8,
120                         .xcvr_setup_offset = 0,
121                         .xcvr_use_fuses = 1,
122                         .xcvr_lsfslew = 2,
123                         .xcvr_lsrslew = 2,
124         },
125 };
126
127 static struct resource cardhu_bcm4329_rfkill_resources[] = {
128         {
129                 .name   = "bcm4329_nshutdown_gpio",
130                 .start  = TEGRA_GPIO_PU0,
131                 .end    = TEGRA_GPIO_PU0,
132                 .flags  = IORESOURCE_IO,
133         },
134 };
135
136 static struct platform_device cardhu_bcm4329_rfkill_device = {
137         .name = "bcm4329_rfkill",
138         .id             = -1,
139         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
140         .resource       = cardhu_bcm4329_rfkill_resources,
141 };
142
143 static struct resource cardhu_bluesleep_resources[] = {
144         [0] = {
145                 .name = "gpio_host_wake",
146                         .start  = TEGRA_GPIO_PU6,
147                         .end    = TEGRA_GPIO_PU6,
148                         .flags  = IORESOURCE_IO,
149         },
150         [1] = {
151                 .name = "gpio_ext_wake",
152                         .start  = TEGRA_GPIO_PU1,
153                         .end    = TEGRA_GPIO_PU1,
154                         .flags  = IORESOURCE_IO,
155         },
156         [2] = {
157                 .name = "host_wake",
158                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
159                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
160                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
161         },
162 };
163
164 static struct platform_device cardhu_bluesleep_device = {
165         .name           = "bluesleep",
166         .id             = -1,
167         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
168         .resource       = cardhu_bluesleep_resources,
169 };
170
171 static noinline void __init cardhu_setup_bluesleep(void)
172 {
173         platform_device_register(&cardhu_bluesleep_device);
174         tegra_gpio_enable(TEGRA_GPIO_PU6);
175         tegra_gpio_enable(TEGRA_GPIO_PU1);
176         return;
177 }
178
179 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
180         /* name         parent          rate            enabled */
181         { "pll_m",      NULL,           0,              false},
182         { "hda",        "pll_p",        108000000,      false},
183         { "hda2codec_2x","pll_p",       48000000,       false},
184         { "pwm",        "pll_p",        3187500,        false},
185         { "blink",      "clk_32k",      32768,          true},
186         { "i2s0",       "pll_a_out0",   0,              false},
187         { "i2s1",       "pll_a_out0",   0,              false},
188         { "i2s3",       "pll_a_out0",   0,              false},
189         { "spdif_out",  "pll_a_out0",   0,              false},
190         { "d_audio",    "clk_m",        12000000,       false},
191         { "dam0",       "clk_m",        12000000,       false},
192         { "dam1",       "clk_m",        12000000,       false},
193         { "dam2",       "clk_m",        12000000,       false},
194         { "audio1",     "i2s1_sync",    0,              false},
195         { "audio3",     "i2s3_sync",    0,              false},
196         { "vi_sensor",  "pll_p",        150000000,      false},
197         { "i2c1",       "pll_p",        3200000,        false},
198         { "i2c2",       "pll_p",        3200000,        false},
199         { "i2c3",       "pll_p",        3200000,        false},
200         { "i2c4",       "pll_p",        3200000,        false},
201         { "i2c5",       "pll_p",        3200000,        false},
202         { NULL,         NULL,           0,              0},
203 };
204
205 static struct pn544_i2c_platform_data nfc_pdata = {
206         .irq_gpio = TEGRA_GPIO_PX0,
207         .ven_gpio = TEGRA_GPIO_PP3,
208         .firm_gpio = TEGRA_GPIO_PO7,
209         };
210
211 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
212         {
213                 I2C_BOARD_INFO("pn544", 0x28),
214                 .platform_data = &nfc_pdata,
215                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
216         },
217 };
218 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
219         .adapter_nr     = 0,
220         .bus_count      = 1,
221         .bus_clk_rate   = { 100000, 0 },
222         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
223         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
224         .arb_recovery = arb_lost_recovery,
225 };
226
227 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
228         .adapter_nr     = 1,
229         .bus_count      = 1,
230         .bus_clk_rate   = { 100000, 0 },
231         .is_clkon_always = true,
232         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
233         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
234         .arb_recovery = arb_lost_recovery,
235 };
236
237 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
238         .adapter_nr     = 2,
239         .bus_count      = 1,
240         .bus_clk_rate   = { 100000, 0 },
241         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
242         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
243         .arb_recovery = arb_lost_recovery,
244 };
245
246 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
247         .adapter_nr     = 3,
248         .bus_count      = 1,
249         .bus_clk_rate   = { 100000, 0 },
250         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
251         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
252         .arb_recovery = arb_lost_recovery,
253 };
254
255 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
256         .adapter_nr     = 4,
257         .bus_count      = 1,
258         .bus_clk_rate   = { 400000, 0 },
259         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
260         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
261         .arb_recovery = arb_lost_recovery,
262 };
263
264
265 #if 0
266 struct tegra_wired_jack_conf audio_wr_jack_conf = {
267         .hp_det_n = TEGRA_GPIO_PW2,
268         .en_mic_ext = TEGRA_GPIO_PX1,
269         .en_mic_int = TEGRA_GPIO_PX0,
270 };
271 #endif
272
273 static struct wm8903_platform_data cardhu_wm8903_pdata = {
274         .irq_active_low = 0,
275         .micdet_cfg = 0,
276         .micdet_delay = 100,
277         .gpio_base = CARDHU_GPIO_WM8903(0),
278         .gpio_cfg = {
279                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
280                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
281                         WM8903_GP2_DIR,
282                 0,
283                 WM8903_GPIO_NO_CONFIG,
284                 WM8903_GPIO_NO_CONFIG,
285         },
286 };
287
288 /* Equalizer filter coefs generated from the MAXIM MAX98095
289  * evkit software tool */
290 static struct max98095_eq_cfg max98095_eq_cfg[] = {
291         {
292                 .name = "FLAT",
293                 .rate = 44100,
294                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
295                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
296                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
297                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
298                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
299         },
300         {
301                 .name = "LOWPASS1K",
302                 .rate = 44100,
303                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
304                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
305                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
306                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
307                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
308         },
309         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
310                 .name = "HIBOOST",
311                 .rate = 44100,
312                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
313                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
314                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
315                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
316                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
317         },
318         { /* BASS=12dB, TREBLE=+12dB */
319                 .name = "LOUD12DB",
320                 .rate = 44100,
321                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
322                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
323                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
324                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
325                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
326         },
327         {
328                 .name = "FLAT",
329                 .rate = 16000,
330                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
331                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
332                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
333                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
334                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
335         },
336         {
337                 .name = "LOWPASS1K",
338                 .rate = 16000,
339                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
340                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
341                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
342                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
343                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
344         },
345         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
346                 .name = "HIBOOST",
347                 .rate = 16000,
348                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
349                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
350                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
351                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
352                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
353         },
354         { /* BASS=12dB, TREBLE=+12dB */
355                 .name = "LOUD12DB",
356                 .rate = 16000,
357                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
358                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
359                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
360                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
361                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
362         },
363 };
364
365 static struct max98095_pdata cardhu_max98095_pdata = {
366         /* equalizer configuration */
367         .eq_cfg = max98095_eq_cfg,
368         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
369
370         /* Biquad filter response configuration */
371         .bq_cfg = NULL,
372         .bq_cfgcnt = 0,
373
374         /* microphone configuration */
375         .digmic_left_mode = 1,
376         .digmic_right_mode = 1,
377 };
378
379 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
380         I2C_BOARD_INFO("wm8903", 0x1a),
381         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
382         .platform_data = &cardhu_wm8903_pdata,
383 };
384
385 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
386         I2C_BOARD_INFO("aic3262-codec", 0x18),
387         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
388 };
389
390 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
391         I2C_BOARD_INFO("max98095", 0x10),
392         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
393         .platform_data = &cardhu_max98095_pdata,
394 };
395
396 static void cardhu_i2c_init(void)
397 {
398         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
399         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
400         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
401         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
402         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
403
404         platform_device_register(&tegra_i2c_device5);
405         platform_device_register(&tegra_i2c_device4);
406         platform_device_register(&tegra_i2c_device3);
407         platform_device_register(&tegra_i2c_device2);
408         platform_device_register(&tegra_i2c_device1);
409
410         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
411         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
412         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
413
414         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
415 }
416
417 static struct platform_device *cardhu_uart_devices[] __initdata = {
418         &tegra_uarta_device,
419         &tegra_uartb_device,
420         &tegra_uartc_device,
421         &tegra_uartd_device,
422         &tegra_uarte_device,
423 };
424 static struct uart_clk_parent uart_parent_clk[] = {
425         [0] = {.name = "clk_m"},
426         [1] = {.name = "pll_p"},
427 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
428         [2] = {.name = "pll_m"},
429 #endif
430 };
431
432 static struct tegra_uart_platform_data cardhu_uart_pdata;
433 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
434
435 static void __init uart_debug_init(void)
436 {
437         struct board_info board_info;
438         int debug_port_id;
439
440         tegra_get_board_info(&board_info);
441
442         debug_port_id = get_tegra_uart_debug_port_id();
443         if (debug_port_id < 0) {
444                 debug_port_id = 0;
445                         /* UARTB is debug port
446                          *       for SLT - E1186/E1187/PM269
447                          *       for E1256/E1257
448                          */
449                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
450                         ((board_info.board_id == BOARD_E1186) ||
451                         (board_info.board_id == BOARD_E1187) ||
452                         (board_info.board_id == BOARD_PM269))) ||
453                         (board_info.board_id == BOARD_E1256) ||
454                         (board_info.board_id == BOARD_E1257))
455                                 debug_port_id = 1;
456         }
457
458         switch (debug_port_id) {
459         case 0:
460                 /* UARTA is the debug port. */
461                 pr_info("Selecting UARTA as the debug console\n");
462                 cardhu_uart_devices[0] = &debug_uarta_device;
463                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
464                 debug_uart_port_base = ((struct plat_serial8250_port *)(
465                         debug_uarta_device.dev.platform_data))->mapbase;
466                 break;
467
468         case 1:
469                 /* UARTB is the debug port. */
470                 pr_info("Selecting UARTB as the debug console\n");
471                 cardhu_uart_devices[1] = &debug_uartb_device;
472                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
473                 debug_uart_port_base = ((struct plat_serial8250_port *)(
474                         debug_uartb_device.dev.platform_data))->mapbase;
475                 break;
476
477         case 2:
478                 /* UARTC is the debug port. */
479                 pr_info("Selecting UARTC as the debug console\n");
480                 cardhu_uart_devices[2] = &debug_uartc_device;
481                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
482                 debug_uart_port_base = ((struct plat_serial8250_port *)(
483                         debug_uartc_device.dev.platform_data))->mapbase;
484                 break;
485
486         case 3:
487                 /* UARTD is the debug port. */
488                 pr_info("Selecting UARTD as the debug console\n");
489                 cardhu_uart_devices[3] = &debug_uartd_device;
490                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
491                 debug_uart_port_base = ((struct plat_serial8250_port *)(
492                         debug_uartd_device.dev.platform_data))->mapbase;
493                 break;
494
495         case 4:
496                 /* UARTE is the debug port. */
497                 pr_info("Selecting UARTE as the debug console\n");
498                 cardhu_uart_devices[4] = &debug_uarte_device;
499                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
500                 debug_uart_port_base = ((struct plat_serial8250_port *)(
501                         debug_uarte_device.dev.platform_data))->mapbase;
502                 break;
503
504         default:
505                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
506                 cardhu_uart_devices[0] = &debug_uarta_device;
507                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
508                 debug_uart_port_base = ((struct plat_serial8250_port *)(
509                         debug_uarta_device.dev.platform_data))->mapbase;
510                 break;
511         }
512         return;
513 }
514
515 static void __init cardhu_uart_init(void)
516 {
517         struct clk *c;
518         int i;
519
520         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
521                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
522                 if (IS_ERR_OR_NULL(c)) {
523                         pr_err("Not able to get the clock for %s\n",
524                                                 uart_parent_clk[i].name);
525                         continue;
526                 }
527                 uart_parent_clk[i].parent_clk = c;
528                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
529         }
530         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
531         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
532         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
533         cardhu_loopback_uart_pdata.parent_clk_count =
534                                                 ARRAY_SIZE(uart_parent_clk);
535         cardhu_loopback_uart_pdata.is_loopback = true;
536         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
537         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
538         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
539         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
540         /* UARTE is used for loopback test purpose */
541         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
542
543         /* Register low speed only if it is selected */
544         if (!is_tegra_debug_uartport_hs()) {
545                 uart_debug_init();
546                 /* Clock enable for the debug channel */
547                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
548                         pr_info("The debug console clock name is %s\n",
549                                                 debug_uart_clk->name);
550                         c = tegra_get_clock_by_name("pll_p");
551                         if (IS_ERR_OR_NULL(c))
552                                 pr_err("Not getting the parent clock pll_p\n");
553                         else
554                                 clk_set_parent(debug_uart_clk, c);
555
556                         clk_enable(debug_uart_clk);
557                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
558                 } else {
559                         pr_err("Not getting the clock %s for debug console\n",
560                                         debug_uart_clk->name);
561                 }
562         }
563
564         platform_add_devices(cardhu_uart_devices,
565                                 ARRAY_SIZE(cardhu_uart_devices));
566 }
567
568 static struct platform_device tegra_camera = {
569         .name = "tegra_camera",
570         .id = -1,
571 };
572
573 static struct platform_device *cardhu_spi_devices[] __initdata = {
574         &tegra_spi_device4,
575 };
576
577 struct spi_clk_parent spi_parent_clk[] = {
578         [0] = {.name = "pll_p"},
579 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
580         [1] = {.name = "pll_m"},
581         [2] = {.name = "clk_m"},
582 #else
583         [1] = {.name = "clk_m"},
584 #endif
585 };
586
587 static struct tegra_spi_platform_data cardhu_spi_pdata = {
588         .is_dma_based           = true,
589         .max_dma_buffer         = (16 * 1024),
590         .is_clkon_always        = false,
591         .max_rate               = 100000000,
592 };
593
594 static void __init cardhu_spi_init(void)
595 {
596         int i;
597         struct clk *c;
598         struct board_info board_info;
599
600         tegra_get_board_info(&board_info);
601
602         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
603                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
604                 if (IS_ERR_OR_NULL(c)) {
605                         pr_err("Not able to get the clock for %s\n",
606                                                 spi_parent_clk[i].name);
607                         continue;
608                 }
609                 spi_parent_clk[i].parent_clk = c;
610                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
611         }
612         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
613         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
614         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
615         platform_add_devices(cardhu_spi_devices,
616                                 ARRAY_SIZE(cardhu_spi_devices));
617
618         if (board_info.board_id == BOARD_E1198) {
619                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
620                 platform_device_register(&tegra_spi_device2);
621                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
622                 platform_device_register(&tegra_spi_slave_device1);
623         }
624 }
625
626 static void __init cardhu_dtv_init(void)
627 {
628         struct board_info board_info;
629
630         tegra_get_board_info(&board_info);
631
632         if (board_info.board_id == BOARD_E1186)
633                 platform_device_register(&tegra_dtv_device);
634 }
635
636 static struct resource tegra_rtc_resources[] = {
637         [0] = {
638                 .start = TEGRA_RTC_BASE,
639                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
640                 .flags = IORESOURCE_MEM,
641         },
642         [1] = {
643                 .start = INT_RTC,
644                 .end = INT_RTC,
645                 .flags = IORESOURCE_IRQ,
646         },
647 };
648
649 static struct platform_device tegra_rtc_device = {
650         .name = "tegra_rtc",
651         .id   = -1,
652         .resource = tegra_rtc_resources,
653         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
654 };
655
656 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
657         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
658         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
659         .gpio_hp_mute           = -1,
660         .gpio_int_mic_en        = -1,
661         .gpio_ext_mic_en        = -1,
662 };
663
664 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
665         .gpio_spkr_en           = -1,
666         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
667         .gpio_hp_mute           = -1,
668         .gpio_int_mic_en        = -1,
669         .gpio_ext_mic_en        = -1,
670 };
671
672 static struct platform_device cardhu_audio_wm8903_device = {
673         .name   = "tegra-snd-wm8903",
674         .id     = 0,
675         .dev    = {
676                 .platform_data = &cardhu_audio_wm8903_pdata,
677         },
678 };
679
680 static struct platform_device cardhu_audio_max98095_device = {
681         .name   = "tegra-snd-max98095",
682         .id     = 0,
683         .dev    = {
684                 .platform_data = &cardhu_audio_max98095_pdata,
685         },
686 };
687
688 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
689         .gpio_spkr_en           = -1,
690         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
691         .gpio_hp_mute           = -1,
692         .gpio_int_mic_en        = -1,
693         .gpio_ext_mic_en        = -1,
694         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
695         .audio_port_id          = {
696                 [HIFI_CODEC] = 0,
697                 [BASEBAND] = -1,
698                 [BT_SCO] = 3,
699         },
700         .baseband_param         = {
701                 .rate = -1,
702                 .channels = -1,
703         },
704 };
705
706 static struct platform_device cardhu_audio_aic326x_device = {
707         .name   = "tegra-snd-aic326x",
708         .id     = 0,
709         .dev    = {
710                 .platform_data  = &cardhu_audio_aic326x_pdata,
711         },
712 };
713
714 static struct platform_device *cardhu_devices[] __initdata = {
715         &tegra_pmu_device,
716         &tegra_rtc_device,
717         &tegra_udc_device,
718 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
719         &tegra_smmu_device,
720 #endif
721         &tegra_wdt_device,
722 #if defined(CONFIG_TEGRA_AVP)
723         &tegra_avp_device,
724 #endif
725         &tegra_camera,
726 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
727         &tegra_se_device,
728 #endif
729         &tegra_ahub_device,
730         &tegra_dam_device0,
731         &tegra_dam_device1,
732         &tegra_dam_device2,
733         &tegra_i2s_device0,
734         &tegra_i2s_device1,
735         &tegra_i2s_device3,
736         &tegra_spdif_device,
737         &spdif_dit_device,
738         &bluetooth_dit_device,
739         &baseband_dit_device,
740         &cardhu_bcm4329_rfkill_device,
741         &tegra_pcm_device,
742         &cardhu_audio_wm8903_device,
743         &cardhu_audio_max98095_device,
744         &cardhu_audio_aic326x_device,
745         &tegra_hda_device,
746 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
747         &tegra_aes_device,
748 #endif
749 };
750
751 #define MXT_CONFIG_CRC  0xD62DE8
752 static const u8 config[] = {
753         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
754         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
755         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
756         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
757         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
758         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
759         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
760         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
762         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
763         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
764         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
765         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
766         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
767         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
768         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
769         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
770         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
771         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
772         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
773 };
774
775 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
776 static const u8 config_sku2000[] = {
777         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
778         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
779         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
780         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
781         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
782         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
783         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
784         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
786         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
788         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
789         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
790         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
791         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
792         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
793         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
794         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
795         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
796         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
797 };
798
799 static struct mxt_platform_data atmel_mxt_info = {
800         .x_line         = 27,
801         .y_line         = 42,
802         .x_size         = 768,
803         .y_size         = 1366,
804         .blen           = 0x20,
805         .threshold      = 0x3C,
806         .voltage        = 3300000,              /* 3.3V */
807         .orient         = 5,
808         .config         = config,
809         .config_length  = 157,
810         .config_crc     = MXT_CONFIG_CRC,
811         .irqflags       = IRQF_TRIGGER_FALLING,
812 /*      .read_chg       = &read_chg, */
813         .read_chg       = NULL,
814 };
815
816 static struct i2c_board_info __initdata atmel_i2c_info[] = {
817         {
818                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
819                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
820                 .platform_data = &atmel_mxt_info,
821         }
822 };
823
824 static int __init cardhu_touch_init(void)
825 {
826         struct board_info BoardInfo;
827
828         tegra_gpio_enable(TEGRA_GPIO_PH4);
829         tegra_gpio_enable(TEGRA_GPIO_PH6);
830
831         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
832         gpio_direction_input(TEGRA_GPIO_PH4);
833
834         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
835         gpio_direction_output(TEGRA_GPIO_PH6, 0);
836         msleep(1);
837         gpio_set_value(TEGRA_GPIO_PH6, 1);
838         msleep(100);
839
840         tegra_get_board_info(&BoardInfo);
841         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
842                 atmel_mxt_info.config = config_sku2000;
843                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
844         }
845
846         i2c_register_board_info(1, atmel_i2c_info, 1);
847
848         return 0;
849 }
850
851 static struct tegra_uhsic_config uhsic_phy_config = {
852         .enable_gpio = EN_HSIC_GPIO,
853         .reset_gpio = -1,
854         .sync_start_delay = 9,
855         .idle_wait_delay = 17,
856         .term_range_adj = 0,
857         .elastic_underrun_limit = 16,
858         .elastic_overrun_limit = 16,
859 };
860
861 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
862         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
863         .phy_config = &uhsic_phy_config,
864         .operating_mode = TEGRA_USB_HOST,
865         .power_down_on_bus_suspend = 1,
866         .default_enable = true,
867 };
868
869 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
870         [0] = {
871                         .phy_config = &utmi_phy_config[0],
872                         .operating_mode = TEGRA_USB_HOST,
873                         .power_down_on_bus_suspend = 1,
874                         .default_enable = true,
875         },
876         [1] = {
877                         .phy_config = &utmi_phy_config[1],
878                         .operating_mode = TEGRA_USB_HOST,
879                         .power_down_on_bus_suspend = 1,
880                         .default_enable = true,
881         },
882         [2] = {
883                         .phy_config = &utmi_phy_config[2],
884                         .operating_mode = TEGRA_USB_HOST,
885                         .power_down_on_bus_suspend = 1,
886                         .hotplug = 1,
887                         .default_enable = true,
888         },
889 };
890
891 static struct tegra_otg_platform_data tegra_otg_pdata = {
892         .ehci_device = &tegra_ehci1_device,
893         .ehci_pdata = &tegra_ehci_pdata[0],
894 };
895
896 #ifdef CONFIG_USB_SUPPORT
897 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
898         [0] = {
899                         .instance = 0,
900                         .vbus_gpio = -1,
901                         .vbus_reg_supply = "vdd_vbus_micro_usb",
902         },
903         [1] = {
904                         .instance = 1,
905                         .vbus_gpio = -1,
906         },
907         [2] = {
908                         .instance = 2,
909                         .vbus_gpio = -1,
910                         .vbus_reg_supply = "vdd_vbus_typea_usb",
911         },
912 };
913
914 static int cardhu_usb_hsic_postsupend(void)
915 {
916 #ifdef CONFIG_TEGRA_BB_XMM_POWER
917         baseband_xmm_set_power_status(BBXMM_PS_L2);
918 #endif
919         return 0;
920 }
921
922 static int cardhu_usb_hsic_preresume(void)
923 {
924 #ifdef CONFIG_TEGRA_BB_XMM_POWER
925         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
926 #endif
927         return 0;
928 }
929
930 static int cardhu_usb_hsic_phy_ready(void)
931 {
932 #ifdef CONFIG_TEGRA_BB_XMM_POWER
933         baseband_xmm_set_power_status(BBXMM_PS_L0);
934 #endif
935         return 0;
936 }
937
938 static int cardhu_usb_hsic_phy_off(void)
939 {
940 #ifdef CONFIG_TEGRA_BB_XMM_POWER
941         baseband_xmm_set_power_status(BBXMM_PS_L3);
942 #endif
943         return 0;
944 }
945
946 static void cardhu_usb_init(void)
947 {
948         struct board_info bi;
949
950         tegra_get_board_info(&bi);
951
952         tegra_usb_phy_init(tegra_usb_phy_pdata,
953                         ARRAY_SIZE(tegra_usb_phy_pdata));
954
955         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
956         platform_device_register(&tegra_otg_device);
957         if (bi.board_id == BOARD_PM267) {
958                 uhsic_phy_config.reset_gpio =
959                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
960                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
961                 platform_device_register(&tegra_ehci2_device);
962         } else if (bi.board_id == BOARD_E1256) {
963                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
964                 platform_device_register(&tegra_ehci2_device);
965         } else if (bi.board_id == BOARD_E1186) {
966                 /* for baseband devices do not switch off phy during suspend */
967                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
968                 uhsic_phy_config.postsuspend = cardhu_usb_hsic_postsupend;
969                 uhsic_phy_config.preresume = cardhu_usb_hsic_preresume;
970                 uhsic_phy_config.usb_phy_ready = cardhu_usb_hsic_phy_ready;
971                 uhsic_phy_config.post_phy_off = cardhu_usb_hsic_phy_off;
972                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
973                 /* baseband registration happens in baseband-xmm-power  */
974         } else {
975                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
976                 platform_device_register(&tegra_ehci2_device);
977         }
978
979         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
980         platform_device_register(&tegra_ehci3_device);
981
982 }
983 #else
984 static void cardhu_usb_init(void) { }
985 #endif
986
987 static void cardhu_gps_init(void)
988 {
989         tegra_gpio_enable(TEGRA_GPIO_PU2);
990         tegra_gpio_enable(TEGRA_GPIO_PU3);
991 }
992
993 static void cardhu_nfc_init(void)
994 {
995         tegra_gpio_enable(TEGRA_GPIO_PX0);
996         tegra_gpio_enable(TEGRA_GPIO_PP3);
997         tegra_gpio_enable(TEGRA_GPIO_PO7);
998 }
999
1000 static struct baseband_power_platform_data tegra_baseband_power_data = {
1001         .baseband_type = BASEBAND_XMM,
1002         .modem = {
1003         .xmm = {
1004                         .bb_rst = XMM_GPIO_BB_RST,
1005                         .bb_on = XMM_GPIO_BB_ON,
1006                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1007                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1008                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1009                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1010                         .hsic_device = &tegra_ehci2_device,
1011                 },
1012         },
1013 };
1014
1015 static struct platform_device tegra_baseband_power_device = {
1016         .name = "baseband_xmm_power",
1017         .id = -1,
1018         .dev = {
1019                 .platform_data = &tegra_baseband_power_data,
1020         },
1021 };
1022
1023 static struct platform_device tegra_baseband_power2_device = {
1024         .name = "baseband_xmm_power2",
1025         .id = -1,
1026         .dev = {
1027                 .platform_data = &tegra_baseband_power_data,
1028         },
1029 };
1030
1031
1032 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1033         .port_status[0] = 1,
1034         .port_status[1] = 1,
1035         .port_status[2] = 1,
1036         .use_dock_detect        = 0,
1037         .gpio           = 0,
1038 };
1039
1040 static void cardhu_pci_init(void)
1041 {
1042         struct board_info board_info;
1043
1044         tegra_get_board_info(&board_info);
1045         if (board_info.board_id == BOARD_E1291) {
1046                 cardhu_pci_platform_data.port_status[0] = 0;
1047                 cardhu_pci_platform_data.port_status[1] = 0;
1048                 cardhu_pci_platform_data.port_status[2] = 1;
1049                 cardhu_pci_platform_data.use_dock_detect = 1;
1050                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1051         }
1052         if ((board_info.board_id == BOARD_E1186) ||
1053                 (board_info.board_id == BOARD_E1187) ||
1054                 (board_info.board_id == BOARD_E1291)) {
1055                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1056                 platform_device_register(&tegra_pci_device);
1057         }
1058 }
1059
1060 static void cardhu_modem_init(void)
1061 {
1062         struct board_info board_info;
1063         int w_disable_gpio, ret;
1064
1065         tegra_get_board_info(&board_info);
1066         switch (board_info.board_id) {
1067         case BOARD_E1291:
1068         case BOARD_E1198:
1069                 if (((board_info.board_id == BOARD_E1291) &&
1070                                 (board_info.fab < BOARD_FAB_A03)) ||
1071                         ((board_info.board_id == BOARD_E1198) &&
1072                                         (board_info.fab < BOARD_FAB_A02))) {
1073                         w_disable_gpio = TEGRA_GPIO_PH5;
1074                 } else {
1075                         w_disable_gpio = TEGRA_GPIO_PDD5;
1076                 }
1077                 tegra_gpio_enable(w_disable_gpio);
1078                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1079                 if (ret < 0)
1080                         pr_err("%s: gpio_request failed for gpio %d\n",
1081                                 __func__, w_disable_gpio);
1082                 else
1083                         gpio_direction_input(w_disable_gpio);
1084
1085                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1086                 if (((board_info.board_id == BOARD_E1291) &&
1087                                 (board_info.fab >= BOARD_FAB_A04)) ||
1088                         ((board_info.board_id == BOARD_E1198) &&
1089                                         (board_info.fab >= BOARD_FAB_A02))) {
1090                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1091                         if (ret < 0) {
1092                                 pr_err("%s(): Error in allocating gpio "
1093                                         "TEGRA_GPIO_PH7\n", __func__);
1094                                 break;
1095                         }
1096                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1097                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1098                 }
1099                 break;
1100         case BOARD_E1186:
1101                 tegra_gpio_enable(
1102                         tegra_baseband_power_data.modem.xmm.bb_rst);
1103                 tegra_gpio_enable(
1104                         tegra_baseband_power_data.modem.xmm.bb_on);
1105                 tegra_gpio_enable(
1106                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1107                 tegra_gpio_enable(
1108                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1109                 tegra_gpio_enable(
1110                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1111                 tegra_gpio_enable(
1112                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1113                 platform_device_register(&tegra_baseband_power_device);
1114                 platform_device_register(&tegra_baseband_power2_device);
1115                 break;
1116         default:
1117                 break;
1118         }
1119
1120 }
1121
1122 #ifdef CONFIG_SATA_AHCI_TEGRA
1123 static void cardhu_sata_init(void)
1124 {
1125         platform_device_register(&tegra_sata_device);
1126 }
1127 #else
1128 static void cardhu_sata_init(void) { }
1129 #endif
1130
1131 static void __init tegra_cardhu_init(void)
1132 {
1133         tegra_thermal_init(&thermal_data);
1134         tegra_clk_init_from_table(cardhu_clk_init_table);
1135         cardhu_pinmux_init();
1136         cardhu_i2c_init();
1137         cardhu_spi_init();
1138         cardhu_usb_init();
1139 #ifdef CONFIG_TEGRA_EDP_LIMITS
1140         cardhu_edp_init();
1141 #endif
1142         cardhu_uart_init();
1143         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1144         tegra_ram_console_debug_init();
1145         cardhu_sdhci_init();
1146         cardhu_regulator_init();
1147         cardhu_dtv_init();
1148         cardhu_suspend_init();
1149         cardhu_touch_init();
1150         cardhu_gps_init();
1151         cardhu_modem_init();
1152         cardhu_kbc_init();
1153         cardhu_scroll_init();
1154         cardhu_keys_init();
1155         cardhu_panel_init();
1156         cardhu_pmon_init();
1157         cardhu_sensors_init();
1158         cardhu_setup_bluesleep();
1159         cardhu_sata_init();
1160         //audio_wired_jack_init();
1161         cardhu_pins_state_init();
1162         cardhu_emc_init();
1163         tegra_release_bootloader_fb();
1164         cardhu_nfc_init();
1165         cardhu_pci_init();
1166 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1167         tegra_wdt_recovery_init();
1168 #endif
1169 }
1170
1171 static void __init tegra_cardhu_reserve(void)
1172 {
1173 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1174         /* support 1920X1200 with 24bpp */
1175         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1176 #else
1177         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1178 #endif
1179         tegra_ram_console_debug_reserve(SZ_1M);
1180 }
1181
1182 MACHINE_START(CARDHU, "cardhu")
1183         .boot_params    = 0x80000100,
1184         .map_io         = tegra_map_common_io,
1185         .reserve        = tegra_cardhu_reserve,
1186         .init_early     = tegra_init_early,
1187         .init_irq       = tegra_init_irq,
1188         .timer          = &tegra_timer,
1189         .init_machine   = tegra_cardhu_init,
1190 MACHINE_END