ARM: tegra: integration of slave mode support.
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  * Copyright (c) 2011-2012, NVIDIA Corporation.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/serial_8250.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/panjit_ts.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/gpio.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/spi/spi.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44
45 #include <sound/wm8903.h>
46 #include <sound/max98095.h>
47 #include <media/tegra_dtv.h>
48
49 #include <mach/clk.h>
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/pinmux.h>
53 #include <mach/iomap.h>
54 #include <mach/io_dpd.h>
55 #include <mach/io.h>
56 #include <mach/i2s.h>
57 #include <mach/tegra_asoc_pdata.h>
58 #include <mach/tegra_wm8903_pdata.h>
59 #include <asm/mach-types.h>
60 #include <asm/mach/arch.h>
61 #include <mach/usb_phy.h>
62 #include <mach/thermal.h>
63 #include <mach/pci.h>
64 #include <mach/tegra_fiq_debugger.h>
65
66 #include "board.h"
67 #include "clock.h"
68 #include "board-cardhu.h"
69 #include "board-touch.h"
70 #include "devices.h"
71 #include "gpio-names.h"
72 #include "fuse.h"
73 #include "pm.h"
74 #include "baseband-xmm-power.h"
75 #include "wdt-recovery.h"
76
77 static struct balanced_throttle throttle_list[] = {
78 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
79         {
80                 .id = BALANCED_THROTTLE_ID_TJ,
81                 .throt_tab_size = 10,
82                 .throt_tab = {
83                         {      0, 1000 },
84                         { 640000, 1000 },
85                         { 640000, 1000 },
86                         { 640000, 1000 },
87                         { 640000, 1000 },
88                         { 640000, 1000 },
89                         { 760000, 1000 },
90                         { 760000, 1050 },
91                         {1000000, 1050 },
92                         {1000000, 1100 },
93                 },
94         },
95 #endif
96 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
97         {
98                 .id = BALANCED_THROTTLE_ID_SKIN,
99                 .throt_tab_size = 6,
100                 .throt_tab = {
101                         { 640000, 1200 },
102                         { 640000, 1200 },
103                         { 760000, 1200 },
104                         { 760000, 1200 },
105                         {1000000, 1200 },
106                         {1000000, 1200 },
107                 },
108         },
109 #endif
110 };
111
112 /* All units are in millicelsius */
113 static struct tegra_thermal_data thermal_data = {
114         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
115         .temp_shutdown = 90000,
116
117 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
118         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
119 #endif
120 #ifdef CONFIG_TEGRA_EDP_LIMITS
121         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
122         .hysteresis_edp = 3000,
123 #endif
124 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
125         .temp_throttle = 85000,
126         .tc1 = 0,
127         .tc2 = 1,
128         .passive_delay = 2000,
129 #endif
130 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
131         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
132         .temp_throttle_skin = 43000,
133         .tc1_skin = 0,
134         .tc2_skin = 1,
135         .passive_delay_skin = 5000,
136
137         .skin_temp_offset = 9793,
138         .skin_period = 1100,
139         .skin_devs_size = 2,
140         .skin_devs = {
141                 {
142                         THERMAL_DEVICE_ID_NCT_EXT,
143                         {
144                                 2, 1, 1, 1,
145                                 1, 1, 1, 1,
146                                 1, 1, 1, 0,
147                                 1, 1, 0, 0,
148                                 0, 0, -1, -7
149                         }
150                 },
151                 {
152                         THERMAL_DEVICE_ID_NCT_INT,
153                         {
154                                 -11, -7, -5, -3,
155                                 -3, -2, -1, 0,
156                                 0, 0, 1, 1,
157                                 1, 2, 2, 3,
158                                 4, 6, 11, 18
159                         }
160                 },
161         },
162 #endif
163 };
164
165 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
166         {
167                 .name           = "bt_rfkill",
168                 .shutdown_gpio  = TEGRA_GPIO_PU0,
169                 .reset_gpio     = TEGRA_GPIO_INVALID,
170                 .type           = RFKILL_TYPE_BLUETOOTH,
171         },
172 };
173
174 static struct platform_device cardhu_bt_rfkill_device = {
175         .name = "rfkill_gpio",
176         .id             = -1,
177         .dev = {
178                 .platform_data = &cardhu_bt_rfkill_pdata,
179         },
180 };
181
182 static struct resource cardhu_bluesleep_resources[] = {
183         [0] = {
184                 .name = "gpio_host_wake",
185                         .start  = TEGRA_GPIO_PU6,
186                         .end    = TEGRA_GPIO_PU6,
187                         .flags  = IORESOURCE_IO,
188         },
189         [1] = {
190                 .name = "gpio_ext_wake",
191                         .start  = TEGRA_GPIO_PU1,
192                         .end    = TEGRA_GPIO_PU1,
193                         .flags  = IORESOURCE_IO,
194         },
195         [2] = {
196                 .name = "host_wake",
197                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
198                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
199                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
200         },
201 };
202
203 static struct platform_device cardhu_bluesleep_device = {
204         .name           = "bluesleep",
205         .id             = -1,
206         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
207         .resource       = cardhu_bluesleep_resources,
208 };
209
210 static noinline void __init cardhu_setup_bluesleep(void)
211 {
212         platform_device_register(&cardhu_bluesleep_device);
213         return;
214 }
215
216 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
217         /* name         parent          rate            enabled */
218         { "pll_m",      NULL,           0,              false},
219         { "hda",        "pll_p",        108000000,      false},
220         { "hda2codec_2x","pll_p",       48000000,       false},
221         { "pwm",        "pll_p",        3187500,        false},
222         { "blink",      "clk_32k",      32768,          true},
223         { "i2s0",       "pll_a_out0",   0,              false},
224         { "i2s1",       "pll_a_out0",   0,              false},
225         { "i2s3",       "pll_a_out0",   0,              false},
226         { "spdif_out",  "pll_a_out0",   0,              false},
227         { "d_audio",    "clk_m",        12000000,       false},
228         { "dam0",       "clk_m",        12000000,       false},
229         { "dam1",       "clk_m",        12000000,       false},
230         { "dam2",       "clk_m",        12000000,       false},
231         { "audio1",     "i2s1_sync",    0,              false},
232         { "audio3",     "i2s3_sync",    0,              false},
233         { "vi_sensor",  "pll_p",        150000000,      false},
234         { "i2c1",       "pll_p",        3200000,        false},
235         { "i2c2",       "pll_p",        3200000,        false},
236         { "i2c3",       "pll_p",        3200000,        false},
237         { "i2c4",       "pll_p",        3200000,        false},
238         { "i2c5",       "pll_p",        3200000,        false},
239         { "vi",         "pll_p",        0,              false},
240         { NULL,         NULL,           0,              0},
241 };
242
243 static struct pn544_i2c_platform_data nfc_pdata = {
244         .irq_gpio = TEGRA_GPIO_PX0,
245         .ven_gpio = TEGRA_GPIO_PP3,
246         .firm_gpio = TEGRA_GPIO_PO7,
247         };
248
249 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
250         {
251                 I2C_BOARD_INFO("pn544", 0x28),
252                 .platform_data = &nfc_pdata,
253                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
254         },
255 };
256 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
257         .adapter_nr     = 0,
258         .bus_count      = 1,
259         .bus_clk_rate   = { 100000, 0 },
260         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
261         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
262         .arb_recovery = arb_lost_recovery,
263 };
264
265 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
266         .adapter_nr     = 1,
267         .bus_count      = 1,
268         .bus_clk_rate   = { 400000, 0 },
269         .is_clkon_always = true,
270         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
271         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
272         .arb_recovery = arb_lost_recovery,
273 };
274
275 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
276         .adapter_nr     = 2,
277         .bus_count      = 1,
278         .bus_clk_rate   = { 100000, 0 },
279         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
280         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
281         .arb_recovery = arb_lost_recovery,
282 };
283
284 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
285         .adapter_nr     = 3,
286         .bus_count      = 1,
287         .bus_clk_rate   = { 10000, 0 },
288         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
289         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
290         .arb_recovery = arb_lost_recovery,
291 };
292
293 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
294         .adapter_nr     = 4,
295         .bus_count      = 1,
296         .bus_clk_rate   = { 400000, 0 },
297         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
298         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
299         .arb_recovery = arb_lost_recovery,
300 };
301
302
303 #if 0
304 struct tegra_wired_jack_conf audio_wr_jack_conf = {
305         .hp_det_n = TEGRA_GPIO_PW2,
306         .en_mic_ext = TEGRA_GPIO_PX1,
307         .en_mic_int = TEGRA_GPIO_PX0,
308 };
309 #endif
310
311 static struct wm8903_platform_data cardhu_wm8903_pdata = {
312         .irq_active_low = 0,
313         .micdet_cfg = 0,
314         .micdet_delay = 100,
315         .gpio_base = CARDHU_GPIO_WM8903(0),
316         .gpio_cfg = {
317                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
318                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
319                         WM8903_GP2_DIR,
320                 0,
321                 WM8903_GPIO_NO_CONFIG,
322                 WM8903_GPIO_NO_CONFIG,
323         },
324 };
325
326 /* Equalizer filter coefs generated from the MAXIM MAX98095
327  * evkit software tool */
328 static struct max98095_eq_cfg max98095_eq_cfg[] = {
329         {
330                 .name = "FLAT",
331                 .rate = 44100,
332                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
333                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
334                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
335                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
336                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
337         },
338         {
339                 .name = "LOWPASS1K",
340                 .rate = 44100,
341                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
342                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
343                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
344                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
345                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
346         },
347         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
348                 .name = "HIBOOST",
349                 .rate = 44100,
350                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
351                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
352                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
353                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
354                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
355         },
356         { /* BASS=12dB, TREBLE=+12dB */
357                 .name = "LOUD12DB",
358                 .rate = 44100,
359                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
360                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
361                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
362                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
363                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
364         },
365         {
366                 .name = "FLAT",
367                 .rate = 16000,
368                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
369                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
370                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
371                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
372                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
373         },
374         {
375                 .name = "LOWPASS1K",
376                 .rate = 16000,
377                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
378                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
379                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
380                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
381                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
382         },
383         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
384                 .name = "HIBOOST",
385                 .rate = 16000,
386                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
387                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
388                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
389                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
390                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
391         },
392         { /* BASS=12dB, TREBLE=+12dB */
393                 .name = "LOUD12DB",
394                 .rate = 16000,
395                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
396                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
397                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
398                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
399                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
400         },
401 };
402
403 static struct max98095_pdata cardhu_max98095_pdata = {
404         /* equalizer configuration */
405         .eq_cfg = max98095_eq_cfg,
406         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
407
408         /* Biquad filter response configuration */
409         .bq_cfg = NULL,
410         .bq_cfgcnt = 0,
411
412         /* microphone configuration */
413         .digmic_left_mode = 1,
414         .digmic_right_mode = 1,
415 };
416
417 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
418         I2C_BOARD_INFO("wm8903", 0x1a),
419         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
420         .platform_data = &cardhu_wm8903_pdata,
421 };
422
423 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
424         I2C_BOARD_INFO("aic3262-codec", 0x18),
425         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
426 };
427
428 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
429         I2C_BOARD_INFO("max98095", 0x10),
430         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
431         .platform_data = &cardhu_max98095_pdata,
432 };
433
434 static void cardhu_i2c_init(void)
435 {
436         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
437         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
438         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
439         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
440         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
441
442         platform_device_register(&tegra_i2c_device5);
443         platform_device_register(&tegra_i2c_device4);
444         platform_device_register(&tegra_i2c_device3);
445         platform_device_register(&tegra_i2c_device2);
446         platform_device_register(&tegra_i2c_device1);
447
448         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
449         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
450         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
451
452         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
453 }
454
455 static struct platform_device *cardhu_uart_devices[] __initdata = {
456         &tegra_uarta_device,
457         &tegra_uartb_device,
458         &tegra_uartc_device,
459         &tegra_uartd_device,
460         &tegra_uarte_device,
461 };
462 static struct uart_clk_parent uart_parent_clk[] = {
463         [0] = {.name = "clk_m"},
464         [1] = {.name = "pll_p"},
465 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
466         [2] = {.name = "pll_m"},
467 #endif
468 };
469
470 static struct tegra_uart_platform_data cardhu_uart_pdata;
471 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
472
473 static void __init uart_debug_init(void)
474 {
475         struct board_info board_info;
476         int debug_port_id;
477
478         tegra_get_board_info(&board_info);
479
480         debug_port_id = get_tegra_uart_debug_port_id();
481         if (debug_port_id < 0) {
482                 debug_port_id = 0;
483                         /* UARTB is debug port
484                          *       for SLT - E1186/E1187/PM269
485                          *       for E1256/E1257
486                          */
487                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
488                         ((board_info.board_id == BOARD_E1186) ||
489                         (board_info.board_id == BOARD_E1187) ||
490                         (board_info.board_id == BOARD_PM269))) ||
491                         (board_info.board_id == BOARD_E1256) ||
492                         (board_info.board_id == BOARD_E1257))
493                                 debug_port_id = 1;
494         }
495
496 #ifdef CONFIG_TEGRA_IRDA
497         if ((board_info.board_id == BOARD_E1186) ||
498                 (board_info.board_id == BOARD_E1198)) {
499                 if (debug_port_id == 1) {
500                         cardhu_irda_pdata.is_irda = false;
501                         pr_err("UARTB is not available for IrDA\n");
502                 }
503         }
504 #endif
505
506         switch (debug_port_id) {
507         case 0:
508                 /* UARTA is the debug port. */
509                 pr_info("Selecting UARTA as the debug console\n");
510                 cardhu_uart_devices[0] = &debug_uarta_device;
511                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
512                 debug_uart_port_base = ((struct plat_serial8250_port *)(
513                         debug_uarta_device.dev.platform_data))->mapbase;
514                 break;
515
516         case 1:
517                 /* UARTB is the debug port. */
518                 pr_info("Selecting UARTB as the debug console\n");
519                 cardhu_uart_devices[1] = &debug_uartb_device;
520                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
521                 debug_uart_port_base = ((struct plat_serial8250_port *)(
522                         debug_uartb_device.dev.platform_data))->mapbase;
523                 break;
524
525         case 2:
526                 /* UARTC is the debug port. */
527                 pr_info("Selecting UARTC as the debug console\n");
528                 cardhu_uart_devices[2] = &debug_uartc_device;
529                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
530                 debug_uart_port_base = ((struct plat_serial8250_port *)(
531                         debug_uartc_device.dev.platform_data))->mapbase;
532                 break;
533
534         case 3:
535                 /* UARTD is the debug port. */
536                 pr_info("Selecting UARTD as the debug console\n");
537                 cardhu_uart_devices[3] = &debug_uartd_device;
538                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
539                 debug_uart_port_base = ((struct plat_serial8250_port *)(
540                         debug_uartd_device.dev.platform_data))->mapbase;
541                 break;
542
543         case 4:
544                 /* UARTE is the debug port. */
545                 pr_info("Selecting UARTE as the debug console\n");
546                 cardhu_uart_devices[4] = &debug_uarte_device;
547                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
548                 debug_uart_port_base = ((struct plat_serial8250_port *)(
549                         debug_uarte_device.dev.platform_data))->mapbase;
550                 break;
551
552         default:
553                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
554                 cardhu_uart_devices[0] = &debug_uarta_device;
555                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
556                 debug_uart_port_base = ((struct plat_serial8250_port *)(
557                         debug_uarta_device.dev.platform_data))->mapbase;
558                 break;
559         }
560         return;
561 }
562
563 static void __init cardhu_uart_init(void)
564 {
565         struct clk *c;
566         int i;
567         struct board_info board_info;
568
569         tegra_get_board_info(&board_info);
570
571         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
572                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
573                 if (IS_ERR_OR_NULL(c)) {
574                         pr_err("Not able to get the clock for %s\n",
575                                                 uart_parent_clk[i].name);
576                         continue;
577                 }
578                 uart_parent_clk[i].parent_clk = c;
579                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
580         }
581         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
582         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
583         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
584         cardhu_loopback_uart_pdata.parent_clk_count =
585                                                 ARRAY_SIZE(uart_parent_clk);
586         cardhu_loopback_uart_pdata.is_loopback = true;
587         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
588         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
589         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
590         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
591         /* UARTE is used for loopback test purpose */
592         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
593
594         /* Register low speed only if it is selected */
595         if (!is_tegra_debug_uartport_hs()) {
596                 uart_debug_init();
597                 /* Clock enable for the debug channel */
598                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
599                         pr_info("The debug console clock name is %s\n",
600                                                 debug_uart_clk->name);
601                         c = tegra_get_clock_by_name("pll_p");
602                         if (IS_ERR_OR_NULL(c))
603                                 pr_err("Not getting the parent clock pll_p\n");
604                         else
605                                 clk_set_parent(debug_uart_clk, c);
606
607                         clk_enable(debug_uart_clk);
608                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
609                 } else {
610                         pr_err("Not getting the clock %s for debug console\n",
611                                         debug_uart_clk->name);
612                 }
613         }
614
615 #ifdef CONFIG_TEGRA_IRDA
616         if (((board_info.board_id == BOARD_E1186) ||
617                 (board_info.board_id == BOARD_E1198)) &&
618                         cardhu_irda_pdata.is_irda) {
619                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
620                 cardhu_irda_pdata.parent_clk_count =
621                                         ARRAY_SIZE(uart_parent_clk);
622
623                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
624         }
625 #endif
626
627         platform_add_devices(cardhu_uart_devices,
628                                 ARRAY_SIZE(cardhu_uart_devices));
629 }
630
631 static struct platform_device tegra_camera = {
632         .name = "tegra_camera",
633         .id = -1,
634 };
635
636 static struct platform_device *cardhu_spi_devices[] __initdata = {
637         &tegra_spi_device4,
638 };
639
640 static struct platform_device *touch_spi_device[] __initdata = {
641         &tegra_spi_device1,
642 };
643
644 struct spi_clk_parent spi_parent_clk[] = {
645         [0] = {.name = "pll_p"},
646 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
647         [1] = {.name = "pll_m"},
648         [2] = {.name = "clk_m"},
649 #else
650         [1] = {.name = "clk_m"},
651 #endif
652 };
653
654 static struct tegra_spi_platform_data cardhu_spi_pdata = {
655         .is_dma_based           = true,
656         .max_dma_buffer         = (16 * 1024),
657         .is_clkon_always        = false,
658         .max_rate               = 100000000,
659 };
660
661 static void __init cardhu_spi_init(void)
662 {
663         int i;
664         struct clk *c;
665         struct board_info board_info, display_board_info;
666
667         tegra_get_board_info(&board_info);
668         tegra_get_display_board_info(&display_board_info);
669
670         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
671                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
672                 if (IS_ERR_OR_NULL(c)) {
673                         pr_err("Not able to get the clock for %s\n",
674                                                 spi_parent_clk[i].name);
675                         continue;
676                 }
677                 spi_parent_clk[i].parent_clk = c;
678                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
679         }
680         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
681         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
682         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
683         platform_add_devices(cardhu_spi_devices,
684                                 ARRAY_SIZE(cardhu_spi_devices));
685
686         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
687                 platform_add_devices(touch_spi_device,
688                                 ARRAY_SIZE(touch_spi_device));
689         }
690         if (board_info.board_id == BOARD_E1198) {
691                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
692                 platform_device_register(&tegra_spi_device2);
693                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
694                 platform_device_register(&tegra_spi_slave_device1);
695         }
696 }
697
698 static void __init cardhu_dtv_init(void)
699 {
700         struct board_info board_info;
701
702         tegra_get_board_info(&board_info);
703
704         if (board_info.board_id == BOARD_E1186)
705                 platform_device_register(&tegra_dtv_device);
706 }
707
708 static struct resource tegra_rtc_resources[] = {
709         [0] = {
710                 .start = TEGRA_RTC_BASE,
711                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
712                 .flags = IORESOURCE_MEM,
713         },
714         [1] = {
715                 .start = INT_RTC,
716                 .end = INT_RTC,
717                 .flags = IORESOURCE_IRQ,
718         },
719 };
720
721 static struct platform_device tegra_rtc_device = {
722         .name = "tegra_rtc",
723         .id   = -1,
724         .resource = tegra_rtc_resources,
725         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
726 };
727
728 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
729         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
730         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
731         .gpio_hp_mute           = -1,
732         .gpio_int_mic_en        = -1,
733         .gpio_ext_mic_en        = -1,
734         .i2s_param[HIFI_CODEC]  = {
735                 .audio_port_id  = 0,
736                 .is_i2s_master  = 1,
737                 .i2s_mode       = TEGRA_DAIFMT_I2S,
738         },
739         .i2s_param[BASEBAND]    = {
740                 .audio_port_id  = -1,
741         },
742         .i2s_param[BT_SCO]      = {
743                 .audio_port_id  = 3,
744                 .is_i2s_master  = 1,
745                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
746         },
747 };
748
749 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
750         .gpio_spkr_en           = -1,
751         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
752         .gpio_hp_mute           = -1,
753         .gpio_int_mic_en        = -1,
754         .gpio_ext_mic_en        = -1,
755         .i2s_param[HIFI_CODEC]  = {
756                 .audio_port_id  = 0,
757                 .is_i2s_master  = 1,
758                 .i2s_mode       = TEGRA_DAIFMT_I2S,
759         },
760         .i2s_param[BASEBAND]    = {
761                 .audio_port_id  = -1,
762         },
763         .i2s_param[BT_SCO]      = {
764                 .audio_port_id  = 3,
765                 .is_i2s_master  = 1,
766                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
767         },
768 };
769
770 static struct platform_device cardhu_audio_wm8903_device = {
771         .name   = "tegra-snd-wm8903",
772         .id     = 0,
773         .dev    = {
774                 .platform_data = &cardhu_audio_wm8903_pdata,
775         },
776 };
777
778 static struct platform_device cardhu_audio_max98095_device = {
779         .name   = "tegra-snd-max98095",
780         .id     = 0,
781         .dev    = {
782                 .platform_data = &cardhu_audio_max98095_pdata,
783         },
784 };
785
786 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
787         .gpio_spkr_en           = -1,
788         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
789         .gpio_hp_mute           = -1,
790         .gpio_int_mic_en        = -1,
791         .gpio_ext_mic_en        = -1,
792         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
793         .i2s_param[HIFI_CODEC]  = {
794                 .audio_port_id  = 0,
795                 .is_i2s_master  = 1,
796                 .i2s_mode       = TEGRA_DAIFMT_I2S,
797                 .sample_size    = 16,
798         },
799         .i2s_param[BT_SCO]      = {
800                 .sample_size    = 16,
801                 .audio_port_id  = 3,
802                 .is_i2s_master  = 1,
803                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
804         },
805 };
806
807 static struct platform_device cardhu_audio_aic326x_device = {
808         .name   = "tegra-snd-aic326x",
809         .id     = 0,
810         .dev    = {
811                 .platform_data  = &cardhu_audio_aic326x_pdata,
812         },
813 };
814
815 static struct platform_device *cardhu_devices[] __initdata = {
816         &tegra_pmu_device,
817         &tegra_rtc_device,
818         &tegra_udc_device,
819 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
820         &tegra_smmu_device,
821 #endif
822         &tegra_wdt0_device,
823         &tegra_wdt1_device,
824         &tegra_wdt2_device,
825 #if defined(CONFIG_TEGRA_AVP)
826         &tegra_avp_device,
827 #endif
828         &tegra_camera,
829 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
830         &tegra_se_device,
831 #endif
832         &tegra_ahub_device,
833         &tegra_dam_device0,
834         &tegra_dam_device1,
835         &tegra_dam_device2,
836         &tegra_i2s_device0,
837         &tegra_i2s_device1,
838         &tegra_i2s_device3,
839         &tegra_spdif_device,
840         &spdif_dit_device,
841         &bluetooth_dit_device,
842         &baseband_dit_device,
843         &cardhu_bt_rfkill_device,
844         &tegra_pcm_device,
845         &cardhu_audio_wm8903_device,
846         &cardhu_audio_max98095_device,
847         &cardhu_audio_aic326x_device,
848         &tegra_hda_device,
849         &tegra_cec_device,
850 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
851         &tegra_aes_device,
852 #endif
853 };
854
855 #define E1506_MXT_CONFIG_CRC 0x62F903
856 static const u8 e1506_config[] = {
857         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
858         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
859         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
860         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
861         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
862         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
863         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
867         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
869         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
870         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
871         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
876         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
877         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
878         0x00
879 };
880
881 #define MXT_CONFIG_CRC  0xD62DE8
882 static const u8 config[] = {
883         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
884         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
885         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
886         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
887         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
888         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
889         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
890         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
891         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
892         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
893         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
894         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
895         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
896         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
897         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
899         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
900         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
901         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
903 };
904
905 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
906 static const u8 config_sku2000[] = {
907         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
908         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
909         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
910         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
911         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
912         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
913         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
914         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
915         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
916         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
917         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
918         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
919         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
920         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
921         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
922         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
923         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
924         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
925         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
926         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
927 };
928
929 static struct mxt_platform_data atmel_mxt_info = {
930         .x_line         = 27,
931         .y_line         = 42,
932         .x_size         = 768,
933         .y_size         = 1366,
934         .blen           = 0x20,
935         .threshold      = 0x3C,
936         .voltage        = 3300000,              /* 3.3V */
937         .orient         = 5,
938         .config         = config,
939         .config_length  = 157,
940         .config_crc     = MXT_CONFIG_CRC,
941         .irqflags       = IRQF_TRIGGER_FALLING,
942 /*      .read_chg       = &read_chg, */
943         .read_chg       = NULL,
944 };
945
946 static struct mxt_platform_data e1506_atmel_mxt_info = {
947         .x_line         = 19,
948         .y_line         = 11,
949         .x_size         = 960,
950         .y_size         = 540,
951         .blen           = 0x10,
952         .threshold      = 0x32,
953         .voltage        = 3300000,              /* 3.3V */
954         .orient         = 3,
955         .config         = e1506_config,
956         .config_length  = 168,
957         .config_crc     = E1506_MXT_CONFIG_CRC,
958         .irqflags       = IRQF_TRIGGER_FALLING,
959 /*      .read_chg       = &read_chg, */
960         .read_chg       = NULL,
961 };
962
963 static struct i2c_board_info __initdata atmel_i2c_info[] = {
964         {
965                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
966                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
967                 .platform_data = &atmel_mxt_info,
968         }
969 };
970
971 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
972         {
973                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
974                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
975                 .platform_data = &e1506_atmel_mxt_info,
976         }
977 };
978
979 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
980         /* name         parent          rate            enabled */
981         { "sbc1",       "pll_p",        52000000,       true},
982         { NULL,         NULL,           0,              0},
983 };
984
985 static int __init cardhu_touch_init(void)
986 {
987         struct board_info BoardInfo, DisplayBoardInfo;
988
989         tegra_get_board_info(&BoardInfo);
990         tegra_get_display_board_info(&DisplayBoardInfo);
991         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
992                 tegra_clk_init_from_table(spi_clk_init_table);
993
994                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
995         } else {
996                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
997                 gpio_direction_input(TEGRA_GPIO_PH4);
998
999                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1000                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1001                 msleep(1);
1002                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1003                 msleep(100);
1004
1005                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1006                         atmel_mxt_info.config = config_sku2000;
1007                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1008                 }
1009
1010                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506)
1011                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1012                 else
1013                         i2c_register_board_info(1, atmel_i2c_info, 1);
1014         }
1015
1016         return 0;
1017 }
1018
1019 #if defined(CONFIG_USB_SUPPORT)
1020
1021 static void cardu_usb_hsic_postsupend(void)
1022 {
1023 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1024         baseband_xmm_set_power_status(BBXMM_PS_L2);
1025 #endif
1026 }
1027
1028 static void cardu_usb_hsic_preresume(void)
1029 {
1030 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1031         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1032 #endif
1033 }
1034
1035 static void cardu_usb_hsic_phy_ready(void)
1036 {
1037 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1038         baseband_xmm_set_power_status(BBXMM_PS_L0);
1039 #endif
1040 }
1041
1042 static void cardu_usb_hsic_phy_off(void)
1043 {
1044 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1045         baseband_xmm_set_power_status(BBXMM_PS_L3);
1046 #endif
1047 }
1048
1049 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1050         .post_suspend = cardu_usb_hsic_postsupend,
1051         .pre_resume = cardu_usb_hsic_preresume,
1052         .port_power = cardu_usb_hsic_phy_ready,
1053         .post_phy_off = cardu_usb_hsic_phy_off,
1054 };
1055
1056 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1057         .port_otg = false,
1058         .has_hostpc = true,
1059         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1060         .op_mode        = TEGRA_USB_OPMODE_HOST,
1061         .u_data.host = {
1062                 .vbus_gpio = -1,
1063                 .hot_plug = false,
1064                 .remote_wakeup_supported = false,
1065                 .power_off_on_suspend = false,
1066         },
1067         .u_cfg.hsic = {
1068                 .sync_start_delay = 9,
1069                 .idle_wait_delay = 17,
1070                 .term_range_adj = 0,
1071                 .elastic_underrun_limit = 16,
1072                 .elastic_overrun_limit = 16,
1073         },
1074         .ops = &hsic_xmm_plat_ops,
1075 };
1076 #endif
1077
1078 static int hsic_enable_gpio = -1;
1079 static int hsic_reset_gpio = -1;
1080
1081 void hsic_platform_open(void)
1082 {
1083         int reset_gpio = 0, enable_gpio = 0;
1084
1085         if (hsic_enable_gpio != -1)
1086                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1087         if (hsic_reset_gpio != -1)
1088                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1089         /* hsic enable signal deasserted, hsic reset asserted */
1090         if (!enable_gpio)
1091                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1092         if (!reset_gpio)
1093                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1094         if (!enable_gpio)
1095                 tegra_gpio_enable(hsic_enable_gpio);
1096         if (!reset_gpio)
1097                 tegra_gpio_enable(hsic_reset_gpio);
1098         /* keep hsic reset asserted for 1 ms */
1099         udelay(1000);
1100         /* enable (power on) hsic */
1101         if (!enable_gpio)
1102                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1103         udelay(1000);
1104         /* deassert reset */
1105         if (!reset_gpio)
1106                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1107
1108 }
1109
1110 void hsic_platform_close(void)
1111 {
1112         if (hsic_enable_gpio != -1) {
1113                 gpio_set_value(hsic_enable_gpio, 0);
1114                 gpio_free(hsic_enable_gpio);
1115         }
1116         if (hsic_reset_gpio != -1) {
1117                 gpio_set_value(hsic_reset_gpio, 0);
1118                 gpio_free(hsic_reset_gpio);
1119         }
1120 }
1121
1122 void hsic_power_on(void)
1123 {
1124         if (hsic_enable_gpio != -1) {
1125                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1126                 udelay(1000);
1127         }
1128 }
1129
1130 void hsic_power_off(void)
1131 {
1132         if (hsic_enable_gpio != -1) {
1133                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1134                 udelay(1000);
1135         }
1136 }
1137
1138 #if defined(CONFIG_USB_SUPPORT)
1139 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1140         .open = hsic_platform_open,
1141         .close = hsic_platform_close,
1142         .pre_phy_on = hsic_power_on,
1143         .post_phy_off = hsic_power_off,
1144 };
1145
1146 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1147         .port_otg = false,
1148         .has_hostpc = true,
1149         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1150         .op_mode        = TEGRA_USB_OPMODE_HOST,
1151         .u_data.host = {
1152                 .vbus_gpio = -1,
1153                 .hot_plug = false,
1154                 .remote_wakeup_supported = false,
1155                 .power_off_on_suspend = false,
1156         },
1157         .u_cfg.hsic = {
1158                 .sync_start_delay = 9,
1159                 .idle_wait_delay = 17,
1160                 .term_range_adj = 0,
1161                 .elastic_underrun_limit = 16,
1162                 .elastic_overrun_limit = 16,
1163         },
1164         .ops = &hsic_plat_ops,
1165 };
1166
1167 static struct tegra_usb_platform_data tegra_udc_pdata = {
1168         .port_otg = true,
1169         .has_hostpc = true,
1170         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1171         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1172         .u_data.dev = {
1173                 .vbus_pmu_irq = 0,
1174                 .vbus_gpio = -1,
1175                 .charging_supported = false,
1176                 .remote_wakeup_supported = false,
1177         },
1178         .u_cfg.utmi = {
1179                 .hssync_start_delay = 0,
1180                 .elastic_limit = 16,
1181                 .idle_wait_delay = 17,
1182                 .term_range_adj = 6,
1183                 .xcvr_setup = 8,
1184                 .xcvr_lsfslew = 2,
1185                 .xcvr_lsrslew = 2,
1186                 .xcvr_setup_offset = 0,
1187                 .xcvr_use_fuses = 1,
1188         },
1189 };
1190
1191 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1192         .port_otg = false,
1193         .has_hostpc = true,
1194         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1195         .op_mode        = TEGRA_USB_OPMODE_HOST,
1196         .u_data.host = {
1197                 .vbus_gpio = -1,
1198                 .hot_plug = false,
1199                 .remote_wakeup_supported = true,
1200                 .power_off_on_suspend = true,
1201         },
1202         .u_cfg.utmi = {
1203                 .hssync_start_delay = 0,
1204                 .elastic_limit = 16,
1205                 .idle_wait_delay = 17,
1206                 .term_range_adj = 6,
1207                 .xcvr_setup = 15,
1208                 .xcvr_lsfslew = 2,
1209                 .xcvr_lsrslew = 2,
1210                 .xcvr_setup_offset = 0,
1211                 .xcvr_use_fuses = 1,
1212         },
1213 };
1214
1215 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1216         .port_otg = false,
1217         .has_hostpc = true,
1218         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1219         .op_mode = TEGRA_USB_OPMODE_HOST,
1220         .u_data.host = {
1221                 .vbus_gpio = -1,
1222                 .vbus_reg = "vdd_vbus_typea_usb",
1223                 .hot_plug = true,
1224                 .remote_wakeup_supported = true,
1225                 .power_off_on_suspend = true,
1226         },
1227         .u_cfg.utmi = {
1228                 .hssync_start_delay = 0,
1229                 .elastic_limit = 16,
1230                 .idle_wait_delay = 17,
1231                 .term_range_adj = 6,
1232                 .xcvr_setup = 8,
1233                 .xcvr_lsfslew = 2,
1234                 .xcvr_lsrslew = 2,
1235                 .xcvr_setup_offset = 0,
1236                 .xcvr_use_fuses = 1,
1237         },
1238 };
1239
1240 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1241         .port_otg = true,
1242         .has_hostpc = true,
1243         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1244         .op_mode = TEGRA_USB_OPMODE_HOST,
1245         .u_data.host = {
1246                 .vbus_gpio = -1,
1247                 .vbus_reg = "vdd_vbus_micro_usb",
1248                 .hot_plug = true,
1249                 .remote_wakeup_supported = true,
1250                 .power_off_on_suspend = true,
1251         },
1252         .u_cfg.utmi = {
1253                 .hssync_start_delay = 0,
1254                 .elastic_limit = 16,
1255                 .idle_wait_delay = 17,
1256                 .term_range_adj = 6,
1257                 .xcvr_setup = 15,
1258                 .xcvr_lsfslew = 2,
1259                 .xcvr_lsrslew = 2,
1260                 .xcvr_setup_offset = 0,
1261                 .xcvr_use_fuses = 1,
1262         },
1263 };
1264
1265 static struct tegra_usb_otg_data tegra_otg_pdata = {
1266         .ehci_device = &tegra_ehci1_device,
1267         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1268 };
1269 #endif
1270
1271 #if defined(CONFIG_USB_SUPPORT)
1272 static void cardhu_usb_init(void)
1273 {
1274         struct board_info bi;
1275
1276         tegra_get_board_info(&bi);
1277
1278         /* OTG should be the first to be registered */
1279         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1280         platform_device_register(&tegra_otg_device);
1281
1282         /* setup the udc platform data */
1283         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1284
1285         if (bi.board_id == BOARD_PM267) {
1286                 hsic_enable_gpio = EN_HSIC_GPIO;
1287                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1288                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1289                 platform_device_register(&tegra_ehci2_device);
1290         } else if (bi.board_id == BOARD_E1256) {
1291                 hsic_enable_gpio = EN_HSIC_GPIO;
1292                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1293                 platform_device_register(&tegra_ehci2_device);
1294         } else if (bi.board_id == BOARD_E1186) {
1295                 tegra_ehci2_device.dev.platform_data =
1296                                                 &tegra_ehci2_hsic_xmm_pdata;
1297                 /* ehci2 registration happens in baseband-xmm-power  */
1298         } else {
1299                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1300                 platform_device_register(&tegra_ehci2_device);
1301         }
1302
1303         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1304         platform_device_register(&tegra_ehci3_device);
1305
1306 }
1307 #else
1308 static void cardhu_usb_init(void) { }
1309 #endif
1310
1311 static struct baseband_power_platform_data tegra_baseband_power_data = {
1312         .baseband_type = BASEBAND_XMM,
1313         .modem = {
1314         .xmm = {
1315                         .bb_rst = XMM_GPIO_BB_RST,
1316                         .bb_on = XMM_GPIO_BB_ON,
1317                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1318                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1319                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1320                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1321                         .hsic_device = &tegra_ehci2_device,
1322                 },
1323         },
1324 };
1325
1326 static struct platform_device tegra_baseband_power_device = {
1327         .name = "baseband_xmm_power",
1328         .id = -1,
1329         .dev = {
1330                 .platform_data = &tegra_baseband_power_data,
1331         },
1332 };
1333
1334 static struct platform_device tegra_baseband_power2_device = {
1335         .name = "baseband_xmm_power2",
1336         .id = -1,
1337         .dev = {
1338                 .platform_data = &tegra_baseband_power_data,
1339         },
1340 };
1341
1342
1343 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1344         .port_status[0] = 1,
1345         .port_status[1] = 1,
1346         .port_status[2] = 1,
1347         .use_dock_detect        = 0,
1348         .gpio           = 0,
1349 };
1350
1351 static void cardhu_pci_init(void)
1352 {
1353         struct board_info board_info;
1354
1355         tegra_get_board_info(&board_info);
1356         if (board_info.board_id == BOARD_E1291) {
1357                 cardhu_pci_platform_data.port_status[0] = 0;
1358                 cardhu_pci_platform_data.port_status[1] = 0;
1359                 cardhu_pci_platform_data.port_status[2] = 1;
1360                 cardhu_pci_platform_data.use_dock_detect = 1;
1361                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1362         }
1363         if ((board_info.board_id == BOARD_E1186) ||
1364                 (board_info.board_id == BOARD_E1187) ||
1365                 (board_info.board_id == BOARD_E1291)) {
1366                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1367                 platform_device_register(&tegra_pci_device);
1368         }
1369 }
1370
1371 static void cardhu_modem_init(void)
1372 {
1373         struct board_info board_info;
1374         int w_disable_gpio, ret;
1375
1376         tegra_get_board_info(&board_info);
1377         switch (board_info.board_id) {
1378         case BOARD_E1291:
1379         case BOARD_E1198:
1380                 if (((board_info.board_id == BOARD_E1291) &&
1381                                 (board_info.fab < BOARD_FAB_A03)) ||
1382                         ((board_info.board_id == BOARD_E1198) &&
1383                                         (board_info.fab < BOARD_FAB_A02))) {
1384                         w_disable_gpio = TEGRA_GPIO_PH5;
1385                 } else {
1386                         w_disable_gpio = TEGRA_GPIO_PDD5;
1387                 }
1388
1389                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1390                 if (ret < 0)
1391                         pr_err("%s: gpio_request failed for gpio %d\n",
1392                                 __func__, w_disable_gpio);
1393                 else
1394                         gpio_direction_input(w_disable_gpio);
1395
1396                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1397                 if (((board_info.board_id == BOARD_E1291) &&
1398                                 (board_info.fab >= BOARD_FAB_A04)) ||
1399                         ((board_info.board_id == BOARD_E1198) &&
1400                                         (board_info.fab >= BOARD_FAB_A02))) {
1401                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1402                         if (ret < 0) {
1403                                 pr_err("%s(): Error in allocating gpio "
1404                                         "TEGRA_GPIO_PH7\n", __func__);
1405                                 break;
1406                         }
1407                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1408                 }
1409                 break;
1410         case BOARD_E1186:
1411                 platform_device_register(&tegra_baseband_power_device);
1412                 platform_device_register(&tegra_baseband_power2_device);
1413                 break;
1414         default:
1415                 break;
1416         }
1417
1418 }
1419
1420 #ifdef CONFIG_SATA_AHCI_TEGRA
1421 static void cardhu_sata_init(void)
1422 {
1423         platform_device_register(&tegra_sata_device);
1424 }
1425 #else
1426 static void cardhu_sata_init(void) { }
1427 #endif
1428
1429 static void __init tegra_cardhu_init(void)
1430 {
1431         tegra_thermal_init(&thermal_data,
1432                                 throttle_list,
1433                                 ARRAY_SIZE(throttle_list));
1434         tegra_clk_init_from_table(cardhu_clk_init_table);
1435         cardhu_pinmux_init();
1436         cardhu_i2c_init();
1437         cardhu_spi_init();
1438         cardhu_usb_init();
1439 #ifdef CONFIG_TEGRA_EDP_LIMITS
1440         cardhu_edp_init();
1441 #endif
1442         cardhu_uart_init();
1443         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1444         tegra_ram_console_debug_init();
1445         tegra_io_dpd_init();
1446         cardhu_sdhci_init();
1447         cardhu_regulator_init();
1448         cardhu_dtv_init();
1449         cardhu_suspend_init();
1450         cardhu_touch_init();
1451         cardhu_modem_init();
1452         cardhu_kbc_init();
1453         cardhu_scroll_init();
1454         cardhu_keys_init();
1455         cardhu_panel_init();
1456         cardhu_pmon_init();
1457         cardhu_sensors_init();
1458         cardhu_setup_bluesleep();
1459         cardhu_sata_init();
1460         //audio_wired_jack_init();
1461         cardhu_pins_state_init();
1462         cardhu_emc_init();
1463         tegra_release_bootloader_fb();
1464         cardhu_pci_init();
1465 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1466         tegra_wdt_recovery_init();
1467 #endif
1468         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1469 }
1470
1471 static void __init tegra_cardhu_reserve(void)
1472 {
1473 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1474         /* support 1920X1200 with 24bpp */
1475         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1476 #else
1477         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1478 #endif
1479         tegra_ram_console_debug_reserve(SZ_1M);
1480 }
1481
1482 MACHINE_START(CARDHU, "cardhu")
1483         .boot_params    = 0x80000100,
1484         .map_io         = tegra_map_common_io,
1485         .reserve        = tegra_cardhu_reserve,
1486         .init_early     = tegra_init_early,
1487         .init_irq       = tegra_init_irq,
1488         .timer          = &tegra_timer,
1489         .init_machine   = tegra_cardhu_init,
1490 MACHINE_END