arm: tegra: Cardhu board file, 400K I2C touch drvr
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <asm/hardware/gic.h>
48
49 #include <mach/clk.h>
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/pinmux.h>
53 #include <mach/iomap.h>
54 #include <mach/io.h>
55 #include <mach/i2s.h>
56 #include <mach/tegra_asoc_pdata.h>
57 #include <mach/tegra_wm8903_pdata.h>
58 #include <asm/mach-types.h>
59 #include <asm/mach/arch.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/gpio-tegra.h>
64
65 #include "board.h"
66 #include "clock.h"
67 #include "board-cardhu.h"
68 #include "board-touch.h"
69 #include "devices.h"
70 #include "gpio-names.h"
71 #include "fuse.h"
72 #include "pm.h"
73 #include "baseband-xmm-power.h"
74 #include "wdt-recovery.h"
75
76 /* All units are in millicelsius */
77 static struct tegra_thermal_data thermal_data = {
78         .temp_throttle = 85000,
79         .temp_shutdown = 90000,
80         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
81 #ifdef CONFIG_TEGRA_EDP_LIMITS
82         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
83         .hysteresis_edp = 3000,
84 #endif
85 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
86         .tc1 = 0,
87         .tc2 = 1,
88         .passive_delay = 2000,
89 #else
90         .hysteresis_throttle = 1000,
91 #endif
92 };
93
94 /* !!!TODO: Change for cardhu (Taken from Ventana) */
95 static struct tegra_utmip_config utmi_phy_config[] = {
96         [0] = {
97                         .hssync_start_delay = 0,
98                         .idle_wait_delay = 17,
99                         .elastic_limit = 16,
100                         .term_range_adj = 6,
101                         .xcvr_setup = 15,
102                         .xcvr_setup_offset = 0,
103                         .xcvr_use_fuses = 1,
104                         .xcvr_lsfslew = 2,
105                         .xcvr_lsrslew = 2,
106         },
107         [1] = {
108                         .hssync_start_delay = 0,
109                         .idle_wait_delay = 17,
110                         .elastic_limit = 16,
111                         .term_range_adj = 6,
112                         .xcvr_setup = 15,
113                         .xcvr_setup_offset = 0,
114                         .xcvr_use_fuses = 1,
115                         .xcvr_lsfslew = 2,
116                         .xcvr_lsrslew = 2,
117         },
118         [2] = {
119                         .hssync_start_delay = 0,
120                         .idle_wait_delay = 17,
121                         .elastic_limit = 16,
122                         .term_range_adj = 6,
123                         .xcvr_setup = 8,
124                         .xcvr_setup_offset = 0,
125                         .xcvr_use_fuses = 1,
126                         .xcvr_lsfslew = 2,
127                         .xcvr_lsrslew = 2,
128         },
129 };
130
131 static struct resource cardhu_bcm4329_rfkill_resources[] = {
132         {
133                 .name   = "bcm4329_nshutdown_gpio",
134                 .start  = TEGRA_GPIO_PU0,
135                 .end    = TEGRA_GPIO_PU0,
136                 .flags  = IORESOURCE_IO,
137         },
138 };
139
140 static struct platform_device cardhu_bcm4329_rfkill_device = {
141         .name = "bcm4329_rfkill",
142         .id             = -1,
143         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
144         .resource       = cardhu_bcm4329_rfkill_resources,
145 };
146
147 static struct resource cardhu_bluesleep_resources[] = {
148         [0] = {
149                 .name = "gpio_host_wake",
150                         .start  = TEGRA_GPIO_PU6,
151                         .end    = TEGRA_GPIO_PU6,
152                         .flags  = IORESOURCE_IO,
153         },
154         [1] = {
155                 .name = "gpio_ext_wake",
156                         .start  = TEGRA_GPIO_PU1,
157                         .end    = TEGRA_GPIO_PU1,
158                         .flags  = IORESOURCE_IO,
159         },
160         [2] = {
161                 .name = "host_wake",
162                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
163                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
164                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
165         },
166 };
167
168 static struct platform_device cardhu_bluesleep_device = {
169         .name           = "bluesleep",
170         .id             = -1,
171         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
172         .resource       = cardhu_bluesleep_resources,
173 };
174
175 static noinline void __init cardhu_setup_bluesleep(void)
176 {
177         platform_device_register(&cardhu_bluesleep_device);
178         tegra_gpio_enable(TEGRA_GPIO_PU6);
179         tegra_gpio_enable(TEGRA_GPIO_PU1);
180         return;
181 }
182
183 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
184         /* name         parent          rate            enabled */
185         { "pll_m",      NULL,           0,              false},
186         { "hda",        "pll_p",        108000000,      false},
187         { "hda2codec_2x","pll_p",       48000000,       false},
188         { "pwm",        "pll_p",        3187500,        false},
189         { "blink",      "clk_32k",      32768,          true},
190         { "i2s0",       "pll_a_out0",   0,              false},
191         { "i2s1",       "pll_a_out0",   0,              false},
192         { "i2s3",       "pll_a_out0",   0,              false},
193         { "spdif_out",  "pll_a_out0",   0,              false},
194         { "d_audio",    "clk_m",        12000000,       false},
195         { "dam0",       "clk_m",        12000000,       false},
196         { "dam1",       "clk_m",        12000000,       false},
197         { "dam2",       "clk_m",        12000000,       false},
198         { "audio1",     "i2s1_sync",    0,              false},
199         { "audio3",     "i2s3_sync",    0,              false},
200         { "vi_sensor",  "pll_p",        150000000,      false},
201         { "i2c1",       "pll_p",        3200000,        false},
202         { "i2c2",       "pll_p",        3200000,        false},
203         { "i2c3",       "pll_p",        3200000,        false},
204         { "i2c4",       "pll_p",        3200000,        false},
205         { "i2c5",       "pll_p",        3200000,        false},
206         { NULL,         NULL,           0,              0},
207 };
208
209 static struct pn544_i2c_platform_data nfc_pdata = {
210         .irq_gpio = TEGRA_GPIO_PX0,
211         .ven_gpio = TEGRA_GPIO_PP3,
212         .firm_gpio = TEGRA_GPIO_PO7,
213         };
214
215 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
216         {
217                 I2C_BOARD_INFO("pn544", 0x28),
218                 .platform_data = &nfc_pdata,
219                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
220         },
221 };
222 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
223         .adapter_nr     = 0,
224         .bus_count      = 1,
225         .bus_clk_rate   = { 100000, 0 },
226         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
227         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
228         .arb_recovery = arb_lost_recovery,
229 };
230
231 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
232         .adapter_nr     = 1,
233         .bus_count      = 1,
234         .bus_clk_rate   = { 400000, 0 },
235         .is_clkon_always = true,
236         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
237         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
238         .arb_recovery = arb_lost_recovery,
239 };
240
241 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
242         .adapter_nr     = 2,
243         .bus_count      = 1,
244         .bus_clk_rate   = { 100000, 0 },
245         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
246         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
247         .arb_recovery = arb_lost_recovery,
248 };
249
250 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
251         .adapter_nr     = 3,
252         .bus_count      = 1,
253         .bus_clk_rate   = { 10000, 0 },
254         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
255         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
256         .arb_recovery = arb_lost_recovery,
257 };
258
259 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
260         .adapter_nr     = 4,
261         .bus_count      = 1,
262         .bus_clk_rate   = { 400000, 0 },
263         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
264         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
265         .arb_recovery = arb_lost_recovery,
266 };
267
268
269 #if 0
270 struct tegra_wired_jack_conf audio_wr_jack_conf = {
271         .hp_det_n = TEGRA_GPIO_PW2,
272         .en_mic_ext = TEGRA_GPIO_PX1,
273         .en_mic_int = TEGRA_GPIO_PX0,
274 };
275 #endif
276
277 static struct wm8903_platform_data cardhu_wm8903_pdata = {
278         .irq_active_low = 0,
279         .micdet_cfg = 0,
280         .micdet_delay = 100,
281         .gpio_base = CARDHU_GPIO_WM8903(0),
282         .gpio_cfg = {
283                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
284                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
285                         WM8903_GP2_DIR,
286                 WM8903_GPIO_CONFIG_ZERO,
287                 0,
288                 0,
289         },
290 };
291
292 /* Equalizer filter coefs generated from the MAXIM MAX98095
293  * evkit software tool */
294 static struct max98095_eq_cfg max98095_eq_cfg[] = {
295         {
296                 .name = "FLAT",
297                 .rate = 44100,
298                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
299                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
300                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
301                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
302                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
303         },
304         {
305                 .name = "LOWPASS1K",
306                 .rate = 44100,
307                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
308                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
309                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
310                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
311                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
312         },
313         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
314                 .name = "HIBOOST",
315                 .rate = 44100,
316                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
317                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
318                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
319                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
320                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
321         },
322         { /* BASS=12dB, TREBLE=+12dB */
323                 .name = "LOUD12DB",
324                 .rate = 44100,
325                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
326                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
327                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
328                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
329                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
330         },
331         {
332                 .name = "FLAT",
333                 .rate = 16000,
334                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
335                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
336                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
337                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
338                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
339         },
340         {
341                 .name = "LOWPASS1K",
342                 .rate = 16000,
343                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
344                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
345                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
346                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
347                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
348         },
349         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
350                 .name = "HIBOOST",
351                 .rate = 16000,
352                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
353                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
354                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
355                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
356                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
357         },
358         { /* BASS=12dB, TREBLE=+12dB */
359                 .name = "LOUD12DB",
360                 .rate = 16000,
361                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
362                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
363                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
364                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
365                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
366         },
367 };
368
369 static struct max98095_pdata cardhu_max98095_pdata = {
370         /* equalizer configuration */
371         .eq_cfg = max98095_eq_cfg,
372         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
373
374         /* Biquad filter response configuration */
375         .bq_cfg = NULL,
376         .bq_cfgcnt = 0,
377
378         /* microphone configuration */
379         .digmic_left_mode = 1,
380         .digmic_right_mode = 1,
381 };
382
383 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
384         I2C_BOARD_INFO("wm8903", 0x1a),
385         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
386         .platform_data = &cardhu_wm8903_pdata,
387 };
388
389 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
390         I2C_BOARD_INFO("aic3262-codec", 0x18),
391         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
392 };
393
394 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
395         I2C_BOARD_INFO("max98095", 0x10),
396         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
397         .platform_data = &cardhu_max98095_pdata,
398 };
399
400 static void cardhu_i2c_init(void)
401 {
402         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
403         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
404         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
405         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
406         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
407
408         platform_device_register(&tegra_i2c_device5);
409         platform_device_register(&tegra_i2c_device4);
410         platform_device_register(&tegra_i2c_device3);
411         platform_device_register(&tegra_i2c_device2);
412         platform_device_register(&tegra_i2c_device1);
413
414         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
415         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
416         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
417
418         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
419 }
420
421 static struct platform_device *cardhu_uart_devices[] __initdata = {
422         &tegra_uarta_device,
423         &tegra_uartb_device,
424         &tegra_uartc_device,
425         &tegra_uartd_device,
426         &tegra_uarte_device,
427 };
428 static struct uart_clk_parent uart_parent_clk[] = {
429         [0] = {.name = "clk_m"},
430         [1] = {.name = "pll_p"},
431 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
432         [2] = {.name = "pll_m"},
433 #endif
434 };
435
436 static struct tegra_uart_platform_data cardhu_uart_pdata;
437 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
438
439 static void __init uart_debug_init(void)
440 {
441         struct board_info board_info;
442         int debug_port_id;
443
444         tegra_get_board_info(&board_info);
445
446         debug_port_id = get_tegra_uart_debug_port_id();
447         if (debug_port_id < 0) {
448                 debug_port_id = 0;
449                         /* UARTB is debug port
450                          *       for SLT - E1186/E1187/PM269
451                          *       for E1256/E1257
452                          */
453                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
454                         ((board_info.board_id == BOARD_E1186) ||
455                         (board_info.board_id == BOARD_E1187) ||
456                         (board_info.board_id == BOARD_PM269))) ||
457                         (board_info.board_id == BOARD_E1256) ||
458                         (board_info.board_id == BOARD_E1257))
459                                 debug_port_id = 1;
460         }
461
462         switch (debug_port_id) {
463         case 0:
464                 /* UARTA is the debug port. */
465                 pr_info("Selecting UARTA as the debug console\n");
466                 cardhu_uart_devices[0] = &debug_uarta_device;
467                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
468                 debug_uart_port_base = ((struct plat_serial8250_port *)(
469                         debug_uarta_device.dev.platform_data))->mapbase;
470                 break;
471
472         case 1:
473                 /* UARTB is the debug port. */
474                 pr_info("Selecting UARTB as the debug console\n");
475                 cardhu_uart_devices[1] = &debug_uartb_device;
476                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
477                 debug_uart_port_base = ((struct plat_serial8250_port *)(
478                         debug_uartb_device.dev.platform_data))->mapbase;
479                 break;
480
481         case 2:
482                 /* UARTC is the debug port. */
483                 pr_info("Selecting UARTC as the debug console\n");
484                 cardhu_uart_devices[2] = &debug_uartc_device;
485                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
486                 debug_uart_port_base = ((struct plat_serial8250_port *)(
487                         debug_uartc_device.dev.platform_data))->mapbase;
488                 break;
489
490         case 3:
491                 /* UARTD is the debug port. */
492                 pr_info("Selecting UARTD as the debug console\n");
493                 cardhu_uart_devices[3] = &debug_uartd_device;
494                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
495                 debug_uart_port_base = ((struct plat_serial8250_port *)(
496                         debug_uartd_device.dev.platform_data))->mapbase;
497                 break;
498
499         case 4:
500                 /* UARTE is the debug port. */
501                 pr_info("Selecting UARTE as the debug console\n");
502                 cardhu_uart_devices[4] = &debug_uarte_device;
503                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
504                 debug_uart_port_base = ((struct plat_serial8250_port *)(
505                         debug_uarte_device.dev.platform_data))->mapbase;
506                 break;
507
508         default:
509                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
510                 cardhu_uart_devices[0] = &debug_uarta_device;
511                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
512                 debug_uart_port_base = ((struct plat_serial8250_port *)(
513                         debug_uarta_device.dev.platform_data))->mapbase;
514                 break;
515         }
516         return;
517 }
518
519 static void __init cardhu_uart_init(void)
520 {
521         struct clk *c;
522         int i;
523
524         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
525                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
526                 if (IS_ERR_OR_NULL(c)) {
527                         pr_err("Not able to get the clock for %s\n",
528                                                 uart_parent_clk[i].name);
529                         continue;
530                 }
531                 uart_parent_clk[i].parent_clk = c;
532                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
533         }
534         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
535         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
536         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
537         cardhu_loopback_uart_pdata.parent_clk_count =
538                                                 ARRAY_SIZE(uart_parent_clk);
539         cardhu_loopback_uart_pdata.is_loopback = true;
540         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
541         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
542         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
543         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
544         /* UARTE is used for loopback test purpose */
545         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
546
547         /* Register low speed only if it is selected */
548         if (!is_tegra_debug_uartport_hs()) {
549                 uart_debug_init();
550                 /* Clock enable for the debug channel */
551                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
552                         pr_info("The debug console clock name is %s\n",
553                                                 debug_uart_clk->name);
554                         c = tegra_get_clock_by_name("pll_p");
555                         if (IS_ERR_OR_NULL(c))
556                                 pr_err("Not getting the parent clock pll_p\n");
557                         else
558                                 clk_set_parent(debug_uart_clk, c);
559
560                         clk_enable(debug_uart_clk);
561                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
562                 } else {
563                         pr_err("Not getting the clock %s for debug console\n",
564                                         debug_uart_clk->name);
565                 }
566         }
567
568         platform_add_devices(cardhu_uart_devices,
569                                 ARRAY_SIZE(cardhu_uart_devices));
570 }
571
572 static struct platform_device tegra_camera = {
573         .name = "tegra_camera",
574         .id = -1,
575 };
576
577 static struct platform_device *cardhu_spi_devices[] __initdata = {
578         &tegra_spi_device4,
579 };
580
581 static struct platform_device *touch_spi_device[] __initdata = {
582         &tegra_spi_device1,
583 };
584
585 struct spi_clk_parent spi_parent_clk[] = {
586         [0] = {.name = "pll_p"},
587 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
588         [1] = {.name = "pll_m"},
589         [2] = {.name = "clk_m"},
590 #else
591         [1] = {.name = "clk_m"},
592 #endif
593 };
594
595 static struct tegra_spi_platform_data cardhu_spi_pdata = {
596         .is_dma_based           = true,
597         .max_dma_buffer         = (16 * 1024),
598         .is_clkon_always        = false,
599         .max_rate               = 100000000,
600 };
601
602 static void __init cardhu_spi_init(void)
603 {
604         int i;
605         struct clk *c;
606         struct board_info board_info, display_board_info;
607
608         tegra_get_board_info(&board_info);
609         tegra_get_display_board_info(&display_board_info);
610
611         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
612                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
613                 if (IS_ERR_OR_NULL(c)) {
614                         pr_err("Not able to get the clock for %s\n",
615                                                 spi_parent_clk[i].name);
616                         continue;
617                 }
618                 spi_parent_clk[i].parent_clk = c;
619                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
620         }
621         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
622         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
623         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
624         platform_add_devices(cardhu_spi_devices,
625                                 ARRAY_SIZE(cardhu_spi_devices));
626
627         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
628                 platform_add_devices(touch_spi_device,
629                                 ARRAY_SIZE(touch_spi_device));
630         }
631         if (board_info.board_id == BOARD_E1198) {
632                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
633                 platform_device_register(&tegra_spi_device2);
634                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
635                 platform_device_register(&tegra_spi_slave_device1);
636         }
637 }
638
639 static void __init cardhu_dtv_init(void)
640 {
641         struct board_info board_info;
642
643         tegra_get_board_info(&board_info);
644
645         if (board_info.board_id == BOARD_E1186)
646                 platform_device_register(&tegra_dtv_device);
647 }
648
649 static struct resource tegra_rtc_resources[] = {
650         [0] = {
651                 .start = TEGRA_RTC_BASE,
652                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
653                 .flags = IORESOURCE_MEM,
654         },
655         [1] = {
656                 .start = INT_RTC,
657                 .end = INT_RTC,
658                 .flags = IORESOURCE_IRQ,
659         },
660 };
661
662 static struct platform_device tegra_rtc_device = {
663         .name = "tegra_rtc",
664         .id   = -1,
665         .resource = tegra_rtc_resources,
666         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
667 };
668
669 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
670         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
671         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
672         .gpio_hp_mute           = -1,
673         .gpio_int_mic_en        = -1,
674         .gpio_ext_mic_en        = -1,
675 };
676
677 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
678         .gpio_spkr_en           = -1,
679         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
680         .gpio_hp_mute           = -1,
681         .gpio_int_mic_en        = -1,
682         .gpio_ext_mic_en        = -1,
683 };
684
685 static struct platform_device cardhu_audio_wm8903_device = {
686         .name   = "tegra-snd-wm8903",
687         .id     = 0,
688         .dev    = {
689                 .platform_data = &cardhu_audio_wm8903_pdata,
690         },
691 };
692
693 static struct platform_device cardhu_audio_max98095_device = {
694         .name   = "tegra-snd-max98095",
695         .id     = 0,
696         .dev    = {
697                 .platform_data = &cardhu_audio_max98095_pdata,
698         },
699 };
700
701 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
702         .gpio_spkr_en           = -1,
703         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
704         .gpio_hp_mute           = -1,
705         .gpio_int_mic_en        = -1,
706         .gpio_ext_mic_en        = -1,
707         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
708         .audio_port_id          = {
709                 [HIFI_CODEC] = 0,
710                 [BASEBAND] = -1,
711                 [BT_SCO] = 3,
712         },
713         .baseband_param         = {
714                 .rate = -1,
715                 .channels = -1,
716         },
717 };
718
719 static struct platform_device cardhu_audio_aic326x_device = {
720         .name   = "tegra-snd-aic326x",
721         .id     = 0,
722         .dev    = {
723                 .platform_data  = &cardhu_audio_aic326x_pdata,
724         },
725 };
726
727 static struct platform_device *cardhu_devices[] __initdata = {
728         &tegra_pmu_device,
729         &tegra_rtc_device,
730         &tegra_udc_device,
731 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
732         &tegra_smmu_device,
733 #endif
734         &tegra_wdt_device,
735 #if defined(CONFIG_TEGRA_AVP)
736         &tegra_avp_device,
737 #endif
738         &tegra_camera,
739 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
740         &tegra_se_device,
741 #endif
742         &tegra_ahub_device,
743         &tegra_dam_device0,
744         &tegra_dam_device1,
745         &tegra_dam_device2,
746         &tegra_i2s_device0,
747         &tegra_i2s_device1,
748         &tegra_i2s_device3,
749         &tegra_spdif_device,
750         &spdif_dit_device,
751         &bluetooth_dit_device,
752         &baseband_dit_device,
753         &cardhu_bcm4329_rfkill_device,
754         &tegra_pcm_device,
755         &cardhu_audio_wm8903_device,
756         &cardhu_audio_max98095_device,
757         &cardhu_audio_aic326x_device,
758         &tegra_hda_device,
759 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
760         &tegra_aes_device,
761 #endif
762 };
763
764 #define MXT_CONFIG_CRC  0xD62DE8
765 static const u8 config[] = {
766         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
767         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
768         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
769         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
770         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
771         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
772         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
773         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
774         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
775         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
776         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
777         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
778         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
779         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
780         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
781         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
782         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
783         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
784         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
786 };
787
788 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
789 static const u8 config_sku2000[] = {
790         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
791         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
792         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
793         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
794         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
795         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
796         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
797         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
798         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
799         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
800         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
801         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
802         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
803         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
804         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
806         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
808         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
810 };
811
812 static struct mxt_platform_data atmel_mxt_info = {
813         .x_line         = 27,
814         .y_line         = 42,
815         .x_size         = 768,
816         .y_size         = 1366,
817         .blen           = 0x20,
818         .threshold      = 0x3C,
819         .voltage        = 3300000,              /* 3.3V */
820         .orient         = 5,
821         .config         = config,
822         .config_length  = 157,
823         .config_crc     = MXT_CONFIG_CRC,
824         .irqflags       = IRQF_TRIGGER_FALLING,
825 /*      .read_chg       = &read_chg, */
826         .read_chg       = NULL,
827 };
828
829 static struct i2c_board_info __initdata atmel_i2c_info[] = {
830         {
831                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
832                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
833                 .platform_data = &atmel_mxt_info,
834         }
835 };
836
837 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
838         /* name         parent          rate            enabled */
839         { "sbc1",       "pll_p",        52000000,       true},
840         { NULL,         NULL,           0,              0},
841 };
842
843 static int __init cardhu_touch_init(void)
844 {
845         struct board_info BoardInfo;
846
847         tegra_get_display_board_info(&BoardInfo);
848         if (BoardInfo.board_id == BOARD_DISPLAY_PM313) {
849                 tegra_clk_init_from_table(spi_clk_init_table);
850
851                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
852         } else {
853                 tegra_gpio_enable(TEGRA_GPIO_PH4);
854                 tegra_gpio_enable(TEGRA_GPIO_PH6);
855
856                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
857                 gpio_direction_input(TEGRA_GPIO_PH4);
858
859                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
860                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
861                 msleep(1);
862                 gpio_set_value(TEGRA_GPIO_PH6, 1);
863                 msleep(100);
864
865                 tegra_get_board_info(&BoardInfo);
866                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
867                         atmel_mxt_info.config = config_sku2000;
868                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
869                 }
870
871                 i2c_register_board_info(1, atmel_i2c_info, 1);
872         }
873
874         return 0;
875 }
876
877 static struct tegra_uhsic_config uhsic_phy_config = {
878         .enable_gpio = EN_HSIC_GPIO,
879         .reset_gpio = -1,
880         .sync_start_delay = 9,
881         .idle_wait_delay = 17,
882         .term_range_adj = 0,
883         .elastic_underrun_limit = 16,
884         .elastic_overrun_limit = 16,
885 };
886
887 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
888         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
889         .phy_config = &uhsic_phy_config,
890         .operating_mode = TEGRA_USB_HOST,
891         .power_down_on_bus_suspend = 1,
892         .default_enable = true,
893 };
894
895 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
896         [0] = {
897                         .phy_config = &utmi_phy_config[0],
898                         .operating_mode = TEGRA_USB_HOST,
899                         .power_down_on_bus_suspend = 1,
900                         .default_enable = true,
901         },
902         [1] = {
903                         .phy_config = &utmi_phy_config[1],
904                         .operating_mode = TEGRA_USB_HOST,
905                         .power_down_on_bus_suspend = 1,
906                         .default_enable = true,
907         },
908         [2] = {
909                         .phy_config = &utmi_phy_config[2],
910                         .operating_mode = TEGRA_USB_HOST,
911                         .power_down_on_bus_suspend = 1,
912                         .hotplug = 1,
913                         .default_enable = true,
914         },
915 };
916
917 static struct tegra_otg_platform_data tegra_otg_pdata = {
918         .ehci_device = &tegra_ehci1_device,
919         .ehci_pdata = &tegra_ehci_pdata[0],
920 };
921
922 #ifdef CONFIG_USB_SUPPORT
923 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
924         [0] = {
925                         .instance = 0,
926                         .vbus_gpio = -1,
927                         .vbus_reg_supply = "vdd_vbus_micro_usb",
928         },
929         [1] = {
930                         .instance = 1,
931                         .vbus_gpio = -1,
932         },
933         [2] = {
934                         .instance = 2,
935                         .vbus_gpio = -1,
936                         .vbus_reg_supply = "vdd_vbus_typea_usb",
937         },
938 };
939
940 static int cardhu_usb_hsic_postsupend(void)
941 {
942 #ifdef CONFIG_TEGRA_BB_XMM_POWER
943         baseband_xmm_set_power_status(BBXMM_PS_L2);
944 #endif
945         return 0;
946 }
947
948 static int cardhu_usb_hsic_preresume(void)
949 {
950 #ifdef CONFIG_TEGRA_BB_XMM_POWER
951         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
952 #endif
953         return 0;
954 }
955
956 static int cardhu_usb_hsic_phy_ready(void)
957 {
958 #ifdef CONFIG_TEGRA_BB_XMM_POWER
959         baseband_xmm_set_power_status(BBXMM_PS_L0);
960 #endif
961         return 0;
962 }
963
964 static int cardhu_usb_hsic_phy_off(void)
965 {
966 #ifdef CONFIG_TEGRA_BB_XMM_POWER
967         baseband_xmm_set_power_status(BBXMM_PS_L3);
968 #endif
969         return 0;
970 }
971
972 static void cardhu_usb_init(void)
973 {
974         struct board_info bi;
975
976         tegra_get_board_info(&bi);
977
978         tegra_usb_phy_init(tegra_usb_phy_pdata,
979                         ARRAY_SIZE(tegra_usb_phy_pdata));
980
981         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
982         platform_device_register(&tegra_otg_device);
983         if (bi.board_id == BOARD_PM267) {
984                 uhsic_phy_config.reset_gpio =
985                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
986                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
987                 platform_device_register(&tegra_ehci2_device);
988         } else if (bi.board_id == BOARD_E1256) {
989                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
990                 platform_device_register(&tegra_ehci2_device);
991         } else if (bi.board_id == BOARD_E1186) {
992                 /* for baseband devices do not switch off phy during suspend */
993                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
994                 uhsic_phy_config.postsuspend = cardhu_usb_hsic_postsupend;
995                 uhsic_phy_config.preresume = cardhu_usb_hsic_preresume;
996                 uhsic_phy_config.usb_phy_ready = cardhu_usb_hsic_phy_ready;
997                 uhsic_phy_config.post_phy_off = cardhu_usb_hsic_phy_off;
998                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
999                 /* baseband registration happens in baseband-xmm-power  */
1000         } else {
1001                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
1002                 platform_device_register(&tegra_ehci2_device);
1003         }
1004
1005         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
1006         platform_device_register(&tegra_ehci3_device);
1007
1008 }
1009 #else
1010 static void cardhu_usb_init(void) { }
1011 #endif
1012
1013 static void cardhu_gps_init(void)
1014 {
1015         tegra_gpio_enable(TEGRA_GPIO_PU2);
1016         tegra_gpio_enable(TEGRA_GPIO_PU3);
1017 }
1018
1019 static void cardhu_nfc_init(void)
1020 {
1021         tegra_gpio_enable(TEGRA_GPIO_PX0);
1022         tegra_gpio_enable(TEGRA_GPIO_PP3);
1023         tegra_gpio_enable(TEGRA_GPIO_PO7);
1024 }
1025
1026 static struct baseband_power_platform_data tegra_baseband_power_data = {
1027         .baseband_type = BASEBAND_XMM,
1028         .modem = {
1029         .xmm = {
1030                         .bb_rst = XMM_GPIO_BB_RST,
1031                         .bb_on = XMM_GPIO_BB_ON,
1032                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1033                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1034                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1035                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1036                         .hsic_device = &tegra_ehci2_device,
1037                 },
1038         },
1039 };
1040
1041 static struct platform_device tegra_baseband_power_device = {
1042         .name = "baseband_xmm_power",
1043         .id = -1,
1044         .dev = {
1045                 .platform_data = &tegra_baseband_power_data,
1046         },
1047 };
1048
1049 static struct platform_device tegra_baseband_power2_device = {
1050         .name = "baseband_xmm_power2",
1051         .id = -1,
1052         .dev = {
1053                 .platform_data = &tegra_baseband_power_data,
1054         },
1055 };
1056
1057
1058 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1059         .port_status[0] = 1,
1060         .port_status[1] = 1,
1061         .port_status[2] = 1,
1062         .use_dock_detect        = 0,
1063         .gpio           = 0,
1064 };
1065
1066 static void cardhu_pci_init(void)
1067 {
1068         struct board_info board_info;
1069
1070         tegra_get_board_info(&board_info);
1071         if (board_info.board_id == BOARD_E1291) {
1072                 cardhu_pci_platform_data.port_status[0] = 0;
1073                 cardhu_pci_platform_data.port_status[1] = 0;
1074                 cardhu_pci_platform_data.port_status[2] = 1;
1075                 cardhu_pci_platform_data.use_dock_detect = 1;
1076                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1077         }
1078         if ((board_info.board_id == BOARD_E1186) ||
1079                 (board_info.board_id == BOARD_E1187) ||
1080                 (board_info.board_id == BOARD_E1291)) {
1081                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1082                 platform_device_register(&tegra_pci_device);
1083         }
1084 }
1085
1086 static void cardhu_modem_init(void)
1087 {
1088         struct board_info board_info;
1089         int w_disable_gpio, ret;
1090
1091         tegra_get_board_info(&board_info);
1092         switch (board_info.board_id) {
1093         case BOARD_E1291:
1094         case BOARD_E1198:
1095                 if (((board_info.board_id == BOARD_E1291) &&
1096                                 (board_info.fab < BOARD_FAB_A03)) ||
1097                         ((board_info.board_id == BOARD_E1198) &&
1098                                         (board_info.fab < BOARD_FAB_A02))) {
1099                         w_disable_gpio = TEGRA_GPIO_PH5;
1100                 } else {
1101                         w_disable_gpio = TEGRA_GPIO_PDD5;
1102                 }
1103                 tegra_gpio_enable(w_disable_gpio);
1104                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1105                 if (ret < 0)
1106                         pr_err("%s: gpio_request failed for gpio %d\n",
1107                                 __func__, w_disable_gpio);
1108                 else
1109                         gpio_direction_input(w_disable_gpio);
1110
1111                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1112                 if (((board_info.board_id == BOARD_E1291) &&
1113                                 (board_info.fab >= BOARD_FAB_A04)) ||
1114                         ((board_info.board_id == BOARD_E1198) &&
1115                                         (board_info.fab >= BOARD_FAB_A02))) {
1116                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1117                         if (ret < 0) {
1118                                 pr_err("%s(): Error in allocating gpio "
1119                                         "TEGRA_GPIO_PH7\n", __func__);
1120                                 break;
1121                         }
1122                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1123                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1124                 }
1125                 break;
1126         case BOARD_E1186:
1127                 tegra_gpio_enable(
1128                         tegra_baseband_power_data.modem.xmm.bb_rst);
1129                 tegra_gpio_enable(
1130                         tegra_baseband_power_data.modem.xmm.bb_on);
1131                 tegra_gpio_enable(
1132                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1133                 tegra_gpio_enable(
1134                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1135                 tegra_gpio_enable(
1136                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1137                 tegra_gpio_enable(
1138                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1139                 platform_device_register(&tegra_baseband_power_device);
1140                 platform_device_register(&tegra_baseband_power2_device);
1141                 break;
1142         default:
1143                 break;
1144         }
1145
1146 }
1147
1148 #ifdef CONFIG_SATA_AHCI_TEGRA
1149 static void cardhu_sata_init(void)
1150 {
1151         platform_device_register(&tegra_sata_device);
1152 }
1153 #else
1154 static void cardhu_sata_init(void) { }
1155 #endif
1156
1157 static void __init tegra_cardhu_init(void)
1158 {
1159         tegra_thermal_init(&thermal_data);
1160         tegra_clk_init_from_table(cardhu_clk_init_table);
1161         tegra_enable_pinmux();
1162         cardhu_pinmux_init();
1163         cardhu_i2c_init();
1164         cardhu_spi_init();
1165         cardhu_usb_init();
1166 #ifdef CONFIG_TEGRA_EDP_LIMITS
1167         cardhu_edp_init();
1168 #endif
1169         cardhu_uart_init();
1170         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1171         tegra_ram_console_debug_init();
1172         cardhu_sdhci_init();
1173         cardhu_regulator_init();
1174         cardhu_dtv_init();
1175         cardhu_suspend_init();
1176         cardhu_touch_init();
1177         cardhu_gps_init();
1178         cardhu_modem_init();
1179         cardhu_kbc_init();
1180         cardhu_scroll_init();
1181         cardhu_keys_init();
1182         cardhu_panel_init();
1183         cardhu_pmon_init();
1184         cardhu_sensors_init();
1185         cardhu_setup_bluesleep();
1186         cardhu_sata_init();
1187         //audio_wired_jack_init();
1188         cardhu_pins_state_init();
1189         cardhu_emc_init();
1190         tegra_release_bootloader_fb();
1191         cardhu_nfc_init();
1192         cardhu_pci_init();
1193 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1194         tegra_wdt_recovery_init();
1195 #endif
1196 }
1197
1198 static void __init tegra_cardhu_reserve(void)
1199 {
1200 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1201         /* support 1920X1200 with 24bpp */
1202         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1203 #else
1204         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1205 #endif
1206         tegra_ram_console_debug_reserve(SZ_1M);
1207 }
1208
1209 MACHINE_START(CARDHU, "cardhu")
1210         .atag_offset    = 0x100,
1211         .map_io         = tegra_map_common_io,
1212         .reserve        = tegra_cardhu_reserve,
1213         .init_early     = tegra30_init_early,
1214         .init_irq       = tegra_init_irq,
1215         .handle_irq     = gic_handle_irq,
1216         .timer          = &tegra_timer,
1217         .init_machine   = tegra_cardhu_init,
1218         .restart        = tegra_assert_system_reset,
1219 MACHINE_END