arm: tegra: cardhu: IrDA support on UARTB
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <mach/clk.h>
49 #include <mach/iomap.h>
50 #include <mach/irqs.h>
51 #include <mach/pinmux.h>
52 #include <mach/iomap.h>
53 #include <mach/io_dpd.h>
54 #include <mach/io.h>
55 #include <mach/i2s.h>
56 #include <mach/tegra_asoc_pdata.h>
57 #include <mach/tegra_wm8903_pdata.h>
58 #include <asm/mach-types.h>
59 #include <asm/mach/arch.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/tegra_fiq_debugger.h>
64
65 #include "board.h"
66 #include "clock.h"
67 #include "board-cardhu.h"
68 #include "board-touch.h"
69 #include "devices.h"
70 #include "gpio-names.h"
71 #include "fuse.h"
72 #include "pm.h"
73 #include "baseband-xmm-power.h"
74 #include "wdt-recovery.h"
75
76 static struct balanced_throttle throttle_list[] = {
77 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
78         {
79                 .id = BALANCED_THROTTLE_ID_TJ,
80                 .throt_tab_size = 10,
81                 .throt_tab = {
82                         {      0, 1000 },
83                         { 640000, 1000 },
84                         { 640000, 1000 },
85                         { 640000, 1000 },
86                         { 640000, 1000 },
87                         { 640000, 1000 },
88                         { 760000, 1000 },
89                         { 760000, 1050 },
90                         {1000000, 1050 },
91                         {1000000, 1100 },
92                 },
93         },
94 #endif
95 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
96         {
97                 .id = BALANCED_THROTTLE_ID_SKIN,
98                 .throt_tab_size = 6,
99                 .throt_tab = {
100                         { 640000, 1200 },
101                         { 640000, 1200 },
102                         { 760000, 1200 },
103                         { 760000, 1200 },
104                         {1000000, 1200 },
105                         {1000000, 1200 },
106                 },
107         },
108 #endif
109 };
110
111 /* All units are in millicelsius */
112 static struct tegra_thermal_data thermal_data = {
113         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
114         .temp_shutdown = 90000,
115
116 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
117         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
118 #endif
119 #ifdef CONFIG_TEGRA_EDP_LIMITS
120         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
121         .hysteresis_edp = 3000,
122 #endif
123 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
124         .temp_throttle = 85000,
125         .tc1 = 0,
126         .tc2 = 1,
127         .passive_delay = 2000,
128 #endif
129 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
130         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
131         .temp_throttle_skin = 43000,
132         .tc1_skin = 0,
133         .tc2_skin = 1,
134         .passive_delay_skin = 5000,
135
136         .skin_temp_offset = 9793,
137         .skin_period = 1100,
138         .skin_devs_size = 2,
139         .skin_devs = {
140                 {
141                         THERMAL_DEVICE_ID_NCT_EXT,
142                         {
143                                 2, 1, 1, 1,
144                                 1, 1, 1, 1,
145                                 1, 1, 1, 0,
146                                 1, 1, 0, 0,
147                                 0, 0, -1, -7
148                         }
149                 },
150                 {
151                         THERMAL_DEVICE_ID_NCT_INT,
152                         {
153                                 -11, -7, -5, -3,
154                                 -3, -2, -1, 0,
155                                 0, 0, 1, 1,
156                                 1, 2, 2, 3,
157                                 4, 6, 11, 18
158                         }
159                 },
160         },
161 #endif
162 };
163
164 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
165         {
166                 .name           = "bt_rfkill",
167                 .shutdown_gpio  = TEGRA_GPIO_PU0,
168                 .reset_gpio     = TEGRA_GPIO_INVALID,
169                 .type           = RFKILL_TYPE_BLUETOOTH,
170         },
171 };
172
173 static struct platform_device cardhu_bt_rfkill_device = {
174         .name = "rfkill_gpio",
175         .id             = -1,
176         .dev = {
177                 .platform_data = &cardhu_bt_rfkill_pdata,
178         },
179 };
180
181 static struct resource cardhu_bluesleep_resources[] = {
182         [0] = {
183                 .name = "gpio_host_wake",
184                         .start  = TEGRA_GPIO_PU6,
185                         .end    = TEGRA_GPIO_PU6,
186                         .flags  = IORESOURCE_IO,
187         },
188         [1] = {
189                 .name = "gpio_ext_wake",
190                         .start  = TEGRA_GPIO_PU1,
191                         .end    = TEGRA_GPIO_PU1,
192                         .flags  = IORESOURCE_IO,
193         },
194         [2] = {
195                 .name = "host_wake",
196                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
197                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
198                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
199         },
200 };
201
202 static struct platform_device cardhu_bluesleep_device = {
203         .name           = "bluesleep",
204         .id             = -1,
205         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
206         .resource       = cardhu_bluesleep_resources,
207 };
208
209 static noinline void __init cardhu_setup_bluesleep(void)
210 {
211         platform_device_register(&cardhu_bluesleep_device);
212         return;
213 }
214
215 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
216         /* name         parent          rate            enabled */
217         { "pll_m",      NULL,           0,              false},
218         { "hda",        "pll_p",        108000000,      false},
219         { "hda2codec_2x","pll_p",       48000000,       false},
220         { "pwm",        "pll_p",        3187500,        false},
221         { "blink",      "clk_32k",      32768,          true},
222         { "i2s0",       "pll_a_out0",   0,              false},
223         { "i2s1",       "pll_a_out0",   0,              false},
224         { "i2s3",       "pll_a_out0",   0,              false},
225         { "spdif_out",  "pll_a_out0",   0,              false},
226         { "d_audio",    "clk_m",        12000000,       false},
227         { "dam0",       "clk_m",        12000000,       false},
228         { "dam1",       "clk_m",        12000000,       false},
229         { "dam2",       "clk_m",        12000000,       false},
230         { "audio1",     "i2s1_sync",    0,              false},
231         { "audio3",     "i2s3_sync",    0,              false},
232         { "vi_sensor",  "pll_p",        150000000,      false},
233         { "i2c1",       "pll_p",        3200000,        false},
234         { "i2c2",       "pll_p",        3200000,        false},
235         { "i2c3",       "pll_p",        3200000,        false},
236         { "i2c4",       "pll_p",        3200000,        false},
237         { "i2c5",       "pll_p",        3200000,        false},
238         { "vi",         "pll_p",        0,              false},
239         { NULL,         NULL,           0,              0},
240 };
241
242 static struct pn544_i2c_platform_data nfc_pdata = {
243         .irq_gpio = TEGRA_GPIO_PX0,
244         .ven_gpio = TEGRA_GPIO_PP3,
245         .firm_gpio = TEGRA_GPIO_PO7,
246         };
247
248 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
249         {
250                 I2C_BOARD_INFO("pn544", 0x28),
251                 .platform_data = &nfc_pdata,
252                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
253         },
254 };
255 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
256         .adapter_nr     = 0,
257         .bus_count      = 1,
258         .bus_clk_rate   = { 100000, 0 },
259         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
260         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
261         .arb_recovery = arb_lost_recovery,
262 };
263
264 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
265         .adapter_nr     = 1,
266         .bus_count      = 1,
267         .bus_clk_rate   = { 400000, 0 },
268         .is_clkon_always = true,
269         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
270         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
271         .arb_recovery = arb_lost_recovery,
272 };
273
274 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
275         .adapter_nr     = 2,
276         .bus_count      = 1,
277         .bus_clk_rate   = { 100000, 0 },
278         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
279         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
280         .arb_recovery = arb_lost_recovery,
281 };
282
283 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
284         .adapter_nr     = 3,
285         .bus_count      = 1,
286         .bus_clk_rate   = { 10000, 0 },
287         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
288         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
289         .arb_recovery = arb_lost_recovery,
290 };
291
292 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
293         .adapter_nr     = 4,
294         .bus_count      = 1,
295         .bus_clk_rate   = { 400000, 0 },
296         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
297         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
298         .arb_recovery = arb_lost_recovery,
299 };
300
301
302 #if 0
303 struct tegra_wired_jack_conf audio_wr_jack_conf = {
304         .hp_det_n = TEGRA_GPIO_PW2,
305         .en_mic_ext = TEGRA_GPIO_PX1,
306         .en_mic_int = TEGRA_GPIO_PX0,
307 };
308 #endif
309
310 static struct wm8903_platform_data cardhu_wm8903_pdata = {
311         .irq_active_low = 0,
312         .micdet_cfg = 0,
313         .micdet_delay = 100,
314         .gpio_base = CARDHU_GPIO_WM8903(0),
315         .gpio_cfg = {
316                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
317                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
318                         WM8903_GP2_DIR,
319                 0,
320                 WM8903_GPIO_NO_CONFIG,
321                 WM8903_GPIO_NO_CONFIG,
322         },
323 };
324
325 /* Equalizer filter coefs generated from the MAXIM MAX98095
326  * evkit software tool */
327 static struct max98095_eq_cfg max98095_eq_cfg[] = {
328         {
329                 .name = "FLAT",
330                 .rate = 44100,
331                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
332                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
333                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
334                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
335                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
336         },
337         {
338                 .name = "LOWPASS1K",
339                 .rate = 44100,
340                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
341                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
342                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
343                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
344                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
345         },
346         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
347                 .name = "HIBOOST",
348                 .rate = 44100,
349                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
350                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
351                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
352                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
353                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
354         },
355         { /* BASS=12dB, TREBLE=+12dB */
356                 .name = "LOUD12DB",
357                 .rate = 44100,
358                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
359                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
360                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
361                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
362                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
363         },
364         {
365                 .name = "FLAT",
366                 .rate = 16000,
367                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
368                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
369                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
370                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
371                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
372         },
373         {
374                 .name = "LOWPASS1K",
375                 .rate = 16000,
376                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
377                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
378                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
379                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
380                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
381         },
382         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
383                 .name = "HIBOOST",
384                 .rate = 16000,
385                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
386                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
387                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
388                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
389                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
390         },
391         { /* BASS=12dB, TREBLE=+12dB */
392                 .name = "LOUD12DB",
393                 .rate = 16000,
394                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
395                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
396                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
397                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
398                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
399         },
400 };
401
402 static struct max98095_pdata cardhu_max98095_pdata = {
403         /* equalizer configuration */
404         .eq_cfg = max98095_eq_cfg,
405         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
406
407         /* Biquad filter response configuration */
408         .bq_cfg = NULL,
409         .bq_cfgcnt = 0,
410
411         /* microphone configuration */
412         .digmic_left_mode = 1,
413         .digmic_right_mode = 1,
414 };
415
416 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
417         I2C_BOARD_INFO("wm8903", 0x1a),
418         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
419         .platform_data = &cardhu_wm8903_pdata,
420 };
421
422 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
423         I2C_BOARD_INFO("aic3262-codec", 0x18),
424         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
425 };
426
427 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
428         I2C_BOARD_INFO("max98095", 0x10),
429         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
430         .platform_data = &cardhu_max98095_pdata,
431 };
432
433 static void cardhu_i2c_init(void)
434 {
435         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
436         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
437         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
438         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
439         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
440
441         platform_device_register(&tegra_i2c_device5);
442         platform_device_register(&tegra_i2c_device4);
443         platform_device_register(&tegra_i2c_device3);
444         platform_device_register(&tegra_i2c_device2);
445         platform_device_register(&tegra_i2c_device1);
446
447         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
448         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
449         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
450
451         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
452 }
453
454 static struct platform_device *cardhu_uart_devices[] __initdata = {
455         &tegra_uarta_device,
456         &tegra_uartb_device,
457         &tegra_uartc_device,
458         &tegra_uartd_device,
459         &tegra_uarte_device,
460 };
461 static struct uart_clk_parent uart_parent_clk[] = {
462         [0] = {.name = "clk_m"},
463         [1] = {.name = "pll_p"},
464 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
465         [2] = {.name = "pll_m"},
466 #endif
467 };
468
469 static struct tegra_uart_platform_data cardhu_uart_pdata;
470 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
471
472 static void __init uart_debug_init(void)
473 {
474         struct board_info board_info;
475         int debug_port_id;
476
477         tegra_get_board_info(&board_info);
478
479         debug_port_id = get_tegra_uart_debug_port_id();
480         if (debug_port_id < 0) {
481                 debug_port_id = 0;
482                         /* UARTB is debug port
483                          *       for SLT - E1186/E1187/PM269
484                          *       for E1256/E1257
485                          */
486                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
487                         ((board_info.board_id == BOARD_E1186) ||
488                         (board_info.board_id == BOARD_E1187) ||
489                         (board_info.board_id == BOARD_PM269))) ||
490                         (board_info.board_id == BOARD_E1256) ||
491                         (board_info.board_id == BOARD_E1257))
492                                 debug_port_id = 1;
493         }
494
495 #ifdef CONFIG_TEGRA_IRDA
496         if ((board_info.board_id == BOARD_E1186) ||
497                 (board_info.board_id == BOARD_E1198)) {
498                 if (debug_port_id == 1) {
499                         cardhu_irda_pdata.is_irda = false;
500                         pr_err("UARTB is not available for IrDA\n");
501                 }
502         }
503 #endif
504
505         switch (debug_port_id) {
506         case 0:
507                 /* UARTA is the debug port. */
508                 pr_info("Selecting UARTA as the debug console\n");
509                 cardhu_uart_devices[0] = &debug_uarta_device;
510                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
511                 debug_uart_port_base = ((struct plat_serial8250_port *)(
512                         debug_uarta_device.dev.platform_data))->mapbase;
513                 break;
514
515         case 1:
516                 /* UARTB is the debug port. */
517                 pr_info("Selecting UARTB as the debug console\n");
518                 cardhu_uart_devices[1] = &debug_uartb_device;
519                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
520                 debug_uart_port_base = ((struct plat_serial8250_port *)(
521                         debug_uartb_device.dev.platform_data))->mapbase;
522                 break;
523
524         case 2:
525                 /* UARTC is the debug port. */
526                 pr_info("Selecting UARTC as the debug console\n");
527                 cardhu_uart_devices[2] = &debug_uartc_device;
528                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
529                 debug_uart_port_base = ((struct plat_serial8250_port *)(
530                         debug_uartc_device.dev.platform_data))->mapbase;
531                 break;
532
533         case 3:
534                 /* UARTD is the debug port. */
535                 pr_info("Selecting UARTD as the debug console\n");
536                 cardhu_uart_devices[3] = &debug_uartd_device;
537                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
538                 debug_uart_port_base = ((struct plat_serial8250_port *)(
539                         debug_uartd_device.dev.platform_data))->mapbase;
540                 break;
541
542         case 4:
543                 /* UARTE is the debug port. */
544                 pr_info("Selecting UARTE as the debug console\n");
545                 cardhu_uart_devices[4] = &debug_uarte_device;
546                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
547                 debug_uart_port_base = ((struct plat_serial8250_port *)(
548                         debug_uarte_device.dev.platform_data))->mapbase;
549                 break;
550
551         default:
552                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
553                 cardhu_uart_devices[0] = &debug_uarta_device;
554                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
555                 debug_uart_port_base = ((struct plat_serial8250_port *)(
556                         debug_uarta_device.dev.platform_data))->mapbase;
557                 break;
558         }
559         return;
560 }
561
562 static void __init cardhu_uart_init(void)
563 {
564         struct clk *c;
565         int i;
566         struct board_info board_info;
567
568         tegra_get_board_info(&board_info);
569
570         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
571                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
572                 if (IS_ERR_OR_NULL(c)) {
573                         pr_err("Not able to get the clock for %s\n",
574                                                 uart_parent_clk[i].name);
575                         continue;
576                 }
577                 uart_parent_clk[i].parent_clk = c;
578                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
579         }
580         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
581         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
582         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
583         cardhu_loopback_uart_pdata.parent_clk_count =
584                                                 ARRAY_SIZE(uart_parent_clk);
585         cardhu_loopback_uart_pdata.is_loopback = true;
586         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
587         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
588         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
589         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
590         /* UARTE is used for loopback test purpose */
591         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
592
593         /* Register low speed only if it is selected */
594         if (!is_tegra_debug_uartport_hs()) {
595                 uart_debug_init();
596                 /* Clock enable for the debug channel */
597                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
598                         pr_info("The debug console clock name is %s\n",
599                                                 debug_uart_clk->name);
600                         c = tegra_get_clock_by_name("pll_p");
601                         if (IS_ERR_OR_NULL(c))
602                                 pr_err("Not getting the parent clock pll_p\n");
603                         else
604                                 clk_set_parent(debug_uart_clk, c);
605
606                         clk_enable(debug_uart_clk);
607                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
608                 } else {
609                         pr_err("Not getting the clock %s for debug console\n",
610                                         debug_uart_clk->name);
611                 }
612         }
613
614 #ifdef CONFIG_TEGRA_IRDA
615         if (((board_info.board_id == BOARD_E1186) ||
616                 (board_info.board_id == BOARD_E1198)) &&
617                         cardhu_irda_pdata.is_irda) {
618                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
619                 cardhu_irda_pdata.parent_clk_count =
620                                         ARRAY_SIZE(uart_parent_clk);
621
622                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
623         }
624 #endif
625
626         platform_add_devices(cardhu_uart_devices,
627                                 ARRAY_SIZE(cardhu_uart_devices));
628 }
629
630 static struct platform_device tegra_camera = {
631         .name = "tegra_camera",
632         .id = -1,
633 };
634
635 static struct platform_device *cardhu_spi_devices[] __initdata = {
636         &tegra_spi_device4,
637 };
638
639 static struct platform_device *touch_spi_device[] __initdata = {
640         &tegra_spi_device1,
641 };
642
643 struct spi_clk_parent spi_parent_clk[] = {
644         [0] = {.name = "pll_p"},
645 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
646         [1] = {.name = "pll_m"},
647         [2] = {.name = "clk_m"},
648 #else
649         [1] = {.name = "clk_m"},
650 #endif
651 };
652
653 static struct tegra_spi_platform_data cardhu_spi_pdata = {
654         .is_dma_based           = true,
655         .max_dma_buffer         = (16 * 1024),
656         .is_clkon_always        = false,
657         .max_rate               = 100000000,
658 };
659
660 static void __init cardhu_spi_init(void)
661 {
662         int i;
663         struct clk *c;
664         struct board_info board_info, display_board_info;
665
666         tegra_get_board_info(&board_info);
667         tegra_get_display_board_info(&display_board_info);
668
669         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
670                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
671                 if (IS_ERR_OR_NULL(c)) {
672                         pr_err("Not able to get the clock for %s\n",
673                                                 spi_parent_clk[i].name);
674                         continue;
675                 }
676                 spi_parent_clk[i].parent_clk = c;
677                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
678         }
679         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
680         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
681         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
682         platform_add_devices(cardhu_spi_devices,
683                                 ARRAY_SIZE(cardhu_spi_devices));
684
685         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
686                 platform_add_devices(touch_spi_device,
687                                 ARRAY_SIZE(touch_spi_device));
688         }
689         if (board_info.board_id == BOARD_E1198) {
690                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
691                 platform_device_register(&tegra_spi_device2);
692                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
693                 platform_device_register(&tegra_spi_slave_device1);
694         }
695 }
696
697 static void __init cardhu_dtv_init(void)
698 {
699         struct board_info board_info;
700
701         tegra_get_board_info(&board_info);
702
703         if (board_info.board_id == BOARD_E1186)
704                 platform_device_register(&tegra_dtv_device);
705 }
706
707 static struct resource tegra_rtc_resources[] = {
708         [0] = {
709                 .start = TEGRA_RTC_BASE,
710                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
711                 .flags = IORESOURCE_MEM,
712         },
713         [1] = {
714                 .start = INT_RTC,
715                 .end = INT_RTC,
716                 .flags = IORESOURCE_IRQ,
717         },
718 };
719
720 static struct platform_device tegra_rtc_device = {
721         .name = "tegra_rtc",
722         .id   = -1,
723         .resource = tegra_rtc_resources,
724         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
725 };
726
727 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
728         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
729         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
730         .gpio_hp_mute           = -1,
731         .gpio_int_mic_en        = -1,
732         .gpio_ext_mic_en        = -1,
733 };
734
735 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
736         .gpio_spkr_en           = -1,
737         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
738         .gpio_hp_mute           = -1,
739         .gpio_int_mic_en        = -1,
740         .gpio_ext_mic_en        = -1,
741 };
742
743 static struct platform_device cardhu_audio_wm8903_device = {
744         .name   = "tegra-snd-wm8903",
745         .id     = 0,
746         .dev    = {
747                 .platform_data = &cardhu_audio_wm8903_pdata,
748         },
749 };
750
751 static struct platform_device cardhu_audio_max98095_device = {
752         .name   = "tegra-snd-max98095",
753         .id     = 0,
754         .dev    = {
755                 .platform_data = &cardhu_audio_max98095_pdata,
756         },
757 };
758
759 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
760         .gpio_spkr_en           = -1,
761         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
762         .gpio_hp_mute           = -1,
763         .gpio_int_mic_en        = -1,
764         .gpio_ext_mic_en        = -1,
765         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
766         .audio_port_id          = {
767                 [HIFI_CODEC] = 0,
768                 [BASEBAND] = -1,
769                 [BT_SCO] = 3,
770         },
771         .baseband_param         = {
772                 .rate = -1,
773                 .channels = -1,
774         },
775 };
776
777 static struct platform_device cardhu_audio_aic326x_device = {
778         .name   = "tegra-snd-aic326x",
779         .id     = 0,
780         .dev    = {
781                 .platform_data  = &cardhu_audio_aic326x_pdata,
782         },
783 };
784
785 static struct platform_device *cardhu_devices[] __initdata = {
786         &tegra_pmu_device,
787         &tegra_rtc_device,
788         &tegra_udc_device,
789 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
790         &tegra_smmu_device,
791 #endif
792         &tegra_wdt0_device,
793         &tegra_wdt1_device,
794         &tegra_wdt2_device,
795 #if defined(CONFIG_TEGRA_AVP)
796         &tegra_avp_device,
797 #endif
798         &tegra_camera,
799 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
800         &tegra_se_device,
801 #endif
802         &tegra_ahub_device,
803         &tegra_dam_device0,
804         &tegra_dam_device1,
805         &tegra_dam_device2,
806         &tegra_i2s_device0,
807         &tegra_i2s_device1,
808         &tegra_i2s_device3,
809         &tegra_spdif_device,
810         &spdif_dit_device,
811         &bluetooth_dit_device,
812         &baseband_dit_device,
813         &cardhu_bt_rfkill_device,
814         &tegra_pcm_device,
815         &cardhu_audio_wm8903_device,
816         &cardhu_audio_max98095_device,
817         &cardhu_audio_aic326x_device,
818         &tegra_hda_device,
819         &tegra_cec_device,
820 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
821         &tegra_aes_device,
822 #endif
823 };
824
825 #define E1506_MXT_CONFIG_CRC 0x62F903
826 static const u8 e1506_config[] = {
827         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
829         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
830         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
831         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
832         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
833         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
835         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
836         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
837         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
839         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
840         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
843         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
844         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
845         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
846         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
847         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
848         0x00
849 };
850
851 #define MXT_CONFIG_CRC  0xD62DE8
852 static const u8 config[] = {
853         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
854         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
855         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
856         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
857         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
858         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
859         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
860         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
861         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
862         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
863         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
864         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
865         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
866         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
867         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
869         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
870         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
871         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
873 };
874
875 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
876 static const u8 config_sku2000[] = {
877         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
878         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
879         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
880         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
881         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
882         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
883         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
884         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
885         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
886         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
887         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
888         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
889         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
890         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
891         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
892         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
893         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
894         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
895         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
896         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
897 };
898
899 static struct mxt_platform_data atmel_mxt_info = {
900         .x_line         = 27,
901         .y_line         = 42,
902         .x_size         = 768,
903         .y_size         = 1366,
904         .blen           = 0x20,
905         .threshold      = 0x3C,
906         .voltage        = 3300000,              /* 3.3V */
907         .orient         = 5,
908         .config         = config,
909         .config_length  = 157,
910         .config_crc     = MXT_CONFIG_CRC,
911         .irqflags       = IRQF_TRIGGER_FALLING,
912 /*      .read_chg       = &read_chg, */
913         .read_chg       = NULL,
914 };
915
916 static struct mxt_platform_data e1506_atmel_mxt_info = {
917         .x_line         = 19,
918         .y_line         = 11,
919         .x_size         = 960,
920         .y_size         = 540,
921         .blen           = 0x10,
922         .threshold      = 0x32,
923         .voltage        = 3300000,              /* 3.3V */
924         .orient         = 3,
925         .config         = e1506_config,
926         .config_length  = 168,
927         .config_crc     = E1506_MXT_CONFIG_CRC,
928         .irqflags       = IRQF_TRIGGER_FALLING,
929 /*      .read_chg       = &read_chg, */
930         .read_chg       = NULL,
931 };
932
933 static struct i2c_board_info __initdata atmel_i2c_info[] = {
934         {
935                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
936                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
937                 .platform_data = &atmel_mxt_info,
938         }
939 };
940
941 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
942         {
943                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
944                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
945                 .platform_data = &e1506_atmel_mxt_info,
946         }
947 };
948
949 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
950         /* name         parent          rate            enabled */
951         { "sbc1",       "pll_p",        52000000,       true},
952         { NULL,         NULL,           0,              0},
953 };
954
955 static int __init cardhu_touch_init(void)
956 {
957         struct board_info BoardInfo, DisplayBoardInfo;
958
959         tegra_get_board_info(&BoardInfo);
960         tegra_get_display_board_info(&DisplayBoardInfo);
961         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
962                 tegra_clk_init_from_table(spi_clk_init_table);
963
964                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
965         } else {
966                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
967                 gpio_direction_input(TEGRA_GPIO_PH4);
968
969                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
970                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
971                 msleep(1);
972                 gpio_set_value(TEGRA_GPIO_PH6, 1);
973                 msleep(100);
974
975                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
976                         atmel_mxt_info.config = config_sku2000;
977                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
978                 }
979
980                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506)
981                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
982                 else
983                         i2c_register_board_info(1, atmel_i2c_info, 1);
984         }
985
986         return 0;
987 }
988
989 #if defined(CONFIG_USB_SUPPORT)
990
991 static void cardu_usb_hsic_postsupend(void)
992 {
993 #ifdef CONFIG_TEGRA_BB_XMM_POWER
994         baseband_xmm_set_power_status(BBXMM_PS_L2);
995 #endif
996 }
997
998 static void cardu_usb_hsic_preresume(void)
999 {
1000 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1001         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1002 #endif
1003 }
1004
1005 static void cardu_usb_hsic_phy_ready(void)
1006 {
1007 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1008         baseband_xmm_set_power_status(BBXMM_PS_L0);
1009 #endif
1010 }
1011
1012 static void cardu_usb_hsic_phy_off(void)
1013 {
1014 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1015         baseband_xmm_set_power_status(BBXMM_PS_L3);
1016 #endif
1017 }
1018
1019 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1020         .post_suspend = cardu_usb_hsic_postsupend,
1021         .pre_resume = cardu_usb_hsic_preresume,
1022         .port_power = cardu_usb_hsic_phy_ready,
1023         .post_phy_off = cardu_usb_hsic_phy_off,
1024 };
1025
1026 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1027         .port_otg = false,
1028         .has_hostpc = true,
1029         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1030         .op_mode        = TEGRA_USB_OPMODE_HOST,
1031         .u_data.host = {
1032                 .vbus_gpio = -1,
1033                 .hot_plug = false,
1034                 .remote_wakeup_supported = false,
1035                 .power_off_on_suspend = false,
1036         },
1037         .u_cfg.hsic = {
1038                 .sync_start_delay = 9,
1039                 .idle_wait_delay = 17,
1040                 .term_range_adj = 0,
1041                 .elastic_underrun_limit = 16,
1042                 .elastic_overrun_limit = 16,
1043         },
1044         .ops = &hsic_xmm_plat_ops,
1045 };
1046 #endif
1047
1048 static int hsic_enable_gpio = -1;
1049 static int hsic_reset_gpio = -1;
1050
1051 void hsic_platform_open(void)
1052 {
1053         int reset_gpio = 0, enable_gpio = 0;
1054
1055         if (hsic_enable_gpio != -1)
1056                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1057         if (hsic_reset_gpio != -1)
1058                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1059         /* hsic enable signal deasserted, hsic reset asserted */
1060         if (!enable_gpio)
1061                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1062         if (!reset_gpio)
1063                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1064         if (!enable_gpio)
1065                 tegra_gpio_enable(hsic_enable_gpio);
1066         if (!reset_gpio)
1067                 tegra_gpio_enable(hsic_reset_gpio);
1068         /* keep hsic reset asserted for 1 ms */
1069         udelay(1000);
1070         /* enable (power on) hsic */
1071         if (!enable_gpio)
1072                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1073         udelay(1000);
1074         /* deassert reset */
1075         if (!reset_gpio)
1076                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1077
1078 }
1079
1080 void hsic_platform_close(void)
1081 {
1082         if (hsic_enable_gpio != -1) {
1083                 gpio_set_value(hsic_enable_gpio, 0);
1084                 gpio_free(hsic_enable_gpio);
1085         }
1086         if (hsic_reset_gpio != -1) {
1087                 gpio_set_value(hsic_reset_gpio, 0);
1088                 gpio_free(hsic_reset_gpio);
1089         }
1090 }
1091
1092 void hsic_power_on(void)
1093 {
1094         if (hsic_enable_gpio != -1) {
1095                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1096                 udelay(1000);
1097         }
1098 }
1099
1100 void hsic_power_off(void)
1101 {
1102         if (hsic_enable_gpio != -1) {
1103                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1104                 udelay(1000);
1105         }
1106 }
1107
1108 #if defined(CONFIG_USB_SUPPORT)
1109 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1110         .open = hsic_platform_open,
1111         .close = hsic_platform_close,
1112         .pre_phy_on = hsic_power_on,
1113         .post_phy_off = hsic_power_off,
1114 };
1115
1116 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1117         .port_otg = false,
1118         .has_hostpc = true,
1119         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1120         .op_mode        = TEGRA_USB_OPMODE_HOST,
1121         .u_data.host = {
1122                 .vbus_gpio = -1,
1123                 .hot_plug = false,
1124                 .remote_wakeup_supported = false,
1125                 .power_off_on_suspend = false,
1126         },
1127         .u_cfg.hsic = {
1128                 .sync_start_delay = 9,
1129                 .idle_wait_delay = 17,
1130                 .term_range_adj = 0,
1131                 .elastic_underrun_limit = 16,
1132                 .elastic_overrun_limit = 16,
1133         },
1134         .ops = &hsic_plat_ops,
1135 };
1136
1137 static struct tegra_usb_platform_data tegra_udc_pdata = {
1138         .port_otg = true,
1139         .has_hostpc = true,
1140         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1141         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1142         .u_data.dev = {
1143                 .vbus_pmu_irq = 0,
1144                 .vbus_gpio = -1,
1145                 .charging_supported = false,
1146                 .remote_wakeup_supported = false,
1147         },
1148         .u_cfg.utmi = {
1149                 .hssync_start_delay = 0,
1150                 .elastic_limit = 16,
1151                 .idle_wait_delay = 17,
1152                 .term_range_adj = 6,
1153                 .xcvr_setup = 8,
1154                 .xcvr_lsfslew = 2,
1155                 .xcvr_lsrslew = 2,
1156                 .xcvr_setup_offset = 0,
1157                 .xcvr_use_fuses = 1,
1158         },
1159 };
1160
1161 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1162         .port_otg = false,
1163         .has_hostpc = true,
1164         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1165         .op_mode        = TEGRA_USB_OPMODE_HOST,
1166         .u_data.host = {
1167                 .vbus_gpio = -1,
1168                 .hot_plug = false,
1169                 .remote_wakeup_supported = true,
1170                 .power_off_on_suspend = true,
1171         },
1172         .u_cfg.utmi = {
1173                 .hssync_start_delay = 0,
1174                 .elastic_limit = 16,
1175                 .idle_wait_delay = 17,
1176                 .term_range_adj = 6,
1177                 .xcvr_setup = 15,
1178                 .xcvr_lsfslew = 2,
1179                 .xcvr_lsrslew = 2,
1180                 .xcvr_setup_offset = 0,
1181                 .xcvr_use_fuses = 1,
1182         },
1183 };
1184
1185 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1186         .port_otg = false,
1187         .has_hostpc = true,
1188         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1189         .op_mode = TEGRA_USB_OPMODE_HOST,
1190         .u_data.host = {
1191                 .vbus_gpio = -1,
1192                 .vbus_reg = "vdd_vbus_typea_usb",
1193                 .hot_plug = true,
1194                 .remote_wakeup_supported = true,
1195                 .power_off_on_suspend = true,
1196         },
1197         .u_cfg.utmi = {
1198                 .hssync_start_delay = 0,
1199                 .elastic_limit = 16,
1200                 .idle_wait_delay = 17,
1201                 .term_range_adj = 6,
1202                 .xcvr_setup = 8,
1203                 .xcvr_lsfslew = 2,
1204                 .xcvr_lsrslew = 2,
1205                 .xcvr_setup_offset = 0,
1206                 .xcvr_use_fuses = 1,
1207         },
1208 };
1209
1210 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1211         .port_otg = true,
1212         .has_hostpc = true,
1213         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1214         .op_mode = TEGRA_USB_OPMODE_HOST,
1215         .u_data.host = {
1216                 .vbus_gpio = -1,
1217                 .vbus_reg = "vdd_vbus_micro_usb",
1218                 .hot_plug = true,
1219                 .remote_wakeup_supported = true,
1220                 .power_off_on_suspend = true,
1221         },
1222         .u_cfg.utmi = {
1223                 .hssync_start_delay = 0,
1224                 .elastic_limit = 16,
1225                 .idle_wait_delay = 17,
1226                 .term_range_adj = 6,
1227                 .xcvr_setup = 15,
1228                 .xcvr_lsfslew = 2,
1229                 .xcvr_lsrslew = 2,
1230                 .xcvr_setup_offset = 0,
1231                 .xcvr_use_fuses = 1,
1232         },
1233 };
1234
1235 static struct tegra_usb_otg_data tegra_otg_pdata = {
1236         .ehci_device = &tegra_ehci1_device,
1237         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1238 };
1239 #endif
1240
1241 #if defined(CONFIG_USB_SUPPORT)
1242 static void cardhu_usb_init(void)
1243 {
1244         struct board_info bi;
1245
1246         tegra_get_board_info(&bi);
1247
1248         /* OTG should be the first to be registered */
1249         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1250         platform_device_register(&tegra_otg_device);
1251
1252         /* setup the udc platform data */
1253         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1254
1255         if (bi.board_id == BOARD_PM267) {
1256                 hsic_enable_gpio = EN_HSIC_GPIO;
1257                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1258                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1259                 platform_device_register(&tegra_ehci2_device);
1260         } else if (bi.board_id == BOARD_E1256) {
1261                 hsic_enable_gpio = EN_HSIC_GPIO;
1262                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1263                 platform_device_register(&tegra_ehci2_device);
1264         } else if (bi.board_id == BOARD_E1186) {
1265                 tegra_ehci2_device.dev.platform_data =
1266                                                 &tegra_ehci2_hsic_xmm_pdata;
1267                 /* ehci2 registration happens in baseband-xmm-power  */
1268         } else {
1269                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1270                 platform_device_register(&tegra_ehci2_device);
1271         }
1272
1273         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1274         platform_device_register(&tegra_ehci3_device);
1275
1276 }
1277 #else
1278 static void cardhu_usb_init(void) { }
1279 #endif
1280
1281 static struct baseband_power_platform_data tegra_baseband_power_data = {
1282         .baseband_type = BASEBAND_XMM,
1283         .modem = {
1284         .xmm = {
1285                         .bb_rst = XMM_GPIO_BB_RST,
1286                         .bb_on = XMM_GPIO_BB_ON,
1287                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1288                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1289                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1290                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1291                         .hsic_device = &tegra_ehci2_device,
1292                 },
1293         },
1294 };
1295
1296 static struct platform_device tegra_baseband_power_device = {
1297         .name = "baseband_xmm_power",
1298         .id = -1,
1299         .dev = {
1300                 .platform_data = &tegra_baseband_power_data,
1301         },
1302 };
1303
1304 static struct platform_device tegra_baseband_power2_device = {
1305         .name = "baseband_xmm_power2",
1306         .id = -1,
1307         .dev = {
1308                 .platform_data = &tegra_baseband_power_data,
1309         },
1310 };
1311
1312
1313 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1314         .port_status[0] = 1,
1315         .port_status[1] = 1,
1316         .port_status[2] = 1,
1317         .use_dock_detect        = 0,
1318         .gpio           = 0,
1319 };
1320
1321 static void cardhu_pci_init(void)
1322 {
1323         struct board_info board_info;
1324
1325         tegra_get_board_info(&board_info);
1326         if (board_info.board_id == BOARD_E1291) {
1327                 cardhu_pci_platform_data.port_status[0] = 0;
1328                 cardhu_pci_platform_data.port_status[1] = 0;
1329                 cardhu_pci_platform_data.port_status[2] = 1;
1330                 cardhu_pci_platform_data.use_dock_detect = 1;
1331                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1332         }
1333         if ((board_info.board_id == BOARD_E1186) ||
1334                 (board_info.board_id == BOARD_E1187) ||
1335                 (board_info.board_id == BOARD_E1291)) {
1336                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1337                 platform_device_register(&tegra_pci_device);
1338         }
1339 }
1340
1341 static void cardhu_modem_init(void)
1342 {
1343         struct board_info board_info;
1344         int w_disable_gpio, ret;
1345
1346         tegra_get_board_info(&board_info);
1347         switch (board_info.board_id) {
1348         case BOARD_E1291:
1349         case BOARD_E1198:
1350                 if (((board_info.board_id == BOARD_E1291) &&
1351                                 (board_info.fab < BOARD_FAB_A03)) ||
1352                         ((board_info.board_id == BOARD_E1198) &&
1353                                         (board_info.fab < BOARD_FAB_A02))) {
1354                         w_disable_gpio = TEGRA_GPIO_PH5;
1355                 } else {
1356                         w_disable_gpio = TEGRA_GPIO_PDD5;
1357                 }
1358
1359                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1360                 if (ret < 0)
1361                         pr_err("%s: gpio_request failed for gpio %d\n",
1362                                 __func__, w_disable_gpio);
1363                 else
1364                         gpio_direction_input(w_disable_gpio);
1365
1366                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1367                 if (((board_info.board_id == BOARD_E1291) &&
1368                                 (board_info.fab >= BOARD_FAB_A04)) ||
1369                         ((board_info.board_id == BOARD_E1198) &&
1370                                         (board_info.fab >= BOARD_FAB_A02))) {
1371                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1372                         if (ret < 0) {
1373                                 pr_err("%s(): Error in allocating gpio "
1374                                         "TEGRA_GPIO_PH7\n", __func__);
1375                                 break;
1376                         }
1377                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1378                 }
1379                 break;
1380         case BOARD_E1186:
1381                 platform_device_register(&tegra_baseband_power_device);
1382                 platform_device_register(&tegra_baseband_power2_device);
1383                 break;
1384         default:
1385                 break;
1386         }
1387
1388 }
1389
1390 #ifdef CONFIG_SATA_AHCI_TEGRA
1391 static void cardhu_sata_init(void)
1392 {
1393         platform_device_register(&tegra_sata_device);
1394 }
1395 #else
1396 static void cardhu_sata_init(void) { }
1397 #endif
1398
1399 static void __init tegra_cardhu_init(void)
1400 {
1401         tegra_thermal_init(&thermal_data,
1402                                 throttle_list,
1403                                 ARRAY_SIZE(throttle_list));
1404         tegra_clk_init_from_table(cardhu_clk_init_table);
1405         cardhu_pinmux_init();
1406         cardhu_i2c_init();
1407         cardhu_spi_init();
1408         cardhu_usb_init();
1409 #ifdef CONFIG_TEGRA_EDP_LIMITS
1410         cardhu_edp_init();
1411 #endif
1412         cardhu_uart_init();
1413         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1414         tegra_ram_console_debug_init();
1415         tegra_io_dpd_init();
1416         cardhu_sdhci_init();
1417         cardhu_regulator_init();
1418         cardhu_dtv_init();
1419         cardhu_suspend_init();
1420         cardhu_touch_init();
1421         cardhu_modem_init();
1422         cardhu_kbc_init();
1423         cardhu_scroll_init();
1424         cardhu_keys_init();
1425         cardhu_panel_init();
1426         cardhu_pmon_init();
1427         cardhu_sensors_init();
1428         cardhu_setup_bluesleep();
1429         cardhu_sata_init();
1430         //audio_wired_jack_init();
1431         cardhu_pins_state_init();
1432         cardhu_emc_init();
1433         tegra_release_bootloader_fb();
1434         cardhu_pci_init();
1435 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1436         tegra_wdt_recovery_init();
1437 #endif
1438         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1439 }
1440
1441 static void __init tegra_cardhu_reserve(void)
1442 {
1443 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1444         /* support 1920X1200 with 24bpp */
1445         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1446 #else
1447         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1448 #endif
1449         tegra_ram_console_debug_reserve(SZ_1M);
1450 }
1451
1452 MACHINE_START(CARDHU, "cardhu")
1453         .boot_params    = 0x80000100,
1454         .map_io         = tegra_map_common_io,
1455         .reserve        = tegra_cardhu_reserve,
1456         .init_early     = tegra_init_early,
1457         .init_irq       = tegra_init_irq,
1458         .timer          = &tegra_timer,
1459         .init_machine   = tegra_cardhu_init,
1460 MACHINE_END