Tegra: Cardhu: Added dtv device to cardhu board
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41
42 #include <sound/wm8903.h>
43 #include <media/tegra_dtv.h>
44
45 #include <mach/clk.h>
46 #include <mach/iomap.h>
47 #include <mach/irqs.h>
48 #include <mach/pinmux.h>
49 #include <mach/iomap.h>
50 #include <mach/io.h>
51 #include <mach/i2s.h>
52 #include <mach/tegra_wm8903_pdata.h>
53 #include <asm/mach-types.h>
54 #include <asm/mach/arch.h>
55 #include <mach/usb_phy.h>
56 #include <mach/thermal.h>
57 #include <mach/pci.h>
58
59 #include "board.h"
60 #include "clock.h"
61 #include "board-cardhu.h"
62 #include "devices.h"
63 #include "gpio-names.h"
64 #include "fuse.h"
65 #include "pm.h"
66 #include "baseband-xmm-power.h"
67 #include "wdt-recovery.h"
68
69 /* All units are in millicelsius */
70 static struct tegra_thermal_data thermal_data = {
71         .temp_throttle = 85000,
72         .temp_shutdown = 90000,
73         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
74 #ifdef CONFIG_TEGRA_EDP_LIMITS
75         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
76         .hysteresis_edp = 3000,
77 #endif
78 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
79         .tc1 = 0,
80         .tc2 = 1,
81         .passive_delay = 2000,
82 #else
83         .hysteresis_throttle = 1000,
84 #endif
85 };
86
87 /* !!!TODO: Change for cardhu (Taken from Ventana) */
88 static struct tegra_utmip_config utmi_phy_config[] = {
89         [0] = {
90                         .hssync_start_delay = 0,
91                         .idle_wait_delay = 17,
92                         .elastic_limit = 16,
93                         .term_range_adj = 6,
94                         .xcvr_setup = 15,
95                         .xcvr_setup_offset = 0,
96                         .xcvr_use_fuses = 1,
97                         .xcvr_lsfslew = 2,
98                         .xcvr_lsrslew = 2,
99         },
100         [1] = {
101                         .hssync_start_delay = 0,
102                         .idle_wait_delay = 17,
103                         .elastic_limit = 16,
104                         .term_range_adj = 6,
105                         .xcvr_setup = 15,
106                         .xcvr_setup_offset = 0,
107                         .xcvr_use_fuses = 1,
108                         .xcvr_lsfslew = 2,
109                         .xcvr_lsrslew = 2,
110         },
111         [2] = {
112                         .hssync_start_delay = 0,
113                         .idle_wait_delay = 17,
114                         .elastic_limit = 16,
115                         .term_range_adj = 6,
116                         .xcvr_setup = 8,
117                         .xcvr_setup_offset = 0,
118                         .xcvr_use_fuses = 1,
119                         .xcvr_lsfslew = 2,
120                         .xcvr_lsrslew = 2,
121         },
122 };
123
124 #ifdef CONFIG_BCM4329_RFKILL
125 static struct resource cardhu_bcm4329_rfkill_resources[] = {
126         {
127                 .name   = "bcm4329_nshutdown_gpio",
128                 .start  = TEGRA_GPIO_PU0,
129                 .end    = TEGRA_GPIO_PU0,
130                 .flags  = IORESOURCE_IO,
131         },
132 };
133
134 static struct platform_device cardhu_bcm4329_rfkill_device = {
135         .name = "bcm4329_rfkill",
136         .id             = -1,
137         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
138         .resource       = cardhu_bcm4329_rfkill_resources,
139 };
140
141 static noinline void __init cardhu_bt_rfkill(void)
142 {
143         platform_device_register(&cardhu_bcm4329_rfkill_device);
144
145         return;
146 }
147 #else
148 static inline void cardhu_bt_rfkill(void) { }
149 #endif
150
151 #ifdef CONFIG_BT_BLUESLEEP
152 static noinline void __init tegra_setup_bluesleep(void)
153 {
154         struct platform_device *pdev = NULL;
155         struct resource *res;
156
157         pdev = platform_device_alloc("bluesleep", 0);
158         if (!pdev) {
159                 pr_err("unable to allocate platform device for bluesleep");
160                 return;
161         }
162
163         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
164         if (!res) {
165                 pr_err("unable to allocate resource for bluesleep\n");
166                 goto err_free_dev;
167         }
168
169         res[0].name   = "gpio_host_wake";
170         res[0].start  = TEGRA_GPIO_PU6;
171         res[0].end    = TEGRA_GPIO_PU6;
172         res[0].flags  = IORESOURCE_IO;
173
174         res[1].name   = "gpio_ext_wake";
175         res[1].start  = TEGRA_GPIO_PU1;
176         res[1].end    = TEGRA_GPIO_PU1;
177         res[1].flags  = IORESOURCE_IO;
178
179         res[2].name   = "host_wake";
180         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
181         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
182         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
183
184         if (platform_device_add_resources(pdev, res, 3)) {
185                 pr_err("unable to add resources to bluesleep device\n");
186                 goto err_free_res;
187         }
188
189         if (platform_device_add(pdev)) {
190                 pr_err("unable to add bluesleep device\n");
191                 goto err_free_res;
192         }
193         tegra_gpio_enable(TEGRA_GPIO_PU6);
194         tegra_gpio_enable(TEGRA_GPIO_PU1);
195
196 return;
197
198 err_free_res:
199         kfree(res);
200 err_free_dev:
201         platform_device_put(pdev);
202         return;
203 }
204 #else
205 static inline void tegra_setup_bluesleep(void) { }
206 #endif
207
208 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
209         /* name         parent          rate            enabled */
210         { "pll_m",      NULL,           0,              false},
211         { "hda",        "pll_p",        108000000,      false},
212         { "hda2codec_2x","pll_p",       48000000,       false},
213         { "pwm",        "pll_p",        3187500,        false},
214         { "blink",      "clk_32k",      32768,          true},
215         { "i2s1",       "pll_a_out0",   0,              false},
216         { "i2s3",       "pll_a_out0",   0,              false},
217         { "spdif_out",  "pll_a_out0",   0,              false},
218         { "d_audio",    "pll_a_out0",   0,              false},
219         { "dam0",       "pll_a_out0",   0,              false},
220         { "dam1",       "pll_a_out0",   0,              false},
221         { "dam2",       "pll_a_out0",   0,              false},
222         { "audio1",     "i2s1_sync",    0,              false},
223         { "audio3",     "i2s3_sync",    0,              false},
224         { "vi_sensor",  "pll_p",        150000000,      false},
225         { "i2c1",       "pll_p",        3200000,        false},
226         { "i2c2",       "pll_p",        3200000,        false},
227         { "i2c3",       "pll_p",        3200000,        false},
228         { "i2c4",       "pll_p",        3200000,        false},
229         { "i2c5",       "pll_p",        3200000,        false},
230         { NULL,         NULL,           0,              0},
231 };
232
233 static struct pn544_i2c_platform_data nfc_pdata = {
234         .irq_gpio = TEGRA_GPIO_PX0,
235         .ven_gpio = TEGRA_GPIO_PP3,
236         .firm_gpio = TEGRA_GPIO_PO7,
237         };
238
239 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
240         {
241                 I2C_BOARD_INFO("pn544", 0x28),
242                 .platform_data = &nfc_pdata,
243                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
244         },
245 };
246 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
247         .adapter_nr     = 0,
248         .bus_count      = 1,
249         .bus_clk_rate   = { 100000, 0 },
250         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
251         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
252         .arb_recovery = arb_lost_recovery,
253 };
254
255 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
256         .adapter_nr     = 1,
257         .bus_count      = 1,
258         .bus_clk_rate   = { 100000, 0 },
259         .is_clkon_always = true,
260         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
261         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
262         .arb_recovery = arb_lost_recovery,
263 };
264
265 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
266         .adapter_nr     = 2,
267         .bus_count      = 1,
268         .bus_clk_rate   = { 100000, 0 },
269         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
270         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
271         .arb_recovery = arb_lost_recovery,
272 };
273
274 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
275         .adapter_nr     = 3,
276         .bus_count      = 1,
277         .bus_clk_rate   = { 100000, 0 },
278         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
279         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
280         .arb_recovery = arb_lost_recovery,
281 };
282
283 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
284         .adapter_nr     = 4,
285         .bus_count      = 1,
286         .bus_clk_rate   = { 400000, 0 },
287         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
288         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
289         .arb_recovery = arb_lost_recovery,
290 };
291
292
293 #if 0
294 struct tegra_wired_jack_conf audio_wr_jack_conf = {
295         .hp_det_n = TEGRA_GPIO_PW2,
296         .en_mic_ext = TEGRA_GPIO_PX1,
297         .en_mic_int = TEGRA_GPIO_PX0,
298 };
299 #endif
300
301 static struct wm8903_platform_data cardhu_wm8903_pdata = {
302         .irq_active_low = 0,
303         .micdet_cfg = 0,
304         .micdet_delay = 100,
305         .gpio_base = CARDHU_GPIO_WM8903(0),
306         .gpio_cfg = {
307                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
308                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
309                         WM8903_GP2_DIR,
310                 0,
311                 WM8903_GPIO_NO_CONFIG,
312                 WM8903_GPIO_NO_CONFIG,
313         },
314 };
315
316 static struct i2c_board_info __initdata wm8903_board_info = {
317         I2C_BOARD_INFO("wm8903", 0x1a),
318         .platform_data = &cardhu_wm8903_pdata,
319         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
320 };
321
322 static void cardhu_i2c_init(void)
323 {
324         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
325         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
326         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
327         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
328         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
329
330         platform_device_register(&tegra_i2c_device5);
331         platform_device_register(&tegra_i2c_device4);
332         platform_device_register(&tegra_i2c_device3);
333         platform_device_register(&tegra_i2c_device2);
334         platform_device_register(&tegra_i2c_device1);
335
336         i2c_register_board_info(4, &wm8903_board_info, 1);
337         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
338 }
339
340 static struct platform_device *cardhu_uart_devices[] __initdata = {
341         &tegra_uarta_device,
342         &tegra_uartb_device,
343         &tegra_uartc_device,
344         &tegra_uartd_device,
345         &tegra_uarte_device,
346 };
347 static struct uart_clk_parent uart_parent_clk[] = {
348         [0] = {.name = "clk_m"},
349         [1] = {.name = "pll_p"},
350 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
351         [2] = {.name = "pll_m"},
352 #endif
353 };
354
355 static struct tegra_uart_platform_data cardhu_uart_pdata;
356 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
357
358 static void __init uart_debug_init(void)
359 {
360         struct board_info board_info;
361         int debug_port_id;
362
363         tegra_get_board_info(&board_info);
364
365         debug_port_id = get_tegra_uart_debug_port_id();
366         if (debug_port_id < 0) {
367                 debug_port_id = 0;
368                         /* UARTB is debug port
369                          *       for SLT - E1186/E1187/PM269
370                          *       for E1256/E1257
371                          */
372                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
373                         ((board_info.board_id == BOARD_E1186) ||
374                         (board_info.board_id == BOARD_E1187) ||
375                         (board_info.board_id == BOARD_PM269))) ||
376                         (board_info.board_id == BOARD_E1256) ||
377                         (board_info.board_id == BOARD_E1257))
378                                 debug_port_id = 1;
379         }
380         switch (debug_port_id) {
381         case 0:
382                 /* UARTA is the debug port. */
383                 pr_info("Selecting UARTA as the debug console\n");
384                 cardhu_uart_devices[0] = &debug_uarta_device;
385                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
386                 debug_uart_port_base = ((struct plat_serial8250_port *)(
387                         debug_uarta_device.dev.platform_data))->mapbase;
388                 break;
389
390         case 1:
391                 /* UARTB is the debug port. */
392                 pr_info("Selecting UARTB as the debug console\n");
393                 cardhu_uart_devices[1] = &debug_uartb_device;
394                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
395                 debug_uart_port_base = ((struct plat_serial8250_port *)(
396                         debug_uartb_device.dev.platform_data))->mapbase;
397                 break;
398
399         case 2:
400                 /* UARTC is the debug port. */
401                 pr_info("Selecting UARTC as the debug console\n");
402                 cardhu_uart_devices[2] = &debug_uartc_device;
403                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
404                 debug_uart_port_base = ((struct plat_serial8250_port *)(
405                         debug_uartc_device.dev.platform_data))->mapbase;
406                 break;
407
408         case 3:
409                 /* UARTD is the debug port. */
410                 pr_info("Selecting UARTD as the debug console\n");
411                 cardhu_uart_devices[3] = &debug_uartd_device;
412                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
413                 debug_uart_port_base = ((struct plat_serial8250_port *)(
414                         debug_uartd_device.dev.platform_data))->mapbase;
415                 break;
416
417         case 4:
418                 /* UARTE is the debug port. */
419                 pr_info("Selecting UARTE as the debug console\n");
420                 cardhu_uart_devices[4] = &debug_uarte_device;
421                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
422                 debug_uart_port_base = ((struct plat_serial8250_port *)(
423                         debug_uarte_device.dev.platform_data))->mapbase;
424                 break;
425
426         default:
427                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
428                 cardhu_uart_devices[0] = &debug_uarta_device;
429                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
430                 debug_uart_port_base = ((struct plat_serial8250_port *)(
431                         debug_uarta_device.dev.platform_data))->mapbase;
432                 break;
433         }
434         return;
435 }
436
437 static void __init cardhu_uart_init(void)
438 {
439         struct clk *c;
440         int i;
441
442         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
443                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
444                 if (IS_ERR_OR_NULL(c)) {
445                         pr_err("Not able to get the clock for %s\n",
446                                                 uart_parent_clk[i].name);
447                         continue;
448                 }
449                 uart_parent_clk[i].parent_clk = c;
450                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
451         }
452         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
453         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
454         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
455         cardhu_loopback_uart_pdata.parent_clk_count =
456                                                 ARRAY_SIZE(uart_parent_clk);
457         cardhu_loopback_uart_pdata.is_loopback = true;
458         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
459         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
460         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
461         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
462         /* UARTE is used for loopback test purpose */
463         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
464
465         /* Register low speed only if it is selected */
466         if (!is_tegra_debug_uartport_hs()) {
467                 uart_debug_init();
468                 /* Clock enable for the debug channel */
469                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
470                         pr_info("The debug console clock name is %s\n",
471                                                 debug_uart_clk->name);
472                         c = tegra_get_clock_by_name("pll_p");
473                         if (IS_ERR_OR_NULL(c))
474                                 pr_err("Not getting the parent clock pll_p\n");
475                         else
476                                 clk_set_parent(debug_uart_clk, c);
477
478                         clk_enable(debug_uart_clk);
479                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
480                 } else {
481                         pr_err("Not getting the clock %s for debug console\n",
482                                         debug_uart_clk->name);
483                 }
484         }
485
486         platform_add_devices(cardhu_uart_devices,
487                                 ARRAY_SIZE(cardhu_uart_devices));
488 }
489
490 static struct platform_device tegra_camera = {
491         .name = "tegra_camera",
492         .id = -1,
493 };
494
495 static struct platform_device *cardhu_spi_devices[] __initdata = {
496         &tegra_spi_device4,
497 };
498
499 struct spi_clk_parent spi_parent_clk[] = {
500         [0] = {.name = "pll_p"},
501 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
502         [1] = {.name = "pll_m"},
503         [2] = {.name = "clk_m"},
504 #else
505         [1] = {.name = "clk_m"},
506 #endif
507 };
508
509 static struct tegra_spi_platform_data cardhu_spi_pdata = {
510         .is_dma_based           = true,
511         .max_dma_buffer         = (16 * 1024),
512         .is_clkon_always        = false,
513         .max_rate               = 100000000,
514 };
515
516 static void __init cardhu_spi_init(void)
517 {
518         int i;
519         struct clk *c;
520         struct board_info board_info;
521
522         tegra_get_board_info(&board_info);
523
524         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
525                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
526                 if (IS_ERR_OR_NULL(c)) {
527                         pr_err("Not able to get the clock for %s\n",
528                                                 spi_parent_clk[i].name);
529                         continue;
530                 }
531                 spi_parent_clk[i].parent_clk = c;
532                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
533         }
534         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
535         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
536         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
537         platform_add_devices(cardhu_spi_devices,
538                                 ARRAY_SIZE(cardhu_spi_devices));
539
540         if (board_info.board_id == BOARD_E1198) {
541                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
542                 platform_device_register(&tegra_spi_device2);
543                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
544                 platform_device_register(&tegra_spi_slave_device1);
545         }
546 }
547
548 static void __init cardhu_dtv_init(void)
549 {
550         struct board_info board_info;
551
552         tegra_get_board_info(&board_info);
553
554         if (board_info.board_id == BOARD_E1186)
555                 platform_device_register(&tegra_dtv_device);
556 }
557
558 static struct resource tegra_rtc_resources[] = {
559         [0] = {
560                 .start = TEGRA_RTC_BASE,
561                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
562                 .flags = IORESOURCE_MEM,
563         },
564         [1] = {
565                 .start = INT_RTC,
566                 .end = INT_RTC,
567                 .flags = IORESOURCE_IRQ,
568         },
569 };
570
571 static struct platform_device tegra_rtc_device = {
572         .name = "tegra_rtc",
573         .id   = -1,
574         .resource = tegra_rtc_resources,
575         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
576 };
577
578 static struct tegra_wm8903_platform_data cardhu_audio_pdata = {
579         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
580         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
581         .gpio_hp_mute           = -1,
582         .gpio_int_mic_en        = -1,
583         .gpio_ext_mic_en        = -1,
584 };
585
586 static struct platform_device cardhu_audio_device = {
587         .name   = "tegra-snd-wm8903",
588         .id     = 0,
589         .dev    = {
590                 .platform_data  = &cardhu_audio_pdata,
591         },
592 };
593
594 static struct platform_device *cardhu_devices[] __initdata = {
595         &tegra_pmu_device,
596         &tegra_rtc_device,
597         &tegra_udc_device,
598 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
599         &tegra_smmu_device,
600 #endif
601         &tegra_wdt_device,
602 #if defined(CONFIG_TEGRA_AVP)
603         &tegra_avp_device,
604 #endif
605         &tegra_camera,
606 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
607         &tegra_se_device,
608 #endif
609         &tegra_ahub_device,
610         &tegra_dam_device0,
611         &tegra_dam_device1,
612         &tegra_dam_device2,
613         &tegra_i2s_device1,
614         &tegra_i2s_device3,
615         &tegra_spdif_device,
616         &spdif_dit_device,
617         &bluetooth_dit_device,
618         &tegra_pcm_device,
619         &cardhu_audio_device,
620         &tegra_hda_device,
621 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
622         &tegra_aes_device,
623 #endif
624 };
625
626 #define MXT_CONFIG_CRC  0xD62DE8
627 static const u8 config[] = {
628         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
629         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
630         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
631         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
632         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
633         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
634         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
635         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
636         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
637         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
638         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
639         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
640         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
641         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
642         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
643         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
644         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
645         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
646         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
647         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
648 };
649
650 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
651 static const u8 config_sku2000[] = {
652         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
653         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
654         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
655         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
656         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
657         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
658         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
659         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
660         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
661         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
662         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
663         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
664         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
665         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
666         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
667         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
668         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
669         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
670         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
671         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
672 };
673
674 static struct mxt_platform_data atmel_mxt_info = {
675         .x_line         = 27,
676         .y_line         = 42,
677         .x_size         = 768,
678         .y_size         = 1366,
679         .blen           = 0x20,
680         .threshold      = 0x3C,
681         .voltage        = 3300000,              /* 3.3V */
682         .orient         = 5,
683         .config         = config,
684         .config_length  = 157,
685         .config_crc     = MXT_CONFIG_CRC,
686         .irqflags       = IRQF_TRIGGER_FALLING,
687 /*      .read_chg       = &read_chg, */
688         .read_chg       = NULL,
689 };
690
691 static struct i2c_board_info __initdata atmel_i2c_info[] = {
692         {
693                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
694                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
695                 .platform_data = &atmel_mxt_info,
696         }
697 };
698
699 static int __init cardhu_touch_init(void)
700 {
701         struct board_info BoardInfo;
702
703         tegra_gpio_enable(TEGRA_GPIO_PH4);
704         tegra_gpio_enable(TEGRA_GPIO_PH6);
705
706         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
707         gpio_direction_input(TEGRA_GPIO_PH4);
708
709         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
710         gpio_direction_output(TEGRA_GPIO_PH6, 0);
711         msleep(1);
712         gpio_set_value(TEGRA_GPIO_PH6, 1);
713         msleep(100);
714
715         tegra_get_board_info(&BoardInfo);
716         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
717                 atmel_mxt_info.config = config_sku2000;
718                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
719         }
720
721         i2c_register_board_info(1, atmel_i2c_info, 1);
722
723         return 0;
724 }
725
726 static struct tegra_uhsic_config uhsic_phy_config = {
727         .enable_gpio = EN_HSIC_GPIO,
728         .reset_gpio = -1,
729         .sync_start_delay = 9,
730         .idle_wait_delay = 17,
731         .term_range_adj = 0,
732         .elastic_underrun_limit = 16,
733         .elastic_overrun_limit = 16,
734 };
735
736 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
737         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
738         .phy_config = &uhsic_phy_config,
739         .operating_mode = TEGRA_USB_HOST,
740         .power_down_on_bus_suspend = 1,
741 };
742
743 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
744         [0] = {
745                         .phy_config = &utmi_phy_config[0],
746                         .operating_mode = TEGRA_USB_HOST,
747                         .power_down_on_bus_suspend = 1,
748         },
749         [1] = {
750                         .phy_config = &utmi_phy_config[1],
751                         .operating_mode = TEGRA_USB_HOST,
752                         .power_down_on_bus_suspend = 1,
753         },
754         [2] = {
755                         .phy_config = &utmi_phy_config[2],
756                         .operating_mode = TEGRA_USB_HOST,
757                         .power_down_on_bus_suspend = 1,
758                         .hotplug = 1,
759         },
760 };
761
762 static struct tegra_otg_platform_data tegra_otg_pdata = {
763         .ehci_device = &tegra_ehci1_device,
764         .ehci_pdata = &tegra_ehci_pdata[0],
765 };
766
767 #ifdef CONFIG_USB_SUPPORT
768 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
769         [0] = {
770                         .instance = 0,
771                         .vbus_gpio = -1,
772                         .vbus_reg_supply = "vdd_vbus_micro_usb",
773         },
774         [1] = {
775                         .instance = 1,
776                         .vbus_gpio = -1,
777         },
778         [2] = {
779                         .instance = 2,
780                         .vbus_gpio = -1,
781                         .vbus_reg_supply = "vdd_vbus_typea_usb",
782         },
783 };
784
785 static void cardhu_usb_init(void)
786 {
787         struct board_info bi;
788
789         tegra_get_board_info(&bi);
790
791         tegra_usb_phy_init(tegra_usb_phy_pdata,
792                         ARRAY_SIZE(tegra_usb_phy_pdata));
793
794         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
795         platform_device_register(&tegra_otg_device);
796         if (bi.board_id == BOARD_PM267) {
797                 uhsic_phy_config.reset_gpio =
798                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
799                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
800                 platform_device_register(&tegra_ehci2_device);
801         } else if (bi.board_id == BOARD_E1256) {
802                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
803                 platform_device_register(&tegra_ehci2_device);
804         } else if (bi.board_id == BOARD_E1186) {
805                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
806                 /* baseband registration happens in baseband-xmm-power  */
807         } else {
808                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
809                 platform_device_register(&tegra_ehci2_device);
810         }
811
812         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
813         platform_device_register(&tegra_ehci3_device);
814
815 }
816 #else
817 static void cardhu_usb_init(void) { }
818 #endif
819
820 static void cardhu_gps_init(void)
821 {
822         tegra_gpio_enable(TEGRA_GPIO_PU2);
823         tegra_gpio_enable(TEGRA_GPIO_PU3);
824 }
825
826 static void cardhu_nfc_init(void)
827 {
828         tegra_gpio_enable(TEGRA_GPIO_PX0);
829         tegra_gpio_enable(TEGRA_GPIO_PP3);
830         tegra_gpio_enable(TEGRA_GPIO_PO7);
831 }
832
833 static struct baseband_power_platform_data tegra_baseband_power_data = {
834         .baseband_type = BASEBAND_XMM,
835         .modem = {
836         .xmm = {
837                         .bb_rst = XMM_GPIO_BB_RST,
838                         .bb_on = XMM_GPIO_BB_ON,
839                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
840                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
841                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
842                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
843                         .hsic_device = &tegra_ehci2_device,
844                 },
845         },
846 };
847
848 static struct platform_device tegra_baseband_power_device = {
849         .name = "baseband_xmm_power",
850         .id = -1,
851         .dev = {
852                 .platform_data = &tegra_baseband_power_data,
853         },
854 };
855
856 static struct platform_device tegra_baseband_power2_device = {
857         .name = "baseband_xmm_power2",
858         .id = -1,
859         .dev = {
860                 .platform_data = &tegra_baseband_power_data,
861         },
862 };
863
864
865 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
866         .port_status[0] = 1,
867         .port_status[1] = 1,
868         .port_status[2] = 1,
869         .use_dock_detect        = 0,
870         .gpio           = 0,
871 };
872
873 static void cardhu_pci_init(void)
874 {
875         struct board_info board_info;
876
877         tegra_get_board_info(&board_info);
878         if (board_info.board_id == BOARD_E1291) {
879                 cardhu_pci_platform_data.port_status[0] = 0;
880                 cardhu_pci_platform_data.port_status[1] = 0;
881                 cardhu_pci_platform_data.port_status[2] = 1;
882                 cardhu_pci_platform_data.use_dock_detect = 1;
883                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
884         }
885         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
886         platform_device_register(&tegra_pci_device);
887 }
888
889 static void cardhu_modem_init(void)
890 {
891         struct board_info board_info;
892         int w_disable_gpio, ret;
893
894         tegra_get_board_info(&board_info);
895         switch (board_info.board_id) {
896         case BOARD_E1291:
897         case BOARD_E1198:
898                 if (((board_info.board_id == BOARD_E1291) &&
899                                 (board_info.fab < BOARD_FAB_A03)) ||
900                         ((board_info.board_id == BOARD_E1198) &&
901                                         (board_info.fab < BOARD_FAB_A02))) {
902                         w_disable_gpio = TEGRA_GPIO_PH5;
903                 } else {
904                         w_disable_gpio = TEGRA_GPIO_PDD5;
905                 }
906                 tegra_gpio_enable(w_disable_gpio);
907                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
908                 if (ret < 0)
909                         pr_err("%s: gpio_request failed for gpio %d\n",
910                                 __func__, w_disable_gpio);
911                 else
912                         gpio_direction_input(w_disable_gpio);
913
914                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
915                 if (((board_info.board_id == BOARD_E1291) &&
916                                 (board_info.fab >= BOARD_FAB_A04)) ||
917                         ((board_info.board_id == BOARD_E1198) &&
918                                         (board_info.fab >= BOARD_FAB_A02))) {
919                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
920                         if (ret < 0) {
921                                 pr_err("%s(): Error in allocating gpio "
922                                         "TEGRA_GPIO_PH7\n", __func__);
923                                 break;
924                         }
925                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
926                         tegra_gpio_enable(TEGRA_GPIO_PH7);
927                 }
928                 break;
929         case BOARD_E1186:
930                 tegra_gpio_enable(
931                         tegra_baseband_power_data.modem.xmm.bb_rst);
932                 tegra_gpio_enable(
933                         tegra_baseband_power_data.modem.xmm.bb_on);
934                 tegra_gpio_enable(
935                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
936                 tegra_gpio_enable(
937                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
938                 tegra_gpio_enable(
939                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
940                 tegra_gpio_enable(
941                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
942                 platform_device_register(&tegra_baseband_power_device);
943                 platform_device_register(&tegra_baseband_power2_device);
944                 break;
945         default:
946                 break;
947         }
948
949 }
950
951 #ifdef CONFIG_SATA_AHCI_TEGRA
952 static void cardhu_sata_init(void)
953 {
954         platform_device_register(&tegra_sata_device);
955 }
956 #else
957 static void cardhu_sata_init(void) { }
958 #endif
959
960 static void __init tegra_cardhu_init(void)
961 {
962         tegra_thermal_init(&thermal_data);
963         tegra_clk_init_from_table(cardhu_clk_init_table);
964         cardhu_pinmux_init();
965         cardhu_i2c_init();
966         cardhu_spi_init();
967         cardhu_usb_init();
968 #ifdef CONFIG_TEGRA_EDP_LIMITS
969         cardhu_edp_init();
970 #endif
971         cardhu_uart_init();
972         cardhu_tsensor_init();
973         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
974         cardhu_sdhci_init();
975         cardhu_regulator_init();
976         cardhu_dtv_init();
977         cardhu_gpio_switch_regulator_init();
978         cardhu_suspend_init();
979         cardhu_power_off_init();
980         cardhu_touch_init();
981         cardhu_gps_init();
982         cardhu_modem_init();
983         cardhu_kbc_init();
984         cardhu_scroll_init();
985         cardhu_keys_init();
986         cardhu_panel_init();
987         cardhu_pmon_init();
988         cardhu_sensors_init();
989         cardhu_bt_rfkill();
990         tegra_setup_bluesleep();
991         cardhu_sata_init();
992         //audio_wired_jack_init();
993         cardhu_pins_state_init();
994         cardhu_emc_init();
995         tegra_release_bootloader_fb();
996         cardhu_nfc_init();
997         cardhu_pci_init();
998 #ifdef CONFIG_TEGRA_WDT_RECOVERY
999         tegra_wdt_recovery_init();
1000 #endif
1001 }
1002
1003 static void __init tegra_cardhu_reserve(void)
1004 {
1005 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1006         /* support 1920X1200 with 24bpp */
1007         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1008 #else
1009         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1010 #endif
1011 }
1012
1013 MACHINE_START(CARDHU, "cardhu")
1014         .boot_params    = 0x80000100,
1015         .map_io         = tegra_map_common_io,
1016         .reserve        = tegra_cardhu_reserve,
1017         .init_early     = tegra_init_early,
1018         .init_irq       = tegra_init_irq,
1019         .timer          = &tegra_timer,
1020         .init_machine   = tegra_cardhu_init,
1021 MACHINE_END