arm: tegra: power: add watchdog recovery function
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41
42 #include <sound/wm8903.h>
43
44 #include <mach/clk.h>
45 #include <mach/iomap.h>
46 #include <mach/irqs.h>
47 #include <mach/pinmux.h>
48 #include <mach/iomap.h>
49 #include <mach/io.h>
50 #include <mach/i2s.h>
51 #include <mach/tegra_wm8903_pdata.h>
52 #include <asm/mach-types.h>
53 #include <asm/mach/arch.h>
54 #include <mach/usb_phy.h>
55 #include <mach/thermal.h>
56 #include <mach/pci.h>
57
58 #include "board.h"
59 #include "clock.h"
60 #include "board-cardhu.h"
61 #include "devices.h"
62 #include "gpio-names.h"
63 #include "fuse.h"
64 #include "pm.h"
65 #include "baseband-xmm-power.h"
66 #include "wdt-recovery.h"
67
68 /* All units are in millicelsius */
69 static struct tegra_thermal_data thermal_data = {
70         .temp_throttle = 85000,
71         .temp_shutdown = 90000,
72         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
73 #ifdef CONFIG_TEGRA_EDP_LIMITS
74         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
75         .hysteresis_edp = 3000,
76 #endif
77 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
78         .tc1 = 0,
79         .tc2 = 1,
80         .passive_delay = 2000,
81 #else
82         .hysteresis_throttle = 1000,
83 #endif
84 };
85
86 /* !!!TODO: Change for cardhu (Taken from Ventana) */
87 static struct tegra_utmip_config utmi_phy_config[] = {
88         [0] = {
89                         .hssync_start_delay = 0,
90                         .idle_wait_delay = 17,
91                         .elastic_limit = 16,
92                         .term_range_adj = 6,
93                         .xcvr_setup = 15,
94                         .xcvr_setup_offset = 0,
95                         .xcvr_use_fuses = 1,
96                         .xcvr_lsfslew = 2,
97                         .xcvr_lsrslew = 2,
98         },
99         [1] = {
100                         .hssync_start_delay = 0,
101                         .idle_wait_delay = 17,
102                         .elastic_limit = 16,
103                         .term_range_adj = 6,
104                         .xcvr_setup = 15,
105                         .xcvr_setup_offset = 0,
106                         .xcvr_use_fuses = 1,
107                         .xcvr_lsfslew = 2,
108                         .xcvr_lsrslew = 2,
109         },
110         [2] = {
111                         .hssync_start_delay = 0,
112                         .idle_wait_delay = 17,
113                         .elastic_limit = 16,
114                         .term_range_adj = 6,
115                         .xcvr_setup = 8,
116                         .xcvr_setup_offset = 0,
117                         .xcvr_use_fuses = 1,
118                         .xcvr_lsfslew = 2,
119                         .xcvr_lsrslew = 2,
120         },
121 };
122
123 #ifdef CONFIG_BCM4329_RFKILL
124 static struct resource cardhu_bcm4329_rfkill_resources[] = {
125         {
126                 .name   = "bcm4329_nshutdown_gpio",
127                 .start  = TEGRA_GPIO_PU0,
128                 .end    = TEGRA_GPIO_PU0,
129                 .flags  = IORESOURCE_IO,
130         },
131 };
132
133 static struct platform_device cardhu_bcm4329_rfkill_device = {
134         .name = "bcm4329_rfkill",
135         .id             = -1,
136         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
137         .resource       = cardhu_bcm4329_rfkill_resources,
138 };
139
140 static noinline void __init cardhu_bt_rfkill(void)
141 {
142         platform_device_register(&cardhu_bcm4329_rfkill_device);
143
144         return;
145 }
146 #else
147 static inline void cardhu_bt_rfkill(void) { }
148 #endif
149
150 #ifdef CONFIG_BT_BLUESLEEP
151 static noinline void __init tegra_setup_bluesleep(void)
152 {
153         struct platform_device *pdev = NULL;
154         struct resource *res;
155
156         pdev = platform_device_alloc("bluesleep", 0);
157         if (!pdev) {
158                 pr_err("unable to allocate platform device for bluesleep");
159                 return;
160         }
161
162         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
163         if (!res) {
164                 pr_err("unable to allocate resource for bluesleep\n");
165                 goto err_free_dev;
166         }
167
168         res[0].name   = "gpio_host_wake";
169         res[0].start  = TEGRA_GPIO_PU6;
170         res[0].end    = TEGRA_GPIO_PU6;
171         res[0].flags  = IORESOURCE_IO;
172
173         res[1].name   = "gpio_ext_wake";
174         res[1].start  = TEGRA_GPIO_PU1;
175         res[1].end    = TEGRA_GPIO_PU1;
176         res[1].flags  = IORESOURCE_IO;
177
178         res[2].name   = "host_wake";
179         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
180         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
181         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
182
183         if (platform_device_add_resources(pdev, res, 3)) {
184                 pr_err("unable to add resources to bluesleep device\n");
185                 goto err_free_res;
186         }
187
188         if (platform_device_add(pdev)) {
189                 pr_err("unable to add bluesleep device\n");
190                 goto err_free_res;
191         }
192         tegra_gpio_enable(TEGRA_GPIO_PU6);
193         tegra_gpio_enable(TEGRA_GPIO_PU1);
194
195 return;
196
197 err_free_res:
198         kfree(res);
199 err_free_dev:
200         platform_device_put(pdev);
201         return;
202 }
203 #else
204 static inline void tegra_setup_bluesleep(void) { }
205 #endif
206
207 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
208         /* name         parent          rate            enabled */
209         { "pll_m",      NULL,           0,              false},
210         { "hda",        "pll_p",        108000000,      false},
211         { "hda2codec_2x","pll_p",       48000000,       false},
212         { "pwm",        "pll_p",        3187500,        false},
213         { "blink",      "clk_32k",      32768,          true},
214         { "i2s1",       "pll_a_out0",   0,              false},
215         { "i2s3",       "pll_a_out0",   0,              false},
216         { "spdif_out",  "pll_a_out0",   0,              false},
217         { "d_audio",    "pll_a_out0",   0,              false},
218         { "dam0",       "pll_a_out0",   0,              false},
219         { "dam1",       "pll_a_out0",   0,              false},
220         { "dam2",       "pll_a_out0",   0,              false},
221         { "audio1",     "i2s1_sync",    0,              false},
222         { "audio3",     "i2s3_sync",    0,              false},
223         { "vi_sensor",  "pll_p",        150000000,      false},
224         { "i2c1",       "pll_p",        3200000,        false},
225         { "i2c2",       "pll_p",        3200000,        false},
226         { "i2c3",       "pll_p",        3200000,        false},
227         { "i2c4",       "pll_p",        3200000,        false},
228         { "i2c5",       "pll_p",        3200000,        false},
229         { NULL,         NULL,           0,              0},
230 };
231
232 static struct pn544_i2c_platform_data nfc_pdata = {
233         .irq_gpio = TEGRA_GPIO_PX0,
234         .ven_gpio = TEGRA_GPIO_PP3,
235         .firm_gpio = TEGRA_GPIO_PO7,
236         };
237
238 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
239         {
240                 I2C_BOARD_INFO("pn544", 0x28),
241                 .platform_data = &nfc_pdata,
242                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
243         },
244 };
245 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
246         .adapter_nr     = 0,
247         .bus_count      = 1,
248         .bus_clk_rate   = { 100000, 0 },
249         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
250         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
251         .arb_recovery = arb_lost_recovery,
252 };
253
254 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
255         .adapter_nr     = 1,
256         .bus_count      = 1,
257         .bus_clk_rate   = { 100000, 0 },
258         .is_clkon_always = true,
259         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
260         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
261         .arb_recovery = arb_lost_recovery,
262 };
263
264 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
265         .adapter_nr     = 2,
266         .bus_count      = 1,
267         .bus_clk_rate   = { 100000, 0 },
268         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
269         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
270         .arb_recovery = arb_lost_recovery,
271 };
272
273 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
274         .adapter_nr     = 3,
275         .bus_count      = 1,
276         .bus_clk_rate   = { 100000, 0 },
277         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
278         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
279         .arb_recovery = arb_lost_recovery,
280 };
281
282 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
283         .adapter_nr     = 4,
284         .bus_count      = 1,
285         .bus_clk_rate   = { 400000, 0 },
286         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
287         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
288         .arb_recovery = arb_lost_recovery,
289 };
290
291
292 #if 0
293 struct tegra_wired_jack_conf audio_wr_jack_conf = {
294         .hp_det_n = TEGRA_GPIO_PW2,
295         .en_mic_ext = TEGRA_GPIO_PX1,
296         .en_mic_int = TEGRA_GPIO_PX0,
297 };
298 #endif
299
300 static struct wm8903_platform_data cardhu_wm8903_pdata = {
301         .irq_active_low = 0,
302         .micdet_cfg = 0,
303         .micdet_delay = 100,
304         .gpio_base = CARDHU_GPIO_WM8903(0),
305         .gpio_cfg = {
306                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
307                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
308                         WM8903_GP2_DIR,
309                 0,
310                 WM8903_GPIO_NO_CONFIG,
311                 WM8903_GPIO_NO_CONFIG,
312         },
313 };
314
315 static struct i2c_board_info __initdata wm8903_board_info = {
316         I2C_BOARD_INFO("wm8903", 0x1a),
317         .platform_data = &cardhu_wm8903_pdata,
318         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
319 };
320
321 static void cardhu_i2c_init(void)
322 {
323         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
324         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
325         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
326         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
327         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
328
329         platform_device_register(&tegra_i2c_device5);
330         platform_device_register(&tegra_i2c_device4);
331         platform_device_register(&tegra_i2c_device3);
332         platform_device_register(&tegra_i2c_device2);
333         platform_device_register(&tegra_i2c_device1);
334
335         i2c_register_board_info(4, &wm8903_board_info, 1);
336         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
337 }
338
339 static struct platform_device *cardhu_uart_devices[] __initdata = {
340         &tegra_uarta_device,
341         &tegra_uartb_device,
342         &tegra_uartc_device,
343         &tegra_uartd_device,
344         &tegra_uarte_device,
345 };
346 static struct uart_clk_parent uart_parent_clk[] = {
347         [0] = {.name = "clk_m"},
348         [1] = {.name = "pll_p"},
349 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
350         [2] = {.name = "pll_m"},
351 #endif
352 };
353
354 static struct tegra_uart_platform_data cardhu_uart_pdata;
355
356 static void __init uart_debug_init(void)
357 {
358         struct board_info board_info;
359         int debug_port_id;
360
361         tegra_get_board_info(&board_info);
362
363         debug_port_id = get_tegra_uart_debug_port_id();
364         if (debug_port_id < 0) {
365                 debug_port_id = 0;
366                         /* UARTB is debug port
367                          *       for SLT - E1186/E1187/PM269
368                          *       for E1256/E1257
369                          */
370                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
371                         ((board_info.board_id == BOARD_E1186) ||
372                         (board_info.board_id == BOARD_E1187) ||
373                         (board_info.board_id == BOARD_PM269))) ||
374                         (board_info.board_id == BOARD_E1256) ||
375                         (board_info.board_id == BOARD_E1257))
376                                 debug_port_id = 1;
377         }
378         switch (debug_port_id) {
379         case 0:
380                 /* UARTA is the debug port. */
381                 pr_info("Selecting UARTA as the debug console\n");
382                 cardhu_uart_devices[0] = &debug_uarta_device;
383                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
384                 debug_uart_port_base = ((struct plat_serial8250_port *)(
385                         debug_uarta_device.dev.platform_data))->mapbase;
386                 break;
387
388         case 1:
389                 /* UARTB is the debug port. */
390                 pr_info("Selecting UARTB as the debug console\n");
391                 cardhu_uart_devices[1] = &debug_uartb_device;
392                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
393                 debug_uart_port_base = ((struct plat_serial8250_port *)(
394                         debug_uartb_device.dev.platform_data))->mapbase;
395                 break;
396
397         case 2:
398                 /* UARTC is the debug port. */
399                 pr_info("Selecting UARTC as the debug console\n");
400                 cardhu_uart_devices[2] = &debug_uartc_device;
401                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
402                 debug_uart_port_base = ((struct plat_serial8250_port *)(
403                         debug_uartc_device.dev.platform_data))->mapbase;
404                 break;
405
406         case 3:
407                 /* UARTD is the debug port. */
408                 pr_info("Selecting UARTD as the debug console\n");
409                 cardhu_uart_devices[3] = &debug_uartd_device;
410                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
411                 debug_uart_port_base = ((struct plat_serial8250_port *)(
412                         debug_uartd_device.dev.platform_data))->mapbase;
413                 break;
414
415         case 4:
416                 /* UARTE is the debug port. */
417                 pr_info("Selecting UARTE as the debug console\n");
418                 cardhu_uart_devices[4] = &debug_uarte_device;
419                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
420                 debug_uart_port_base = ((struct plat_serial8250_port *)(
421                         debug_uarte_device.dev.platform_data))->mapbase;
422                 break;
423
424         default:
425                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
426                 cardhu_uart_devices[0] = &debug_uarta_device;
427                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
428                 debug_uart_port_base = ((struct plat_serial8250_port *)(
429                         debug_uarta_device.dev.platform_data))->mapbase;
430                 break;
431         }
432         return;
433 }
434
435 static void __init cardhu_uart_init(void)
436 {
437         struct clk *c;
438         int i;
439
440         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
441                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
442                 if (IS_ERR_OR_NULL(c)) {
443                         pr_err("Not able to get the clock for %s\n",
444                                                 uart_parent_clk[i].name);
445                         continue;
446                 }
447                 uart_parent_clk[i].parent_clk = c;
448                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
449         }
450         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
451         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
452         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
453         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
454         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
455         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
456         tegra_uarte_device.dev.platform_data = &cardhu_uart_pdata;
457
458         /* Register low speed only if it is selected */
459         if (!is_tegra_debug_uartport_hs()) {
460                 uart_debug_init();
461                 /* Clock enable for the debug channel */
462                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
463                         pr_info("The debug console clock name is %s\n",
464                                                 debug_uart_clk->name);
465                         c = tegra_get_clock_by_name("pll_p");
466                         if (IS_ERR_OR_NULL(c))
467                                 pr_err("Not getting the parent clock pll_p\n");
468                         else
469                                 clk_set_parent(debug_uart_clk, c);
470
471                         clk_enable(debug_uart_clk);
472                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
473                 } else {
474                         pr_err("Not getting the clock %s for debug console\n",
475                                         debug_uart_clk->name);
476                 }
477         }
478
479         platform_add_devices(cardhu_uart_devices,
480                                 ARRAY_SIZE(cardhu_uart_devices));
481 }
482
483 static struct platform_device tegra_camera = {
484         .name = "tegra_camera",
485         .id = -1,
486 };
487
488 static struct platform_device *cardhu_spi_devices[] __initdata = {
489         &tegra_spi_device4,
490 };
491
492 struct spi_clk_parent spi_parent_clk[] = {
493         [0] = {.name = "pll_p"},
494 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
495         [1] = {.name = "pll_m"},
496         [2] = {.name = "clk_m"},
497 #else
498         [1] = {.name = "clk_m"},
499 #endif
500 };
501
502 static struct tegra_spi_platform_data cardhu_spi_pdata = {
503         .is_dma_based           = true,
504         .max_dma_buffer         = (16 * 1024),
505         .is_clkon_always        = false,
506         .max_rate               = 100000000,
507 };
508
509 static void __init cardhu_spi_init(void)
510 {
511         int i;
512         struct clk *c;
513         struct board_info board_info;
514
515         tegra_get_board_info(&board_info);
516
517         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
518                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
519                 if (IS_ERR_OR_NULL(c)) {
520                         pr_err("Not able to get the clock for %s\n",
521                                                 spi_parent_clk[i].name);
522                         continue;
523                 }
524                 spi_parent_clk[i].parent_clk = c;
525                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
526         }
527         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
528         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
529         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
530         platform_add_devices(cardhu_spi_devices,
531                                 ARRAY_SIZE(cardhu_spi_devices));
532
533         if (board_info.board_id == BOARD_E1198) {
534                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
535                 platform_device_register(&tegra_spi_device2);
536                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
537                 platform_device_register(&tegra_spi_slave_device1);
538         }
539 }
540
541 static struct resource tegra_rtc_resources[] = {
542         [0] = {
543                 .start = TEGRA_RTC_BASE,
544                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
545                 .flags = IORESOURCE_MEM,
546         },
547         [1] = {
548                 .start = INT_RTC,
549                 .end = INT_RTC,
550                 .flags = IORESOURCE_IRQ,
551         },
552 };
553
554 static struct platform_device tegra_rtc_device = {
555         .name = "tegra_rtc",
556         .id   = -1,
557         .resource = tegra_rtc_resources,
558         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
559 };
560
561 static struct tegra_wm8903_platform_data cardhu_audio_pdata = {
562         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
563         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
564         .gpio_hp_mute           = -1,
565         .gpio_int_mic_en        = -1,
566         .gpio_ext_mic_en        = -1,
567 };
568
569 static struct platform_device cardhu_audio_device = {
570         .name   = "tegra-snd-wm8903",
571         .id     = 0,
572         .dev    = {
573                 .platform_data  = &cardhu_audio_pdata,
574         },
575 };
576
577 static struct platform_device *cardhu_devices[] __initdata = {
578         &tegra_pmu_device,
579         &tegra_rtc_device,
580         &tegra_udc_device,
581 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
582         &tegra_smmu_device,
583 #endif
584         &tegra_wdt_device,
585 #if defined(CONFIG_TEGRA_AVP)
586         &tegra_avp_device,
587 #endif
588         &tegra_camera,
589 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
590         &tegra_se_device,
591 #endif
592         &tegra_ahub_device,
593         &tegra_dam_device0,
594         &tegra_dam_device1,
595         &tegra_dam_device2,
596         &tegra_i2s_device1,
597         &tegra_i2s_device3,
598         &tegra_spdif_device,
599         &spdif_dit_device,
600         &bluetooth_dit_device,
601         &tegra_pcm_device,
602         &cardhu_audio_device,
603         &tegra_hda_device,
604 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
605         &tegra_aes_device,
606 #endif
607 };
608
609 #define MXT_CONFIG_CRC  0xD62DE8
610 static const u8 config[] = {
611         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
612         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
613         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
614         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
615         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
616         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
617         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
618         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
619         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
620         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
621         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
622         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
623         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
624         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
625         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
626         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
627         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
628         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
629         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
631 };
632
633 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
634 static const u8 config_sku2000[] = {
635         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
636         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
637         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
638         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
639         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
640         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
641         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
642         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
643         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
644         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
645         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
646         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
647         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
648         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
649         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
650         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
651         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
652         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
653         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
654         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
655 };
656
657 static struct mxt_platform_data atmel_mxt_info = {
658         .x_line         = 27,
659         .y_line         = 42,
660         .x_size         = 768,
661         .y_size         = 1366,
662         .blen           = 0x20,
663         .threshold      = 0x3C,
664         .voltage        = 3300000,              /* 3.3V */
665         .orient         = 5,
666         .config         = config,
667         .config_length  = 157,
668         .config_crc     = MXT_CONFIG_CRC,
669         .irqflags       = IRQF_TRIGGER_FALLING,
670 /*      .read_chg       = &read_chg, */
671         .read_chg       = NULL,
672 };
673
674 static struct i2c_board_info __initdata atmel_i2c_info[] = {
675         {
676                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
677                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
678                 .platform_data = &atmel_mxt_info,
679         }
680 };
681
682 static int __init cardhu_touch_init(void)
683 {
684         struct board_info BoardInfo;
685
686         tegra_gpio_enable(TEGRA_GPIO_PH4);
687         tegra_gpio_enable(TEGRA_GPIO_PH6);
688
689         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
690         gpio_direction_input(TEGRA_GPIO_PH4);
691
692         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
693         gpio_direction_output(TEGRA_GPIO_PH6, 0);
694         msleep(1);
695         gpio_set_value(TEGRA_GPIO_PH6, 1);
696         msleep(100);
697
698         tegra_get_board_info(&BoardInfo);
699         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
700                 atmel_mxt_info.config = config_sku2000;
701                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
702         }
703
704         i2c_register_board_info(1, atmel_i2c_info, 1);
705
706         return 0;
707 }
708
709 static struct tegra_uhsic_config uhsic_phy_config = {
710         .enable_gpio = EN_HSIC_GPIO,
711         .reset_gpio = -1,
712         .sync_start_delay = 9,
713         .idle_wait_delay = 17,
714         .term_range_adj = 0,
715         .elastic_underrun_limit = 16,
716         .elastic_overrun_limit = 16,
717 };
718
719 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
720         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
721         .phy_config = &uhsic_phy_config,
722         .operating_mode = TEGRA_USB_HOST,
723         .power_down_on_bus_suspend = 1,
724 };
725
726 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
727         [0] = {
728                         .phy_config = &utmi_phy_config[0],
729                         .operating_mode = TEGRA_USB_HOST,
730                         .power_down_on_bus_suspend = 1,
731         },
732         [1] = {
733                         .phy_config = &utmi_phy_config[1],
734                         .operating_mode = TEGRA_USB_HOST,
735                         .power_down_on_bus_suspend = 1,
736         },
737         [2] = {
738                         .phy_config = &utmi_phy_config[2],
739                         .operating_mode = TEGRA_USB_HOST,
740                         .power_down_on_bus_suspend = 1,
741                         .hotplug = 1,
742         },
743 };
744
745 static struct tegra_otg_platform_data tegra_otg_pdata = {
746         .ehci_device = &tegra_ehci1_device,
747         .ehci_pdata = &tegra_ehci_pdata[0],
748 };
749
750 #ifdef CONFIG_USB_SUPPORT
751 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
752         [0] = {
753                         .instance = 0,
754                         .vbus_gpio = -1,
755                         .vbus_reg_supply = "vdd_vbus_micro_usb",
756         },
757         [1] = {
758                         .instance = 1,
759                         .vbus_gpio = -1,
760         },
761         [2] = {
762                         .instance = 2,
763                         .vbus_gpio = -1,
764                         .vbus_reg_supply = "vdd_vbus_typea_usb",
765         },
766 };
767
768 static void cardhu_usb_init(void)
769 {
770         struct board_info bi;
771
772         tegra_get_board_info(&bi);
773
774         tegra_usb_phy_init(tegra_usb_phy_pdata,
775                         ARRAY_SIZE(tegra_usb_phy_pdata));
776
777         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
778         platform_device_register(&tegra_otg_device);
779         if (bi.board_id == BOARD_PM267) {
780                 uhsic_phy_config.reset_gpio =
781                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
782                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
783                 platform_device_register(&tegra_ehci2_device);
784         } else if (bi.board_id == BOARD_E1256) {
785                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
786                 platform_device_register(&tegra_ehci2_device);
787         } else if (bi.board_id == BOARD_E1186) {
788                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
789                 /* baseband registration happens in baseband-xmm-power  */
790         } else {
791                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
792                 platform_device_register(&tegra_ehci2_device);
793         }
794
795         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
796         platform_device_register(&tegra_ehci3_device);
797
798 }
799 #else
800 static void cardhu_usb_init(void) { }
801 #endif
802
803 static void cardhu_gps_init(void)
804 {
805         tegra_gpio_enable(TEGRA_GPIO_PU2);
806         tegra_gpio_enable(TEGRA_GPIO_PU3);
807 }
808
809 static void cardhu_nfc_init(void)
810 {
811         tegra_gpio_enable(TEGRA_GPIO_PX0);
812         tegra_gpio_enable(TEGRA_GPIO_PP3);
813         tegra_gpio_enable(TEGRA_GPIO_PO7);
814 }
815
816 static struct baseband_power_platform_data tegra_baseband_power_data = {
817         .baseband_type = BASEBAND_XMM,
818         .modem = {
819         .xmm = {
820                         .bb_rst = XMM_GPIO_BB_RST,
821                         .bb_on = XMM_GPIO_BB_ON,
822                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
823                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
824                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
825                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
826                         .hsic_device = &tegra_ehci2_device,
827                 },
828         },
829 };
830
831 static struct platform_device tegra_baseband_power_device = {
832         .name = "baseband_xmm_power",
833         .id = -1,
834         .dev = {
835                 .platform_data = &tegra_baseband_power_data,
836         },
837 };
838
839 static struct platform_device tegra_baseband_power2_device = {
840         .name = "baseband_xmm_power2",
841         .id = -1,
842         .dev = {
843                 .platform_data = &tegra_baseband_power_data,
844         },
845 };
846
847
848 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
849         .port_status[0] = 1,
850         .port_status[1] = 1,
851         .port_status[2] = 1,
852         .use_dock_detect        = 0,
853         .gpio           = 0,
854 };
855
856 static void cardhu_pci_init(void)
857 {
858         struct board_info board_info;
859
860         tegra_get_board_info(&board_info);
861         if (board_info.board_id == BOARD_E1291) {
862                 cardhu_pci_platform_data.port_status[0] = 0;
863                 cardhu_pci_platform_data.port_status[1] = 0;
864                 cardhu_pci_platform_data.port_status[2] = 1;
865                 cardhu_pci_platform_data.use_dock_detect = 1;
866                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
867         }
868         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
869         platform_device_register(&tegra_pci_device);
870 }
871
872 static void cardhu_modem_init(void)
873 {
874         struct board_info board_info;
875         int w_disable_gpio, ret;
876
877         tegra_get_board_info(&board_info);
878         switch (board_info.board_id) {
879         case BOARD_E1291:
880         case BOARD_E1198:
881                 if (((board_info.board_id == BOARD_E1291) &&
882                                 (board_info.fab < BOARD_FAB_A03)) ||
883                         ((board_info.board_id == BOARD_E1198) &&
884                                         (board_info.fab < BOARD_FAB_A02))) {
885                         w_disable_gpio = TEGRA_GPIO_PH5;
886                 } else {
887                         w_disable_gpio = TEGRA_GPIO_PDD5;
888                 }
889                 tegra_gpio_enable(w_disable_gpio);
890                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
891                 if (ret < 0)
892                         pr_err("%s: gpio_request failed for gpio %d\n",
893                                 __func__, w_disable_gpio);
894                 else
895                         gpio_direction_input(w_disable_gpio);
896
897                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
898                 if (((board_info.board_id == BOARD_E1291) &&
899                                 (board_info.fab >= BOARD_FAB_A04)) ||
900                         ((board_info.board_id == BOARD_E1198) &&
901                                         (board_info.fab >= BOARD_FAB_A02))) {
902                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
903                         if (ret < 0) {
904                                 pr_err("%s(): Error in allocating gpio "
905                                         "TEGRA_GPIO_PH7\n", __func__);
906                                 break;
907                         }
908                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
909                         tegra_gpio_enable(TEGRA_GPIO_PH7);
910                 }
911                 break;
912         case BOARD_E1186:
913                 tegra_gpio_enable(
914                         tegra_baseband_power_data.modem.xmm.bb_rst);
915                 tegra_gpio_enable(
916                         tegra_baseband_power_data.modem.xmm.bb_on);
917                 tegra_gpio_enable(
918                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
919                 tegra_gpio_enable(
920                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
921                 tegra_gpio_enable(
922                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
923                 tegra_gpio_enable(
924                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
925                 platform_device_register(&tegra_baseband_power_device);
926                 platform_device_register(&tegra_baseband_power2_device);
927                 break;
928         default:
929                 break;
930         }
931
932 }
933
934 #ifdef CONFIG_SATA_AHCI_TEGRA
935 static void cardhu_sata_init(void)
936 {
937         platform_device_register(&tegra_sata_device);
938 }
939 #else
940 static void cardhu_sata_init(void) { }
941 #endif
942
943 static void __init tegra_cardhu_init(void)
944 {
945         tegra_thermal_init(&thermal_data);
946         tegra_clk_init_from_table(cardhu_clk_init_table);
947         cardhu_pinmux_init();
948         cardhu_i2c_init();
949         cardhu_spi_init();
950         cardhu_usb_init();
951 #ifdef CONFIG_TEGRA_EDP_LIMITS
952         cardhu_edp_init();
953 #endif
954         cardhu_uart_init();
955         cardhu_tsensor_init();
956         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
957         cardhu_sdhci_init();
958         cardhu_regulator_init();
959         cardhu_gpio_switch_regulator_init();
960         cardhu_suspend_init();
961         cardhu_power_off_init();
962         cardhu_touch_init();
963         cardhu_gps_init();
964         cardhu_modem_init();
965         cardhu_kbc_init();
966         cardhu_scroll_init();
967         cardhu_keys_init();
968         cardhu_panel_init();
969         cardhu_pmon_init();
970         cardhu_sensors_init();
971         cardhu_bt_rfkill();
972         tegra_setup_bluesleep();
973         cardhu_sata_init();
974         //audio_wired_jack_init();
975         cardhu_pins_state_init();
976         cardhu_emc_init();
977         tegra_release_bootloader_fb();
978         cardhu_nfc_init();
979         cardhu_pci_init();
980 #ifdef CONFIG_TEGRA_WDT_RECOVERY
981         tegra_wdt_recovery_init();
982 #endif
983 }
984
985 static void __init tegra_cardhu_reserve(void)
986 {
987 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
988         /* support 1920X1200 with 24bpp */
989         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
990 #else
991         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
992 #endif
993 }
994
995 MACHINE_START(CARDHU, "cardhu")
996         .boot_params    = 0x80000100,
997         .map_io         = tegra_map_common_io,
998         .reserve        = tegra_cardhu_reserve,
999         .init_early     = tegra_init_early,
1000         .init_irq       = tegra_init_irq,
1001         .timer          = &tegra_timer,
1002         .init_machine   = tegra_cardhu_init,
1003 MACHINE_END