arm: tegra: cardhu: enable support for wifi
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "devices.h"
66 #include "gpio-names.h"
67 #include "fuse.h"
68 #include "pm.h"
69 #include "baseband-xmm-power.h"
70 #include "wdt-recovery.h"
71
72 static unsigned long ramconsole_start;
73 static unsigned long ramconsole_size;
74
75 /* All units are in millicelsius */
76 static struct tegra_thermal_data thermal_data = {
77         .temp_throttle = 85000,
78         .temp_shutdown = 90000,
79         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
80 #ifdef CONFIG_TEGRA_EDP_LIMITS
81         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
82         .hysteresis_edp = 3000,
83 #endif
84 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
85         .tc1 = 0,
86         .tc2 = 1,
87         .passive_delay = 2000,
88 #else
89         .hysteresis_throttle = 1000,
90 #endif
91 };
92
93 /* !!!TODO: Change for cardhu (Taken from Ventana) */
94 static struct tegra_utmip_config utmi_phy_config[] = {
95         [0] = {
96                         .hssync_start_delay = 0,
97                         .idle_wait_delay = 17,
98                         .elastic_limit = 16,
99                         .term_range_adj = 6,
100                         .xcvr_setup = 15,
101                         .xcvr_setup_offset = 0,
102                         .xcvr_use_fuses = 1,
103                         .xcvr_lsfslew = 2,
104                         .xcvr_lsrslew = 2,
105         },
106         [1] = {
107                         .hssync_start_delay = 0,
108                         .idle_wait_delay = 17,
109                         .elastic_limit = 16,
110                         .term_range_adj = 6,
111                         .xcvr_setup = 15,
112                         .xcvr_setup_offset = 0,
113                         .xcvr_use_fuses = 1,
114                         .xcvr_lsfslew = 2,
115                         .xcvr_lsrslew = 2,
116         },
117         [2] = {
118                         .hssync_start_delay = 0,
119                         .idle_wait_delay = 17,
120                         .elastic_limit = 16,
121                         .term_range_adj = 6,
122                         .xcvr_setup = 8,
123                         .xcvr_setup_offset = 0,
124                         .xcvr_use_fuses = 1,
125                         .xcvr_lsfslew = 2,
126                         .xcvr_lsrslew = 2,
127         },
128 };
129
130 #ifdef CONFIG_BCM4329_RFKILL
131 static struct resource cardhu_bcm4329_rfkill_resources[] = {
132         {
133                 .name   = "bcm4329_nshutdown_gpio",
134                 .start  = TEGRA_GPIO_PU0,
135                 .end    = TEGRA_GPIO_PU0,
136                 .flags  = IORESOURCE_IO,
137         },
138 };
139
140 static struct platform_device cardhu_bcm4329_rfkill_device = {
141         .name = "bcm4329_rfkill",
142         .id             = -1,
143         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
144         .resource       = cardhu_bcm4329_rfkill_resources,
145 };
146
147 static noinline void __init cardhu_bt_rfkill(void)
148 {
149         platform_device_register(&cardhu_bcm4329_rfkill_device);
150
151         return;
152 }
153 #else
154 static inline void cardhu_bt_rfkill(void) { }
155 #endif
156
157 #ifdef CONFIG_BT_BLUESLEEP
158 static noinline void __init tegra_setup_bluesleep(void)
159 {
160         struct platform_device *pdev = NULL;
161         struct resource *res;
162
163         pdev = platform_device_alloc("bluesleep", 0);
164         if (!pdev) {
165                 pr_err("unable to allocate platform device for bluesleep");
166                 return;
167         }
168
169         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
170         if (!res) {
171                 pr_err("unable to allocate resource for bluesleep\n");
172                 goto err_free_dev;
173         }
174
175         res[0].name   = "gpio_host_wake";
176         res[0].start  = TEGRA_GPIO_PU6;
177         res[0].end    = TEGRA_GPIO_PU6;
178         res[0].flags  = IORESOURCE_IO;
179
180         res[1].name   = "gpio_ext_wake";
181         res[1].start  = TEGRA_GPIO_PU1;
182         res[1].end    = TEGRA_GPIO_PU1;
183         res[1].flags  = IORESOURCE_IO;
184
185         res[2].name   = "host_wake";
186         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
187         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
188         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
189
190         if (platform_device_add_resources(pdev, res, 3)) {
191                 pr_err("unable to add resources to bluesleep device\n");
192                 goto err_free_res;
193         }
194
195         if (platform_device_add(pdev)) {
196                 pr_err("unable to add bluesleep device\n");
197                 goto err_free_res;
198         }
199         tegra_gpio_enable(TEGRA_GPIO_PU6);
200         tegra_gpio_enable(TEGRA_GPIO_PU1);
201
202 return;
203
204 err_free_res:
205         kfree(res);
206 err_free_dev:
207         platform_device_put(pdev);
208         return;
209 }
210 #else
211 static inline void tegra_setup_bluesleep(void) { }
212 #endif
213
214 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
215         /* name         parent          rate            enabled */
216         { "pll_m",      NULL,           0,              false},
217         { "hda",        "pll_p",        108000000,      false},
218         { "hda2codec_2x","pll_p",       48000000,       false},
219         { "pwm",        "pll_p",        3187500,        false},
220         { "blink",      "clk_32k",      32768,          true},
221         { "i2s0",       "pll_a_out0",   0,              false},
222         { "i2s1",       "pll_a_out0",   0,              false},
223         { "i2s3",       "pll_a_out0",   0,              false},
224         { "spdif_out",  "pll_a_out0",   0,              false},
225         { "d_audio",    "clk_m",        12000000,       false},
226         { "dam0",       "clk_m",        12000000,       false},
227         { "dam1",       "clk_m",        12000000,       false},
228         { "dam2",       "clk_m",        12000000,       false},
229         { "audio1",     "i2s1_sync",    0,              false},
230         { "audio3",     "i2s3_sync",    0,              false},
231         { "sdmmc3",     "clk_m",        12000000,       true},
232         { "vi_sensor",  "pll_p",        150000000,      false},
233         { "i2c1",       "pll_p",        3200000,        false},
234         { "i2c2",       "pll_p",        3200000,        false},
235         { "i2c3",       "pll_p",        3200000,        false},
236         { "i2c4",       "pll_p",        3200000,        false},
237         { "i2c5",       "pll_p",        3200000,        false},
238         { NULL,         NULL,           0,              0},
239 };
240
241 static struct pn544_i2c_platform_data nfc_pdata = {
242         .irq_gpio = TEGRA_GPIO_PX0,
243         .ven_gpio = TEGRA_GPIO_PP3,
244         .firm_gpio = TEGRA_GPIO_PO7,
245         };
246
247 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
248         {
249                 I2C_BOARD_INFO("pn544", 0x28),
250                 .platform_data = &nfc_pdata,
251                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
252         },
253 };
254 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
255         .adapter_nr     = 0,
256         .bus_count      = 1,
257         .bus_clk_rate   = { 100000, 0 },
258         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
259         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
260         .arb_recovery = arb_lost_recovery,
261 };
262
263 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
264         .adapter_nr     = 1,
265         .bus_count      = 1,
266         .bus_clk_rate   = { 100000, 0 },
267         .is_clkon_always = true,
268         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
269         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
270         .arb_recovery = arb_lost_recovery,
271 };
272
273 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
274         .adapter_nr     = 2,
275         .bus_count      = 1,
276         .bus_clk_rate   = { 100000, 0 },
277         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
278         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
279         .arb_recovery = arb_lost_recovery,
280 };
281
282 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
283         .adapter_nr     = 3,
284         .bus_count      = 1,
285         .bus_clk_rate   = { 100000, 0 },
286         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
287         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
288         .arb_recovery = arb_lost_recovery,
289 };
290
291 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
292         .adapter_nr     = 4,
293         .bus_count      = 1,
294         .bus_clk_rate   = { 400000, 0 },
295         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
296         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
297         .arb_recovery = arb_lost_recovery,
298 };
299
300
301 #if 0
302 struct tegra_wired_jack_conf audio_wr_jack_conf = {
303         .hp_det_n = TEGRA_GPIO_PW2,
304         .en_mic_ext = TEGRA_GPIO_PX1,
305         .en_mic_int = TEGRA_GPIO_PX0,
306 };
307 #endif
308
309 static struct wm8903_platform_data cardhu_wm8903_pdata = {
310         .irq_active_low = 0,
311         .micdet_cfg = 0,
312         .micdet_delay = 100,
313         .gpio_base = CARDHU_GPIO_WM8903(0),
314         .gpio_cfg = {
315                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
316                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
317                         WM8903_GP2_DIR,
318                 0,
319                 WM8903_GPIO_NO_CONFIG,
320                 WM8903_GPIO_NO_CONFIG,
321         },
322 };
323
324 /* Equalizer filter coefs generated from the MAXIM MAX98095
325  * evkit software tool */
326 static struct max98095_eq_cfg max98095_eq_cfg[] = {
327         {
328                 .name = "FLAT",
329                 .rate = 44100,
330                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
331                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
332                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
333                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
334                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
335         },
336         {
337                 .name = "LOWPASS1K",
338                 .rate = 44100,
339                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
340                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
341                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
342                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
343                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
344         },
345         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
346                 .name = "HIBOOST",
347                 .rate = 44100,
348                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
349                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
350                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
351                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
352                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
353         },
354         { /* BASS=12dB, TREBLE=+12dB */
355                 .name = "LOUD12DB",
356                 .rate = 44100,
357                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
358                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
359                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
360                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
361                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
362         },
363         {
364                 .name = "FLAT",
365                 .rate = 16000,
366                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
367                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
368                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
369                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
370                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
371         },
372         {
373                 .name = "LOWPASS1K",
374                 .rate = 16000,
375                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
376                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
377                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
378                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
379                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
380         },
381         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
382                 .name = "HIBOOST",
383                 .rate = 16000,
384                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
385                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
386                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
387                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
388                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
389         },
390         { /* BASS=12dB, TREBLE=+12dB */
391                 .name = "LOUD12DB",
392                 .rate = 16000,
393                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
394                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
395                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
396                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
397                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
398         },
399 };
400
401 static struct max98095_pdata cardhu_max98095_pdata = {
402         /* equalizer configuration */
403         .eq_cfg = max98095_eq_cfg,
404         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
405
406         /* Biquad filter response configuration */
407         .bq_cfg = NULL,
408         .bq_cfgcnt = 0,
409
410         /* microphone configuration */
411         .digmic_left_mode = 1,
412         .digmic_right_mode = 1,
413 };
414
415 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
416         I2C_BOARD_INFO("wm8903", 0x1a),
417         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
418         .platform_data = &cardhu_wm8903_pdata,
419 };
420
421 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
422         I2C_BOARD_INFO("aic3262-codec", 0x18),
423         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
424 };
425
426 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
427         I2C_BOARD_INFO("max98095", 0x10),
428         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
429         .platform_data = &cardhu_max98095_pdata,
430 };
431
432 static void cardhu_i2c_init(void)
433 {
434         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
435         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
436         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
437         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
438         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
439
440         platform_device_register(&tegra_i2c_device5);
441         platform_device_register(&tegra_i2c_device4);
442         platform_device_register(&tegra_i2c_device3);
443         platform_device_register(&tegra_i2c_device2);
444         platform_device_register(&tegra_i2c_device1);
445
446         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
447         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
448         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
449
450         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
451 }
452
453 static struct platform_device *cardhu_uart_devices[] __initdata = {
454         &tegra_uarta_device,
455         &tegra_uartb_device,
456         &tegra_uartc_device,
457         &tegra_uartd_device,
458         &tegra_uarte_device,
459 };
460 static struct uart_clk_parent uart_parent_clk[] = {
461         [0] = {.name = "clk_m"},
462         [1] = {.name = "pll_p"},
463 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
464         [2] = {.name = "pll_m"},
465 #endif
466 };
467
468 static struct tegra_uart_platform_data cardhu_uart_pdata;
469 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
470
471 static void __init uart_debug_init(void)
472 {
473         struct board_info board_info;
474         int debug_port_id;
475
476         tegra_get_board_info(&board_info);
477
478         debug_port_id = get_tegra_uart_debug_port_id();
479         if (debug_port_id < 0) {
480                 debug_port_id = 0;
481                         /* UARTB is debug port
482                          *       for SLT - E1186/E1187/PM269
483                          *       for E1256/E1257
484                          */
485                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
486                         ((board_info.board_id == BOARD_E1186) ||
487                         (board_info.board_id == BOARD_E1187) ||
488                         (board_info.board_id == BOARD_PM269))) ||
489                         (board_info.board_id == BOARD_E1256) ||
490                         (board_info.board_id == BOARD_E1257))
491                                 debug_port_id = 1;
492         }
493
494         switch (debug_port_id) {
495         case 0:
496                 /* UARTA is the debug port. */
497                 pr_info("Selecting UARTA as the debug console\n");
498                 cardhu_uart_devices[0] = &debug_uarta_device;
499                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
500                 debug_uart_port_base = ((struct plat_serial8250_port *)(
501                         debug_uarta_device.dev.platform_data))->mapbase;
502                 break;
503
504         case 1:
505                 /* UARTB is the debug port. */
506                 pr_info("Selecting UARTB as the debug console\n");
507                 cardhu_uart_devices[1] = &debug_uartb_device;
508                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
509                 debug_uart_port_base = ((struct plat_serial8250_port *)(
510                         debug_uartb_device.dev.platform_data))->mapbase;
511                 break;
512
513         case 2:
514                 /* UARTC is the debug port. */
515                 pr_info("Selecting UARTC as the debug console\n");
516                 cardhu_uart_devices[2] = &debug_uartc_device;
517                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
518                 debug_uart_port_base = ((struct plat_serial8250_port *)(
519                         debug_uartc_device.dev.platform_data))->mapbase;
520                 break;
521
522         case 3:
523                 /* UARTD is the debug port. */
524                 pr_info("Selecting UARTD as the debug console\n");
525                 cardhu_uart_devices[3] = &debug_uartd_device;
526                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
527                 debug_uart_port_base = ((struct plat_serial8250_port *)(
528                         debug_uartd_device.dev.platform_data))->mapbase;
529                 break;
530
531         case 4:
532                 /* UARTE is the debug port. */
533                 pr_info("Selecting UARTE as the debug console\n");
534                 cardhu_uart_devices[4] = &debug_uarte_device;
535                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
536                 debug_uart_port_base = ((struct plat_serial8250_port *)(
537                         debug_uarte_device.dev.platform_data))->mapbase;
538                 break;
539
540         default:
541                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
542                 cardhu_uart_devices[0] = &debug_uarta_device;
543                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
544                 debug_uart_port_base = ((struct plat_serial8250_port *)(
545                         debug_uarta_device.dev.platform_data))->mapbase;
546                 break;
547         }
548         return;
549 }
550
551 static void __init cardhu_uart_init(void)
552 {
553         struct clk *c;
554         int i;
555
556         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
557                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
558                 if (IS_ERR_OR_NULL(c)) {
559                         pr_err("Not able to get the clock for %s\n",
560                                                 uart_parent_clk[i].name);
561                         continue;
562                 }
563                 uart_parent_clk[i].parent_clk = c;
564                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
565         }
566         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
567         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
568         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
569         cardhu_loopback_uart_pdata.parent_clk_count =
570                                                 ARRAY_SIZE(uart_parent_clk);
571         cardhu_loopback_uart_pdata.is_loopback = true;
572         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
573         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
574         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
575         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
576         /* UARTE is used for loopback test purpose */
577         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
578
579         /* Register low speed only if it is selected */
580         if (!is_tegra_debug_uartport_hs()) {
581                 uart_debug_init();
582                 /* Clock enable for the debug channel */
583                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
584                         pr_info("The debug console clock name is %s\n",
585                                                 debug_uart_clk->name);
586                         c = tegra_get_clock_by_name("pll_p");
587                         if (IS_ERR_OR_NULL(c))
588                                 pr_err("Not getting the parent clock pll_p\n");
589                         else
590                                 clk_set_parent(debug_uart_clk, c);
591
592                         clk_enable(debug_uart_clk);
593                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
594                 } else {
595                         pr_err("Not getting the clock %s for debug console\n",
596                                         debug_uart_clk->name);
597                 }
598         }
599
600         platform_add_devices(cardhu_uart_devices,
601                                 ARRAY_SIZE(cardhu_uart_devices));
602 }
603
604 static struct platform_device tegra_camera = {
605         .name = "tegra_camera",
606         .id = -1,
607 };
608
609 static struct platform_device *cardhu_spi_devices[] __initdata = {
610         &tegra_spi_device4,
611 };
612
613 struct spi_clk_parent spi_parent_clk[] = {
614         [0] = {.name = "pll_p"},
615 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
616         [1] = {.name = "pll_m"},
617         [2] = {.name = "clk_m"},
618 #else
619         [1] = {.name = "clk_m"},
620 #endif
621 };
622
623 static struct tegra_spi_platform_data cardhu_spi_pdata = {
624         .is_dma_based           = true,
625         .max_dma_buffer         = (16 * 1024),
626         .is_clkon_always        = false,
627         .max_rate               = 100000000,
628 };
629
630 static void __init cardhu_spi_init(void)
631 {
632         int i;
633         struct clk *c;
634         struct board_info board_info;
635
636         tegra_get_board_info(&board_info);
637
638         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
639                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
640                 if (IS_ERR_OR_NULL(c)) {
641                         pr_err("Not able to get the clock for %s\n",
642                                                 spi_parent_clk[i].name);
643                         continue;
644                 }
645                 spi_parent_clk[i].parent_clk = c;
646                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
647         }
648         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
649         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
650         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
651         platform_add_devices(cardhu_spi_devices,
652                                 ARRAY_SIZE(cardhu_spi_devices));
653
654         if (board_info.board_id == BOARD_E1198) {
655                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
656                 platform_device_register(&tegra_spi_device2);
657                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
658                 platform_device_register(&tegra_spi_slave_device1);
659         }
660 }
661
662 static void __init cardhu_dtv_init(void)
663 {
664         struct board_info board_info;
665
666         tegra_get_board_info(&board_info);
667
668         if (board_info.board_id == BOARD_E1186)
669                 platform_device_register(&tegra_dtv_device);
670 }
671
672 static struct resource tegra_rtc_resources[] = {
673         [0] = {
674                 .start = TEGRA_RTC_BASE,
675                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
676                 .flags = IORESOURCE_MEM,
677         },
678         [1] = {
679                 .start = INT_RTC,
680                 .end = INT_RTC,
681                 .flags = IORESOURCE_IRQ,
682         },
683 };
684
685 static struct platform_device tegra_rtc_device = {
686         .name = "tegra_rtc",
687         .id   = -1,
688         .resource = tegra_rtc_resources,
689         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
690 };
691
692 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
693         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
694         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
695         .gpio_hp_mute           = -1,
696         .gpio_int_mic_en        = -1,
697         .gpio_ext_mic_en        = -1,
698 };
699
700 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
701         .gpio_spkr_en           = -1,
702         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
703         .gpio_hp_mute           = -1,
704         .gpio_int_mic_en        = -1,
705         .gpio_ext_mic_en        = -1,
706 };
707
708 static struct platform_device cardhu_audio_wm8903_device = {
709         .name   = "tegra-snd-wm8903",
710         .id     = 0,
711         .dev    = {
712                 .platform_data = &cardhu_audio_wm8903_pdata,
713         },
714 };
715
716 static struct platform_device cardhu_audio_max98095_device = {
717         .name   = "tegra-snd-max98095",
718         .id     = 0,
719         .dev    = {
720                 .platform_data = &cardhu_audio_max98095_pdata,
721         },
722 };
723
724 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
725         .gpio_spkr_en           = -1,
726         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
727         .gpio_hp_mute           = -1,
728         .gpio_int_mic_en        = -1,
729         .gpio_ext_mic_en        = -1,
730 };
731
732 static struct platform_device cardhu_audio_aic326x_device = {
733         .name   = "tegra-snd-aic326x",
734         .id     = 0,
735         .dev    = {
736                 .platform_data  = &cardhu_audio_aic326x_pdata,
737         },
738 };
739
740 static struct resource ram_console_resources[] = {
741         {
742                 .flags = IORESOURCE_MEM,
743         },
744 };
745
746 static struct platform_device ram_console_device = {
747         .name           = "ram_console",
748         .id             = -1,
749         .num_resources  = ARRAY_SIZE(ram_console_resources),
750         .resource       = ram_console_resources,
751 };
752
753 static struct platform_device *cardhu_devices[] __initdata = {
754         &tegra_pmu_device,
755         &tegra_rtc_device,
756         &tegra_udc_device,
757 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
758         &tegra_smmu_device,
759 #endif
760         &tegra_wdt_device,
761 #if defined(CONFIG_TEGRA_AVP)
762         &tegra_avp_device,
763 #endif
764         &tegra_camera,
765 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
766         &tegra_se_device,
767 #endif
768         &tegra_ahub_device,
769         &tegra_dam_device0,
770         &tegra_dam_device1,
771         &tegra_dam_device2,
772         &tegra_i2s_device0,
773         &tegra_i2s_device1,
774         &tegra_i2s_device3,
775         &tegra_spdif_device,
776         &spdif_dit_device,
777         &bluetooth_dit_device,
778         &baseband_dit_device,
779         &tegra_pcm_device,
780         &cardhu_audio_wm8903_device,
781         &cardhu_audio_max98095_device,
782         &cardhu_audio_aic326x_device,
783         &tegra_hda_device,
784 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
785         &tegra_aes_device,
786 #endif
787         &ram_console_device,
788 };
789
790 #define MXT_CONFIG_CRC  0xD62DE8
791 static const u8 config[] = {
792         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
793         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
794         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
795         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
796         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
797         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
798         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
799         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
800         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
801         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
802         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
803         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
804         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
805         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
806         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
810         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
811         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
812 };
813
814 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
815 static const u8 config_sku2000[] = {
816         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
817         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
818         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
819         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
820         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
821         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
822         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
823         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
824         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
825         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
826         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
827         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
828         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
829         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
830         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
832         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
833         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
834         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
835         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
836 };
837
838 static struct mxt_platform_data atmel_mxt_info = {
839         .x_line         = 27,
840         .y_line         = 42,
841         .x_size         = 768,
842         .y_size         = 1366,
843         .blen           = 0x20,
844         .threshold      = 0x3C,
845         .voltage        = 3300000,              /* 3.3V */
846         .orient         = 5,
847         .config         = config,
848         .config_length  = 157,
849         .config_crc     = MXT_CONFIG_CRC,
850         .irqflags       = IRQF_TRIGGER_FALLING,
851 /*      .read_chg       = &read_chg, */
852         .read_chg       = NULL,
853 };
854
855 static struct i2c_board_info __initdata atmel_i2c_info[] = {
856         {
857                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
858                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
859                 .platform_data = &atmel_mxt_info,
860         }
861 };
862
863 static int __init cardhu_touch_init(void)
864 {
865         struct board_info BoardInfo;
866
867         tegra_gpio_enable(TEGRA_GPIO_PH4);
868         tegra_gpio_enable(TEGRA_GPIO_PH6);
869
870         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
871         gpio_direction_input(TEGRA_GPIO_PH4);
872
873         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
874         gpio_direction_output(TEGRA_GPIO_PH6, 0);
875         msleep(1);
876         gpio_set_value(TEGRA_GPIO_PH6, 1);
877         msleep(100);
878
879         tegra_get_board_info(&BoardInfo);
880         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
881                 atmel_mxt_info.config = config_sku2000;
882                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
883         }
884
885         i2c_register_board_info(1, atmel_i2c_info, 1);
886
887         return 0;
888 }
889
890 static struct tegra_uhsic_config uhsic_phy_config = {
891         .enable_gpio = EN_HSIC_GPIO,
892         .reset_gpio = -1,
893         .sync_start_delay = 9,
894         .idle_wait_delay = 17,
895         .term_range_adj = 0,
896         .elastic_underrun_limit = 16,
897         .elastic_overrun_limit = 16,
898 };
899
900 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
901         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
902         .phy_config = &uhsic_phy_config,
903         .operating_mode = TEGRA_USB_HOST,
904         .power_down_on_bus_suspend = 1,
905         .default_enable = true,
906 };
907
908 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
909         [0] = {
910                         .phy_config = &utmi_phy_config[0],
911                         .operating_mode = TEGRA_USB_HOST,
912                         .power_down_on_bus_suspend = 1,
913                         .default_enable = true,
914         },
915         [1] = {
916                         .phy_config = &utmi_phy_config[1],
917                         .operating_mode = TEGRA_USB_HOST,
918                         .power_down_on_bus_suspend = 1,
919                         .default_enable = true,
920         },
921         [2] = {
922                         .phy_config = &utmi_phy_config[2],
923                         .operating_mode = TEGRA_USB_HOST,
924                         .power_down_on_bus_suspend = 1,
925                         .hotplug = 1,
926                         .default_enable = true,
927         },
928 };
929
930 static struct tegra_otg_platform_data tegra_otg_pdata = {
931         .ehci_device = &tegra_ehci1_device,
932         .ehci_pdata = &tegra_ehci_pdata[0],
933 };
934
935 #ifdef CONFIG_USB_SUPPORT
936 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
937         [0] = {
938                         .instance = 0,
939                         .vbus_gpio = -1,
940                         .vbus_reg_supply = "vdd_vbus_micro_usb",
941         },
942         [1] = {
943                         .instance = 1,
944                         .vbus_gpio = -1,
945         },
946         [2] = {
947                         .instance = 2,
948                         .vbus_gpio = -1,
949                         .vbus_reg_supply = "vdd_vbus_typea_usb",
950         },
951 };
952
953 static int cardu_usb_hsic_postsupend(void)
954 {
955         baseband_xmm_set_power_status(BBXMM_PS_L2);
956         return 0;
957 }
958
959 static int cardu_usb_hsic_preresume(void)
960 {
961         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
962         return 0;
963 }
964
965 static void cardhu_usb_init(void)
966 {
967         struct board_info bi;
968
969         tegra_get_board_info(&bi);
970
971         tegra_usb_phy_init(tegra_usb_phy_pdata,
972                         ARRAY_SIZE(tegra_usb_phy_pdata));
973
974         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
975         platform_device_register(&tegra_otg_device);
976         if (bi.board_id == BOARD_PM267) {
977                 uhsic_phy_config.reset_gpio =
978                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
979                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
980                 platform_device_register(&tegra_ehci2_device);
981         } else if (bi.board_id == BOARD_E1256) {
982                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
983                 platform_device_register(&tegra_ehci2_device);
984         } else if (bi.board_id == BOARD_E1186) {
985                 /* for baseband devices do not switch off phy during suspend */
986                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
987                 uhsic_phy_config.postsuspend = cardu_usb_hsic_postsupend;
988                 uhsic_phy_config.preresume = cardu_usb_hsic_preresume;
989                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
990                 /* baseband registration happens in baseband-xmm-power  */
991         } else {
992                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
993                 platform_device_register(&tegra_ehci2_device);
994         }
995
996         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
997         platform_device_register(&tegra_ehci3_device);
998
999 }
1000 #else
1001 static void cardhu_usb_init(void) { }
1002 #endif
1003
1004 static void cardhu_gps_init(void)
1005 {
1006         tegra_gpio_enable(TEGRA_GPIO_PU2);
1007         tegra_gpio_enable(TEGRA_GPIO_PU3);
1008 }
1009
1010 static void cardhu_nfc_init(void)
1011 {
1012         tegra_gpio_enable(TEGRA_GPIO_PX0);
1013         tegra_gpio_enable(TEGRA_GPIO_PP3);
1014         tegra_gpio_enable(TEGRA_GPIO_PO7);
1015 }
1016
1017 static struct baseband_power_platform_data tegra_baseband_power_data = {
1018         .baseband_type = BASEBAND_XMM,
1019         .modem = {
1020         .xmm = {
1021                         .bb_rst = XMM_GPIO_BB_RST,
1022                         .bb_on = XMM_GPIO_BB_ON,
1023                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1024                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1025                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1026                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1027                         .hsic_device = &tegra_ehci2_device,
1028                 },
1029         },
1030 };
1031
1032 static struct platform_device tegra_baseband_power_device = {
1033         .name = "baseband_xmm_power",
1034         .id = -1,
1035         .dev = {
1036                 .platform_data = &tegra_baseband_power_data,
1037         },
1038 };
1039
1040 static struct platform_device tegra_baseband_power2_device = {
1041         .name = "baseband_xmm_power2",
1042         .id = -1,
1043         .dev = {
1044                 .platform_data = &tegra_baseband_power_data,
1045         },
1046 };
1047
1048
1049 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1050         .port_status[0] = 1,
1051         .port_status[1] = 1,
1052         .port_status[2] = 1,
1053         .use_dock_detect        = 0,
1054         .gpio           = 0,
1055 };
1056
1057 static void cardhu_pci_init(void)
1058 {
1059         struct board_info board_info;
1060
1061         tegra_get_board_info(&board_info);
1062         if (board_info.board_id == BOARD_E1291) {
1063                 cardhu_pci_platform_data.port_status[0] = 0;
1064                 cardhu_pci_platform_data.port_status[1] = 0;
1065                 cardhu_pci_platform_data.port_status[2] = 1;
1066                 cardhu_pci_platform_data.use_dock_detect = 1;
1067                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1068         }
1069         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1070         platform_device_register(&tegra_pci_device);
1071 }
1072
1073 static void cardhu_modem_init(void)
1074 {
1075         struct board_info board_info;
1076         int w_disable_gpio, ret;
1077
1078         tegra_get_board_info(&board_info);
1079         switch (board_info.board_id) {
1080         case BOARD_E1291:
1081         case BOARD_E1198:
1082                 if (((board_info.board_id == BOARD_E1291) &&
1083                                 (board_info.fab < BOARD_FAB_A03)) ||
1084                         ((board_info.board_id == BOARD_E1198) &&
1085                                         (board_info.fab < BOARD_FAB_A02))) {
1086                         w_disable_gpio = TEGRA_GPIO_PH5;
1087                 } else {
1088                         w_disable_gpio = TEGRA_GPIO_PDD5;
1089                 }
1090                 tegra_gpio_enable(w_disable_gpio);
1091                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1092                 if (ret < 0)
1093                         pr_err("%s: gpio_request failed for gpio %d\n",
1094                                 __func__, w_disable_gpio);
1095                 else
1096                         gpio_direction_input(w_disable_gpio);
1097
1098                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1099                 if (((board_info.board_id == BOARD_E1291) &&
1100                                 (board_info.fab >= BOARD_FAB_A04)) ||
1101                         ((board_info.board_id == BOARD_E1198) &&
1102                                         (board_info.fab >= BOARD_FAB_A02))) {
1103                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1104                         if (ret < 0) {
1105                                 pr_err("%s(): Error in allocating gpio "
1106                                         "TEGRA_GPIO_PH7\n", __func__);
1107                                 break;
1108                         }
1109                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1110                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1111                 }
1112                 break;
1113         case BOARD_E1186:
1114                 tegra_gpio_enable(
1115                         tegra_baseband_power_data.modem.xmm.bb_rst);
1116                 tegra_gpio_enable(
1117                         tegra_baseband_power_data.modem.xmm.bb_on);
1118                 tegra_gpio_enable(
1119                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1120                 tegra_gpio_enable(
1121                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1122                 tegra_gpio_enable(
1123                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1124                 tegra_gpio_enable(
1125                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1126                 platform_device_register(&tegra_baseband_power_device);
1127                 platform_device_register(&tegra_baseband_power2_device);
1128                 break;
1129         default:
1130                 break;
1131         }
1132
1133 }
1134
1135 #ifdef CONFIG_SATA_AHCI_TEGRA
1136 static void cardhu_sata_init(void)
1137 {
1138         platform_device_register(&tegra_sata_device);
1139 }
1140 #else
1141 static void cardhu_sata_init(void) { }
1142 #endif
1143
1144 static void cardhu_ramconsole_init(void)
1145 {
1146         struct resource *res;
1147         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
1148         res->start = ramconsole_start;
1149         res->end = res->start + ramconsole_size - 1;
1150 }
1151
1152 static void __init tegra_cardhu_init(void)
1153 {
1154         tegra_thermal_init(&thermal_data);
1155         tegra_clk_init_from_table(cardhu_clk_init_table);
1156         cardhu_pinmux_init();
1157         cardhu_i2c_init();
1158         cardhu_spi_init();
1159         cardhu_usb_init();
1160 #ifdef CONFIG_TEGRA_EDP_LIMITS
1161         cardhu_edp_init();
1162 #endif
1163         cardhu_uart_init();
1164         cardhu_ramconsole_init();
1165         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1166         cardhu_sdhci_init();
1167         cardhu_regulator_init();
1168         cardhu_dtv_init();
1169         cardhu_suspend_init();
1170         cardhu_touch_init();
1171         cardhu_gps_init();
1172         cardhu_modem_init();
1173         cardhu_kbc_init();
1174         cardhu_scroll_init();
1175         cardhu_keys_init();
1176         cardhu_panel_init();
1177         cardhu_pmon_init();
1178         cardhu_sensors_init();
1179         cardhu_bt_rfkill();
1180         tegra_setup_bluesleep();
1181         cardhu_sata_init();
1182         //audio_wired_jack_init();
1183         cardhu_pins_state_init();
1184         cardhu_emc_init();
1185         tegra_release_bootloader_fb();
1186         cardhu_nfc_init();
1187         cardhu_pci_init();
1188 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1189         tegra_wdt_recovery_init();
1190 #endif
1191 }
1192
1193 static void __init tegra_cardhu_reserve(void)
1194 {
1195         long ret;
1196         ramconsole_size = SZ_1M;
1197         ramconsole_start = memblock_end_of_DRAM() - ramconsole_size;
1198         ret = memblock_remove(ramconsole_start, ramconsole_size);
1199         if (ret) {
1200                 ramconsole_size = 0;
1201                 pr_err("Failed to reserve memory block for ram console\n");
1202         }
1203
1204 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1205         /* support 1920X1200 with 24bpp */
1206         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1207 #else
1208         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1209 #endif
1210 }
1211
1212 MACHINE_START(CARDHU, "cardhu")
1213         .boot_params    = 0x80000100,
1214         .map_io         = tegra_map_common_io,
1215         .reserve        = tegra_cardhu_reserve,
1216         .init_early     = tegra_init_early,
1217         .init_irq       = tegra_init_irq,
1218         .timer          = &tegra_timer,
1219         .init_machine   = tegra_cardhu_init,
1220 MACHINE_END