ARM: tegra: cardhu: Remove tegra_gpio_enb/disable
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "board-touch.h"
66 #include "devices.h"
67 #include "gpio-names.h"
68 #include "fuse.h"
69 #include "pm.h"
70 #include "baseband-xmm-power.h"
71 #include "wdt-recovery.h"
72
73 /* All units are in millicelsius */
74 static struct tegra_thermal_data thermal_data = {
75         .temp_shutdown = 90000,
76         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
77 #ifdef CONFIG_TEGRA_EDP_LIMITS
78         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
79         .hysteresis_edp = 3000,
80 #endif
81 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
82         .temp_throttle = 85000,
83         .tc1 = 0,
84         .tc2 = 1,
85         .passive_delay = 2000,
86 #endif
87 };
88
89 static struct resource cardhu_bcm4329_rfkill_resources[] = {
90         {
91                 .name   = "bcm4329_nshutdown_gpio",
92                 .start  = TEGRA_GPIO_PU0,
93                 .end    = TEGRA_GPIO_PU0,
94                 .flags  = IORESOURCE_IO,
95         },
96 };
97
98 static struct platform_device cardhu_bcm4329_rfkill_device = {
99         .name = "bcm4329_rfkill",
100         .id             = -1,
101         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
102         .resource       = cardhu_bcm4329_rfkill_resources,
103 };
104
105 static struct resource cardhu_bluesleep_resources[] = {
106         [0] = {
107                 .name = "gpio_host_wake",
108                         .start  = TEGRA_GPIO_PU6,
109                         .end    = TEGRA_GPIO_PU6,
110                         .flags  = IORESOURCE_IO,
111         },
112         [1] = {
113                 .name = "gpio_ext_wake",
114                         .start  = TEGRA_GPIO_PU1,
115                         .end    = TEGRA_GPIO_PU1,
116                         .flags  = IORESOURCE_IO,
117         },
118         [2] = {
119                 .name = "host_wake",
120                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
121                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
122                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
123         },
124 };
125
126 static struct platform_device cardhu_bluesleep_device = {
127         .name           = "bluesleep",
128         .id             = -1,
129         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
130         .resource       = cardhu_bluesleep_resources,
131 };
132
133 static noinline void __init cardhu_setup_bluesleep(void)
134 {
135         platform_device_register(&cardhu_bluesleep_device);
136         return;
137 }
138
139 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
140         /* name         parent          rate            enabled */
141         { "pll_m",      NULL,           0,              false},
142         { "hda",        "pll_p",        108000000,      false},
143         { "hda2codec_2x","pll_p",       48000000,       false},
144         { "pwm",        "pll_p",        3187500,        false},
145         { "blink",      "clk_32k",      32768,          true},
146         { "i2s0",       "pll_a_out0",   0,              false},
147         { "i2s1",       "pll_a_out0",   0,              false},
148         { "i2s3",       "pll_a_out0",   0,              false},
149         { "spdif_out",  "pll_a_out0",   0,              false},
150         { "d_audio",    "clk_m",        12000000,       false},
151         { "dam0",       "clk_m",        12000000,       false},
152         { "dam1",       "clk_m",        12000000,       false},
153         { "dam2",       "clk_m",        12000000,       false},
154         { "audio1",     "i2s1_sync",    0,              false},
155         { "audio3",     "i2s3_sync",    0,              false},
156         { "vi_sensor",  "pll_p",        150000000,      false},
157         { "i2c1",       "pll_p",        3200000,        false},
158         { "i2c2",       "pll_p",        3200000,        false},
159         { "i2c3",       "pll_p",        3200000,        false},
160         { "i2c4",       "pll_p",        3200000,        false},
161         { "i2c5",       "pll_p",        3200000,        false},
162         { NULL,         NULL,           0,              0},
163 };
164
165 static struct pn544_i2c_platform_data nfc_pdata = {
166         .irq_gpio = TEGRA_GPIO_PX0,
167         .ven_gpio = TEGRA_GPIO_PP3,
168         .firm_gpio = TEGRA_GPIO_PO7,
169         };
170
171 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
172         {
173                 I2C_BOARD_INFO("pn544", 0x28),
174                 .platform_data = &nfc_pdata,
175                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
176         },
177 };
178 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
179         .adapter_nr     = 0,
180         .bus_count      = 1,
181         .bus_clk_rate   = { 100000, 0 },
182         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
183         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
184         .arb_recovery = arb_lost_recovery,
185 };
186
187 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
188         .adapter_nr     = 1,
189         .bus_count      = 1,
190         .bus_clk_rate   = { 400000, 0 },
191         .is_clkon_always = true,
192         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
193         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
194         .arb_recovery = arb_lost_recovery,
195 };
196
197 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
198         .adapter_nr     = 2,
199         .bus_count      = 1,
200         .bus_clk_rate   = { 100000, 0 },
201         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
202         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
203         .arb_recovery = arb_lost_recovery,
204 };
205
206 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
207         .adapter_nr     = 3,
208         .bus_count      = 1,
209         .bus_clk_rate   = { 10000, 0 },
210         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
211         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
212         .arb_recovery = arb_lost_recovery,
213 };
214
215 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
216         .adapter_nr     = 4,
217         .bus_count      = 1,
218         .bus_clk_rate   = { 400000, 0 },
219         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
220         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
221         .arb_recovery = arb_lost_recovery,
222 };
223
224
225 #if 0
226 struct tegra_wired_jack_conf audio_wr_jack_conf = {
227         .hp_det_n = TEGRA_GPIO_PW2,
228         .en_mic_ext = TEGRA_GPIO_PX1,
229         .en_mic_int = TEGRA_GPIO_PX0,
230 };
231 #endif
232
233 static struct wm8903_platform_data cardhu_wm8903_pdata = {
234         .irq_active_low = 0,
235         .micdet_cfg = 0,
236         .micdet_delay = 100,
237         .gpio_base = CARDHU_GPIO_WM8903(0),
238         .gpio_cfg = {
239                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
240                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
241                         WM8903_GP2_DIR,
242                 0,
243                 WM8903_GPIO_NO_CONFIG,
244                 WM8903_GPIO_NO_CONFIG,
245         },
246 };
247
248 /* Equalizer filter coefs generated from the MAXIM MAX98095
249  * evkit software tool */
250 static struct max98095_eq_cfg max98095_eq_cfg[] = {
251         {
252                 .name = "FLAT",
253                 .rate = 44100,
254                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
255                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
256                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
257                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
258                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
259         },
260         {
261                 .name = "LOWPASS1K",
262                 .rate = 44100,
263                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
264                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
265                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
266                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
267                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
268         },
269         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
270                 .name = "HIBOOST",
271                 .rate = 44100,
272                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
273                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
274                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
275                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
276                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
277         },
278         { /* BASS=12dB, TREBLE=+12dB */
279                 .name = "LOUD12DB",
280                 .rate = 44100,
281                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
282                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
283                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
284                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
285                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
286         },
287         {
288                 .name = "FLAT",
289                 .rate = 16000,
290                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
291                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
292                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
293                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
294                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
295         },
296         {
297                 .name = "LOWPASS1K",
298                 .rate = 16000,
299                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
300                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
301                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
302                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
303                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
304         },
305         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
306                 .name = "HIBOOST",
307                 .rate = 16000,
308                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
309                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
310                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
311                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
312                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
313         },
314         { /* BASS=12dB, TREBLE=+12dB */
315                 .name = "LOUD12DB",
316                 .rate = 16000,
317                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
318                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
319                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
320                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
321                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
322         },
323 };
324
325 static struct max98095_pdata cardhu_max98095_pdata = {
326         /* equalizer configuration */
327         .eq_cfg = max98095_eq_cfg,
328         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
329
330         /* Biquad filter response configuration */
331         .bq_cfg = NULL,
332         .bq_cfgcnt = 0,
333
334         /* microphone configuration */
335         .digmic_left_mode = 1,
336         .digmic_right_mode = 1,
337 };
338
339 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
340         I2C_BOARD_INFO("wm8903", 0x1a),
341         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
342         .platform_data = &cardhu_wm8903_pdata,
343 };
344
345 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
346         I2C_BOARD_INFO("aic3262-codec", 0x18),
347         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
348 };
349
350 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
351         I2C_BOARD_INFO("max98095", 0x10),
352         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
353         .platform_data = &cardhu_max98095_pdata,
354 };
355
356 static void cardhu_i2c_init(void)
357 {
358         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
359         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
360         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
361         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
362         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
363
364         platform_device_register(&tegra_i2c_device5);
365         platform_device_register(&tegra_i2c_device4);
366         platform_device_register(&tegra_i2c_device3);
367         platform_device_register(&tegra_i2c_device2);
368         platform_device_register(&tegra_i2c_device1);
369
370         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
371         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
372         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
373
374         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
375 }
376
377 static struct platform_device *cardhu_uart_devices[] __initdata = {
378         &tegra_uarta_device,
379         &tegra_uartb_device,
380         &tegra_uartc_device,
381         &tegra_uartd_device,
382         &tegra_uarte_device,
383 };
384 static struct uart_clk_parent uart_parent_clk[] = {
385         [0] = {.name = "clk_m"},
386         [1] = {.name = "pll_p"},
387 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
388         [2] = {.name = "pll_m"},
389 #endif
390 };
391
392 static struct tegra_uart_platform_data cardhu_uart_pdata;
393 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
394
395 static void __init uart_debug_init(void)
396 {
397         struct board_info board_info;
398         int debug_port_id;
399
400         tegra_get_board_info(&board_info);
401
402         debug_port_id = get_tegra_uart_debug_port_id();
403         if (debug_port_id < 0) {
404                 debug_port_id = 0;
405                         /* UARTB is debug port
406                          *       for SLT - E1186/E1187/PM269
407                          *       for E1256/E1257
408                          */
409                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
410                         ((board_info.board_id == BOARD_E1186) ||
411                         (board_info.board_id == BOARD_E1187) ||
412                         (board_info.board_id == BOARD_PM269))) ||
413                         (board_info.board_id == BOARD_E1256) ||
414                         (board_info.board_id == BOARD_E1257))
415                                 debug_port_id = 1;
416         }
417
418         switch (debug_port_id) {
419         case 0:
420                 /* UARTA is the debug port. */
421                 pr_info("Selecting UARTA as the debug console\n");
422                 cardhu_uart_devices[0] = &debug_uarta_device;
423                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
424                 debug_uart_port_base = ((struct plat_serial8250_port *)(
425                         debug_uarta_device.dev.platform_data))->mapbase;
426                 break;
427
428         case 1:
429                 /* UARTB is the debug port. */
430                 pr_info("Selecting UARTB as the debug console\n");
431                 cardhu_uart_devices[1] = &debug_uartb_device;
432                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
433                 debug_uart_port_base = ((struct plat_serial8250_port *)(
434                         debug_uartb_device.dev.platform_data))->mapbase;
435                 break;
436
437         case 2:
438                 /* UARTC is the debug port. */
439                 pr_info("Selecting UARTC as the debug console\n");
440                 cardhu_uart_devices[2] = &debug_uartc_device;
441                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
442                 debug_uart_port_base = ((struct plat_serial8250_port *)(
443                         debug_uartc_device.dev.platform_data))->mapbase;
444                 break;
445
446         case 3:
447                 /* UARTD is the debug port. */
448                 pr_info("Selecting UARTD as the debug console\n");
449                 cardhu_uart_devices[3] = &debug_uartd_device;
450                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
451                 debug_uart_port_base = ((struct plat_serial8250_port *)(
452                         debug_uartd_device.dev.platform_data))->mapbase;
453                 break;
454
455         case 4:
456                 /* UARTE is the debug port. */
457                 pr_info("Selecting UARTE as the debug console\n");
458                 cardhu_uart_devices[4] = &debug_uarte_device;
459                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
460                 debug_uart_port_base = ((struct plat_serial8250_port *)(
461                         debug_uarte_device.dev.platform_data))->mapbase;
462                 break;
463
464         default:
465                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
466                 cardhu_uart_devices[0] = &debug_uarta_device;
467                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
468                 debug_uart_port_base = ((struct plat_serial8250_port *)(
469                         debug_uarta_device.dev.platform_data))->mapbase;
470                 break;
471         }
472         return;
473 }
474
475 static void __init cardhu_uart_init(void)
476 {
477         struct clk *c;
478         int i;
479
480         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
481                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
482                 if (IS_ERR_OR_NULL(c)) {
483                         pr_err("Not able to get the clock for %s\n",
484                                                 uart_parent_clk[i].name);
485                         continue;
486                 }
487                 uart_parent_clk[i].parent_clk = c;
488                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
489         }
490         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
491         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
492         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
493         cardhu_loopback_uart_pdata.parent_clk_count =
494                                                 ARRAY_SIZE(uart_parent_clk);
495         cardhu_loopback_uart_pdata.is_loopback = true;
496         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
497         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
498         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
499         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
500         /* UARTE is used for loopback test purpose */
501         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
502
503         /* Register low speed only if it is selected */
504         if (!is_tegra_debug_uartport_hs()) {
505                 uart_debug_init();
506                 /* Clock enable for the debug channel */
507                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
508                         pr_info("The debug console clock name is %s\n",
509                                                 debug_uart_clk->name);
510                         c = tegra_get_clock_by_name("pll_p");
511                         if (IS_ERR_OR_NULL(c))
512                                 pr_err("Not getting the parent clock pll_p\n");
513                         else
514                                 clk_set_parent(debug_uart_clk, c);
515
516                         clk_enable(debug_uart_clk);
517                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
518                 } else {
519                         pr_err("Not getting the clock %s for debug console\n",
520                                         debug_uart_clk->name);
521                 }
522         }
523
524         platform_add_devices(cardhu_uart_devices,
525                                 ARRAY_SIZE(cardhu_uart_devices));
526 }
527
528 static struct platform_device tegra_camera = {
529         .name = "tegra_camera",
530         .id = -1,
531 };
532
533 static struct platform_device *cardhu_spi_devices[] __initdata = {
534         &tegra_spi_device4,
535 };
536
537 static struct platform_device *touch_spi_device[] __initdata = {
538         &tegra_spi_device1,
539 };
540
541 struct spi_clk_parent spi_parent_clk[] = {
542         [0] = {.name = "pll_p"},
543 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
544         [1] = {.name = "pll_m"},
545         [2] = {.name = "clk_m"},
546 #else
547         [1] = {.name = "clk_m"},
548 #endif
549 };
550
551 static struct tegra_spi_platform_data cardhu_spi_pdata = {
552         .is_dma_based           = true,
553         .max_dma_buffer         = (16 * 1024),
554         .is_clkon_always        = false,
555         .max_rate               = 100000000,
556 };
557
558 static void __init cardhu_spi_init(void)
559 {
560         int i;
561         struct clk *c;
562         struct board_info board_info, display_board_info;
563
564         tegra_get_board_info(&board_info);
565         tegra_get_display_board_info(&display_board_info);
566
567         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
568                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
569                 if (IS_ERR_OR_NULL(c)) {
570                         pr_err("Not able to get the clock for %s\n",
571                                                 spi_parent_clk[i].name);
572                         continue;
573                 }
574                 spi_parent_clk[i].parent_clk = c;
575                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
576         }
577         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
578         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
579         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
580         platform_add_devices(cardhu_spi_devices,
581                                 ARRAY_SIZE(cardhu_spi_devices));
582
583         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
584                 platform_add_devices(touch_spi_device,
585                                 ARRAY_SIZE(touch_spi_device));
586         }
587         if (board_info.board_id == BOARD_E1198) {
588                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
589                 platform_device_register(&tegra_spi_device2);
590                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
591                 platform_device_register(&tegra_spi_slave_device1);
592         }
593 }
594
595 static void __init cardhu_dtv_init(void)
596 {
597         struct board_info board_info;
598
599         tegra_get_board_info(&board_info);
600
601         if (board_info.board_id == BOARD_E1186)
602                 platform_device_register(&tegra_dtv_device);
603 }
604
605 static struct resource tegra_rtc_resources[] = {
606         [0] = {
607                 .start = TEGRA_RTC_BASE,
608                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
609                 .flags = IORESOURCE_MEM,
610         },
611         [1] = {
612                 .start = INT_RTC,
613                 .end = INT_RTC,
614                 .flags = IORESOURCE_IRQ,
615         },
616 };
617
618 static struct platform_device tegra_rtc_device = {
619         .name = "tegra_rtc",
620         .id   = -1,
621         .resource = tegra_rtc_resources,
622         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
623 };
624
625 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
626         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
627         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
628         .gpio_hp_mute           = -1,
629         .gpio_int_mic_en        = -1,
630         .gpio_ext_mic_en        = -1,
631 };
632
633 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
634         .gpio_spkr_en           = -1,
635         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
636         .gpio_hp_mute           = -1,
637         .gpio_int_mic_en        = -1,
638         .gpio_ext_mic_en        = -1,
639 };
640
641 static struct platform_device cardhu_audio_wm8903_device = {
642         .name   = "tegra-snd-wm8903",
643         .id     = 0,
644         .dev    = {
645                 .platform_data = &cardhu_audio_wm8903_pdata,
646         },
647 };
648
649 static struct platform_device cardhu_audio_max98095_device = {
650         .name   = "tegra-snd-max98095",
651         .id     = 0,
652         .dev    = {
653                 .platform_data = &cardhu_audio_max98095_pdata,
654         },
655 };
656
657 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
658         .gpio_spkr_en           = -1,
659         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
660         .gpio_hp_mute           = -1,
661         .gpio_int_mic_en        = -1,
662         .gpio_ext_mic_en        = -1,
663         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
664         .audio_port_id          = {
665                 [HIFI_CODEC] = 0,
666                 [BASEBAND] = -1,
667                 [BT_SCO] = 3,
668         },
669         .baseband_param         = {
670                 .rate = -1,
671                 .channels = -1,
672         },
673 };
674
675 static struct platform_device cardhu_audio_aic326x_device = {
676         .name   = "tegra-snd-aic326x",
677         .id     = 0,
678         .dev    = {
679                 .platform_data  = &cardhu_audio_aic326x_pdata,
680         },
681 };
682
683 static struct platform_device *cardhu_devices[] __initdata = {
684         &tegra_pmu_device,
685         &tegra_rtc_device,
686         &tegra_udc_device,
687 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
688         &tegra_smmu_device,
689 #endif
690         &tegra_wdt_device,
691 #if defined(CONFIG_TEGRA_AVP)
692         &tegra_avp_device,
693 #endif
694         &tegra_camera,
695 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
696         &tegra_se_device,
697 #endif
698         &tegra_ahub_device,
699         &tegra_dam_device0,
700         &tegra_dam_device1,
701         &tegra_dam_device2,
702         &tegra_i2s_device0,
703         &tegra_i2s_device1,
704         &tegra_i2s_device3,
705         &tegra_spdif_device,
706         &spdif_dit_device,
707         &bluetooth_dit_device,
708         &baseband_dit_device,
709         &cardhu_bcm4329_rfkill_device,
710         &tegra_pcm_device,
711         &cardhu_audio_wm8903_device,
712         &cardhu_audio_max98095_device,
713         &cardhu_audio_aic326x_device,
714         &tegra_hda_device,
715 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
716         &tegra_aes_device,
717 #endif
718 };
719
720 #define MXT_CONFIG_CRC  0xD62DE8
721 static const u8 config[] = {
722         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
723         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
724         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
725         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
726         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
727         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
728         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
729         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
730         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
731         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
732         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
733         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
734         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
735         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
736         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
737         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
738         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
739         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
740         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
742 };
743
744 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
745 static const u8 config_sku2000[] = {
746         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
747         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
748         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
749         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
750         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
751         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
752         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
753         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
754         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
755         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
756         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
757         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
758         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
759         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
760         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
762         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
763         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
764         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
766 };
767
768 static struct mxt_platform_data atmel_mxt_info = {
769         .x_line         = 27,
770         .y_line         = 42,
771         .x_size         = 768,
772         .y_size         = 1366,
773         .blen           = 0x20,
774         .threshold      = 0x3C,
775         .voltage        = 3300000,              /* 3.3V */
776         .orient         = 5,
777         .config         = config,
778         .config_length  = 157,
779         .config_crc     = MXT_CONFIG_CRC,
780         .irqflags       = IRQF_TRIGGER_FALLING,
781 /*      .read_chg       = &read_chg, */
782         .read_chg       = NULL,
783 };
784
785 static struct i2c_board_info __initdata atmel_i2c_info[] = {
786         {
787                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
788                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
789                 .platform_data = &atmel_mxt_info,
790         }
791 };
792
793 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
794         /* name         parent          rate            enabled */
795         { "sbc1",       "pll_p",        52000000,       true},
796         { NULL,         NULL,           0,              0},
797 };
798
799 static int __init cardhu_touch_init(void)
800 {
801         struct board_info BoardInfo;
802
803         tegra_get_display_board_info(&BoardInfo);
804         if (BoardInfo.board_id == BOARD_DISPLAY_PM313) {
805                 tegra_clk_init_from_table(spi_clk_init_table);
806
807                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
808         } else {
809                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
810                 gpio_direction_input(TEGRA_GPIO_PH4);
811
812                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
813                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
814                 msleep(1);
815                 gpio_set_value(TEGRA_GPIO_PH6, 1);
816                 msleep(100);
817
818                 tegra_get_board_info(&BoardInfo);
819                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
820                         atmel_mxt_info.config = config_sku2000;
821                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
822                 }
823
824                 i2c_register_board_info(1, atmel_i2c_info, 1);
825         }
826
827         return 0;
828 }
829
830 static void cardu_usb_hsic_postsupend(void)
831 {
832 #ifdef CONFIG_TEGRA_BB_XMM_POWER
833         baseband_xmm_set_power_status(BBXMM_PS_L2);
834 #endif
835 }
836
837 static void cardu_usb_hsic_preresume(void)
838 {
839 #ifdef CONFIG_TEGRA_BB_XMM_POWER
840         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
841 #endif
842 }
843
844 static void cardu_usb_hsic_phy_ready(void)
845 {
846 #ifdef CONFIG_TEGRA_BB_XMM_POWER
847         baseband_xmm_set_power_status(BBXMM_PS_L0);
848 #endif
849 }
850
851 static void cardu_usb_hsic_phy_off(void)
852 {
853 #ifdef CONFIG_TEGRA_BB_XMM_POWER
854         baseband_xmm_set_power_status(BBXMM_PS_L3);
855 #endif
856 }
857
858 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
859         .post_suspend = cardu_usb_hsic_postsupend,
860         .pre_resume = cardu_usb_hsic_preresume,
861         .port_power = cardu_usb_hsic_phy_ready,
862         .post_phy_off = cardu_usb_hsic_phy_off,
863 };
864
865 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
866         .port_otg = false,
867         .has_hostpc = true,
868         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
869         .op_mode        = TEGRA_USB_OPMODE_HOST,
870         .u_data.host = {
871                 .vbus_gpio = -1,
872                 .hot_plug = false,
873                 .remote_wakeup_supported = false,
874                 .power_off_on_suspend = false,
875         },
876         .u_cfg.hsic = {
877                 .sync_start_delay = 9,
878                 .idle_wait_delay = 17,
879                 .term_range_adj = 0,
880                 .elastic_underrun_limit = 16,
881                 .elastic_overrun_limit = 16,
882         },
883         .ops = &hsic_xmm_plat_ops,
884 };
885
886
887 static int hsic_enable_gpio = -1;
888 static int hsic_reset_gpio = -1;
889
890 void hsic_platform_open(void)
891 {
892         int reset_gpio = 0, enable_gpio = 0;
893
894         if (hsic_enable_gpio != -1)
895                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
896         if (hsic_reset_gpio != -1)
897                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
898         /* hsic enable signal deasserted, hsic reset asserted */
899         if (!enable_gpio)
900                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
901         if (!reset_gpio)
902                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
903         if (!enable_gpio)
904                 tegra_gpio_enable(hsic_enable_gpio);
905         if (!reset_gpio)
906                 tegra_gpio_enable(hsic_reset_gpio);
907         /* keep hsic reset asserted for 1 ms */
908         udelay(1000);
909         /* enable (power on) hsic */
910         if (!enable_gpio)
911                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
912         udelay(1000);
913         /* deassert reset */
914         if (!reset_gpio)
915                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
916
917 }
918
919 void hsic_platform_close(void)
920 {
921         if (hsic_enable_gpio != -1) {
922                 gpio_set_value(hsic_enable_gpio, 0);
923                 gpio_free(hsic_enable_gpio);
924         }
925         if (hsic_reset_gpio != -1) {
926                 gpio_set_value(hsic_reset_gpio, 0);
927                 gpio_free(hsic_reset_gpio);
928         }
929 }
930
931 void hsic_power_on(void)
932 {
933         if (hsic_enable_gpio != -1) {
934                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
935                 udelay(1000);
936         }
937 }
938
939 void hsic_power_off(void)
940 {
941         if (hsic_enable_gpio != -1) {
942                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
943                 udelay(1000);
944         }
945 }
946
947 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
948         .open = hsic_platform_open,
949         .close = hsic_platform_close,
950         .pre_phy_on = hsic_power_on,
951         .post_phy_off = hsic_power_off,
952 };
953
954 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
955         .port_otg = false,
956         .has_hostpc = true,
957         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
958         .op_mode        = TEGRA_USB_OPMODE_HOST,
959         .u_data.host = {
960                 .vbus_gpio = -1,
961                 .hot_plug = false,
962                 .remote_wakeup_supported = false,
963                 .power_off_on_suspend = false,
964         },
965         .u_cfg.hsic = {
966                 .sync_start_delay = 9,
967                 .idle_wait_delay = 17,
968                 .term_range_adj = 0,
969                 .elastic_underrun_limit = 16,
970                 .elastic_overrun_limit = 16,
971         },
972         .ops = &hsic_plat_ops,
973 };
974
975 static struct tegra_usb_platform_data tegra_udc_pdata = {
976         .port_otg = true,
977         .has_hostpc = true,
978         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
979         .op_mode = TEGRA_USB_OPMODE_DEVICE,
980         .u_data.dev = {
981                 .vbus_pmu_irq = 0,
982                 .vbus_gpio = -1,
983                 .charging_supported = false,
984                 .remote_wakeup_supported = false,
985         },
986         .u_cfg.utmi = {
987                 .hssync_start_delay = 0,
988                 .elastic_limit = 16,
989                 .idle_wait_delay = 17,
990                 .term_range_adj = 6,
991                 .xcvr_setup = 8,
992                 .xcvr_lsfslew = 2,
993                 .xcvr_lsrslew = 2,
994                 .xcvr_setup_offset = 0,
995                 .xcvr_use_fuses = 1,
996         },
997 };
998
999 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1000         .port_otg = true,
1001         .has_hostpc = true,
1002         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1003         .op_mode = TEGRA_USB_OPMODE_HOST,
1004         .u_data.host = {
1005                 .vbus_gpio = -1,
1006                 .vbus_reg = "vdd_vbus_micro_usb",
1007                 .hot_plug = true,
1008                 .remote_wakeup_supported = true,
1009                 .power_off_on_suspend = true,
1010         },
1011         .u_cfg.utmi = {
1012                 .hssync_start_delay = 0,
1013                 .elastic_limit = 16,
1014                 .idle_wait_delay = 17,
1015                 .term_range_adj = 6,
1016                 .xcvr_setup = 15,
1017                 .xcvr_lsfslew = 2,
1018                 .xcvr_lsrslew = 2,
1019                 .xcvr_setup_offset = 0,
1020                 .xcvr_use_fuses = 1,
1021         },
1022 };
1023
1024 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1025         .port_otg = false,
1026         .has_hostpc = true,
1027         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1028         .op_mode        = TEGRA_USB_OPMODE_HOST,
1029         .u_data.host = {
1030                 .vbus_gpio = -1,
1031                 .hot_plug = true,
1032                 .remote_wakeup_supported = true,
1033                 .power_off_on_suspend = true,
1034         },
1035         .u_cfg.utmi = {
1036                 .hssync_start_delay = 0,
1037                 .elastic_limit = 16,
1038                 .idle_wait_delay = 17,
1039                 .term_range_adj = 6,
1040                 .xcvr_setup = 15,
1041                 .xcvr_lsfslew = 2,
1042                 .xcvr_lsrslew = 2,
1043                 .xcvr_setup_offset = 0,
1044                 .xcvr_use_fuses = 1,
1045         },
1046 };
1047
1048 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1049         .port_otg = false,
1050         .has_hostpc = true,
1051         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1052         .op_mode        = TEGRA_USB_OPMODE_HOST,
1053         .u_data.host = {
1054                 .vbus_gpio = -1,
1055                 .vbus_reg = "vdd_vbus_typea_usb",
1056                 .hot_plug = true,
1057                 .remote_wakeup_supported = true,
1058                 .power_off_on_suspend = true,
1059         },
1060         .u_cfg.utmi = {
1061                 .hssync_start_delay = 0,
1062                 .elastic_limit = 16,
1063                 .idle_wait_delay = 17,
1064                 .term_range_adj = 6,
1065                 .xcvr_setup = 8,
1066                 .xcvr_lsfslew = 2,
1067                 .xcvr_lsrslew = 2,
1068                 .xcvr_setup_offset = 0,
1069                 .xcvr_use_fuses = 1,
1070         },
1071 };
1072
1073 static struct tegra_usb_otg_data tegra_otg_pdata = {
1074         .ehci_device = &tegra_ehci1_device,
1075         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1076 };
1077
1078 #if CONFIG_USB_SUPPORT
1079 static void cardhu_usb_init(void)
1080 {
1081         struct board_info bi;
1082
1083         tegra_get_board_info(&bi);
1084
1085         /* OTG should be the first to be registered */
1086         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1087         platform_device_register(&tegra_otg_device);
1088
1089         /* setup the udc platform data */
1090         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1091
1092         if (bi.board_id == BOARD_PM267) {
1093                 hsic_enable_gpio = EN_HSIC_GPIO;
1094                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1095                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1096                 platform_device_register(&tegra_ehci2_device);
1097         } else if (bi.board_id == BOARD_E1256) {
1098                 hsic_enable_gpio = EN_HSIC_GPIO;
1099                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1100                 platform_device_register(&tegra_ehci2_device);
1101         } else if (bi.board_id == BOARD_E1186) {
1102                 tegra_ehci2_device.dev.platform_data =
1103                                                 &tegra_ehci2_hsic_xmm_pdata;
1104                 /* ehci2 registration happens in baseband-xmm-power  */
1105         } else {
1106                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1107                 platform_device_register(&tegra_ehci2_device);
1108         }
1109
1110         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1111         platform_device_register(&tegra_ehci3_device);
1112
1113 }
1114 #else
1115 static void cardhu_usb_init(void) { }
1116 #endif
1117
1118 static struct baseband_power_platform_data tegra_baseband_power_data = {
1119         .baseband_type = BASEBAND_XMM,
1120         .modem = {
1121         .xmm = {
1122                         .bb_rst = XMM_GPIO_BB_RST,
1123                         .bb_on = XMM_GPIO_BB_ON,
1124                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1125                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1126                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1127                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1128                         .hsic_device = &tegra_ehci2_device,
1129                 },
1130         },
1131 };
1132
1133 static struct platform_device tegra_baseband_power_device = {
1134         .name = "baseband_xmm_power",
1135         .id = -1,
1136         .dev = {
1137                 .platform_data = &tegra_baseband_power_data,
1138         },
1139 };
1140
1141 static struct platform_device tegra_baseband_power2_device = {
1142         .name = "baseband_xmm_power2",
1143         .id = -1,
1144         .dev = {
1145                 .platform_data = &tegra_baseband_power_data,
1146         },
1147 };
1148
1149
1150 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1151         .port_status[0] = 1,
1152         .port_status[1] = 1,
1153         .port_status[2] = 1,
1154         .use_dock_detect        = 0,
1155         .gpio           = 0,
1156 };
1157
1158 static void cardhu_pci_init(void)
1159 {
1160         struct board_info board_info;
1161
1162         tegra_get_board_info(&board_info);
1163         if (board_info.board_id == BOARD_E1291) {
1164                 cardhu_pci_platform_data.port_status[0] = 0;
1165                 cardhu_pci_platform_data.port_status[1] = 0;
1166                 cardhu_pci_platform_data.port_status[2] = 1;
1167                 cardhu_pci_platform_data.use_dock_detect = 1;
1168                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1169         }
1170         if ((board_info.board_id == BOARD_E1186) ||
1171                 (board_info.board_id == BOARD_E1187) ||
1172                 (board_info.board_id == BOARD_E1291)) {
1173                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1174                 platform_device_register(&tegra_pci_device);
1175         }
1176 }
1177
1178 static void cardhu_modem_init(void)
1179 {
1180         struct board_info board_info;
1181         int w_disable_gpio, ret;
1182
1183         tegra_get_board_info(&board_info);
1184         switch (board_info.board_id) {
1185         case BOARD_E1291:
1186         case BOARD_E1198:
1187                 if (((board_info.board_id == BOARD_E1291) &&
1188                                 (board_info.fab < BOARD_FAB_A03)) ||
1189                         ((board_info.board_id == BOARD_E1198) &&
1190                                         (board_info.fab < BOARD_FAB_A02))) {
1191                         w_disable_gpio = TEGRA_GPIO_PH5;
1192                 } else {
1193                         w_disable_gpio = TEGRA_GPIO_PDD5;
1194                 }
1195
1196                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1197                 if (ret < 0)
1198                         pr_err("%s: gpio_request failed for gpio %d\n",
1199                                 __func__, w_disable_gpio);
1200                 else
1201                         gpio_direction_input(w_disable_gpio);
1202
1203                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1204                 if (((board_info.board_id == BOARD_E1291) &&
1205                                 (board_info.fab >= BOARD_FAB_A04)) ||
1206                         ((board_info.board_id == BOARD_E1198) &&
1207                                         (board_info.fab >= BOARD_FAB_A02))) {
1208                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1209                         if (ret < 0) {
1210                                 pr_err("%s(): Error in allocating gpio "
1211                                         "TEGRA_GPIO_PH7\n", __func__);
1212                                 break;
1213                         }
1214                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1215                 }
1216                 break;
1217         case BOARD_E1186:
1218                 platform_device_register(&tegra_baseband_power_device);
1219                 platform_device_register(&tegra_baseband_power2_device);
1220                 break;
1221         default:
1222                 break;
1223         }
1224
1225 }
1226
1227 #ifdef CONFIG_SATA_AHCI_TEGRA
1228 static void cardhu_sata_init(void)
1229 {
1230         platform_device_register(&tegra_sata_device);
1231 }
1232 #else
1233 static void cardhu_sata_init(void) { }
1234 #endif
1235
1236 static void __init tegra_cardhu_init(void)
1237 {
1238         tegra_thermal_init(&thermal_data);
1239         tegra_clk_init_from_table(cardhu_clk_init_table);
1240         cardhu_pinmux_init();
1241         cardhu_i2c_init();
1242         cardhu_spi_init();
1243         cardhu_usb_init();
1244 #ifdef CONFIG_TEGRA_EDP_LIMITS
1245         cardhu_edp_init();
1246 #endif
1247         cardhu_uart_init();
1248         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1249         tegra_ram_console_debug_init();
1250         cardhu_sdhci_init();
1251         cardhu_regulator_init();
1252         cardhu_dtv_init();
1253         cardhu_suspend_init();
1254         cardhu_touch_init();
1255         cardhu_modem_init();
1256         cardhu_kbc_init();
1257         cardhu_scroll_init();
1258         cardhu_keys_init();
1259         cardhu_panel_init();
1260         cardhu_pmon_init();
1261         cardhu_sensors_init();
1262         cardhu_setup_bluesleep();
1263         cardhu_sata_init();
1264         //audio_wired_jack_init();
1265         cardhu_pins_state_init();
1266         cardhu_emc_init();
1267         tegra_release_bootloader_fb();
1268         cardhu_pci_init();
1269 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1270         tegra_wdt_recovery_init();
1271 #endif
1272 }
1273
1274 static void __init tegra_cardhu_reserve(void)
1275 {
1276 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1277         /* support 1920X1200 with 24bpp */
1278         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1279 #else
1280         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1281 #endif
1282         tegra_ram_console_debug_reserve(SZ_1M);
1283 }
1284
1285 MACHINE_START(CARDHU, "cardhu")
1286         .boot_params    = 0x80000100,
1287         .map_io         = tegra_map_common_io,
1288         .reserve        = tegra_cardhu_reserve,
1289         .init_early     = tegra_init_early,
1290         .init_irq       = tegra_init_irq,
1291         .timer          = &tegra_timer,
1292         .init_machine   = tegra_cardhu_init,
1293 MACHINE_END