touch: Radyium: Move panel config structures to board files.
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/rm31080a_ts.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44 #include <linux/of_platform.h>
45
46 #include <sound/wm8903.h>
47 #include <sound/max98095.h>
48 #include <media/tegra_dtv.h>
49
50 #include <asm/hardware/gic.h>
51
52 #include <mach/edp.h>
53 #include <mach/clk.h>
54 #include <mach/iomap.h>
55 #include <mach/irqs.h>
56 #include <mach/pinmux.h>
57 #include <mach/iomap.h>
58 #include <mach/io_dpd.h>
59 #include <mach/io.h>
60 #include <mach/i2s.h>
61 #include <mach/tegra_asoc_pdata.h>
62 #include <mach/tegra_wm8903_pdata.h>
63 #include <mach/usb_phy.h>
64 #include <mach/thermal.h>
65 #include <mach/pci.h>
66 #include <mach/gpio-tegra.h>
67 #include <mach/tegra_fiq_debugger.h>
68 #include <linux/thermal.h>
69
70 #include <asm/hardware/gic.h>
71 #include <asm/mach-types.h>
72 #include <asm/mach/arch.h>
73
74 #include "board.h"
75 #include "clock.h"
76 #include "board-cardhu.h"
77 #include "board-touch-raydium.h"
78 #include "devices.h"
79 #include "gpio-names.h"
80 #include "fuse.h"
81 #include "pm.h"
82 #include "baseband-xmm-power.h"
83 #include "wdt-recovery.h"
84 #include "common.h"
85
86 static struct balanced_throttle throttle_list[] = {
87         {
88                 .tegra_cdev = {
89                         .id = CDEV_BTHROT_ID_TJ,
90                 },
91                 .throt_tab_size = 10,
92                 .throt_tab = {
93                         {      0, 1000 },
94                         { 640000, 1000 },
95                         { 640000, 1000 },
96                         { 640000, 1000 },
97                         { 640000, 1000 },
98                         { 640000, 1000 },
99                         { 760000, 1000 },
100                         { 760000, 1050 },
101                         {1000000, 1050 },
102                         {1000000, 1100 },
103                 },
104         },
105 };
106
107 static struct tegra_thermal_bind thermal_binds[] = {
108         /* Thermal Throttling */
109         {
110                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
111                 .cdev_id = CDEV_BTHROT_ID_TJ,
112                 .type = THERMAL_TRIP_PASSIVE,
113                 .passive = {
114                         .trip_temp = 85000,
115                         .tc1 = 0,
116                         .tc2 = 1,
117                         .passive_delay = 2000,
118                 }
119         },
120         /* EDP Capping */
121         {
122                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
123                 .cdev_id = CDEV_EDPTABLE_ID_EDP,
124                 .type = THERMAL_TRIP_ACTIVE,
125                 .get_trip_temp = tegra_edp_get_trip_temp,
126                 .get_trip_size = tegra_edp_get_trip_size,
127         },
128         {
129                 .tdev_id = THERMAL_DEVICE_ID_NULL,
130         },
131 };
132
133 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
134         {
135                 .name           = "bt_rfkill",
136                 .shutdown_gpio  = TEGRA_GPIO_PU0,
137                 .reset_gpio     = TEGRA_GPIO_INVALID,
138                 .type           = RFKILL_TYPE_BLUETOOTH,
139         },
140 };
141
142 static struct platform_device cardhu_bt_rfkill_device = {
143         .name = "rfkill_gpio",
144         .id             = -1,
145         .dev = {
146                 .platform_data = &cardhu_bt_rfkill_pdata,
147         },
148 };
149
150 static struct resource cardhu_bluesleep_resources[] = {
151         [0] = {
152                 .name = "gpio_host_wake",
153                         .start  = TEGRA_GPIO_PU6,
154                         .end    = TEGRA_GPIO_PU6,
155                         .flags  = IORESOURCE_IO,
156         },
157         [1] = {
158                 .name = "gpio_ext_wake",
159                         .start  = TEGRA_GPIO_PU1,
160                         .end    = TEGRA_GPIO_PU1,
161                         .flags  = IORESOURCE_IO,
162         },
163         [2] = {
164                 .name = "host_wake",
165                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
166         },
167 };
168
169 static struct platform_device cardhu_bluesleep_device = {
170         .name           = "bluesleep",
171         .id             = -1,
172         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
173         .resource       = cardhu_bluesleep_resources,
174 };
175
176 static noinline void __init cardhu_setup_bluesleep(void)
177 {
178         cardhu_bluesleep_resources[2].start =
179                 cardhu_bluesleep_resources[2].end =
180                         gpio_to_irq(TEGRA_GPIO_PU6);
181         platform_device_register(&cardhu_bluesleep_device);
182         return;
183 }
184
185 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
186         /* name         parent          rate            enabled */
187         { "pll_m",      NULL,           0,              false},
188         { "hda",        "pll_p",        108000000,      false},
189         { "hda2codec_2x","pll_p",       48000000,       false},
190         { "pwm",        "pll_p",        3187500,        false},
191         { "blink",      "clk_32k",      32768,          true},
192         { "i2s0",       "pll_a_out0",   0,              false},
193         { "i2s1",       "pll_a_out0",   0,              false},
194         { "i2s3",       "pll_a_out0",   0,              false},
195         { "spdif_out",  "pll_a_out0",   0,              false},
196         { "d_audio",    "clk_m",        12000000,       false},
197         { "dam0",       "clk_m",        12000000,       false},
198         { "dam1",       "clk_m",        12000000,       false},
199         { "dam2",       "clk_m",        12000000,       false},
200         { "audio1",     "i2s1_sync",    0,              false},
201         { "audio3",     "i2s3_sync",    0,              false},
202         { "vi_sensor",  "pll_p",        150000000,      false},
203         { "i2c1",       "pll_p",        3200000,        false},
204         { "i2c2",       "pll_p",        3200000,        false},
205         { "i2c3",       "pll_p",        3200000,        false},
206         { "i2c4",       "pll_p",        3200000,        false},
207         { "i2c5",       "pll_p",        3200000,        false},
208         { "vi",         "pll_p",        0,              false},
209         { NULL,         NULL,           0,              0},
210 };
211
212 static struct pn544_i2c_platform_data nfc_pdata = {
213         .irq_gpio = TEGRA_GPIO_PX0,
214         .ven_gpio = TEGRA_GPIO_PP3,
215         .firm_gpio = TEGRA_GPIO_PO7,
216         };
217
218 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
219         {
220                 I2C_BOARD_INFO("pn544", 0x28),
221                 .platform_data = &nfc_pdata,
222         },
223 };
224 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
225         .adapter_nr     = 0,
226         .bus_count      = 1,
227         .bus_clk_rate   = { 100000, 0 },
228         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
229         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
230         .arb_recovery = arb_lost_recovery,
231 };
232
233 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
234         .adapter_nr     = 1,
235         .bus_count      = 1,
236         .bus_clk_rate   = { 400000, 0 },
237         .is_clkon_always = true,
238         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
239         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
240         .arb_recovery = arb_lost_recovery,
241 };
242
243 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
244         .adapter_nr     = 2,
245         .bus_count      = 1,
246         .bus_clk_rate   = { 100000, 0 },
247         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
248         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
249         .arb_recovery = arb_lost_recovery,
250 };
251
252 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
253         .adapter_nr     = 3,
254         .bus_count      = 1,
255         .bus_clk_rate   = { 10000, 0 },
256         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
257         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
258         .arb_recovery = arb_lost_recovery,
259 };
260
261 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
262         .adapter_nr     = 4,
263         .bus_count      = 1,
264         .bus_clk_rate   = { 400000, 0 },
265         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
266         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
267         .arb_recovery = arb_lost_recovery,
268 };
269
270
271 #if 0
272 struct tegra_wired_jack_conf audio_wr_jack_conf = {
273         .hp_det_n = TEGRA_GPIO_PW2,
274         .en_mic_ext = TEGRA_GPIO_PX1,
275         .en_mic_int = TEGRA_GPIO_PX0,
276 };
277 #endif
278
279 static struct wm8903_platform_data cardhu_wm8903_pdata = {
280         .irq_active_low = 0,
281         .micdet_cfg = 0,
282         .micdet_delay = 100,
283         .gpio_base = CARDHU_GPIO_WM8903(0),
284         .gpio_cfg = {
285                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
286                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
287                         WM8903_GP2_DIR,
288                 WM8903_GPIO_CONFIG_ZERO,
289                 0,
290                 0,
291         },
292 };
293
294 /* Equalizer filter coefs generated from the MAXIM MAX98095
295  * evkit software tool */
296 static struct max98095_eq_cfg max98095_eq_cfg[] = {
297         {
298                 .name = "FLAT",
299                 .rate = 44100,
300                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
301                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
302                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
303                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
304                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
305         },
306         {
307                 .name = "LOWPASS1K",
308                 .rate = 44100,
309                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
310                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
311                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
312                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
313                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
314         },
315         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
316                 .name = "HIBOOST",
317                 .rate = 44100,
318                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
319                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
320                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
321                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
322                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
323         },
324         { /* BASS=12dB, TREBLE=+12dB */
325                 .name = "LOUD12DB",
326                 .rate = 44100,
327                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
328                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
329                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
330                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
331                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
332         },
333         {
334                 .name = "FLAT",
335                 .rate = 16000,
336                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
337                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
338                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
339                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
340                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
341         },
342         {
343                 .name = "LOWPASS1K",
344                 .rate = 16000,
345                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
346                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
347                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
348                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
349                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
350         },
351         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
352                 .name = "HIBOOST",
353                 .rate = 16000,
354                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
355                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
356                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
357                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
358                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
359         },
360         { /* BASS=12dB, TREBLE=+12dB */
361                 .name = "LOUD12DB",
362                 .rate = 16000,
363                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
364                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
365                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
366                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
367                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
368         },
369 };
370
371 static struct max98095_pdata cardhu_max98095_pdata = {
372         /* equalizer configuration */
373         .eq_cfg = max98095_eq_cfg,
374         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
375
376         /* Biquad filter response configuration */
377         .bq_cfg = NULL,
378         .bq_cfgcnt = 0,
379
380         /* microphone configuration */
381         .digmic_left_mode = 1,
382         .digmic_right_mode = 1,
383 };
384
385 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
386         I2C_BOARD_INFO("wm8903", 0x1a),
387         .platform_data = &cardhu_wm8903_pdata,
388 };
389
390 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
391         I2C_BOARD_INFO("aic3262-codec", 0x18),
392 };
393
394 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
395         I2C_BOARD_INFO("max98095", 0x10),
396         .platform_data = &cardhu_max98095_pdata,
397 };
398
399 static void cardhu_i2c_init(void)
400 {
401         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
402         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
403         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
404         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
405         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
406
407         platform_device_register(&tegra_i2c_device5);
408         platform_device_register(&tegra_i2c_device4);
409         platform_device_register(&tegra_i2c_device3);
410         platform_device_register(&tegra_i2c_device2);
411         platform_device_register(&tegra_i2c_device1);
412
413         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
414                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
415         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
416         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
417         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
418
419         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
420         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
421 }
422
423 static struct platform_device *cardhu_uart_devices[] __initdata = {
424         &tegra_uarta_device,
425         &tegra_uartb_device,
426         &tegra_uartc_device,
427         &tegra_uartd_device,
428         &tegra_uarte_device,
429 };
430 static struct uart_clk_parent uart_parent_clk[] = {
431         [0] = {.name = "clk_m"},
432         [1] = {.name = "pll_p"},
433 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
434         [2] = {.name = "pll_m"},
435 #endif
436 };
437
438 static struct tegra_uart_platform_data cardhu_uart_pdata;
439 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
440
441 static void __init uart_debug_init(void)
442 {
443         struct board_info board_info;
444         int debug_port_id;
445
446         tegra_get_board_info(&board_info);
447
448         debug_port_id = get_tegra_uart_debug_port_id();
449         if (debug_port_id < 0) {
450                 debug_port_id = 0;
451                         /* UARTB is debug port
452                          *       for SLT - E1186/E1187/PM269
453                          *       for E1256/E1257
454                          */
455                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
456                         ((board_info.board_id == BOARD_E1186) ||
457                         (board_info.board_id == BOARD_E1187) ||
458                         (board_info.board_id == BOARD_PM269))) ||
459                         (board_info.board_id == BOARD_E1256) ||
460                         (board_info.board_id == BOARD_E1257))
461                                 debug_port_id = 1;
462         }
463
464 #ifdef CONFIG_TEGRA_IRDA
465         if ((board_info.board_id == BOARD_E1186) ||
466                 (board_info.board_id == BOARD_E1198)) {
467                 if (debug_port_id == 1) {
468                         cardhu_irda_pdata.is_irda = false;
469                         pr_err("UARTB is not available for IrDA\n");
470                 }
471         }
472 #endif
473
474         switch (debug_port_id) {
475         case 0:
476                 /* UARTA is the debug port. */
477                 pr_info("Selecting UARTA as the debug console\n");
478                 cardhu_uart_devices[0] = &debug_uarta_device;
479                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
480                 debug_uart_port_base = ((struct plat_serial8250_port *)(
481                         debug_uarta_device.dev.platform_data))->mapbase;
482                 break;
483
484         case 1:
485                 /* UARTB is the debug port. */
486                 pr_info("Selecting UARTB as the debug console\n");
487                 cardhu_uart_devices[1] = &debug_uartb_device;
488                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
489                 debug_uart_port_base = ((struct plat_serial8250_port *)(
490                         debug_uartb_device.dev.platform_data))->mapbase;
491                 break;
492
493         case 2:
494                 /* UARTC is the debug port. */
495                 pr_info("Selecting UARTC as the debug console\n");
496                 cardhu_uart_devices[2] = &debug_uartc_device;
497                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
498                 debug_uart_port_base = ((struct plat_serial8250_port *)(
499                         debug_uartc_device.dev.platform_data))->mapbase;
500                 break;
501
502         case 3:
503                 /* UARTD is the debug port. */
504                 pr_info("Selecting UARTD as the debug console\n");
505                 cardhu_uart_devices[3] = &debug_uartd_device;
506                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
507                 debug_uart_port_base = ((struct plat_serial8250_port *)(
508                         debug_uartd_device.dev.platform_data))->mapbase;
509                 break;
510
511         case 4:
512                 /* UARTE is the debug port. */
513                 pr_info("Selecting UARTE as the debug console\n");
514                 cardhu_uart_devices[4] = &debug_uarte_device;
515                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
516                 debug_uart_port_base = ((struct plat_serial8250_port *)(
517                         debug_uarte_device.dev.platform_data))->mapbase;
518                 break;
519
520         default:
521                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
522                 cardhu_uart_devices[0] = &debug_uarta_device;
523                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
524                 debug_uart_port_base = ((struct plat_serial8250_port *)(
525                         debug_uarta_device.dev.platform_data))->mapbase;
526                 break;
527         }
528         return;
529 }
530
531 static void __init cardhu_uart_init(void)
532 {
533         struct clk *c;
534         int i;
535         struct board_info board_info;
536
537         tegra_get_board_info(&board_info);
538
539         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
540                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
541                 if (IS_ERR_OR_NULL(c)) {
542                         pr_err("Not able to get the clock for %s\n",
543                                                 uart_parent_clk[i].name);
544                         continue;
545                 }
546                 uart_parent_clk[i].parent_clk = c;
547                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
548         }
549         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
550         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
551         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
552         cardhu_loopback_uart_pdata.parent_clk_count =
553                                                 ARRAY_SIZE(uart_parent_clk);
554         cardhu_loopback_uart_pdata.is_loopback = true;
555         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
556         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
557         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
558         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
559         /* UARTE is used for loopback test purpose */
560         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
561
562         /* Register low speed only if it is selected */
563         if (!is_tegra_debug_uartport_hs()) {
564                 uart_debug_init();
565                 /* Clock enable for the debug channel */
566                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
567                         pr_info("The debug console clock name is %s\n",
568                                                 debug_uart_clk->name);
569                         c = tegra_get_clock_by_name("pll_p");
570                         if (IS_ERR_OR_NULL(c))
571                                 pr_err("Not getting the parent clock pll_p\n");
572                         else
573                                 clk_set_parent(debug_uart_clk, c);
574
575                         clk_enable(debug_uart_clk);
576                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
577                 } else {
578                         pr_err("Not getting the clock %s for debug console\n",
579                                         debug_uart_clk->name);
580                 }
581         }
582
583 #ifdef CONFIG_TEGRA_IRDA
584         if (((board_info.board_id == BOARD_E1186) ||
585                 (board_info.board_id == BOARD_E1198)) &&
586                         cardhu_irda_pdata.is_irda) {
587                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
588                 cardhu_irda_pdata.parent_clk_count =
589                                         ARRAY_SIZE(uart_parent_clk);
590
591                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
592         }
593 #endif
594
595         platform_add_devices(cardhu_uart_devices,
596                                 ARRAY_SIZE(cardhu_uart_devices));
597 }
598
599 static struct platform_device tegra_camera = {
600         .name = "tegra_camera",
601         .id = -1,
602 };
603
604 static struct platform_device *cardhu_spi_devices[] __initdata = {
605         &tegra_spi_device4,
606 };
607
608 static struct platform_device *touch_spi_device[] __initdata = {
609         &tegra_spi_device1,
610 };
611
612 struct spi_clk_parent spi_parent_clk[] = {
613         [0] = {.name = "pll_p"},
614 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
615         [1] = {.name = "pll_m"},
616         [2] = {.name = "clk_m"},
617 #else
618         [1] = {.name = "clk_m"},
619 #endif
620 };
621
622 static struct tegra_spi_platform_data cardhu_spi_pdata = {
623         .is_dma_based           = true,
624         .max_dma_buffer         = (16 * 1024),
625         .is_clkon_always        = false,
626         .max_rate               = 100000000,
627 };
628
629 static void __init cardhu_spi_init(void)
630 {
631         int i;
632         struct clk *c;
633         struct board_info board_info, display_board_info;
634
635         tegra_get_board_info(&board_info);
636         tegra_get_display_board_info(&display_board_info);
637
638         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
639                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
640                 if (IS_ERR_OR_NULL(c)) {
641                         pr_err("Not able to get the clock for %s\n",
642                                                 spi_parent_clk[i].name);
643                         continue;
644                 }
645                 spi_parent_clk[i].parent_clk = c;
646                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
647         }
648         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
649         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
650         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
651         platform_add_devices(cardhu_spi_devices,
652                                 ARRAY_SIZE(cardhu_spi_devices));
653
654         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
655                 platform_add_devices(touch_spi_device,
656                                 ARRAY_SIZE(touch_spi_device));
657         }
658         if (board_info.board_id == BOARD_E1198) {
659                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
660                 platform_device_register(&tegra_spi_device2);
661                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
662                 platform_device_register(&tegra_spi_slave_device1);
663         }
664 }
665
666 static void __init cardhu_dtv_init(void)
667 {
668         struct board_info board_info;
669
670         tegra_get_board_info(&board_info);
671
672         if (board_info.board_id == BOARD_E1186)
673                 platform_device_register(&tegra_dtv_device);
674 }
675
676 static struct resource tegra_rtc_resources[] = {
677         [0] = {
678                 .start = TEGRA_RTC_BASE,
679                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
680                 .flags = IORESOURCE_MEM,
681         },
682         [1] = {
683                 .start = INT_RTC,
684                 .end = INT_RTC,
685                 .flags = IORESOURCE_IRQ,
686         },
687 };
688
689 static struct platform_device tegra_rtc_device = {
690         .name = "tegra_rtc",
691         .id   = -1,
692         .resource = tegra_rtc_resources,
693         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
694 };
695
696 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
697         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
698         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
699         .gpio_hp_mute           = -1,
700         .gpio_int_mic_en        = -1,
701         .gpio_ext_mic_en        = -1,
702         .i2s_param[HIFI_CODEC]  = {
703                 .audio_port_id  = 0,
704                 .is_i2s_master  = 1,
705                 .i2s_mode       = TEGRA_DAIFMT_I2S,
706         },
707         .i2s_param[BASEBAND]    = {
708                 .audio_port_id  = -1,
709         },
710         .i2s_param[BT_SCO]      = {
711                 .audio_port_id  = 3,
712                 .is_i2s_master  = 1,
713                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
714         },
715 };
716
717 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
718         .gpio_spkr_en           = -1,
719         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
720         .gpio_hp_mute           = -1,
721         .gpio_int_mic_en        = -1,
722         .gpio_ext_mic_en        = -1,
723         .i2s_param[HIFI_CODEC]  = {
724                 .audio_port_id  = 0,
725                 .is_i2s_master  = 1,
726                 .i2s_mode       = TEGRA_DAIFMT_I2S,
727         },
728         .i2s_param[BASEBAND]    = {
729                 .audio_port_id  = -1,
730         },
731         .i2s_param[BT_SCO]      = {
732                 .audio_port_id  = 3,
733                 .is_i2s_master  = 1,
734                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
735         },
736 };
737
738 static struct platform_device cardhu_audio_wm8903_device = {
739         .name   = "tegra-snd-wm8903",
740         .id     = 0,
741         .dev    = {
742                 .platform_data = &cardhu_audio_wm8903_pdata,
743         },
744 };
745
746 static struct platform_device cardhu_audio_max98095_device = {
747         .name   = "tegra-snd-max98095",
748         .id     = 0,
749         .dev    = {
750                 .platform_data = &cardhu_audio_max98095_pdata,
751         },
752 };
753
754 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
755         .gpio_spkr_en           = -1,
756         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
757         .gpio_hp_mute           = -1,
758         .gpio_int_mic_en        = -1,
759         .gpio_ext_mic_en        = -1,
760         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
761         .i2s_param[HIFI_CODEC]  = {
762                 .audio_port_id  = 0,
763                 .is_i2s_master  = 1,
764                 .i2s_mode       = TEGRA_DAIFMT_I2S,
765                 .sample_size    = 16,
766         },
767         .i2s_param[BT_SCO]      = {
768                 .sample_size    = 16,
769                 .audio_port_id  = 3,
770                 .is_i2s_master  = 1,
771                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
772         },
773 };
774
775 static struct platform_device cardhu_audio_aic326x_device = {
776         .name   = "tegra-snd-aic326x",
777         .id     = 0,
778         .dev    = {
779                 .platform_data  = &cardhu_audio_aic326x_pdata,
780         },
781 };
782
783 static struct platform_device *cardhu_devices[] __initdata = {
784         &tegra_pmu_device,
785         &tegra_rtc_device,
786         &tegra_udc_device,
787         &tegra_wdt0_device,
788         &tegra_wdt1_device,
789         &tegra_wdt2_device,
790 #if defined(CONFIG_TEGRA_AVP)
791         &tegra_avp_device,
792 #endif
793         &tegra_camera,
794 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
795         &tegra_se_device,
796 #endif
797         &tegra_ahub_device,
798         &tegra_dam_device0,
799         &tegra_dam_device1,
800         &tegra_dam_device2,
801         &tegra_i2s_device0,
802         &tegra_i2s_device1,
803         &tegra_i2s_device3,
804         &tegra_spdif_device,
805         &spdif_dit_device,
806         &bluetooth_dit_device,
807         &baseband_dit_device,
808         &cardhu_bt_rfkill_device,
809         &tegra_pcm_device,
810         &cardhu_audio_wm8903_device,
811         &cardhu_audio_max98095_device,
812         &cardhu_audio_aic326x_device,
813         &tegra_hda_device,
814         &tegra_cec_device,
815 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
816         &tegra_aes_device,
817 #endif
818 };
819
820 #define E1506_MXT_CONFIG_CRC 0x62F903
821 static const u8 e1506_config[] = {
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
824         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
825         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
826         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
827         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
828         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
829         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
830         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
832         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
833         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
834         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
835         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
836         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
837         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
839         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
843         0x00
844 };
845
846 #define MXT_CONFIG_CRC  0xD62DE8
847 static const u8 config[] = {
848         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
850         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
851         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
852         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
853         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
854         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
855         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
856         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
857         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
858         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
859         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
860         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
861         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
862         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
863         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
868 };
869
870 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
871 static const u8 config_sku2000[] = {
872         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
874         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
875         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
876         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
877         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
878         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
879         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
880         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
881         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
882         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
883         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
884         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
885         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
886         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
887         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
888         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
889         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
890         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
891         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
892 };
893
894 static struct mxt_platform_data atmel_mxt_info = {
895         .x_line         = 27,
896         .y_line         = 42,
897         .x_size         = 768,
898         .y_size         = 1366,
899         .blen           = 0x20,
900         .threshold      = 0x3C,
901         .voltage        = 3300000,              /* 3.3V */
902         .orient         = 5,
903         .config         = config,
904         .config_length  = 157,
905         .config_crc     = MXT_CONFIG_CRC,
906         .irqflags       = IRQF_TRIGGER_FALLING,
907 /*      .read_chg       = &read_chg, */
908         .read_chg       = NULL,
909 };
910
911 static struct mxt_platform_data e1506_atmel_mxt_info = {
912         .x_line         = 19,
913         .y_line         = 11,
914         .x_size         = 960,
915         .y_size         = 540,
916         .blen           = 0x10,
917         .threshold      = 0x32,
918         .voltage        = 3300000,              /* 3.3V */
919         .orient         = 3,
920         .config         = e1506_config,
921         .config_length  = 168,
922         .config_crc     = E1506_MXT_CONFIG_CRC,
923         .irqflags       = IRQF_TRIGGER_FALLING,
924 /*      .read_chg       = &read_chg, */
925         .read_chg       = NULL,
926 };
927
928 static struct i2c_board_info __initdata atmel_i2c_info[] = {
929         {
930                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
931                 .platform_data = &atmel_mxt_info,
932         }
933 };
934
935 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
936         {
937                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
938                 .platform_data = &e1506_atmel_mxt_info,
939         }
940 };
941
942 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
943         /* name         parent          rate            enabled */
944         { "sbc1",       "pll_p",        52000000,       true},
945         { NULL,         NULL,           0,              0},
946 };
947
948 /* Raydium touchscreen                     Driver data */
949 /*-----------------------------------------------------*/
950 static const u8 rm31080_config_cardhu[] = {
951         0x00, 0x00, 0x00, 0x00, 0x30, 0x1e, 0x20, 0x0f,
952         0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x08,
953         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
954         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
955         0x10, 0x10, 0x06, 0x06, 0x04, 0x01, 0x02, 0x00,
956         0x00, 0x0a, 0x00, 0xd5, 0x2b, 0x00, 0x00, 0x09,
957         0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
958         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
959         0x28, 0xf8, 0x50, 0xce, 0x0a, 0x0c, 0x00, 0x00,
960         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
961         0x16, 0x1b, 0x14, 0x16, 0x16, 0x18, 0x32, 0x19,
962         0x1d, 0x08, 0x30, 0x19, 0x10, 0xf6, 0xe2, 0x08,
963         0x28, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00,
964         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
965         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
966         0x00, 0x21, 0x00, 0x00, 0x21, 0x00, 0x00, 0x21,
967         0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00,
968         0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x80,
969         0x00, 0xc0, 0x00, 0xc2, 0x00, 0xf0, 0xed, 0x02,
970         0xed, 0x02, 0x00, 0x90, 0x0a, 0x06, 0x80, 0x02,
971         0x00, 0x04, 0x00, 0x20, 0x03, 0x02, 0x08, 0x03,
972         0x10, 0x20, 0x20, 0x40, 0x10, 0x00, 0x00, 0x00,
973         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
974         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
975         0x10, 0x10, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00,
976         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
977         0x50, 0x80, 0x02, 0x02, 0x02, 0x00, 0x00, 0x33,
978         0x32, 0x00, 0x01, 0x4c, 0xfa, 0x00, 0x00, 0x43,
979         0x3c, 0x00, 0x01, 0x38, 0xe6, 0x00, 0x00, 0x26,
980         0x19, 0x00, 0x02, 0x66, 0x19, 0x00, 0x02, 0x50,
981         0x64, 0x00, 0x00, 0x36, 0x4a, 0x00, 0x00, 0x0c,
982         0x19, 0x00, 0x02, 0x64, 0x96, 0xab, 0x88, 0x78,
983         0x88, 0x78, 0x04, 0x0f, 0x38, 0xff, 0x02, 0x04,
984         0x80, 0xe0, 0x13, 0x01, 0x00, 0x44, 0x61, 0x12,
985         0x41, 0x00, 0x00, 0x00, 0x00, 0x97, 0x01, 0x0c,
986         0x44, 0x61, 0x12, 0x29, 0x29, 0x41, 0x00, 0x00,
987         0x97, 0x06, 0x0c, 0x12, 0x41, 0x44, 0x52, 0x52,
988         0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
989         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
990         0x00, 0x00, 0x80, 0x80, 0x01, 0x80, 0x01, 0x80,
991         0x22, 0x33, 0x22, 0x33, 0x66, 0x20, 0xff, 0xc9,
992         0x19, 0xd0, 0xd0, 0x44, 0x00, 0x10, 0x00, 0x80,
993         0x05, 0x44, 0xff, 0x00, 0x00, 0x10, 0x50, 0x00,
994         0x00, 0x00, 0x30, 0x00, 0x00, 0x18, 0x18, 0x0f,
995         0x0f, 0xf0, 0xf0, 0x00, 0x00, 0x10, 0x10, 0x00,
996         0x00, 0x18, 0x18, 0x00, 0x00, 0x18, 0x18, 0x00,
997         0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
998         0x00, 0x00, 0x00, 0x10, 0x01, 0x10, 0x01, 0x02,
999 };
1000
1001 struct rm_spi_ts_platform_data rm31080ts_cardhu_data = {
1002         .gpio_reset = 0,
1003         .config = 0,
1004 };
1005
1006 struct spi_board_info rm31080a_cardhu_spi_board[1] = {
1007         {
1008          .modalias = "rm_ts_spidev",
1009          .bus_num = 0,
1010          .chip_select = 0,
1011          .max_speed_hz = 13 * 1000 * 1000,
1012          .mode = SPI_MODE_0,
1013          .platform_data = &rm31080ts_cardhu_data,
1014          },
1015 };
1016
1017 static int __init cardhu_touch_init(void)
1018 {
1019         struct board_info BoardInfo, DisplayBoardInfo;
1020
1021         tegra_get_board_info(&BoardInfo);
1022         tegra_get_display_board_info(&DisplayBoardInfo);
1023         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
1024                 tegra_clk_init_from_table(spi_clk_init_table);
1025                 rm31080ts_cardhu_data.config = (char *) rm31080_config_cardhu;
1026                 rm31080ts_cardhu_data.platform_id = RM_PLATFORM_C210;
1027                 rm31080a_cardhu_spi_board[0].irq = gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
1028                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
1029                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
1030                                         &rm31080ts_cardhu_data,
1031                                         &rm31080a_cardhu_spi_board[0],
1032                                         ARRAY_SIZE(rm31080a_cardhu_spi_board));
1033         } else {
1034                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1035                 gpio_direction_input(TEGRA_GPIO_PH4);
1036
1037                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1038                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1039                 msleep(1);
1040                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1041                 msleep(100);
1042
1043                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1044                         atmel_mxt_info.config = config_sku2000;
1045                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1046                 }
1047
1048                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1049                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1050                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1051                 } else {
1052                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1053                         i2c_register_board_info(1, atmel_i2c_info, 1);
1054                 }
1055         }
1056
1057         return 0;
1058 }
1059
1060 #if defined(CONFIG_USB_SUPPORT)
1061
1062 static void cardu_usb_hsic_postsupend(void)
1063 {
1064 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1065         baseband_xmm_set_power_status(BBXMM_PS_L2);
1066 #endif
1067 }
1068
1069 static void cardu_usb_hsic_preresume(void)
1070 {
1071 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1072         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1073 #endif
1074 }
1075
1076 static void cardu_usb_hsic_phy_ready(void)
1077 {
1078 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1079         baseband_xmm_set_power_status(BBXMM_PS_L0);
1080 #endif
1081 }
1082
1083 static void cardu_usb_hsic_phy_off(void)
1084 {
1085 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1086         baseband_xmm_set_power_status(BBXMM_PS_L3);
1087 #endif
1088 }
1089
1090 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1091         .post_suspend = cardu_usb_hsic_postsupend,
1092         .pre_resume = cardu_usb_hsic_preresume,
1093         .port_power = cardu_usb_hsic_phy_ready,
1094         .post_phy_off = cardu_usb_hsic_phy_off,
1095 };
1096
1097 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1098         .port_otg = false,
1099         .has_hostpc = true,
1100         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1101         .op_mode        = TEGRA_USB_OPMODE_HOST,
1102         .u_data.host = {
1103                 .vbus_gpio = -1,
1104                 .hot_plug = false,
1105                 .remote_wakeup_supported = false,
1106                 .power_off_on_suspend = false,
1107         },
1108         .ops = &hsic_xmm_plat_ops,
1109 };
1110 #endif
1111
1112 static int hsic_enable_gpio = -1;
1113 static int hsic_reset_gpio = -1;
1114
1115 void hsic_platform_open(void)
1116 {
1117         int reset_gpio = -1, enable_gpio = -1;
1118
1119         if (hsic_enable_gpio != -1)
1120                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1121         if (hsic_reset_gpio != -1)
1122                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1123         /* hsic enable signal deasserted, hsic reset asserted */
1124         if (!enable_gpio)
1125                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1126         if (!reset_gpio)
1127                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1128         /* keep hsic reset asserted for 1 ms */
1129         udelay(1000);
1130         /* enable (power on) hsic */
1131         if (!enable_gpio)
1132                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1133         udelay(1000);
1134         /* deassert reset */
1135         if (!reset_gpio)
1136                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1137
1138 }
1139
1140 void hsic_platform_close(void)
1141 {
1142         if (hsic_enable_gpio != -1) {
1143                 gpio_set_value(hsic_enable_gpio, 0);
1144                 gpio_free(hsic_enable_gpio);
1145         }
1146         if (hsic_reset_gpio != -1) {
1147                 gpio_set_value(hsic_reset_gpio, 0);
1148                 gpio_free(hsic_reset_gpio);
1149         }
1150 }
1151
1152 void hsic_power_on(void)
1153 {
1154         if (hsic_enable_gpio != -1) {
1155                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1156                 udelay(1000);
1157         }
1158 }
1159
1160 void hsic_power_off(void)
1161 {
1162         if (hsic_enable_gpio != -1) {
1163                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1164                 udelay(1000);
1165         }
1166 }
1167
1168 #if defined(CONFIG_USB_SUPPORT)
1169 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1170         .open = hsic_platform_open,
1171         .close = hsic_platform_close,
1172         .pre_phy_on = hsic_power_on,
1173         .post_phy_off = hsic_power_off,
1174 };
1175
1176 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1177         .port_otg = false,
1178         .has_hostpc = true,
1179         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1180         .op_mode        = TEGRA_USB_OPMODE_HOST,
1181         .u_data.host = {
1182                 .vbus_gpio = -1,
1183                 .hot_plug = false,
1184                 .remote_wakeup_supported = false,
1185                 .power_off_on_suspend = false,
1186         },
1187         .ops = &hsic_plat_ops,
1188 };
1189
1190 static struct tegra_usb_platform_data tegra_udc_pdata = {
1191         .port_otg = true,
1192         .has_hostpc = true,
1193         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1194         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1195         .u_data.dev = {
1196                 .vbus_pmu_irq = 0,
1197                 .vbus_gpio = -1,
1198                 .charging_supported = false,
1199                 .remote_wakeup_supported = false,
1200         },
1201         .u_cfg.utmi = {
1202                 .hssync_start_delay = 0,
1203                 .elastic_limit = 16,
1204                 .idle_wait_delay = 17,
1205                 .term_range_adj = 6,
1206                 .xcvr_setup = 8,
1207                 .xcvr_lsfslew = 2,
1208                 .xcvr_lsrslew = 2,
1209                 .xcvr_setup_offset = 0,
1210                 .xcvr_use_fuses = 1,
1211         },
1212 };
1213
1214 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1215         .port_otg = false,
1216         .has_hostpc = true,
1217         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1218         .op_mode        = TEGRA_USB_OPMODE_HOST,
1219         .u_data.host = {
1220                 .vbus_gpio = -1,
1221                 .hot_plug = false,
1222                 .remote_wakeup_supported = true,
1223                 .power_off_on_suspend = true,
1224         },
1225         .u_cfg.utmi = {
1226                 .hssync_start_delay = 0,
1227                 .elastic_limit = 16,
1228                 .idle_wait_delay = 17,
1229                 .term_range_adj = 6,
1230                 .xcvr_setup = 15,
1231                 .xcvr_lsfslew = 2,
1232                 .xcvr_lsrslew = 2,
1233                 .xcvr_setup_offset = 0,
1234                 .xcvr_use_fuses = 1,
1235         },
1236 };
1237
1238 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1239         .port_otg = false,
1240         .has_hostpc = true,
1241         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1242         .op_mode = TEGRA_USB_OPMODE_HOST,
1243         .u_data.host = {
1244                 .vbus_gpio = -1,
1245                 .hot_plug = true,
1246                 .remote_wakeup_supported = true,
1247                 .power_off_on_suspend = true,
1248         },
1249         .u_cfg.utmi = {
1250                 .hssync_start_delay = 0,
1251                 .elastic_limit = 16,
1252                 .idle_wait_delay = 17,
1253                 .term_range_adj = 6,
1254                 .xcvr_setup = 8,
1255                 .xcvr_lsfslew = 2,
1256                 .xcvr_lsrslew = 2,
1257                 .xcvr_setup_offset = 0,
1258                 .xcvr_use_fuses = 1,
1259         },
1260 };
1261
1262 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1263         .port_otg = true,
1264         .has_hostpc = true,
1265         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1266         .op_mode = TEGRA_USB_OPMODE_HOST,
1267         .u_data.host = {
1268                 .vbus_gpio = -1,
1269                 .hot_plug = true,
1270                 .remote_wakeup_supported = true,
1271                 .power_off_on_suspend = true,
1272         },
1273         .u_cfg.utmi = {
1274                 .hssync_start_delay = 0,
1275                 .elastic_limit = 16,
1276                 .idle_wait_delay = 17,
1277                 .term_range_adj = 6,
1278                 .xcvr_setup = 15,
1279                 .xcvr_lsfslew = 2,
1280                 .xcvr_lsrslew = 2,
1281                 .xcvr_setup_offset = 0,
1282                 .xcvr_use_fuses = 1,
1283         },
1284 };
1285
1286 static struct tegra_usb_otg_data tegra_otg_pdata = {
1287         .ehci_device = &tegra_ehci1_device,
1288         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1289 };
1290 #endif
1291
1292 #if defined(CONFIG_USB_SUPPORT)
1293 static void cardhu_usb_init(void)
1294 {
1295         struct board_info bi;
1296
1297         tegra_get_board_info(&bi);
1298
1299         /* OTG should be the first to be registered */
1300         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1301         platform_device_register(&tegra_otg_device);
1302
1303         /* setup the udc platform data */
1304         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1305
1306         if (bi.board_id == BOARD_PM267) {
1307                 hsic_enable_gpio = EN_HSIC_GPIO;
1308                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1309                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1310                 platform_device_register(&tegra_ehci2_device);
1311         } else if (bi.board_id == BOARD_E1256) {
1312                 hsic_enable_gpio = EN_HSIC_GPIO;
1313                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1314                 platform_device_register(&tegra_ehci2_device);
1315         } else if (bi.board_id == BOARD_E1186) {
1316                 tegra_ehci2_device.dev.platform_data =
1317                                                 &tegra_ehci2_hsic_xmm_pdata;
1318                 /* ehci2 registration happens in baseband-xmm-power  */
1319         } else {
1320                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1321                 platform_device_register(&tegra_ehci2_device);
1322         }
1323
1324         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1325         platform_device_register(&tegra_ehci3_device);
1326
1327 }
1328 #else
1329 static void cardhu_usb_init(void) { }
1330 #endif
1331
1332 static struct baseband_power_platform_data tegra_baseband_power_data = {
1333         .baseband_type = BASEBAND_XMM,
1334         .modem = {
1335         .xmm = {
1336                         .bb_rst = XMM_GPIO_BB_RST,
1337                         .bb_on = XMM_GPIO_BB_ON,
1338                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1339                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1340                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1341                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1342                         .hsic_device = &tegra_ehci2_device,
1343                 },
1344         },
1345 };
1346
1347 static struct platform_device tegra_baseband_power_device = {
1348         .name = "baseband_xmm_power",
1349         .id = -1,
1350         .dev = {
1351                 .platform_data = &tegra_baseband_power_data,
1352         },
1353 };
1354
1355 static struct platform_device tegra_baseband_power2_device = {
1356         .name = "baseband_xmm_power2",
1357         .id = -1,
1358         .dev = {
1359                 .platform_data = &tegra_baseband_power_data,
1360         },
1361 };
1362
1363
1364 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1365         .port_status[0] = 1,
1366         .port_status[1] = 1,
1367         .port_status[2] = 1,
1368         .use_dock_detect        = 0,
1369         .gpio           = 0,
1370 };
1371
1372 static void cardhu_pci_init(void)
1373 {
1374         struct board_info board_info;
1375
1376         tegra_get_board_info(&board_info);
1377         if (board_info.board_id == BOARD_E1291) {
1378                 cardhu_pci_platform_data.port_status[0] = 0;
1379                 cardhu_pci_platform_data.port_status[1] = 0;
1380                 cardhu_pci_platform_data.port_status[2] = 1;
1381                 cardhu_pci_platform_data.use_dock_detect = 1;
1382                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1383         }
1384         if ((board_info.board_id == BOARD_E1186) ||
1385                 (board_info.board_id == BOARD_E1187) ||
1386                 (board_info.board_id == BOARD_E1291)) {
1387                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1388                 platform_device_register(&tegra_pci_device);
1389         }
1390 }
1391
1392 static void cardhu_modem_init(void)
1393 {
1394         struct board_info board_info;
1395         int w_disable_gpio, ret;
1396
1397         tegra_get_board_info(&board_info);
1398         switch (board_info.board_id) {
1399         case BOARD_E1291:
1400         case BOARD_E1198:
1401                 if (((board_info.board_id == BOARD_E1291) &&
1402                                 (board_info.fab < BOARD_FAB_A03)) ||
1403                         ((board_info.board_id == BOARD_E1198) &&
1404                                         (board_info.fab < BOARD_FAB_A02))) {
1405                         w_disable_gpio = TEGRA_GPIO_PH5;
1406                 } else {
1407                         w_disable_gpio = TEGRA_GPIO_PDD5;
1408                 }
1409
1410                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1411                 if (ret < 0)
1412                         pr_err("%s: gpio_request failed for gpio %d\n",
1413                                 __func__, w_disable_gpio);
1414                 else
1415                         gpio_direction_input(w_disable_gpio);
1416
1417                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1418                 if (((board_info.board_id == BOARD_E1291) &&
1419                                 (board_info.fab >= BOARD_FAB_A04)) ||
1420                         ((board_info.board_id == BOARD_E1198) &&
1421                                         (board_info.fab >= BOARD_FAB_A02))) {
1422                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1423                         if (ret < 0) {
1424                                 pr_err("%s(): Error in allocating gpio "
1425                                         "TEGRA_GPIO_PH7\n", __func__);
1426                                 break;
1427                         }
1428                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1429                 }
1430                 break;
1431         case BOARD_E1186:
1432                 platform_device_register(&tegra_baseband_power_device);
1433                 platform_device_register(&tegra_baseband_power2_device);
1434                 break;
1435         default:
1436                 break;
1437         }
1438
1439 }
1440
1441 #ifdef CONFIG_SATA_AHCI_TEGRA
1442 static void cardhu_sata_init(void)
1443 {
1444         platform_device_register(&tegra_sata_device);
1445 }
1446 #else
1447 static void cardhu_sata_init(void) { }
1448 #endif
1449
1450 /* This needs to be inialized later hand */
1451 static int __init cardhu_throttle_list_init(void)
1452 {
1453         int i;
1454         for (i = 0; i < ARRAY_SIZE(throttle_list); i++)
1455                 if (balanced_throttle_register(&throttle_list[i]))
1456                         return -ENODEV;
1457
1458         return 0;
1459 }
1460 late_initcall(cardhu_throttle_list_init);
1461
1462 static void __init tegra_cardhu_init(void)
1463 {
1464         tegra_thermal_init(thermal_binds);
1465         tegra_clk_init_from_table(cardhu_clk_init_table);
1466         tegra_enable_pinmux();
1467         tegra_smmu_init();
1468         tegra_soc_device_init("cardhu");
1469         cardhu_pinmux_init();
1470         cardhu_i2c_init();
1471         cardhu_spi_init();
1472         cardhu_usb_init();
1473 #ifdef CONFIG_TEGRA_EDP_LIMITS
1474         cardhu_edp_init();
1475 #endif
1476         cardhu_uart_init();
1477         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1478         tegra_ram_console_debug_init();
1479         tegra_io_dpd_init();
1480         cardhu_sdhci_init();
1481         cardhu_regulator_init();
1482         cardhu_dtv_init();
1483         cardhu_suspend_init();
1484         cardhu_touch_init();
1485         cardhu_modem_init();
1486         cardhu_kbc_init();
1487         cardhu_scroll_init();
1488         cardhu_keys_init();
1489         cardhu_panel_init();
1490         cardhu_pmon_init();
1491         cardhu_sensors_init();
1492         cardhu_setup_bluesleep();
1493         cardhu_sata_init();
1494         cardhu_pins_state_init();
1495         cardhu_emc_init();
1496         tegra_release_bootloader_fb();
1497         cardhu_pci_init();
1498 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1499         tegra_wdt_recovery_init();
1500 #endif
1501         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1502 }
1503
1504 static void __init tegra_cardhu_dt_init(void)
1505 {
1506         tegra_cardhu_init();
1507
1508         of_platform_populate(NULL,
1509                 of_default_bus_match_table, NULL, NULL);
1510 }
1511
1512 static void __init tegra_cardhu_reserve(void)
1513 {
1514 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1515         /* support 1920X1200 with 24bpp */
1516         tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M);
1517 #else
1518         tegra_reserve(SZ_128M, SZ_8M, SZ_16M);
1519 #endif
1520 }
1521
1522 static const char *cardhu_dt_board_compat[] = {
1523         "nvidia,cardhu",
1524         NULL
1525 };
1526
1527 MACHINE_START(CARDHU, "cardhu")
1528         .atag_offset    = 0x100,
1529         .soc            = &tegra_soc_desc,
1530         .map_io         = tegra_map_common_io,
1531         .reserve        = tegra_cardhu_reserve,
1532         .init_early     = tegra30_init_early,
1533         .init_irq       = tegra_init_irq,
1534         .handle_irq     = gic_handle_irq,
1535         .timer          = &tegra_timer,
1536         .init_machine   = tegra_cardhu_dt_init,
1537         .restart        = tegra_assert_system_reset,
1538         .dt_compat      = cardhu_dt_board_compat,
1539 MACHINE_END