ARM: tegra: uarte: Enable loopback
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41
42 #include <sound/wm8903.h>
43
44 #include <mach/clk.h>
45 #include <mach/iomap.h>
46 #include <mach/irqs.h>
47 #include <mach/pinmux.h>
48 #include <mach/iomap.h>
49 #include <mach/io.h>
50 #include <mach/i2s.h>
51 #include <mach/tegra_wm8903_pdata.h>
52 #include <asm/mach-types.h>
53 #include <asm/mach/arch.h>
54 #include <mach/usb_phy.h>
55 #include <mach/thermal.h>
56 #include <mach/pci.h>
57
58 #include "board.h"
59 #include "clock.h"
60 #include "board-cardhu.h"
61 #include "devices.h"
62 #include "gpio-names.h"
63 #include "fuse.h"
64 #include "pm.h"
65 #include "baseband-xmm-power.h"
66 #include "wdt-recovery.h"
67
68 /* All units are in millicelsius */
69 static struct tegra_thermal_data thermal_data = {
70         .temp_throttle = 85000,
71         .temp_shutdown = 90000,
72         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
73 #ifdef CONFIG_TEGRA_EDP_LIMITS
74         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
75         .hysteresis_edp = 3000,
76 #endif
77 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
78         .tc1 = 0,
79         .tc2 = 1,
80         .passive_delay = 2000,
81 #else
82         .hysteresis_throttle = 1000,
83 #endif
84 };
85
86 /* !!!TODO: Change for cardhu (Taken from Ventana) */
87 static struct tegra_utmip_config utmi_phy_config[] = {
88         [0] = {
89                         .hssync_start_delay = 0,
90                         .idle_wait_delay = 17,
91                         .elastic_limit = 16,
92                         .term_range_adj = 6,
93                         .xcvr_setup = 15,
94                         .xcvr_setup_offset = 0,
95                         .xcvr_use_fuses = 1,
96                         .xcvr_lsfslew = 2,
97                         .xcvr_lsrslew = 2,
98         },
99         [1] = {
100                         .hssync_start_delay = 0,
101                         .idle_wait_delay = 17,
102                         .elastic_limit = 16,
103                         .term_range_adj = 6,
104                         .xcvr_setup = 15,
105                         .xcvr_setup_offset = 0,
106                         .xcvr_use_fuses = 1,
107                         .xcvr_lsfslew = 2,
108                         .xcvr_lsrslew = 2,
109         },
110         [2] = {
111                         .hssync_start_delay = 0,
112                         .idle_wait_delay = 17,
113                         .elastic_limit = 16,
114                         .term_range_adj = 6,
115                         .xcvr_setup = 8,
116                         .xcvr_setup_offset = 0,
117                         .xcvr_use_fuses = 1,
118                         .xcvr_lsfslew = 2,
119                         .xcvr_lsrslew = 2,
120         },
121 };
122
123 #ifdef CONFIG_BCM4329_RFKILL
124 static struct resource cardhu_bcm4329_rfkill_resources[] = {
125         {
126                 .name   = "bcm4329_nshutdown_gpio",
127                 .start  = TEGRA_GPIO_PU0,
128                 .end    = TEGRA_GPIO_PU0,
129                 .flags  = IORESOURCE_IO,
130         },
131 };
132
133 static struct platform_device cardhu_bcm4329_rfkill_device = {
134         .name = "bcm4329_rfkill",
135         .id             = -1,
136         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
137         .resource       = cardhu_bcm4329_rfkill_resources,
138 };
139
140 static noinline void __init cardhu_bt_rfkill(void)
141 {
142         platform_device_register(&cardhu_bcm4329_rfkill_device);
143
144         return;
145 }
146 #else
147 static inline void cardhu_bt_rfkill(void) { }
148 #endif
149
150 #ifdef CONFIG_BT_BLUESLEEP
151 static noinline void __init tegra_setup_bluesleep(void)
152 {
153         struct platform_device *pdev = NULL;
154         struct resource *res;
155
156         pdev = platform_device_alloc("bluesleep", 0);
157         if (!pdev) {
158                 pr_err("unable to allocate platform device for bluesleep");
159                 return;
160         }
161
162         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
163         if (!res) {
164                 pr_err("unable to allocate resource for bluesleep\n");
165                 goto err_free_dev;
166         }
167
168         res[0].name   = "gpio_host_wake";
169         res[0].start  = TEGRA_GPIO_PU6;
170         res[0].end    = TEGRA_GPIO_PU6;
171         res[0].flags  = IORESOURCE_IO;
172
173         res[1].name   = "gpio_ext_wake";
174         res[1].start  = TEGRA_GPIO_PU1;
175         res[1].end    = TEGRA_GPIO_PU1;
176         res[1].flags  = IORESOURCE_IO;
177
178         res[2].name   = "host_wake";
179         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
180         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
181         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
182
183         if (platform_device_add_resources(pdev, res, 3)) {
184                 pr_err("unable to add resources to bluesleep device\n");
185                 goto err_free_res;
186         }
187
188         if (platform_device_add(pdev)) {
189                 pr_err("unable to add bluesleep device\n");
190                 goto err_free_res;
191         }
192         tegra_gpio_enable(TEGRA_GPIO_PU6);
193         tegra_gpio_enable(TEGRA_GPIO_PU1);
194
195 return;
196
197 err_free_res:
198         kfree(res);
199 err_free_dev:
200         platform_device_put(pdev);
201         return;
202 }
203 #else
204 static inline void tegra_setup_bluesleep(void) { }
205 #endif
206
207 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
208         /* name         parent          rate            enabled */
209         { "pll_m",      NULL,           0,              false},
210         { "hda",        "pll_p",        108000000,      false},
211         { "hda2codec_2x","pll_p",       48000000,       false},
212         { "pwm",        "pll_p",        3187500,        false},
213         { "blink",      "clk_32k",      32768,          true},
214         { "i2s1",       "pll_a_out0",   0,              false},
215         { "i2s3",       "pll_a_out0",   0,              false},
216         { "spdif_out",  "pll_a_out0",   0,              false},
217         { "d_audio",    "pll_a_out0",   0,              false},
218         { "dam0",       "pll_a_out0",   0,              false},
219         { "dam1",       "pll_a_out0",   0,              false},
220         { "dam2",       "pll_a_out0",   0,              false},
221         { "audio1",     "i2s1_sync",    0,              false},
222         { "audio3",     "i2s3_sync",    0,              false},
223         { "vi_sensor",  "pll_p",        150000000,      false},
224         { "i2c1",       "pll_p",        3200000,        false},
225         { "i2c2",       "pll_p",        3200000,        false},
226         { "i2c3",       "pll_p",        3200000,        false},
227         { "i2c4",       "pll_p",        3200000,        false},
228         { "i2c5",       "pll_p",        3200000,        false},
229         { NULL,         NULL,           0,              0},
230 };
231
232 static struct pn544_i2c_platform_data nfc_pdata = {
233         .irq_gpio = TEGRA_GPIO_PX0,
234         .ven_gpio = TEGRA_GPIO_PP3,
235         .firm_gpio = TEGRA_GPIO_PO7,
236         };
237
238 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
239         {
240                 I2C_BOARD_INFO("pn544", 0x28),
241                 .platform_data = &nfc_pdata,
242                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
243         },
244 };
245 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
246         .adapter_nr     = 0,
247         .bus_count      = 1,
248         .bus_clk_rate   = { 100000, 0 },
249         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
250         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
251         .arb_recovery = arb_lost_recovery,
252 };
253
254 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
255         .adapter_nr     = 1,
256         .bus_count      = 1,
257         .bus_clk_rate   = { 100000, 0 },
258         .is_clkon_always = true,
259         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
260         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
261         .arb_recovery = arb_lost_recovery,
262 };
263
264 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
265         .adapter_nr     = 2,
266         .bus_count      = 1,
267         .bus_clk_rate   = { 100000, 0 },
268         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
269         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
270         .arb_recovery = arb_lost_recovery,
271 };
272
273 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
274         .adapter_nr     = 3,
275         .bus_count      = 1,
276         .bus_clk_rate   = { 100000, 0 },
277         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
278         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
279         .arb_recovery = arb_lost_recovery,
280 };
281
282 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
283         .adapter_nr     = 4,
284         .bus_count      = 1,
285         .bus_clk_rate   = { 400000, 0 },
286         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
287         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
288         .arb_recovery = arb_lost_recovery,
289 };
290
291
292 #if 0
293 struct tegra_wired_jack_conf audio_wr_jack_conf = {
294         .hp_det_n = TEGRA_GPIO_PW2,
295         .en_mic_ext = TEGRA_GPIO_PX1,
296         .en_mic_int = TEGRA_GPIO_PX0,
297 };
298 #endif
299
300 static struct wm8903_platform_data cardhu_wm8903_pdata = {
301         .irq_active_low = 0,
302         .micdet_cfg = 0,
303         .micdet_delay = 100,
304         .gpio_base = CARDHU_GPIO_WM8903(0),
305         .gpio_cfg = {
306                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
307                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
308                         WM8903_GP2_DIR,
309                 0,
310                 WM8903_GPIO_NO_CONFIG,
311                 WM8903_GPIO_NO_CONFIG,
312         },
313 };
314
315 static struct i2c_board_info __initdata wm8903_board_info = {
316         I2C_BOARD_INFO("wm8903", 0x1a),
317         .platform_data = &cardhu_wm8903_pdata,
318         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
319 };
320
321 static void cardhu_i2c_init(void)
322 {
323         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
324         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
325         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
326         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
327         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
328
329         platform_device_register(&tegra_i2c_device5);
330         platform_device_register(&tegra_i2c_device4);
331         platform_device_register(&tegra_i2c_device3);
332         platform_device_register(&tegra_i2c_device2);
333         platform_device_register(&tegra_i2c_device1);
334
335         i2c_register_board_info(4, &wm8903_board_info, 1);
336         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
337 }
338
339 static struct platform_device *cardhu_uart_devices[] __initdata = {
340         &tegra_uarta_device,
341         &tegra_uartb_device,
342         &tegra_uartc_device,
343         &tegra_uartd_device,
344         &tegra_uarte_device,
345 };
346 static struct uart_clk_parent uart_parent_clk[] = {
347         [0] = {.name = "clk_m"},
348         [1] = {.name = "pll_p"},
349 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
350         [2] = {.name = "pll_m"},
351 #endif
352 };
353
354 static struct tegra_uart_platform_data cardhu_uart_pdata;
355 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
356
357 static void __init uart_debug_init(void)
358 {
359         struct board_info board_info;
360         int debug_port_id;
361
362         tegra_get_board_info(&board_info);
363
364         debug_port_id = get_tegra_uart_debug_port_id();
365         if (debug_port_id < 0) {
366                 debug_port_id = 0;
367                         /* UARTB is debug port
368                          *       for SLT - E1186/E1187/PM269
369                          *       for E1256/E1257
370                          */
371                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
372                         ((board_info.board_id == BOARD_E1186) ||
373                         (board_info.board_id == BOARD_E1187) ||
374                         (board_info.board_id == BOARD_PM269))) ||
375                         (board_info.board_id == BOARD_E1256) ||
376                         (board_info.board_id == BOARD_E1257))
377                                 debug_port_id = 1;
378         }
379         switch (debug_port_id) {
380         case 0:
381                 /* UARTA is the debug port. */
382                 pr_info("Selecting UARTA as the debug console\n");
383                 cardhu_uart_devices[0] = &debug_uarta_device;
384                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
385                 debug_uart_port_base = ((struct plat_serial8250_port *)(
386                         debug_uarta_device.dev.platform_data))->mapbase;
387                 break;
388
389         case 1:
390                 /* UARTB is the debug port. */
391                 pr_info("Selecting UARTB as the debug console\n");
392                 cardhu_uart_devices[1] = &debug_uartb_device;
393                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
394                 debug_uart_port_base = ((struct plat_serial8250_port *)(
395                         debug_uartb_device.dev.platform_data))->mapbase;
396                 break;
397
398         case 2:
399                 /* UARTC is the debug port. */
400                 pr_info("Selecting UARTC as the debug console\n");
401                 cardhu_uart_devices[2] = &debug_uartc_device;
402                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
403                 debug_uart_port_base = ((struct plat_serial8250_port *)(
404                         debug_uartc_device.dev.platform_data))->mapbase;
405                 break;
406
407         case 3:
408                 /* UARTD is the debug port. */
409                 pr_info("Selecting UARTD as the debug console\n");
410                 cardhu_uart_devices[3] = &debug_uartd_device;
411                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
412                 debug_uart_port_base = ((struct plat_serial8250_port *)(
413                         debug_uartd_device.dev.platform_data))->mapbase;
414                 break;
415
416         case 4:
417                 /* UARTE is the debug port. */
418                 pr_info("Selecting UARTE as the debug console\n");
419                 cardhu_uart_devices[4] = &debug_uarte_device;
420                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
421                 debug_uart_port_base = ((struct plat_serial8250_port *)(
422                         debug_uarte_device.dev.platform_data))->mapbase;
423                 break;
424
425         default:
426                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
427                 cardhu_uart_devices[0] = &debug_uarta_device;
428                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
429                 debug_uart_port_base = ((struct plat_serial8250_port *)(
430                         debug_uarta_device.dev.platform_data))->mapbase;
431                 break;
432         }
433         return;
434 }
435
436 static void __init cardhu_uart_init(void)
437 {
438         struct clk *c;
439         int i;
440
441         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
442                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
443                 if (IS_ERR_OR_NULL(c)) {
444                         pr_err("Not able to get the clock for %s\n",
445                                                 uart_parent_clk[i].name);
446                         continue;
447                 }
448                 uart_parent_clk[i].parent_clk = c;
449                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
450         }
451         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
452         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
453         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
454         cardhu_loopback_uart_pdata.parent_clk_count =
455                                                 ARRAY_SIZE(uart_parent_clk);
456         cardhu_loopback_uart_pdata.is_loopback = true;
457         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
458         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
459         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
460         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
461         /* UARTE is used for loopback test purpose */
462         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
463
464         /* Register low speed only if it is selected */
465         if (!is_tegra_debug_uartport_hs()) {
466                 uart_debug_init();
467                 /* Clock enable for the debug channel */
468                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
469                         pr_info("The debug console clock name is %s\n",
470                                                 debug_uart_clk->name);
471                         c = tegra_get_clock_by_name("pll_p");
472                         if (IS_ERR_OR_NULL(c))
473                                 pr_err("Not getting the parent clock pll_p\n");
474                         else
475                                 clk_set_parent(debug_uart_clk, c);
476
477                         clk_enable(debug_uart_clk);
478                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
479                 } else {
480                         pr_err("Not getting the clock %s for debug console\n",
481                                         debug_uart_clk->name);
482                 }
483         }
484
485         platform_add_devices(cardhu_uart_devices,
486                                 ARRAY_SIZE(cardhu_uart_devices));
487 }
488
489 static struct platform_device tegra_camera = {
490         .name = "tegra_camera",
491         .id = -1,
492 };
493
494 static struct platform_device *cardhu_spi_devices[] __initdata = {
495         &tegra_spi_device4,
496 };
497
498 struct spi_clk_parent spi_parent_clk[] = {
499         [0] = {.name = "pll_p"},
500 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
501         [1] = {.name = "pll_m"},
502         [2] = {.name = "clk_m"},
503 #else
504         [1] = {.name = "clk_m"},
505 #endif
506 };
507
508 static struct tegra_spi_platform_data cardhu_spi_pdata = {
509         .is_dma_based           = true,
510         .max_dma_buffer         = (16 * 1024),
511         .is_clkon_always        = false,
512         .max_rate               = 100000000,
513 };
514
515 static void __init cardhu_spi_init(void)
516 {
517         int i;
518         struct clk *c;
519         struct board_info board_info;
520
521         tegra_get_board_info(&board_info);
522
523         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
524                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
525                 if (IS_ERR_OR_NULL(c)) {
526                         pr_err("Not able to get the clock for %s\n",
527                                                 spi_parent_clk[i].name);
528                         continue;
529                 }
530                 spi_parent_clk[i].parent_clk = c;
531                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
532         }
533         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
534         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
535         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
536         platform_add_devices(cardhu_spi_devices,
537                                 ARRAY_SIZE(cardhu_spi_devices));
538
539         if (board_info.board_id == BOARD_E1198) {
540                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
541                 platform_device_register(&tegra_spi_device2);
542                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
543                 platform_device_register(&tegra_spi_slave_device1);
544         }
545 }
546
547 static struct resource tegra_rtc_resources[] = {
548         [0] = {
549                 .start = TEGRA_RTC_BASE,
550                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
551                 .flags = IORESOURCE_MEM,
552         },
553         [1] = {
554                 .start = INT_RTC,
555                 .end = INT_RTC,
556                 .flags = IORESOURCE_IRQ,
557         },
558 };
559
560 static struct platform_device tegra_rtc_device = {
561         .name = "tegra_rtc",
562         .id   = -1,
563         .resource = tegra_rtc_resources,
564         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
565 };
566
567 static struct tegra_wm8903_platform_data cardhu_audio_pdata = {
568         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
569         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
570         .gpio_hp_mute           = -1,
571         .gpio_int_mic_en        = -1,
572         .gpio_ext_mic_en        = -1,
573 };
574
575 static struct platform_device cardhu_audio_device = {
576         .name   = "tegra-snd-wm8903",
577         .id     = 0,
578         .dev    = {
579                 .platform_data  = &cardhu_audio_pdata,
580         },
581 };
582
583 static struct platform_device *cardhu_devices[] __initdata = {
584         &tegra_pmu_device,
585         &tegra_rtc_device,
586         &tegra_udc_device,
587 #if defined(CONFIG_TEGRA_IOVMM_SMMU)
588         &tegra_smmu_device,
589 #endif
590         &tegra_wdt_device,
591 #if defined(CONFIG_TEGRA_AVP)
592         &tegra_avp_device,
593 #endif
594         &tegra_camera,
595 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
596         &tegra_se_device,
597 #endif
598         &tegra_ahub_device,
599         &tegra_dam_device0,
600         &tegra_dam_device1,
601         &tegra_dam_device2,
602         &tegra_i2s_device1,
603         &tegra_i2s_device3,
604         &tegra_spdif_device,
605         &spdif_dit_device,
606         &bluetooth_dit_device,
607         &tegra_pcm_device,
608         &cardhu_audio_device,
609         &tegra_hda_device,
610 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
611         &tegra_aes_device,
612 #endif
613 };
614
615 #define MXT_CONFIG_CRC  0xD62DE8
616 static const u8 config[] = {
617         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
618         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
619         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
620         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
621         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
622         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
623         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
624         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
625         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
626         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
627         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
628         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
629         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
630         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
631         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
632         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
633         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
634         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
635         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
636         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
637 };
638
639 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
640 static const u8 config_sku2000[] = {
641         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
642         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
643         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
644         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
645         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
646         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
647         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
648         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
649         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
650         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
651         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
652         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
653         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
654         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
655         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
656         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
657         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
658         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
659         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
660         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
661 };
662
663 static struct mxt_platform_data atmel_mxt_info = {
664         .x_line         = 27,
665         .y_line         = 42,
666         .x_size         = 768,
667         .y_size         = 1366,
668         .blen           = 0x20,
669         .threshold      = 0x3C,
670         .voltage        = 3300000,              /* 3.3V */
671         .orient         = 5,
672         .config         = config,
673         .config_length  = 157,
674         .config_crc     = MXT_CONFIG_CRC,
675         .irqflags       = IRQF_TRIGGER_FALLING,
676 /*      .read_chg       = &read_chg, */
677         .read_chg       = NULL,
678 };
679
680 static struct i2c_board_info __initdata atmel_i2c_info[] = {
681         {
682                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
683                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
684                 .platform_data = &atmel_mxt_info,
685         }
686 };
687
688 static int __init cardhu_touch_init(void)
689 {
690         struct board_info BoardInfo;
691
692         tegra_gpio_enable(TEGRA_GPIO_PH4);
693         tegra_gpio_enable(TEGRA_GPIO_PH6);
694
695         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
696         gpio_direction_input(TEGRA_GPIO_PH4);
697
698         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
699         gpio_direction_output(TEGRA_GPIO_PH6, 0);
700         msleep(1);
701         gpio_set_value(TEGRA_GPIO_PH6, 1);
702         msleep(100);
703
704         tegra_get_board_info(&BoardInfo);
705         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
706                 atmel_mxt_info.config = config_sku2000;
707                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
708         }
709
710         i2c_register_board_info(1, atmel_i2c_info, 1);
711
712         return 0;
713 }
714
715 static struct tegra_uhsic_config uhsic_phy_config = {
716         .enable_gpio = EN_HSIC_GPIO,
717         .reset_gpio = -1,
718         .sync_start_delay = 9,
719         .idle_wait_delay = 17,
720         .term_range_adj = 0,
721         .elastic_underrun_limit = 16,
722         .elastic_overrun_limit = 16,
723 };
724
725 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
726         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
727         .phy_config = &uhsic_phy_config,
728         .operating_mode = TEGRA_USB_HOST,
729         .power_down_on_bus_suspend = 1,
730 };
731
732 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
733         [0] = {
734                         .phy_config = &utmi_phy_config[0],
735                         .operating_mode = TEGRA_USB_HOST,
736                         .power_down_on_bus_suspend = 1,
737         },
738         [1] = {
739                         .phy_config = &utmi_phy_config[1],
740                         .operating_mode = TEGRA_USB_HOST,
741                         .power_down_on_bus_suspend = 1,
742         },
743         [2] = {
744                         .phy_config = &utmi_phy_config[2],
745                         .operating_mode = TEGRA_USB_HOST,
746                         .power_down_on_bus_suspend = 1,
747                         .hotplug = 1,
748         },
749 };
750
751 static struct tegra_otg_platform_data tegra_otg_pdata = {
752         .ehci_device = &tegra_ehci1_device,
753         .ehci_pdata = &tegra_ehci_pdata[0],
754 };
755
756 #ifdef CONFIG_USB_SUPPORT
757 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
758         [0] = {
759                         .instance = 0,
760                         .vbus_gpio = -1,
761                         .vbus_reg_supply = "vdd_vbus_micro_usb",
762         },
763         [1] = {
764                         .instance = 1,
765                         .vbus_gpio = -1,
766         },
767         [2] = {
768                         .instance = 2,
769                         .vbus_gpio = -1,
770                         .vbus_reg_supply = "vdd_vbus_typea_usb",
771         },
772 };
773
774 static void cardhu_usb_init(void)
775 {
776         struct board_info bi;
777
778         tegra_get_board_info(&bi);
779
780         tegra_usb_phy_init(tegra_usb_phy_pdata,
781                         ARRAY_SIZE(tegra_usb_phy_pdata));
782
783         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
784         platform_device_register(&tegra_otg_device);
785         if (bi.board_id == BOARD_PM267) {
786                 uhsic_phy_config.reset_gpio =
787                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
788                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
789                 platform_device_register(&tegra_ehci2_device);
790         } else if (bi.board_id == BOARD_E1256) {
791                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
792                 platform_device_register(&tegra_ehci2_device);
793         } else if (bi.board_id == BOARD_E1186) {
794                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
795                 /* baseband registration happens in baseband-xmm-power  */
796         } else {
797                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
798                 platform_device_register(&tegra_ehci2_device);
799         }
800
801         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
802         platform_device_register(&tegra_ehci3_device);
803
804 }
805 #else
806 static void cardhu_usb_init(void) { }
807 #endif
808
809 static void cardhu_gps_init(void)
810 {
811         tegra_gpio_enable(TEGRA_GPIO_PU2);
812         tegra_gpio_enable(TEGRA_GPIO_PU3);
813 }
814
815 static void cardhu_nfc_init(void)
816 {
817         tegra_gpio_enable(TEGRA_GPIO_PX0);
818         tegra_gpio_enable(TEGRA_GPIO_PP3);
819         tegra_gpio_enable(TEGRA_GPIO_PO7);
820 }
821
822 static struct baseband_power_platform_data tegra_baseband_power_data = {
823         .baseband_type = BASEBAND_XMM,
824         .modem = {
825         .xmm = {
826                         .bb_rst = XMM_GPIO_BB_RST,
827                         .bb_on = XMM_GPIO_BB_ON,
828                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
829                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
830                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
831                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
832                         .hsic_device = &tegra_ehci2_device,
833                 },
834         },
835 };
836
837 static struct platform_device tegra_baseband_power_device = {
838         .name = "baseband_xmm_power",
839         .id = -1,
840         .dev = {
841                 .platform_data = &tegra_baseband_power_data,
842         },
843 };
844
845 static struct platform_device tegra_baseband_power2_device = {
846         .name = "baseband_xmm_power2",
847         .id = -1,
848         .dev = {
849                 .platform_data = &tegra_baseband_power_data,
850         },
851 };
852
853
854 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
855         .port_status[0] = 1,
856         .port_status[1] = 1,
857         .port_status[2] = 1,
858         .use_dock_detect        = 0,
859         .gpio           = 0,
860 };
861
862 static void cardhu_pci_init(void)
863 {
864         struct board_info board_info;
865
866         tegra_get_board_info(&board_info);
867         if (board_info.board_id == BOARD_E1291) {
868                 cardhu_pci_platform_data.port_status[0] = 0;
869                 cardhu_pci_platform_data.port_status[1] = 0;
870                 cardhu_pci_platform_data.port_status[2] = 1;
871                 cardhu_pci_platform_data.use_dock_detect = 1;
872                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
873         }
874         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
875         platform_device_register(&tegra_pci_device);
876 }
877
878 static void cardhu_modem_init(void)
879 {
880         struct board_info board_info;
881         int w_disable_gpio, ret;
882
883         tegra_get_board_info(&board_info);
884         switch (board_info.board_id) {
885         case BOARD_E1291:
886         case BOARD_E1198:
887                 if (((board_info.board_id == BOARD_E1291) &&
888                                 (board_info.fab < BOARD_FAB_A03)) ||
889                         ((board_info.board_id == BOARD_E1198) &&
890                                         (board_info.fab < BOARD_FAB_A02))) {
891                         w_disable_gpio = TEGRA_GPIO_PH5;
892                 } else {
893                         w_disable_gpio = TEGRA_GPIO_PDD5;
894                 }
895                 tegra_gpio_enable(w_disable_gpio);
896                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
897                 if (ret < 0)
898                         pr_err("%s: gpio_request failed for gpio %d\n",
899                                 __func__, w_disable_gpio);
900                 else
901                         gpio_direction_input(w_disable_gpio);
902
903                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
904                 if (((board_info.board_id == BOARD_E1291) &&
905                                 (board_info.fab >= BOARD_FAB_A04)) ||
906                         ((board_info.board_id == BOARD_E1198) &&
907                                         (board_info.fab >= BOARD_FAB_A02))) {
908                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
909                         if (ret < 0) {
910                                 pr_err("%s(): Error in allocating gpio "
911                                         "TEGRA_GPIO_PH7\n", __func__);
912                                 break;
913                         }
914                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
915                         tegra_gpio_enable(TEGRA_GPIO_PH7);
916                 }
917                 break;
918         case BOARD_E1186:
919                 tegra_gpio_enable(
920                         tegra_baseband_power_data.modem.xmm.bb_rst);
921                 tegra_gpio_enable(
922                         tegra_baseband_power_data.modem.xmm.bb_on);
923                 tegra_gpio_enable(
924                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
925                 tegra_gpio_enable(
926                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
927                 tegra_gpio_enable(
928                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
929                 tegra_gpio_enable(
930                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
931                 platform_device_register(&tegra_baseband_power_device);
932                 platform_device_register(&tegra_baseband_power2_device);
933                 break;
934         default:
935                 break;
936         }
937
938 }
939
940 #ifdef CONFIG_SATA_AHCI_TEGRA
941 static void cardhu_sata_init(void)
942 {
943         platform_device_register(&tegra_sata_device);
944 }
945 #else
946 static void cardhu_sata_init(void) { }
947 #endif
948
949 static void __init tegra_cardhu_init(void)
950 {
951         tegra_thermal_init(&thermal_data);
952         tegra_clk_init_from_table(cardhu_clk_init_table);
953         cardhu_pinmux_init();
954         cardhu_i2c_init();
955         cardhu_spi_init();
956         cardhu_usb_init();
957 #ifdef CONFIG_TEGRA_EDP_LIMITS
958         cardhu_edp_init();
959 #endif
960         cardhu_uart_init();
961         cardhu_tsensor_init();
962         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
963         cardhu_sdhci_init();
964         cardhu_regulator_init();
965         cardhu_gpio_switch_regulator_init();
966         cardhu_suspend_init();
967         cardhu_power_off_init();
968         cardhu_touch_init();
969         cardhu_gps_init();
970         cardhu_modem_init();
971         cardhu_kbc_init();
972         cardhu_scroll_init();
973         cardhu_keys_init();
974         cardhu_panel_init();
975         cardhu_pmon_init();
976         cardhu_sensors_init();
977         cardhu_bt_rfkill();
978         tegra_setup_bluesleep();
979         cardhu_sata_init();
980         //audio_wired_jack_init();
981         cardhu_pins_state_init();
982         cardhu_emc_init();
983         tegra_release_bootloader_fb();
984         cardhu_nfc_init();
985         cardhu_pci_init();
986 #ifdef CONFIG_TEGRA_WDT_RECOVERY
987         tegra_wdt_recovery_init();
988 #endif
989 }
990
991 static void __init tegra_cardhu_reserve(void)
992 {
993 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
994         /* support 1920X1200 with 24bpp */
995         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
996 #else
997         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
998 #endif
999 }
1000
1001 MACHINE_START(CARDHU, "cardhu")
1002         .boot_params    = 0x80000100,
1003         .map_io         = tegra_map_common_io,
1004         .reserve        = tegra_cardhu_reserve,
1005         .init_early     = tegra_init_early,
1006         .init_irq       = tegra_init_irq,
1007         .timer          = &tegra_timer,
1008         .init_machine   = tegra_cardhu_init,
1009 MACHINE_END