ARM: tegra: cardhu: add device TI aic326x codec
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41
42 #include <sound/wm8903.h>
43 #include <media/tegra_dtv.h>
44
45 #include <mach/clk.h>
46 #include <mach/iomap.h>
47 #include <mach/irqs.h>
48 #include <mach/pinmux.h>
49 #include <mach/iomap.h>
50 #include <mach/io.h>
51 #include <mach/i2s.h>
52 #include <mach/tegra_wm8903_pdata.h>
53 #include <mach/tegra_aic326x_pdata.h>
54 #include <asm/mach-types.h>
55 #include <asm/mach/arch.h>
56 #include <mach/usb_phy.h>
57 #include <mach/thermal.h>
58 #include <mach/pci.h>
59
60 #include "board.h"
61 #include "clock.h"
62 #include "board-cardhu.h"
63 #include "devices.h"
64 #include "gpio-names.h"
65 #include "fuse.h"
66 #include "pm.h"
67 #include "baseband-xmm-power.h"
68 #include "wdt-recovery.h"
69
70 /* All units are in millicelsius */
71 static struct tegra_thermal_data thermal_data = {
72         .temp_throttle = 85000,
73         .temp_shutdown = 90000,
74         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
75 #ifdef CONFIG_TEGRA_EDP_LIMITS
76         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
77         .hysteresis_edp = 3000,
78 #endif
79 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
80         .tc1 = 0,
81         .tc2 = 1,
82         .passive_delay = 2000,
83 #else
84         .hysteresis_throttle = 1000,
85 #endif
86 };
87
88 /* !!!TODO: Change for cardhu (Taken from Ventana) */
89 static struct tegra_utmip_config utmi_phy_config[] = {
90         [0] = {
91                         .hssync_start_delay = 0,
92                         .idle_wait_delay = 17,
93                         .elastic_limit = 16,
94                         .term_range_adj = 6,
95                         .xcvr_setup = 15,
96                         .xcvr_setup_offset = 0,
97                         .xcvr_use_fuses = 1,
98                         .xcvr_lsfslew = 2,
99                         .xcvr_lsrslew = 2,
100         },
101         [1] = {
102                         .hssync_start_delay = 0,
103                         .idle_wait_delay = 17,
104                         .elastic_limit = 16,
105                         .term_range_adj = 6,
106                         .xcvr_setup = 15,
107                         .xcvr_setup_offset = 0,
108                         .xcvr_use_fuses = 1,
109                         .xcvr_lsfslew = 2,
110                         .xcvr_lsrslew = 2,
111         },
112         [2] = {
113                         .hssync_start_delay = 0,
114                         .idle_wait_delay = 17,
115                         .elastic_limit = 16,
116                         .term_range_adj = 6,
117                         .xcvr_setup = 8,
118                         .xcvr_setup_offset = 0,
119                         .xcvr_use_fuses = 1,
120                         .xcvr_lsfslew = 2,
121                         .xcvr_lsrslew = 2,
122         },
123 };
124
125 #ifdef CONFIG_BCM4329_RFKILL
126 static struct resource cardhu_bcm4329_rfkill_resources[] = {
127         {
128                 .name   = "bcm4329_nshutdown_gpio",
129                 .start  = TEGRA_GPIO_PU0,
130                 .end    = TEGRA_GPIO_PU0,
131                 .flags  = IORESOURCE_IO,
132         },
133 };
134
135 static struct platform_device cardhu_bcm4329_rfkill_device = {
136         .name = "bcm4329_rfkill",
137         .id             = -1,
138         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
139         .resource       = cardhu_bcm4329_rfkill_resources,
140 };
141
142 static noinline void __init cardhu_bt_rfkill(void)
143 {
144         platform_device_register(&cardhu_bcm4329_rfkill_device);
145
146         return;
147 }
148 #else
149 static inline void cardhu_bt_rfkill(void) { }
150 #endif
151
152 #ifdef CONFIG_BT_BLUESLEEP
153 static noinline void __init tegra_setup_bluesleep(void)
154 {
155         struct platform_device *pdev = NULL;
156         struct resource *res;
157
158         pdev = platform_device_alloc("bluesleep", 0);
159         if (!pdev) {
160                 pr_err("unable to allocate platform device for bluesleep");
161                 return;
162         }
163
164         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
165         if (!res) {
166                 pr_err("unable to allocate resource for bluesleep\n");
167                 goto err_free_dev;
168         }
169
170         res[0].name   = "gpio_host_wake";
171         res[0].start  = TEGRA_GPIO_PU6;
172         res[0].end    = TEGRA_GPIO_PU6;
173         res[0].flags  = IORESOURCE_IO;
174
175         res[1].name   = "gpio_ext_wake";
176         res[1].start  = TEGRA_GPIO_PU1;
177         res[1].end    = TEGRA_GPIO_PU1;
178         res[1].flags  = IORESOURCE_IO;
179
180         res[2].name   = "host_wake";
181         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
182         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
183         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
184
185         if (platform_device_add_resources(pdev, res, 3)) {
186                 pr_err("unable to add resources to bluesleep device\n");
187                 goto err_free_res;
188         }
189
190         if (platform_device_add(pdev)) {
191                 pr_err("unable to add bluesleep device\n");
192                 goto err_free_res;
193         }
194         tegra_gpio_enable(TEGRA_GPIO_PU6);
195         tegra_gpio_enable(TEGRA_GPIO_PU1);
196
197 return;
198
199 err_free_res:
200         kfree(res);
201 err_free_dev:
202         platform_device_put(pdev);
203         return;
204 }
205 #else
206 static inline void tegra_setup_bluesleep(void) { }
207 #endif
208
209 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
210         /* name         parent          rate            enabled */
211         { "pll_m",      NULL,           0,              false},
212         { "hda",        "pll_p",        108000000,      false},
213         { "hda2codec_2x","pll_p",       48000000,       false},
214         { "pwm",        "pll_p",        3187500,        false},
215         { "blink",      "clk_32k",      32768,          true},
216         { "i2s0",       "pll_a_out0",   0,              false},
217         { "i2s1",       "pll_a_out0",   0,              false},
218         { "i2s3",       "pll_a_out0",   0,              false},
219         { "spdif_out",  "pll_a_out0",   0,              false},
220         { "d_audio",    "clk_m",        12000000,       false},
221         { "dam0",       "clk_m",        12000000,       false},
222         { "dam1",       "clk_m",        12000000,       false},
223         { "dam2",       "clk_m",        12000000,       false},
224         { "audio1",     "i2s1_sync",    0,              false},
225         { "audio3",     "i2s3_sync",    0,              false},
226         { "vi_sensor",  "pll_p",        150000000,      false},
227         { "i2c1",       "pll_p",        3200000,        false},
228         { "i2c2",       "pll_p",        3200000,        false},
229         { "i2c3",       "pll_p",        3200000,        false},
230         { "i2c4",       "pll_p",        3200000,        false},
231         { "i2c5",       "pll_p",        3200000,        false},
232         { NULL,         NULL,           0,              0},
233 };
234
235 static struct pn544_i2c_platform_data nfc_pdata = {
236         .irq_gpio = TEGRA_GPIO_PX0,
237         .ven_gpio = TEGRA_GPIO_PP3,
238         .firm_gpio = TEGRA_GPIO_PO7,
239         };
240
241 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
242         {
243                 I2C_BOARD_INFO("pn544", 0x28),
244                 .platform_data = &nfc_pdata,
245                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
246         },
247 };
248 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
249         .adapter_nr     = 0,
250         .bus_count      = 1,
251         .bus_clk_rate   = { 100000, 0 },
252         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
253         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
254         .arb_recovery = arb_lost_recovery,
255 };
256
257 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
258         .adapter_nr     = 1,
259         .bus_count      = 1,
260         .bus_clk_rate   = { 100000, 0 },
261         .is_clkon_always = true,
262         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
263         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
264         .arb_recovery = arb_lost_recovery,
265 };
266
267 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
268         .adapter_nr     = 2,
269         .bus_count      = 1,
270         .bus_clk_rate   = { 100000, 0 },
271         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
272         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
273         .arb_recovery = arb_lost_recovery,
274 };
275
276 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
277         .adapter_nr     = 3,
278         .bus_count      = 1,
279         .bus_clk_rate   = { 100000, 0 },
280         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
281         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
282         .arb_recovery = arb_lost_recovery,
283 };
284
285 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
286         .adapter_nr     = 4,
287         .bus_count      = 1,
288         .bus_clk_rate   = { 400000, 0 },
289         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
290         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
291         .arb_recovery = arb_lost_recovery,
292 };
293
294
295 #if 0
296 struct tegra_wired_jack_conf audio_wr_jack_conf = {
297         .hp_det_n = TEGRA_GPIO_PW2,
298         .en_mic_ext = TEGRA_GPIO_PX1,
299         .en_mic_int = TEGRA_GPIO_PX0,
300 };
301 #endif
302
303 static struct wm8903_platform_data cardhu_wm8903_pdata = {
304         .irq_active_low = 0,
305         .micdet_cfg = 0,
306         .micdet_delay = 100,
307         .gpio_base = CARDHU_GPIO_WM8903(0),
308         .gpio_cfg = {
309                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
310                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
311                         WM8903_GP2_DIR,
312                 0,
313                 WM8903_GPIO_NO_CONFIG,
314                 WM8903_GPIO_NO_CONFIG,
315         },
316 };
317
318 static struct wm8903_platform_data cardhu_aic3262_pdata = {
319         .irq_active_low = 0,
320         .micdet_cfg = 0,
321         .micdet_delay = 100,
322 };
323
324 static struct i2c_board_info __initdata cardhu_board_info[] = {
325         {
326                 I2C_BOARD_INFO("wm8903", 0x1a),
327                 .platform_data = &cardhu_wm8903_pdata,
328                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
329         },
330         {
331                 I2C_BOARD_INFO("aic3262-codec", 0x18),
332                 .platform_data=&cardhu_aic3262_pdata,
333                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
334         },
335 };
336
337
338 static void cardhu_i2c_init(void)
339 {
340         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
341         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
342         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
343         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
344         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
345
346         platform_device_register(&tegra_i2c_device5);
347         platform_device_register(&tegra_i2c_device4);
348         platform_device_register(&tegra_i2c_device3);
349         platform_device_register(&tegra_i2c_device2);
350         platform_device_register(&tegra_i2c_device1);
351
352         i2c_register_board_info(4, cardhu_board_info, ARRAY_SIZE(cardhu_board_info));
353
354         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
355 }
356
357 static struct platform_device *cardhu_uart_devices[] __initdata = {
358         &tegra_uarta_device,
359         &tegra_uartb_device,
360         &tegra_uartc_device,
361         &tegra_uartd_device,
362         &tegra_uarte_device,
363 };
364 static struct uart_clk_parent uart_parent_clk[] = {
365         [0] = {.name = "clk_m"},
366         [1] = {.name = "pll_p"},
367 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
368         [2] = {.name = "pll_m"},
369 #endif
370 };
371
372 static struct tegra_uart_platform_data cardhu_uart_pdata;
373 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
374
375 static void __init uart_debug_init(void)
376 {
377         struct board_info board_info;
378         int debug_port_id;
379
380         tegra_get_board_info(&board_info);
381
382         debug_port_id = get_tegra_uart_debug_port_id();
383         if (debug_port_id < 0) {
384                 debug_port_id = 0;
385                         /* UARTB is debug port
386                          *       for SLT - E1186/E1187/PM269
387                          *       for E1256/E1257
388                          */
389                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
390                         ((board_info.board_id == BOARD_E1186) ||
391                         (board_info.board_id == BOARD_E1187) ||
392                         (board_info.board_id == BOARD_PM269))) ||
393                         (board_info.board_id == BOARD_E1256) ||
394                         (board_info.board_id == BOARD_E1257))
395                                 debug_port_id = 1;
396         }
397
398         tegra_init_debug_uart_rate();
399         switch (debug_port_id) {
400         case 0:
401                 /* UARTA is the debug port. */
402                 pr_info("Selecting UARTA as the debug console\n");
403                 cardhu_uart_devices[0] = &debug_uarta_device;
404                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
405                 debug_uart_port_base = ((struct plat_serial8250_port *)(
406                         debug_uarta_device.dev.platform_data))->mapbase;
407                 break;
408
409         case 1:
410                 /* UARTB is the debug port. */
411                 pr_info("Selecting UARTB as the debug console\n");
412                 cardhu_uart_devices[1] = &debug_uartb_device;
413                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
414                 debug_uart_port_base = ((struct plat_serial8250_port *)(
415                         debug_uartb_device.dev.platform_data))->mapbase;
416                 break;
417
418         case 2:
419                 /* UARTC is the debug port. */
420                 pr_info("Selecting UARTC as the debug console\n");
421                 cardhu_uart_devices[2] = &debug_uartc_device;
422                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
423                 debug_uart_port_base = ((struct plat_serial8250_port *)(
424                         debug_uartc_device.dev.platform_data))->mapbase;
425                 break;
426
427         case 3:
428                 /* UARTD is the debug port. */
429                 pr_info("Selecting UARTD as the debug console\n");
430                 cardhu_uart_devices[3] = &debug_uartd_device;
431                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
432                 debug_uart_port_base = ((struct plat_serial8250_port *)(
433                         debug_uartd_device.dev.platform_data))->mapbase;
434                 break;
435
436         case 4:
437                 /* UARTE is the debug port. */
438                 pr_info("Selecting UARTE as the debug console\n");
439                 cardhu_uart_devices[4] = &debug_uarte_device;
440                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
441                 debug_uart_port_base = ((struct plat_serial8250_port *)(
442                         debug_uarte_device.dev.platform_data))->mapbase;
443                 break;
444
445         default:
446                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
447                 cardhu_uart_devices[0] = &debug_uarta_device;
448                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
449                 debug_uart_port_base = ((struct plat_serial8250_port *)(
450                         debug_uarta_device.dev.platform_data))->mapbase;
451                 break;
452         }
453         return;
454 }
455
456 static void __init cardhu_uart_init(void)
457 {
458         struct clk *c;
459         int i;
460
461         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
462                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
463                 if (IS_ERR_OR_NULL(c)) {
464                         pr_err("Not able to get the clock for %s\n",
465                                                 uart_parent_clk[i].name);
466                         continue;
467                 }
468                 uart_parent_clk[i].parent_clk = c;
469                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
470         }
471         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
472         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
473         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
474         cardhu_loopback_uart_pdata.parent_clk_count =
475                                                 ARRAY_SIZE(uart_parent_clk);
476         cardhu_loopback_uart_pdata.is_loopback = true;
477         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
478         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
479         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
480         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
481         /* UARTE is used for loopback test purpose */
482         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
483
484         /* Register low speed only if it is selected */
485         if (!is_tegra_debug_uartport_hs()) {
486                 uart_debug_init();
487                 /* Clock enable for the debug channel */
488                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
489                         pr_info("The debug console clock name is %s\n",
490                                                 debug_uart_clk->name);
491                         c = tegra_get_clock_by_name("pll_p");
492                         if (IS_ERR_OR_NULL(c))
493                                 pr_err("Not getting the parent clock pll_p\n");
494                         else
495                                 clk_set_parent(debug_uart_clk, c);
496
497                         clk_enable(debug_uart_clk);
498                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
499                 } else {
500                         pr_err("Not getting the clock %s for debug console\n",
501                                         debug_uart_clk->name);
502                 }
503         }
504
505         platform_add_devices(cardhu_uart_devices,
506                                 ARRAY_SIZE(cardhu_uart_devices));
507 }
508
509 static struct platform_device tegra_camera = {
510         .name = "tegra_camera",
511         .id = -1,
512 };
513
514 static struct platform_device *cardhu_spi_devices[] __initdata = {
515         &tegra_spi_device4,
516 };
517
518 struct spi_clk_parent spi_parent_clk[] = {
519         [0] = {.name = "pll_p"},
520 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
521         [1] = {.name = "pll_m"},
522         [2] = {.name = "clk_m"},
523 #else
524         [1] = {.name = "clk_m"},
525 #endif
526 };
527
528 static struct tegra_spi_platform_data cardhu_spi_pdata = {
529         .is_dma_based           = true,
530         .max_dma_buffer         = (16 * 1024),
531         .is_clkon_always        = false,
532         .max_rate               = 100000000,
533 };
534
535 static void __init cardhu_spi_init(void)
536 {
537         int i;
538         struct clk *c;
539         struct board_info board_info;
540
541         tegra_get_board_info(&board_info);
542
543         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
544                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
545                 if (IS_ERR_OR_NULL(c)) {
546                         pr_err("Not able to get the clock for %s\n",
547                                                 spi_parent_clk[i].name);
548                         continue;
549                 }
550                 spi_parent_clk[i].parent_clk = c;
551                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
552         }
553         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
554         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
555         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
556         platform_add_devices(cardhu_spi_devices,
557                                 ARRAY_SIZE(cardhu_spi_devices));
558
559         if (board_info.board_id == BOARD_E1198) {
560                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
561                 platform_device_register(&tegra_spi_device2);
562                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
563                 platform_device_register(&tegra_spi_slave_device1);
564         }
565 }
566
567 static void __init cardhu_dtv_init(void)
568 {
569         struct board_info board_info;
570
571         tegra_get_board_info(&board_info);
572
573         if (board_info.board_id == BOARD_E1186)
574                 platform_device_register(&tegra_dtv_device);
575 }
576
577 static struct resource tegra_rtc_resources[] = {
578         [0] = {
579                 .start = TEGRA_RTC_BASE,
580                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
581                 .flags = IORESOURCE_MEM,
582         },
583         [1] = {
584                 .start = INT_RTC,
585                 .end = INT_RTC,
586                 .flags = IORESOURCE_IRQ,
587         },
588 };
589
590 static struct platform_device tegra_rtc_device = {
591         .name = "tegra_rtc",
592         .id   = -1,
593         .resource = tegra_rtc_resources,
594         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
595 };
596
597 static struct tegra_wm8903_platform_data cardhu_audio_pdata = {
598         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
599         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
600         .gpio_hp_mute           = -1,
601         .gpio_int_mic_en        = -1,
602         .gpio_ext_mic_en        = -1,
603 };
604
605 static struct platform_device cardhu_audio_device = {
606         .name   = "tegra-snd-wm8903",
607         .id     = 0,
608         .dev    = {
609                 .platform_data  = &cardhu_audio_pdata,
610         },
611 };
612
613 static struct tegra_aic326x_platform_data cardhu_aic326x_audio_pdata = {
614         .gpio_spkr_en           = -1,
615         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
616         .gpio_hp_mute           = -1,
617         .gpio_int_mic_en        = -1,
618         .gpio_ext_mic_en        = -1,
619 };
620
621 static struct platform_device cardhu_aic326x_audio_device = {
622         .name   = "tegra-snd-aic326x",
623         .id     = 0,
624         .dev    = {
625                 .platform_data  = &cardhu_aic326x_audio_pdata,
626         },
627 };
628
629 static struct platform_device *cardhu_devices[] __initdata = {
630         &tegra_pmu_device,
631         &tegra_rtc_device,
632         &tegra_udc_device,
633 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
634         &tegra_smmu_device,
635 #endif
636         &tegra_wdt_device,
637 #if defined(CONFIG_TEGRA_AVP)
638         &tegra_avp_device,
639 #endif
640         &tegra_camera,
641 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
642         &tegra_se_device,
643 #endif
644         &tegra_ahub_device,
645         &tegra_dam_device0,
646         &tegra_dam_device1,
647         &tegra_dam_device2,
648         &tegra_i2s_device0,
649         &tegra_i2s_device1,
650         &tegra_i2s_device3,
651         &tegra_spdif_device,
652         &spdif_dit_device,
653         &bluetooth_dit_device,
654         &baseband_dit_device,
655         &tegra_pcm_device,
656         &cardhu_audio_device,
657         &cardhu_aic326x_audio_device,
658         &tegra_hda_device,
659 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
660         &tegra_aes_device,
661 #endif
662 };
663
664 #define MXT_CONFIG_CRC  0xD62DE8
665 static const u8 config[] = {
666         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
667         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
668         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
669         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
670         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
671         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
672         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
673         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
674         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
675         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
676         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
677         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
678         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
679         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
680         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
681         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
682         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
683         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
684         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
685         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
686 };
687
688 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
689 static const u8 config_sku2000[] = {
690         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
691         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
692         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
693         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
694         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
695         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
696         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
697         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
698         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
699         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
700         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
701         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
702         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
703         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
704         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
705         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
706         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
707         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
708         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
709         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
710 };
711
712 static struct mxt_platform_data atmel_mxt_info = {
713         .x_line         = 27,
714         .y_line         = 42,
715         .x_size         = 768,
716         .y_size         = 1366,
717         .blen           = 0x20,
718         .threshold      = 0x3C,
719         .voltage        = 3300000,              /* 3.3V */
720         .orient         = 5,
721         .config         = config,
722         .config_length  = 157,
723         .config_crc     = MXT_CONFIG_CRC,
724         .irqflags       = IRQF_TRIGGER_FALLING,
725 /*      .read_chg       = &read_chg, */
726         .read_chg       = NULL,
727 };
728
729 static struct i2c_board_info __initdata atmel_i2c_info[] = {
730         {
731                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
732                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
733                 .platform_data = &atmel_mxt_info,
734         }
735 };
736
737 static int __init cardhu_touch_init(void)
738 {
739         struct board_info BoardInfo;
740
741         tegra_gpio_enable(TEGRA_GPIO_PH4);
742         tegra_gpio_enable(TEGRA_GPIO_PH6);
743
744         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
745         gpio_direction_input(TEGRA_GPIO_PH4);
746
747         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
748         gpio_direction_output(TEGRA_GPIO_PH6, 0);
749         msleep(1);
750         gpio_set_value(TEGRA_GPIO_PH6, 1);
751         msleep(100);
752
753         tegra_get_board_info(&BoardInfo);
754         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
755                 atmel_mxt_info.config = config_sku2000;
756                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
757         }
758
759         i2c_register_board_info(1, atmel_i2c_info, 1);
760
761         return 0;
762 }
763
764 static struct tegra_uhsic_config uhsic_phy_config = {
765         .enable_gpio = EN_HSIC_GPIO,
766         .reset_gpio = -1,
767         .sync_start_delay = 9,
768         .idle_wait_delay = 17,
769         .term_range_adj = 0,
770         .elastic_underrun_limit = 16,
771         .elastic_overrun_limit = 16,
772 };
773
774 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
775         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
776         .phy_config = &uhsic_phy_config,
777         .operating_mode = TEGRA_USB_HOST,
778         .power_down_on_bus_suspend = 1,
779         .default_enable = true,
780 };
781
782 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
783         [0] = {
784                         .phy_config = &utmi_phy_config[0],
785                         .operating_mode = TEGRA_USB_HOST,
786                         .power_down_on_bus_suspend = 1,
787                         .default_enable = true,
788         },
789         [1] = {
790                         .phy_config = &utmi_phy_config[1],
791                         .operating_mode = TEGRA_USB_HOST,
792                         .power_down_on_bus_suspend = 1,
793                         .default_enable = true,
794         },
795         [2] = {
796                         .phy_config = &utmi_phy_config[2],
797                         .operating_mode = TEGRA_USB_HOST,
798                         .power_down_on_bus_suspend = 1,
799                         .hotplug = 1,
800                         .default_enable = true,
801         },
802 };
803
804 static struct tegra_otg_platform_data tegra_otg_pdata = {
805         .ehci_device = &tegra_ehci1_device,
806         .ehci_pdata = &tegra_ehci_pdata[0],
807 };
808
809 #ifdef CONFIG_USB_SUPPORT
810 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
811         [0] = {
812                         .instance = 0,
813                         .vbus_gpio = -1,
814                         .vbus_reg_supply = "vdd_vbus_micro_usb",
815         },
816         [1] = {
817                         .instance = 1,
818                         .vbus_gpio = -1,
819         },
820         [2] = {
821                         .instance = 2,
822                         .vbus_gpio = -1,
823                         .vbus_reg_supply = "vdd_vbus_typea_usb",
824         },
825 };
826
827 static void cardhu_usb_init(void)
828 {
829         struct board_info bi;
830
831         tegra_get_board_info(&bi);
832
833         tegra_usb_phy_init(tegra_usb_phy_pdata,
834                         ARRAY_SIZE(tegra_usb_phy_pdata));
835
836         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
837         platform_device_register(&tegra_otg_device);
838         if (bi.board_id == BOARD_PM267) {
839                 uhsic_phy_config.reset_gpio =
840                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
841                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
842                 platform_device_register(&tegra_ehci2_device);
843         } else if (bi.board_id == BOARD_E1256) {
844                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
845                 platform_device_register(&tegra_ehci2_device);
846         } else if (bi.board_id == BOARD_E1186) {
847                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
848                 /* baseband registration happens in baseband-xmm-power  */
849         } else {
850                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
851                 platform_device_register(&tegra_ehci2_device);
852         }
853
854         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
855         platform_device_register(&tegra_ehci3_device);
856
857 }
858 #else
859 static void cardhu_usb_init(void) { }
860 #endif
861
862 static void cardhu_gps_init(void)
863 {
864         tegra_gpio_enable(TEGRA_GPIO_PU2);
865         tegra_gpio_enable(TEGRA_GPIO_PU3);
866 }
867
868 static void cardhu_nfc_init(void)
869 {
870         tegra_gpio_enable(TEGRA_GPIO_PX0);
871         tegra_gpio_enable(TEGRA_GPIO_PP3);
872         tegra_gpio_enable(TEGRA_GPIO_PO7);
873 }
874
875 static struct baseband_power_platform_data tegra_baseband_power_data = {
876         .baseband_type = BASEBAND_XMM,
877         .modem = {
878         .xmm = {
879                         .bb_rst = XMM_GPIO_BB_RST,
880                         .bb_on = XMM_GPIO_BB_ON,
881                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
882                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
883                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
884                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
885                         .hsic_device = &tegra_ehci2_device,
886                 },
887         },
888 };
889
890 static struct platform_device tegra_baseband_power_device = {
891         .name = "baseband_xmm_power",
892         .id = -1,
893         .dev = {
894                 .platform_data = &tegra_baseband_power_data,
895         },
896 };
897
898 static struct platform_device tegra_baseband_power2_device = {
899         .name = "baseband_xmm_power2",
900         .id = -1,
901         .dev = {
902                 .platform_data = &tegra_baseband_power_data,
903         },
904 };
905
906
907 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
908         .port_status[0] = 1,
909         .port_status[1] = 1,
910         .port_status[2] = 1,
911         .use_dock_detect        = 0,
912         .gpio           = 0,
913 };
914
915 static void cardhu_pci_init(void)
916 {
917         struct board_info board_info;
918
919         tegra_get_board_info(&board_info);
920         if (board_info.board_id == BOARD_E1291) {
921                 cardhu_pci_platform_data.port_status[0] = 0;
922                 cardhu_pci_platform_data.port_status[1] = 0;
923                 cardhu_pci_platform_data.port_status[2] = 1;
924                 cardhu_pci_platform_data.use_dock_detect = 1;
925                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
926         }
927         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
928         platform_device_register(&tegra_pci_device);
929 }
930
931 static void cardhu_modem_init(void)
932 {
933         struct board_info board_info;
934         int w_disable_gpio, ret;
935
936         tegra_get_board_info(&board_info);
937         switch (board_info.board_id) {
938         case BOARD_E1291:
939         case BOARD_E1198:
940                 if (((board_info.board_id == BOARD_E1291) &&
941                                 (board_info.fab < BOARD_FAB_A03)) ||
942                         ((board_info.board_id == BOARD_E1198) &&
943                                         (board_info.fab < BOARD_FAB_A02))) {
944                         w_disable_gpio = TEGRA_GPIO_PH5;
945                 } else {
946                         w_disable_gpio = TEGRA_GPIO_PDD5;
947                 }
948                 tegra_gpio_enable(w_disable_gpio);
949                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
950                 if (ret < 0)
951                         pr_err("%s: gpio_request failed for gpio %d\n",
952                                 __func__, w_disable_gpio);
953                 else
954                         gpio_direction_input(w_disable_gpio);
955
956                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
957                 if (((board_info.board_id == BOARD_E1291) &&
958                                 (board_info.fab >= BOARD_FAB_A04)) ||
959                         ((board_info.board_id == BOARD_E1198) &&
960                                         (board_info.fab >= BOARD_FAB_A02))) {
961                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
962                         if (ret < 0) {
963                                 pr_err("%s(): Error in allocating gpio "
964                                         "TEGRA_GPIO_PH7\n", __func__);
965                                 break;
966                         }
967                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
968                         tegra_gpio_enable(TEGRA_GPIO_PH7);
969                 }
970                 break;
971         case BOARD_E1186:
972                 tegra_gpio_enable(
973                         tegra_baseband_power_data.modem.xmm.bb_rst);
974                 tegra_gpio_enable(
975                         tegra_baseband_power_data.modem.xmm.bb_on);
976                 tegra_gpio_enable(
977                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
978                 tegra_gpio_enable(
979                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
980                 tegra_gpio_enable(
981                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
982                 tegra_gpio_enable(
983                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
984                 platform_device_register(&tegra_baseband_power_device);
985                 platform_device_register(&tegra_baseband_power2_device);
986                 break;
987         default:
988                 break;
989         }
990
991 }
992
993 #ifdef CONFIG_SATA_AHCI_TEGRA
994 static void cardhu_sata_init(void)
995 {
996         platform_device_register(&tegra_sata_device);
997 }
998 #else
999 static void cardhu_sata_init(void) { }
1000 #endif
1001
1002 static void __init tegra_cardhu_init(void)
1003 {
1004         tegra_thermal_init(&thermal_data);
1005         tegra_clk_init_from_table(cardhu_clk_init_table);
1006         cardhu_pinmux_init();
1007         cardhu_i2c_init();
1008         cardhu_spi_init();
1009         cardhu_usb_init();
1010 #ifdef CONFIG_TEGRA_EDP_LIMITS
1011         cardhu_edp_init();
1012 #endif
1013         cardhu_uart_init();
1014         cardhu_tsensor_init();
1015         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1016         cardhu_sdhci_init();
1017         cardhu_regulator_init();
1018         cardhu_dtv_init();
1019         cardhu_suspend_init();
1020         cardhu_touch_init();
1021         cardhu_gps_init();
1022         cardhu_modem_init();
1023         cardhu_kbc_init();
1024         cardhu_scroll_init();
1025         cardhu_keys_init();
1026         cardhu_panel_init();
1027         cardhu_pmon_init();
1028         cardhu_sensors_init();
1029         cardhu_bt_rfkill();
1030         tegra_setup_bluesleep();
1031         cardhu_sata_init();
1032         //audio_wired_jack_init();
1033         cardhu_pins_state_init();
1034         cardhu_emc_init();
1035         tegra_release_bootloader_fb();
1036         cardhu_nfc_init();
1037         cardhu_pci_init();
1038 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1039         tegra_wdt_recovery_init();
1040 #endif
1041 }
1042
1043 static void __init tegra_cardhu_reserve(void)
1044 {
1045 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1046         /* support 1920X1200 with 24bpp */
1047         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1048 #else
1049         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1050 #endif
1051 }
1052
1053 MACHINE_START(CARDHU, "cardhu")
1054         .boot_params    = 0x80000100,
1055         .map_io         = tegra_map_common_io,
1056         .reserve        = tegra_cardhu_reserve,
1057         .init_early     = tegra_init_early,
1058         .init_irq       = tegra_init_irq,
1059         .timer          = &tegra_timer,
1060         .init_machine   = tegra_cardhu_init,
1061 MACHINE_END