ARM: tegra: clock src initialisation for debug port in common place
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41
42 #include <sound/wm8903.h>
43 #include <media/tegra_dtv.h>
44
45 #include <mach/clk.h>
46 #include <mach/iomap.h>
47 #include <mach/irqs.h>
48 #include <mach/pinmux.h>
49 #include <mach/iomap.h>
50 #include <mach/io.h>
51 #include <mach/i2s.h>
52 #include <mach/tegra_wm8903_pdata.h>
53 #include <mach/tegra_aic326x_pdata.h>
54 #include <asm/mach-types.h>
55 #include <asm/mach/arch.h>
56 #include <mach/usb_phy.h>
57 #include <mach/thermal.h>
58 #include <mach/pci.h>
59
60 #include "board.h"
61 #include "clock.h"
62 #include "board-cardhu.h"
63 #include "devices.h"
64 #include "gpio-names.h"
65 #include "fuse.h"
66 #include "pm.h"
67 #include "baseband-xmm-power.h"
68 #include "wdt-recovery.h"
69
70 /* All units are in millicelsius */
71 static struct tegra_thermal_data thermal_data = {
72         .temp_throttle = 85000,
73         .temp_shutdown = 90000,
74         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
75 #ifdef CONFIG_TEGRA_EDP_LIMITS
76         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
77         .hysteresis_edp = 3000,
78 #endif
79 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
80         .tc1 = 0,
81         .tc2 = 1,
82         .passive_delay = 2000,
83 #else
84         .hysteresis_throttle = 1000,
85 #endif
86 };
87
88 /* !!!TODO: Change for cardhu (Taken from Ventana) */
89 static struct tegra_utmip_config utmi_phy_config[] = {
90         [0] = {
91                         .hssync_start_delay = 0,
92                         .idle_wait_delay = 17,
93                         .elastic_limit = 16,
94                         .term_range_adj = 6,
95                         .xcvr_setup = 15,
96                         .xcvr_setup_offset = 0,
97                         .xcvr_use_fuses = 1,
98                         .xcvr_lsfslew = 2,
99                         .xcvr_lsrslew = 2,
100         },
101         [1] = {
102                         .hssync_start_delay = 0,
103                         .idle_wait_delay = 17,
104                         .elastic_limit = 16,
105                         .term_range_adj = 6,
106                         .xcvr_setup = 15,
107                         .xcvr_setup_offset = 0,
108                         .xcvr_use_fuses = 1,
109                         .xcvr_lsfslew = 2,
110                         .xcvr_lsrslew = 2,
111         },
112         [2] = {
113                         .hssync_start_delay = 0,
114                         .idle_wait_delay = 17,
115                         .elastic_limit = 16,
116                         .term_range_adj = 6,
117                         .xcvr_setup = 8,
118                         .xcvr_setup_offset = 0,
119                         .xcvr_use_fuses = 1,
120                         .xcvr_lsfslew = 2,
121                         .xcvr_lsrslew = 2,
122         },
123 };
124
125 #ifdef CONFIG_BCM4329_RFKILL
126 static struct resource cardhu_bcm4329_rfkill_resources[] = {
127         {
128                 .name   = "bcm4329_nshutdown_gpio",
129                 .start  = TEGRA_GPIO_PU0,
130                 .end    = TEGRA_GPIO_PU0,
131                 .flags  = IORESOURCE_IO,
132         },
133 };
134
135 static struct platform_device cardhu_bcm4329_rfkill_device = {
136         .name = "bcm4329_rfkill",
137         .id             = -1,
138         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
139         .resource       = cardhu_bcm4329_rfkill_resources,
140 };
141
142 static noinline void __init cardhu_bt_rfkill(void)
143 {
144         platform_device_register(&cardhu_bcm4329_rfkill_device);
145
146         return;
147 }
148 #else
149 static inline void cardhu_bt_rfkill(void) { }
150 #endif
151
152 #ifdef CONFIG_BT_BLUESLEEP
153 static noinline void __init tegra_setup_bluesleep(void)
154 {
155         struct platform_device *pdev = NULL;
156         struct resource *res;
157
158         pdev = platform_device_alloc("bluesleep", 0);
159         if (!pdev) {
160                 pr_err("unable to allocate platform device for bluesleep");
161                 return;
162         }
163
164         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
165         if (!res) {
166                 pr_err("unable to allocate resource for bluesleep\n");
167                 goto err_free_dev;
168         }
169
170         res[0].name   = "gpio_host_wake";
171         res[0].start  = TEGRA_GPIO_PU6;
172         res[0].end    = TEGRA_GPIO_PU6;
173         res[0].flags  = IORESOURCE_IO;
174
175         res[1].name   = "gpio_ext_wake";
176         res[1].start  = TEGRA_GPIO_PU1;
177         res[1].end    = TEGRA_GPIO_PU1;
178         res[1].flags  = IORESOURCE_IO;
179
180         res[2].name   = "host_wake";
181         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
182         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
183         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
184
185         if (platform_device_add_resources(pdev, res, 3)) {
186                 pr_err("unable to add resources to bluesleep device\n");
187                 goto err_free_res;
188         }
189
190         if (platform_device_add(pdev)) {
191                 pr_err("unable to add bluesleep device\n");
192                 goto err_free_res;
193         }
194         tegra_gpio_enable(TEGRA_GPIO_PU6);
195         tegra_gpio_enable(TEGRA_GPIO_PU1);
196
197 return;
198
199 err_free_res:
200         kfree(res);
201 err_free_dev:
202         platform_device_put(pdev);
203         return;
204 }
205 #else
206 static inline void tegra_setup_bluesleep(void) { }
207 #endif
208
209 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
210         /* name         parent          rate            enabled */
211         { "pll_m",      NULL,           0,              false},
212         { "hda",        "pll_p",        108000000,      false},
213         { "hda2codec_2x","pll_p",       48000000,       false},
214         { "pwm",        "pll_p",        3187500,        false},
215         { "blink",      "clk_32k",      32768,          true},
216         { "i2s0",       "pll_a_out0",   0,              false},
217         { "i2s1",       "pll_a_out0",   0,              false},
218         { "i2s3",       "pll_a_out0",   0,              false},
219         { "spdif_out",  "pll_a_out0",   0,              false},
220         { "d_audio",    "clk_m",        12000000,       false},
221         { "dam0",       "clk_m",        12000000,       false},
222         { "dam1",       "clk_m",        12000000,       false},
223         { "dam2",       "clk_m",        12000000,       false},
224         { "audio1",     "i2s1_sync",    0,              false},
225         { "audio3",     "i2s3_sync",    0,              false},
226         { "vi_sensor",  "pll_p",        150000000,      false},
227         { "i2c1",       "pll_p",        3200000,        false},
228         { "i2c2",       "pll_p",        3200000,        false},
229         { "i2c3",       "pll_p",        3200000,        false},
230         { "i2c4",       "pll_p",        3200000,        false},
231         { "i2c5",       "pll_p",        3200000,        false},
232         { NULL,         NULL,           0,              0},
233 };
234
235 static struct pn544_i2c_platform_data nfc_pdata = {
236         .irq_gpio = TEGRA_GPIO_PX0,
237         .ven_gpio = TEGRA_GPIO_PP3,
238         .firm_gpio = TEGRA_GPIO_PO7,
239         };
240
241 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
242         {
243                 I2C_BOARD_INFO("pn544", 0x28),
244                 .platform_data = &nfc_pdata,
245                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
246         },
247 };
248 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
249         .adapter_nr     = 0,
250         .bus_count      = 1,
251         .bus_clk_rate   = { 100000, 0 },
252         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
253         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
254         .arb_recovery = arb_lost_recovery,
255 };
256
257 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
258         .adapter_nr     = 1,
259         .bus_count      = 1,
260         .bus_clk_rate   = { 100000, 0 },
261         .is_clkon_always = true,
262         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
263         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
264         .arb_recovery = arb_lost_recovery,
265 };
266
267 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
268         .adapter_nr     = 2,
269         .bus_count      = 1,
270         .bus_clk_rate   = { 100000, 0 },
271         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
272         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
273         .arb_recovery = arb_lost_recovery,
274 };
275
276 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
277         .adapter_nr     = 3,
278         .bus_count      = 1,
279         .bus_clk_rate   = { 100000, 0 },
280         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
281         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
282         .arb_recovery = arb_lost_recovery,
283 };
284
285 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
286         .adapter_nr     = 4,
287         .bus_count      = 1,
288         .bus_clk_rate   = { 400000, 0 },
289         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
290         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
291         .arb_recovery = arb_lost_recovery,
292 };
293
294
295 #if 0
296 struct tegra_wired_jack_conf audio_wr_jack_conf = {
297         .hp_det_n = TEGRA_GPIO_PW2,
298         .en_mic_ext = TEGRA_GPIO_PX1,
299         .en_mic_int = TEGRA_GPIO_PX0,
300 };
301 #endif
302
303 static struct wm8903_platform_data cardhu_wm8903_pdata = {
304         .irq_active_low = 0,
305         .micdet_cfg = 0,
306         .micdet_delay = 100,
307         .gpio_base = CARDHU_GPIO_WM8903(0),
308         .gpio_cfg = {
309                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
310                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
311                         WM8903_GP2_DIR,
312                 0,
313                 WM8903_GPIO_NO_CONFIG,
314                 WM8903_GPIO_NO_CONFIG,
315         },
316 };
317
318 static struct wm8903_platform_data cardhu_aic3262_pdata = {
319         .irq_active_low = 0,
320         .micdet_cfg = 0,
321         .micdet_delay = 100,
322 };
323
324 static struct i2c_board_info __initdata cardhu_board_info[] = {
325         {
326                 I2C_BOARD_INFO("wm8903", 0x1a),
327                 .platform_data = &cardhu_wm8903_pdata,
328                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
329         },
330         {
331                 I2C_BOARD_INFO("aic3262-codec", 0x18),
332                 .platform_data=&cardhu_aic3262_pdata,
333                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
334         },
335 };
336
337
338 static void cardhu_i2c_init(void)
339 {
340         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
341         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
342         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
343         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
344         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
345
346         platform_device_register(&tegra_i2c_device5);
347         platform_device_register(&tegra_i2c_device4);
348         platform_device_register(&tegra_i2c_device3);
349         platform_device_register(&tegra_i2c_device2);
350         platform_device_register(&tegra_i2c_device1);
351
352         i2c_register_board_info(4, cardhu_board_info, ARRAY_SIZE(cardhu_board_info));
353
354         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
355 }
356
357 static struct platform_device *cardhu_uart_devices[] __initdata = {
358         &tegra_uarta_device,
359         &tegra_uartb_device,
360         &tegra_uartc_device,
361         &tegra_uartd_device,
362         &tegra_uarte_device,
363 };
364 static struct uart_clk_parent uart_parent_clk[] = {
365         [0] = {.name = "clk_m"},
366         [1] = {.name = "pll_p"},
367 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
368         [2] = {.name = "pll_m"},
369 #endif
370 };
371
372 static struct tegra_uart_platform_data cardhu_uart_pdata;
373 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
374
375 static void __init uart_debug_init(void)
376 {
377         struct board_info board_info;
378         int debug_port_id;
379
380         tegra_get_board_info(&board_info);
381
382         debug_port_id = get_tegra_uart_debug_port_id();
383         if (debug_port_id < 0) {
384                 debug_port_id = 0;
385                         /* UARTB is debug port
386                          *       for SLT - E1186/E1187/PM269
387                          *       for E1256/E1257
388                          */
389                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
390                         ((board_info.board_id == BOARD_E1186) ||
391                         (board_info.board_id == BOARD_E1187) ||
392                         (board_info.board_id == BOARD_PM269))) ||
393                         (board_info.board_id == BOARD_E1256) ||
394                         (board_info.board_id == BOARD_E1257))
395                                 debug_port_id = 1;
396         }
397
398         switch (debug_port_id) {
399         case 0:
400                 /* UARTA is the debug port. */
401                 pr_info("Selecting UARTA as the debug console\n");
402                 cardhu_uart_devices[0] = &debug_uarta_device;
403                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
404                 debug_uart_port_base = ((struct plat_serial8250_port *)(
405                         debug_uarta_device.dev.platform_data))->mapbase;
406                 break;
407
408         case 1:
409                 /* UARTB is the debug port. */
410                 pr_info("Selecting UARTB as the debug console\n");
411                 cardhu_uart_devices[1] = &debug_uartb_device;
412                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
413                 debug_uart_port_base = ((struct plat_serial8250_port *)(
414                         debug_uartb_device.dev.platform_data))->mapbase;
415                 break;
416
417         case 2:
418                 /* UARTC is the debug port. */
419                 pr_info("Selecting UARTC as the debug console\n");
420                 cardhu_uart_devices[2] = &debug_uartc_device;
421                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
422                 debug_uart_port_base = ((struct plat_serial8250_port *)(
423                         debug_uartc_device.dev.platform_data))->mapbase;
424                 break;
425
426         case 3:
427                 /* UARTD is the debug port. */
428                 pr_info("Selecting UARTD as the debug console\n");
429                 cardhu_uart_devices[3] = &debug_uartd_device;
430                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
431                 debug_uart_port_base = ((struct plat_serial8250_port *)(
432                         debug_uartd_device.dev.platform_data))->mapbase;
433                 break;
434
435         case 4:
436                 /* UARTE is the debug port. */
437                 pr_info("Selecting UARTE as the debug console\n");
438                 cardhu_uart_devices[4] = &debug_uarte_device;
439                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
440                 debug_uart_port_base = ((struct plat_serial8250_port *)(
441                         debug_uarte_device.dev.platform_data))->mapbase;
442                 break;
443
444         default:
445                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
446                 cardhu_uart_devices[0] = &debug_uarta_device;
447                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
448                 debug_uart_port_base = ((struct plat_serial8250_port *)(
449                         debug_uarta_device.dev.platform_data))->mapbase;
450                 break;
451         }
452         return;
453 }
454
455 static void __init cardhu_uart_init(void)
456 {
457         struct clk *c;
458         int i;
459
460         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
461                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
462                 if (IS_ERR_OR_NULL(c)) {
463                         pr_err("Not able to get the clock for %s\n",
464                                                 uart_parent_clk[i].name);
465                         continue;
466                 }
467                 uart_parent_clk[i].parent_clk = c;
468                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
469         }
470         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
471         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
472         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
473         cardhu_loopback_uart_pdata.parent_clk_count =
474                                                 ARRAY_SIZE(uart_parent_clk);
475         cardhu_loopback_uart_pdata.is_loopback = true;
476         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
477         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
478         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
479         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
480         /* UARTE is used for loopback test purpose */
481         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
482
483         /* Register low speed only if it is selected */
484         if (!is_tegra_debug_uartport_hs()) {
485                 uart_debug_init();
486                 /* Clock enable for the debug channel */
487                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
488                         pr_info("The debug console clock name is %s\n",
489                                                 debug_uart_clk->name);
490                         c = tegra_get_clock_by_name("pll_p");
491                         if (IS_ERR_OR_NULL(c))
492                                 pr_err("Not getting the parent clock pll_p\n");
493                         else
494                                 clk_set_parent(debug_uart_clk, c);
495
496                         clk_enable(debug_uart_clk);
497                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
498                 } else {
499                         pr_err("Not getting the clock %s for debug console\n",
500                                         debug_uart_clk->name);
501                 }
502         }
503
504         platform_add_devices(cardhu_uart_devices,
505                                 ARRAY_SIZE(cardhu_uart_devices));
506 }
507
508 static struct platform_device tegra_camera = {
509         .name = "tegra_camera",
510         .id = -1,
511 };
512
513 static struct platform_device *cardhu_spi_devices[] __initdata = {
514         &tegra_spi_device4,
515 };
516
517 struct spi_clk_parent spi_parent_clk[] = {
518         [0] = {.name = "pll_p"},
519 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
520         [1] = {.name = "pll_m"},
521         [2] = {.name = "clk_m"},
522 #else
523         [1] = {.name = "clk_m"},
524 #endif
525 };
526
527 static struct tegra_spi_platform_data cardhu_spi_pdata = {
528         .is_dma_based           = true,
529         .max_dma_buffer         = (16 * 1024),
530         .is_clkon_always        = false,
531         .max_rate               = 100000000,
532 };
533
534 static void __init cardhu_spi_init(void)
535 {
536         int i;
537         struct clk *c;
538         struct board_info board_info;
539
540         tegra_get_board_info(&board_info);
541
542         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
543                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
544                 if (IS_ERR_OR_NULL(c)) {
545                         pr_err("Not able to get the clock for %s\n",
546                                                 spi_parent_clk[i].name);
547                         continue;
548                 }
549                 spi_parent_clk[i].parent_clk = c;
550                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
551         }
552         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
553         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
554         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
555         platform_add_devices(cardhu_spi_devices,
556                                 ARRAY_SIZE(cardhu_spi_devices));
557
558         if (board_info.board_id == BOARD_E1198) {
559                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
560                 platform_device_register(&tegra_spi_device2);
561                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
562                 platform_device_register(&tegra_spi_slave_device1);
563         }
564 }
565
566 static void __init cardhu_dtv_init(void)
567 {
568         struct board_info board_info;
569
570         tegra_get_board_info(&board_info);
571
572         if (board_info.board_id == BOARD_E1186)
573                 platform_device_register(&tegra_dtv_device);
574 }
575
576 static struct resource tegra_rtc_resources[] = {
577         [0] = {
578                 .start = TEGRA_RTC_BASE,
579                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
580                 .flags = IORESOURCE_MEM,
581         },
582         [1] = {
583                 .start = INT_RTC,
584                 .end = INT_RTC,
585                 .flags = IORESOURCE_IRQ,
586         },
587 };
588
589 static struct platform_device tegra_rtc_device = {
590         .name = "tegra_rtc",
591         .id   = -1,
592         .resource = tegra_rtc_resources,
593         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
594 };
595
596 static struct tegra_wm8903_platform_data cardhu_audio_pdata = {
597         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
598         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
599         .gpio_hp_mute           = -1,
600         .gpio_int_mic_en        = -1,
601         .gpio_ext_mic_en        = -1,
602 };
603
604 static struct platform_device cardhu_audio_device = {
605         .name   = "tegra-snd-wm8903",
606         .id     = 0,
607         .dev    = {
608                 .platform_data  = &cardhu_audio_pdata,
609         },
610 };
611
612 static struct tegra_aic326x_platform_data cardhu_aic326x_audio_pdata = {
613         .gpio_spkr_en           = -1,
614         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
615         .gpio_hp_mute           = -1,
616         .gpio_int_mic_en        = -1,
617         .gpio_ext_mic_en        = -1,
618 };
619
620 static struct platform_device cardhu_aic326x_audio_device = {
621         .name   = "tegra-snd-aic326x",
622         .id     = 0,
623         .dev    = {
624                 .platform_data  = &cardhu_aic326x_audio_pdata,
625         },
626 };
627
628 static struct platform_device *cardhu_devices[] __initdata = {
629         &tegra_pmu_device,
630         &tegra_rtc_device,
631         &tegra_udc_device,
632 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
633         &tegra_smmu_device,
634 #endif
635         &tegra_wdt_device,
636 #if defined(CONFIG_TEGRA_AVP)
637         &tegra_avp_device,
638 #endif
639         &tegra_camera,
640 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
641         &tegra_se_device,
642 #endif
643         &tegra_ahub_device,
644         &tegra_dam_device0,
645         &tegra_dam_device1,
646         &tegra_dam_device2,
647         &tegra_i2s_device0,
648         &tegra_i2s_device1,
649         &tegra_i2s_device3,
650         &tegra_spdif_device,
651         &spdif_dit_device,
652         &bluetooth_dit_device,
653         &baseband_dit_device,
654         &tegra_pcm_device,
655         &cardhu_audio_device,
656         &cardhu_aic326x_audio_device,
657         &tegra_hda_device,
658 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
659         &tegra_aes_device,
660 #endif
661 };
662
663 #define MXT_CONFIG_CRC  0xD62DE8
664 static const u8 config[] = {
665         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
666         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
667         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
668         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
669         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
670         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
671         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
672         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
673         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
674         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
675         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
676         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
677         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
678         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
679         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
680         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
681         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
682         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
683         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
684         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
685 };
686
687 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
688 static const u8 config_sku2000[] = {
689         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
690         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
691         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
692         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
693         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
694         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
695         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
696         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
697         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
698         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
699         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
700         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
701         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
702         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
703         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
704         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
705         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
706         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
707         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
708         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
709 };
710
711 static struct mxt_platform_data atmel_mxt_info = {
712         .x_line         = 27,
713         .y_line         = 42,
714         .x_size         = 768,
715         .y_size         = 1366,
716         .blen           = 0x20,
717         .threshold      = 0x3C,
718         .voltage        = 3300000,              /* 3.3V */
719         .orient         = 5,
720         .config         = config,
721         .config_length  = 157,
722         .config_crc     = MXT_CONFIG_CRC,
723         .irqflags       = IRQF_TRIGGER_FALLING,
724 /*      .read_chg       = &read_chg, */
725         .read_chg       = NULL,
726 };
727
728 static struct i2c_board_info __initdata atmel_i2c_info[] = {
729         {
730                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
731                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
732                 .platform_data = &atmel_mxt_info,
733         }
734 };
735
736 static int __init cardhu_touch_init(void)
737 {
738         struct board_info BoardInfo;
739
740         tegra_gpio_enable(TEGRA_GPIO_PH4);
741         tegra_gpio_enable(TEGRA_GPIO_PH6);
742
743         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
744         gpio_direction_input(TEGRA_GPIO_PH4);
745
746         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
747         gpio_direction_output(TEGRA_GPIO_PH6, 0);
748         msleep(1);
749         gpio_set_value(TEGRA_GPIO_PH6, 1);
750         msleep(100);
751
752         tegra_get_board_info(&BoardInfo);
753         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
754                 atmel_mxt_info.config = config_sku2000;
755                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
756         }
757
758         i2c_register_board_info(1, atmel_i2c_info, 1);
759
760         return 0;
761 }
762
763 static struct tegra_uhsic_config uhsic_phy_config = {
764         .enable_gpio = EN_HSIC_GPIO,
765         .reset_gpio = -1,
766         .sync_start_delay = 9,
767         .idle_wait_delay = 17,
768         .term_range_adj = 0,
769         .elastic_underrun_limit = 16,
770         .elastic_overrun_limit = 16,
771 };
772
773 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
774         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
775         .phy_config = &uhsic_phy_config,
776         .operating_mode = TEGRA_USB_HOST,
777         .power_down_on_bus_suspend = 1,
778         .default_enable = true,
779 };
780
781 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
782         [0] = {
783                         .phy_config = &utmi_phy_config[0],
784                         .operating_mode = TEGRA_USB_HOST,
785                         .power_down_on_bus_suspend = 1,
786                         .default_enable = true,
787         },
788         [1] = {
789                         .phy_config = &utmi_phy_config[1],
790                         .operating_mode = TEGRA_USB_HOST,
791                         .power_down_on_bus_suspend = 1,
792                         .default_enable = true,
793         },
794         [2] = {
795                         .phy_config = &utmi_phy_config[2],
796                         .operating_mode = TEGRA_USB_HOST,
797                         .power_down_on_bus_suspend = 1,
798                         .hotplug = 1,
799                         .default_enable = true,
800         },
801 };
802
803 static struct tegra_otg_platform_data tegra_otg_pdata = {
804         .ehci_device = &tegra_ehci1_device,
805         .ehci_pdata = &tegra_ehci_pdata[0],
806 };
807
808 #ifdef CONFIG_USB_SUPPORT
809 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
810         [0] = {
811                         .instance = 0,
812                         .vbus_gpio = -1,
813                         .vbus_reg_supply = "vdd_vbus_micro_usb",
814         },
815         [1] = {
816                         .instance = 1,
817                         .vbus_gpio = -1,
818         },
819         [2] = {
820                         .instance = 2,
821                         .vbus_gpio = -1,
822                         .vbus_reg_supply = "vdd_vbus_typea_usb",
823         },
824 };
825
826 static void cardhu_usb_init(void)
827 {
828         struct board_info bi;
829
830         tegra_get_board_info(&bi);
831
832         tegra_usb_phy_init(tegra_usb_phy_pdata,
833                         ARRAY_SIZE(tegra_usb_phy_pdata));
834
835         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
836         platform_device_register(&tegra_otg_device);
837         if (bi.board_id == BOARD_PM267) {
838                 uhsic_phy_config.reset_gpio =
839                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
840                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
841                 platform_device_register(&tegra_ehci2_device);
842         } else if (bi.board_id == BOARD_E1256) {
843                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
844                 platform_device_register(&tegra_ehci2_device);
845         } else if (bi.board_id == BOARD_E1186) {
846                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
847                 /* baseband registration happens in baseband-xmm-power  */
848         } else {
849                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
850                 platform_device_register(&tegra_ehci2_device);
851         }
852
853         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
854         platform_device_register(&tegra_ehci3_device);
855
856 }
857 #else
858 static void cardhu_usb_init(void) { }
859 #endif
860
861 static void cardhu_gps_init(void)
862 {
863         tegra_gpio_enable(TEGRA_GPIO_PU2);
864         tegra_gpio_enable(TEGRA_GPIO_PU3);
865 }
866
867 static void cardhu_nfc_init(void)
868 {
869         tegra_gpio_enable(TEGRA_GPIO_PX0);
870         tegra_gpio_enable(TEGRA_GPIO_PP3);
871         tegra_gpio_enable(TEGRA_GPIO_PO7);
872 }
873
874 static struct baseband_power_platform_data tegra_baseband_power_data = {
875         .baseband_type = BASEBAND_XMM,
876         .modem = {
877         .xmm = {
878                         .bb_rst = XMM_GPIO_BB_RST,
879                         .bb_on = XMM_GPIO_BB_ON,
880                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
881                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
882                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
883                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
884                         .hsic_device = &tegra_ehci2_device,
885                 },
886         },
887 };
888
889 static struct platform_device tegra_baseband_power_device = {
890         .name = "baseband_xmm_power",
891         .id = -1,
892         .dev = {
893                 .platform_data = &tegra_baseband_power_data,
894         },
895 };
896
897 static struct platform_device tegra_baseband_power2_device = {
898         .name = "baseband_xmm_power2",
899         .id = -1,
900         .dev = {
901                 .platform_data = &tegra_baseband_power_data,
902         },
903 };
904
905
906 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
907         .port_status[0] = 1,
908         .port_status[1] = 1,
909         .port_status[2] = 1,
910         .use_dock_detect        = 0,
911         .gpio           = 0,
912 };
913
914 static void cardhu_pci_init(void)
915 {
916         struct board_info board_info;
917
918         tegra_get_board_info(&board_info);
919         if (board_info.board_id == BOARD_E1291) {
920                 cardhu_pci_platform_data.port_status[0] = 0;
921                 cardhu_pci_platform_data.port_status[1] = 0;
922                 cardhu_pci_platform_data.port_status[2] = 1;
923                 cardhu_pci_platform_data.use_dock_detect = 1;
924                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
925         }
926         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
927         platform_device_register(&tegra_pci_device);
928 }
929
930 static void cardhu_modem_init(void)
931 {
932         struct board_info board_info;
933         int w_disable_gpio, ret;
934
935         tegra_get_board_info(&board_info);
936         switch (board_info.board_id) {
937         case BOARD_E1291:
938         case BOARD_E1198:
939                 if (((board_info.board_id == BOARD_E1291) &&
940                                 (board_info.fab < BOARD_FAB_A03)) ||
941                         ((board_info.board_id == BOARD_E1198) &&
942                                         (board_info.fab < BOARD_FAB_A02))) {
943                         w_disable_gpio = TEGRA_GPIO_PH5;
944                 } else {
945                         w_disable_gpio = TEGRA_GPIO_PDD5;
946                 }
947                 tegra_gpio_enable(w_disable_gpio);
948                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
949                 if (ret < 0)
950                         pr_err("%s: gpio_request failed for gpio %d\n",
951                                 __func__, w_disable_gpio);
952                 else
953                         gpio_direction_input(w_disable_gpio);
954
955                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
956                 if (((board_info.board_id == BOARD_E1291) &&
957                                 (board_info.fab >= BOARD_FAB_A04)) ||
958                         ((board_info.board_id == BOARD_E1198) &&
959                                         (board_info.fab >= BOARD_FAB_A02))) {
960                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
961                         if (ret < 0) {
962                                 pr_err("%s(): Error in allocating gpio "
963                                         "TEGRA_GPIO_PH7\n", __func__);
964                                 break;
965                         }
966                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
967                         tegra_gpio_enable(TEGRA_GPIO_PH7);
968                 }
969                 break;
970         case BOARD_E1186:
971                 tegra_gpio_enable(
972                         tegra_baseband_power_data.modem.xmm.bb_rst);
973                 tegra_gpio_enable(
974                         tegra_baseband_power_data.modem.xmm.bb_on);
975                 tegra_gpio_enable(
976                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
977                 tegra_gpio_enable(
978                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
979                 tegra_gpio_enable(
980                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
981                 tegra_gpio_enable(
982                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
983                 platform_device_register(&tegra_baseband_power_device);
984                 platform_device_register(&tegra_baseband_power2_device);
985                 break;
986         default:
987                 break;
988         }
989
990 }
991
992 #ifdef CONFIG_SATA_AHCI_TEGRA
993 static void cardhu_sata_init(void)
994 {
995         platform_device_register(&tegra_sata_device);
996 }
997 #else
998 static void cardhu_sata_init(void) { }
999 #endif
1000
1001 static void __init tegra_cardhu_init(void)
1002 {
1003         tegra_thermal_init(&thermal_data);
1004         tegra_clk_init_from_table(cardhu_clk_init_table);
1005         cardhu_pinmux_init();
1006         cardhu_i2c_init();
1007         cardhu_spi_init();
1008         cardhu_usb_init();
1009 #ifdef CONFIG_TEGRA_EDP_LIMITS
1010         cardhu_edp_init();
1011 #endif
1012         cardhu_uart_init();
1013         cardhu_tsensor_init();
1014         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1015         cardhu_sdhci_init();
1016         cardhu_regulator_init();
1017         cardhu_dtv_init();
1018         cardhu_suspend_init();
1019         cardhu_touch_init();
1020         cardhu_gps_init();
1021         cardhu_modem_init();
1022         cardhu_kbc_init();
1023         cardhu_scroll_init();
1024         cardhu_keys_init();
1025         cardhu_panel_init();
1026         cardhu_pmon_init();
1027         cardhu_sensors_init();
1028         cardhu_bt_rfkill();
1029         tegra_setup_bluesleep();
1030         cardhu_sata_init();
1031         //audio_wired_jack_init();
1032         cardhu_pins_state_init();
1033         cardhu_emc_init();
1034         tegra_release_bootloader_fb();
1035         cardhu_nfc_init();
1036         cardhu_pci_init();
1037 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1038         tegra_wdt_recovery_init();
1039 #endif
1040 }
1041
1042 static void __init tegra_cardhu_reserve(void)
1043 {
1044 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1045         /* support 1920X1200 with 24bpp */
1046         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1047 #else
1048         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1049 #endif
1050 }
1051
1052 MACHINE_START(CARDHU, "cardhu")
1053         .boot_params    = 0x80000100,
1054         .map_io         = tegra_map_common_io,
1055         .reserve        = tegra_cardhu_reserve,
1056         .init_early     = tegra_init_early,
1057         .init_irq       = tegra_init_irq,
1058         .timer          = &tegra_timer,
1059         .init_machine   = tegra_cardhu_init,
1060 MACHINE_END