touch: Raydium: Remove hex blob data structures from board files.
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi/rm31080a_ts.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44 #include <linux/of_platform.h>
45
46 #include <sound/wm8903.h>
47 #include <sound/max98095.h>
48 #include <media/tegra_dtv.h>
49
50 #include <asm/hardware/gic.h>
51
52 #include <mach/edp.h>
53 #include <mach/clk.h>
54 #include <mach/iomap.h>
55 #include <mach/irqs.h>
56 #include <mach/pinmux.h>
57 #include <mach/iomap.h>
58 #include <mach/io_dpd.h>
59 #include <mach/io.h>
60 #include <mach/i2s.h>
61 #include <mach/tegra_asoc_pdata.h>
62 #include <mach/tegra_wm8903_pdata.h>
63 #include <mach/usb_phy.h>
64 #include <mach/thermal.h>
65 #include <mach/pci.h>
66 #include <mach/gpio-tegra.h>
67 #include <mach/tegra_fiq_debugger.h>
68 #include <linux/thermal.h>
69
70 #include <asm/hardware/gic.h>
71 #include <asm/mach-types.h>
72 #include <asm/mach/arch.h>
73
74 #include "board.h"
75 #include "clock.h"
76 #include "board-cardhu.h"
77 #include "board-touch-raydium.h"
78 #include "devices.h"
79 #include "gpio-names.h"
80 #include "fuse.h"
81 #include "pm.h"
82 #include "baseband-xmm-power.h"
83 #include "wdt-recovery.h"
84 #include "common.h"
85
86 static struct balanced_throttle throttle_list[] = {
87         {
88                 .tegra_cdev = {
89                         .id = CDEV_BTHROT_ID_TJ,
90                 },
91                 .throt_tab_size = 10,
92                 .throt_tab = {
93                         {      0, 1000 },
94                         { 640000, 1000 },
95                         { 640000, 1000 },
96                         { 640000, 1000 },
97                         { 640000, 1000 },
98                         { 640000, 1000 },
99                         { 760000, 1000 },
100                         { 760000, 1050 },
101                         {1000000, 1050 },
102                         {1000000, 1100 },
103                 },
104         },
105 };
106
107 static struct tegra_thermal_bind thermal_binds[] = {
108         /* Thermal Throttling */
109         {
110                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
111                 .cdev_id = CDEV_BTHROT_ID_TJ,
112                 .type = THERMAL_TRIP_PASSIVE,
113                 .passive = {
114                         .trip_temp = 85000,
115                         .tc1 = 0,
116                         .tc2 = 1,
117                         .passive_delay = 2000,
118                 }
119         },
120         /* EDP Capping */
121         {
122                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
123                 .cdev_id = CDEV_EDPTABLE_ID_EDP,
124                 .type = THERMAL_TRIP_ACTIVE,
125                 .get_trip_temp = tegra_edp_get_trip_temp,
126                 .get_trip_size = tegra_edp_get_trip_size,
127         },
128         {
129                 .tdev_id = THERMAL_DEVICE_ID_NULL,
130         },
131 };
132
133 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
134         {
135                 .name           = "bt_rfkill",
136                 .shutdown_gpio  = TEGRA_GPIO_PU0,
137                 .reset_gpio     = TEGRA_GPIO_INVALID,
138                 .type           = RFKILL_TYPE_BLUETOOTH,
139         },
140 };
141
142 static struct platform_device cardhu_bt_rfkill_device = {
143         .name = "rfkill_gpio",
144         .id             = -1,
145         .dev = {
146                 .platform_data = &cardhu_bt_rfkill_pdata,
147         },
148 };
149
150 static struct resource cardhu_bluesleep_resources[] = {
151         [0] = {
152                 .name = "gpio_host_wake",
153                         .start  = TEGRA_GPIO_PU6,
154                         .end    = TEGRA_GPIO_PU6,
155                         .flags  = IORESOURCE_IO,
156         },
157         [1] = {
158                 .name = "gpio_ext_wake",
159                         .start  = TEGRA_GPIO_PU1,
160                         .end    = TEGRA_GPIO_PU1,
161                         .flags  = IORESOURCE_IO,
162         },
163         [2] = {
164                 .name = "host_wake",
165                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
166         },
167 };
168
169 static struct platform_device cardhu_bluesleep_device = {
170         .name           = "bluesleep",
171         .id             = -1,
172         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
173         .resource       = cardhu_bluesleep_resources,
174 };
175
176 static noinline void __init cardhu_setup_bluesleep(void)
177 {
178         cardhu_bluesleep_resources[2].start =
179                 cardhu_bluesleep_resources[2].end =
180                         gpio_to_irq(TEGRA_GPIO_PU6);
181         platform_device_register(&cardhu_bluesleep_device);
182         return;
183 }
184
185 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
186         /* name         parent          rate            enabled */
187         { "pll_m",      NULL,           0,              false},
188         { "hda",        "pll_p",        108000000,      false},
189         { "hda2codec_2x","pll_p",       48000000,       false},
190         { "pwm",        "pll_p",        3187500,        false},
191         { "blink",      "clk_32k",      32768,          true},
192         { "i2s0",       "pll_a_out0",   0,              false},
193         { "i2s1",       "pll_a_out0",   0,              false},
194         { "i2s3",       "pll_a_out0",   0,              false},
195         { "spdif_out",  "pll_a_out0",   0,              false},
196         { "d_audio",    "clk_m",        12000000,       false},
197         { "dam0",       "clk_m",        12000000,       false},
198         { "dam1",       "clk_m",        12000000,       false},
199         { "dam2",       "clk_m",        12000000,       false},
200         { "audio1",     "i2s1_sync",    0,              false},
201         { "audio3",     "i2s3_sync",    0,              false},
202         { "vi_sensor",  "pll_p",        150000000,      false},
203         { "i2c1",       "pll_p",        3200000,        false},
204         { "i2c2",       "pll_p",        3200000,        false},
205         { "i2c3",       "pll_p",        3200000,        false},
206         { "i2c4",       "pll_p",        3200000,        false},
207         { "i2c5",       "pll_p",        3200000,        false},
208         { "vi",         "pll_p",        0,              false},
209         { NULL,         NULL,           0,              0},
210 };
211
212 static struct pn544_i2c_platform_data nfc_pdata = {
213         .irq_gpio = TEGRA_GPIO_PX0,
214         .ven_gpio = TEGRA_GPIO_PP3,
215         .firm_gpio = TEGRA_GPIO_PO7,
216         };
217
218 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
219         {
220                 I2C_BOARD_INFO("pn544", 0x28),
221                 .platform_data = &nfc_pdata,
222         },
223 };
224 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
225         .adapter_nr     = 0,
226         .bus_count      = 1,
227         .bus_clk_rate   = { 100000, 0 },
228         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
229         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
230         .arb_recovery = arb_lost_recovery,
231 };
232
233 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
234         .adapter_nr     = 1,
235         .bus_count      = 1,
236         .bus_clk_rate   = { 400000, 0 },
237         .is_clkon_always = true,
238         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
239         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
240         .arb_recovery = arb_lost_recovery,
241 };
242
243 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
244         .adapter_nr     = 2,
245         .bus_count      = 1,
246         .bus_clk_rate   = { 100000, 0 },
247         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
248         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
249         .arb_recovery = arb_lost_recovery,
250 };
251
252 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
253         .adapter_nr     = 3,
254         .bus_count      = 1,
255         .bus_clk_rate   = { 10000, 0 },
256         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
257         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
258         .arb_recovery = arb_lost_recovery,
259 };
260
261 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
262         .adapter_nr     = 4,
263         .bus_count      = 1,
264         .bus_clk_rate   = { 400000, 0 },
265         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
266         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
267         .arb_recovery = arb_lost_recovery,
268 };
269
270
271 #if 0
272 struct tegra_wired_jack_conf audio_wr_jack_conf = {
273         .hp_det_n = TEGRA_GPIO_PW2,
274         .en_mic_ext = TEGRA_GPIO_PX1,
275         .en_mic_int = TEGRA_GPIO_PX0,
276 };
277 #endif
278
279 static struct wm8903_platform_data cardhu_wm8903_pdata = {
280         .irq_active_low = 0,
281         .micdet_cfg = 0,
282         .micdet_delay = 100,
283         .gpio_base = CARDHU_GPIO_WM8903(0),
284         .gpio_cfg = {
285                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
286                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
287                         WM8903_GP2_DIR,
288                 WM8903_GPIO_CONFIG_ZERO,
289                 0,
290                 0,
291         },
292 };
293
294 /* Equalizer filter coefs generated from the MAXIM MAX98095
295  * evkit software tool */
296 static struct max98095_eq_cfg max98095_eq_cfg[] = {
297         {
298                 .name = "FLAT",
299                 .rate = 44100,
300                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
301                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
302                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
303                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
304                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
305         },
306         {
307                 .name = "LOWPASS1K",
308                 .rate = 44100,
309                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
310                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
311                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
312                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
313                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
314         },
315         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
316                 .name = "HIBOOST",
317                 .rate = 44100,
318                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
319                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
320                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
321                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
322                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
323         },
324         { /* BASS=12dB, TREBLE=+12dB */
325                 .name = "LOUD12DB",
326                 .rate = 44100,
327                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
328                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
329                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
330                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
331                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
332         },
333         {
334                 .name = "FLAT",
335                 .rate = 16000,
336                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
337                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
338                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
339                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
340                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
341         },
342         {
343                 .name = "LOWPASS1K",
344                 .rate = 16000,
345                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
346                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
347                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
348                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
349                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
350         },
351         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
352                 .name = "HIBOOST",
353                 .rate = 16000,
354                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
355                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
356                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
357                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
358                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
359         },
360         { /* BASS=12dB, TREBLE=+12dB */
361                 .name = "LOUD12DB",
362                 .rate = 16000,
363                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
364                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
365                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
366                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
367                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
368         },
369 };
370
371 static struct max98095_pdata cardhu_max98095_pdata = {
372         /* equalizer configuration */
373         .eq_cfg = max98095_eq_cfg,
374         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
375
376         /* Biquad filter response configuration */
377         .bq_cfg = NULL,
378         .bq_cfgcnt = 0,
379
380         /* microphone configuration */
381         .digmic_left_mode = 1,
382         .digmic_right_mode = 1,
383 };
384
385 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
386         I2C_BOARD_INFO("wm8903", 0x1a),
387         .platform_data = &cardhu_wm8903_pdata,
388 };
389
390 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
391         I2C_BOARD_INFO("aic3262-codec", 0x18),
392 };
393
394 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
395         I2C_BOARD_INFO("max98095", 0x10),
396         .platform_data = &cardhu_max98095_pdata,
397 };
398
399 static void cardhu_i2c_init(void)
400 {
401         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
402         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
403         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
404         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
405         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
406
407         platform_device_register(&tegra_i2c_device5);
408         platform_device_register(&tegra_i2c_device4);
409         platform_device_register(&tegra_i2c_device3);
410         platform_device_register(&tegra_i2c_device2);
411         platform_device_register(&tegra_i2c_device1);
412
413         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
414                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
415         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
416         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
417         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
418
419         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
420         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
421 }
422
423 static struct platform_device *cardhu_uart_devices[] __initdata = {
424         &tegra_uarta_device,
425         &tegra_uartb_device,
426         &tegra_uartc_device,
427         &tegra_uartd_device,
428         &tegra_uarte_device,
429 };
430 static struct uart_clk_parent uart_parent_clk[] = {
431         [0] = {.name = "clk_m"},
432         [1] = {.name = "pll_p"},
433 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
434         [2] = {.name = "pll_m"},
435 #endif
436 };
437
438 static struct tegra_uart_platform_data cardhu_uart_pdata;
439 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
440
441 static void __init uart_debug_init(void)
442 {
443         struct board_info board_info;
444         int debug_port_id;
445
446         tegra_get_board_info(&board_info);
447
448         debug_port_id = get_tegra_uart_debug_port_id();
449         if (debug_port_id < 0) {
450                 debug_port_id = 0;
451                         /* UARTB is debug port
452                          *       for SLT - E1186/E1187/PM269
453                          *       for E1256/E1257
454                          */
455                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
456                         ((board_info.board_id == BOARD_E1186) ||
457                         (board_info.board_id == BOARD_E1187) ||
458                         (board_info.board_id == BOARD_PM269))) ||
459                         (board_info.board_id == BOARD_E1256) ||
460                         (board_info.board_id == BOARD_E1257))
461                                 debug_port_id = 1;
462         }
463
464 #ifdef CONFIG_TEGRA_IRDA
465         if ((board_info.board_id == BOARD_E1186) ||
466                 (board_info.board_id == BOARD_E1198)) {
467                 if (debug_port_id == 1) {
468                         cardhu_irda_pdata.is_irda = false;
469                         pr_err("UARTB is not available for IrDA\n");
470                 }
471         }
472 #endif
473
474         switch (debug_port_id) {
475         case 0:
476                 /* UARTA is the debug port. */
477                 pr_info("Selecting UARTA as the debug console\n");
478                 cardhu_uart_devices[0] = &debug_uarta_device;
479                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
480                 debug_uart_port_base = ((struct plat_serial8250_port *)(
481                         debug_uarta_device.dev.platform_data))->mapbase;
482                 break;
483
484         case 1:
485                 /* UARTB is the debug port. */
486                 pr_info("Selecting UARTB as the debug console\n");
487                 cardhu_uart_devices[1] = &debug_uartb_device;
488                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
489                 debug_uart_port_base = ((struct plat_serial8250_port *)(
490                         debug_uartb_device.dev.platform_data))->mapbase;
491                 break;
492
493         case 2:
494                 /* UARTC is the debug port. */
495                 pr_info("Selecting UARTC as the debug console\n");
496                 cardhu_uart_devices[2] = &debug_uartc_device;
497                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
498                 debug_uart_port_base = ((struct plat_serial8250_port *)(
499                         debug_uartc_device.dev.platform_data))->mapbase;
500                 break;
501
502         case 3:
503                 /* UARTD is the debug port. */
504                 pr_info("Selecting UARTD as the debug console\n");
505                 cardhu_uart_devices[3] = &debug_uartd_device;
506                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
507                 debug_uart_port_base = ((struct plat_serial8250_port *)(
508                         debug_uartd_device.dev.platform_data))->mapbase;
509                 break;
510
511         case 4:
512                 /* UARTE is the debug port. */
513                 pr_info("Selecting UARTE as the debug console\n");
514                 cardhu_uart_devices[4] = &debug_uarte_device;
515                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
516                 debug_uart_port_base = ((struct plat_serial8250_port *)(
517                         debug_uarte_device.dev.platform_data))->mapbase;
518                 break;
519
520         default:
521                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
522                 cardhu_uart_devices[0] = &debug_uarta_device;
523                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
524                 debug_uart_port_base = ((struct plat_serial8250_port *)(
525                         debug_uarta_device.dev.platform_data))->mapbase;
526                 break;
527         }
528         return;
529 }
530
531 static void __init cardhu_uart_init(void)
532 {
533         struct clk *c;
534         int i;
535         struct board_info board_info;
536
537         tegra_get_board_info(&board_info);
538
539         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
540                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
541                 if (IS_ERR_OR_NULL(c)) {
542                         pr_err("Not able to get the clock for %s\n",
543                                                 uart_parent_clk[i].name);
544                         continue;
545                 }
546                 uart_parent_clk[i].parent_clk = c;
547                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
548         }
549         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
550         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
551         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
552         cardhu_loopback_uart_pdata.parent_clk_count =
553                                                 ARRAY_SIZE(uart_parent_clk);
554         cardhu_loopback_uart_pdata.is_loopback = true;
555         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
556         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
557         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
558         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
559         /* UARTE is used for loopback test purpose */
560         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
561
562         /* Register low speed only if it is selected */
563         if (!is_tegra_debug_uartport_hs()) {
564                 uart_debug_init();
565                 /* Clock enable for the debug channel */
566                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
567                         pr_info("The debug console clock name is %s\n",
568                                                 debug_uart_clk->name);
569                         c = tegra_get_clock_by_name("pll_p");
570                         if (IS_ERR_OR_NULL(c))
571                                 pr_err("Not getting the parent clock pll_p\n");
572                         else
573                                 clk_set_parent(debug_uart_clk, c);
574
575                         clk_enable(debug_uart_clk);
576                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
577                 } else {
578                         pr_err("Not getting the clock %s for debug console\n",
579                                         debug_uart_clk->name);
580                 }
581         }
582
583 #ifdef CONFIG_TEGRA_IRDA
584         if (((board_info.board_id == BOARD_E1186) ||
585                 (board_info.board_id == BOARD_E1198)) &&
586                         cardhu_irda_pdata.is_irda) {
587                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
588                 cardhu_irda_pdata.parent_clk_count =
589                                         ARRAY_SIZE(uart_parent_clk);
590
591                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
592         }
593 #endif
594
595         platform_add_devices(cardhu_uart_devices,
596                                 ARRAY_SIZE(cardhu_uart_devices));
597 }
598
599 static struct platform_device tegra_camera = {
600         .name = "tegra_camera",
601         .id = -1,
602 };
603
604 static struct platform_device *cardhu_spi_devices[] __initdata = {
605         &tegra_spi_device4,
606 };
607
608 /*-----------------------------------------------------*/
609 /* Force Cardhu Direct Touch:
610         Valid Choices:
611         0 : Do not force Direct Touch
612         2 : RM_PLATFORM_C210 : Cardhu 10" J-Touch Panel
613         4 : RM_PLATFORM_P005 ; Pluto 5" J-Touch Panel
614 */
615 #define CARDHU_DT_PLATFORM      0 /* RM_PLATFORM_C210 */
616
617 static struct platform_device *touch_spi_device[] __initdata = {
618         &tegra_spi_device1,
619 };
620
621 struct spi_clk_parent spi_parent_clk[] = {
622         [0] = {.name = "pll_p"},
623 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
624         [1] = {.name = "pll_m"},
625         [2] = {.name = "clk_m"},
626 #else
627         [1] = {.name = "clk_m"},
628 #endif
629 };
630
631 static struct tegra_spi_platform_data cardhu_spi_pdata = {
632         .is_dma_based           = true,
633         .max_dma_buffer         = (16 * 1024),
634         .is_clkon_always        = false,
635         .max_rate               = 100000000,
636 };
637
638 static void __init cardhu_spi_init(void)
639 {
640         int i;
641         struct clk *c;
642         struct board_info board_info, display_board_info;
643
644         tegra_get_board_info(&board_info);
645         tegra_get_display_board_info(&display_board_info);
646
647         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
648                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
649                 if (IS_ERR_OR_NULL(c)) {
650                         pr_err("Not able to get the clock for %s\n",
651                                                 spi_parent_clk[i].name);
652                         continue;
653                 }
654                 spi_parent_clk[i].parent_clk = c;
655                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
656         }
657         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
658         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
659         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
660         platform_add_devices(cardhu_spi_devices,
661                                 ARRAY_SIZE(cardhu_spi_devices));
662
663         if ((display_board_info.board_id == BOARD_DISPLAY_PM313)
664                                                 || CARDHU_DT_PLATFORM) {
665                 platform_add_devices(touch_spi_device,
666                                 ARRAY_SIZE(touch_spi_device));
667         }
668
669         if (board_info.board_id == BOARD_E1198) {
670                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
671                 platform_device_register(&tegra_spi_device2);
672                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
673                 platform_device_register(&tegra_spi_slave_device1);
674         }
675 }
676
677 static void __init cardhu_dtv_init(void)
678 {
679         struct board_info board_info;
680
681         tegra_get_board_info(&board_info);
682
683         if (board_info.board_id == BOARD_E1186)
684                 platform_device_register(&tegra_dtv_device);
685 }
686
687 static struct resource tegra_rtc_resources[] = {
688         [0] = {
689                 .start = TEGRA_RTC_BASE,
690                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
691                 .flags = IORESOURCE_MEM,
692         },
693         [1] = {
694                 .start = INT_RTC,
695                 .end = INT_RTC,
696                 .flags = IORESOURCE_IRQ,
697         },
698 };
699
700 static struct platform_device tegra_rtc_device = {
701         .name = "tegra_rtc",
702         .id   = -1,
703         .resource = tegra_rtc_resources,
704         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
705 };
706
707 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
708         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
709         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
710         .gpio_hp_mute           = -1,
711         .gpio_int_mic_en        = -1,
712         .gpio_ext_mic_en        = -1,
713         .i2s_param[HIFI_CODEC]  = {
714                 .audio_port_id  = 0,
715                 .is_i2s_master  = 1,
716                 .i2s_mode       = TEGRA_DAIFMT_I2S,
717         },
718         .i2s_param[BASEBAND]    = {
719                 .audio_port_id  = -1,
720         },
721         .i2s_param[BT_SCO]      = {
722                 .audio_port_id  = 3,
723                 .is_i2s_master  = 1,
724                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
725         },
726 };
727
728 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
729         .gpio_spkr_en           = -1,
730         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
731         .gpio_hp_mute           = -1,
732         .gpio_int_mic_en        = -1,
733         .gpio_ext_mic_en        = -1,
734         .i2s_param[HIFI_CODEC]  = {
735                 .audio_port_id  = 0,
736                 .is_i2s_master  = 1,
737                 .i2s_mode       = TEGRA_DAIFMT_I2S,
738         },
739         .i2s_param[BASEBAND]    = {
740                 .audio_port_id  = -1,
741         },
742         .i2s_param[BT_SCO]      = {
743                 .audio_port_id  = 3,
744                 .is_i2s_master  = 1,
745                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
746         },
747 };
748
749 static struct platform_device cardhu_audio_wm8903_device = {
750         .name   = "tegra-snd-wm8903",
751         .id     = 0,
752         .dev    = {
753                 .platform_data = &cardhu_audio_wm8903_pdata,
754         },
755 };
756
757 static struct platform_device cardhu_audio_max98095_device = {
758         .name   = "tegra-snd-max98095",
759         .id     = 0,
760         .dev    = {
761                 .platform_data = &cardhu_audio_max98095_pdata,
762         },
763 };
764
765 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
766         .gpio_spkr_en           = -1,
767         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
768         .gpio_hp_mute           = -1,
769         .gpio_int_mic_en        = -1,
770         .gpio_ext_mic_en        = -1,
771         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
772         .i2s_param[HIFI_CODEC]  = {
773                 .audio_port_id  = 0,
774                 .is_i2s_master  = 1,
775                 .i2s_mode       = TEGRA_DAIFMT_I2S,
776                 .sample_size    = 16,
777         },
778         .i2s_param[BT_SCO]      = {
779                 .sample_size    = 16,
780                 .audio_port_id  = 3,
781                 .is_i2s_master  = 1,
782                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
783         },
784 };
785
786 static struct platform_device cardhu_audio_aic326x_device = {
787         .name   = "tegra-snd-aic326x",
788         .id     = 0,
789         .dev    = {
790                 .platform_data  = &cardhu_audio_aic326x_pdata,
791         },
792 };
793
794 static struct platform_device *cardhu_devices[] __initdata = {
795         &tegra_pmu_device,
796         &tegra_rtc_device,
797         &tegra_udc_device,
798         &tegra_wdt0_device,
799         &tegra_wdt1_device,
800         &tegra_wdt2_device,
801 #if defined(CONFIG_TEGRA_AVP)
802         &tegra_avp_device,
803 #endif
804         &tegra_camera,
805 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
806         &tegra_se_device,
807 #endif
808         &tegra_ahub_device,
809         &tegra_dam_device0,
810         &tegra_dam_device1,
811         &tegra_dam_device2,
812         &tegra_i2s_device0,
813         &tegra_i2s_device1,
814         &tegra_i2s_device3,
815         &tegra_spdif_device,
816         &spdif_dit_device,
817         &bluetooth_dit_device,
818         &baseband_dit_device,
819         &cardhu_bt_rfkill_device,
820         &tegra_pcm_device,
821         &cardhu_audio_wm8903_device,
822         &cardhu_audio_max98095_device,
823         &cardhu_audio_aic326x_device,
824         &tegra_hda_device,
825         &tegra_cec_device,
826 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
827         &tegra_aes_device,
828 #endif
829 };
830
831 #define E1506_MXT_CONFIG_CRC 0x62F903
832 static const u8 e1506_config[] = {
833         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
835         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
836         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
837         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
838         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
839         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
843         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
844         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
845         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
846         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
847         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
852         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
853         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
854         0x00
855 };
856
857 #define MXT_CONFIG_CRC  0xD62DE8
858 static const u8 config[] = {
859         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
860         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
861         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
862         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
863         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
864         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
869         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
870         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
871         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
872         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
873         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
876         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
877         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
878         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
879 };
880
881 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
882 static const u8 config_sku2000[] = {
883         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
884         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
885         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
886         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
887         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
888         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
889         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
890         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
891         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
892         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
893         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
894         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
895         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
896         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
897         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
899         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
900         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
901         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
903 };
904
905 static struct mxt_platform_data atmel_mxt_info = {
906         .x_line         = 27,
907         .y_line         = 42,
908         .x_size         = 768,
909         .y_size         = 1366,
910         .blen           = 0x20,
911         .threshold      = 0x3C,
912         .voltage        = 3300000,              /* 3.3V */
913         .orient         = 5,
914         .config         = config,
915         .config_length  = 157,
916         .config_crc     = MXT_CONFIG_CRC,
917         .irqflags       = IRQF_TRIGGER_FALLING,
918 /*      .read_chg       = &read_chg, */
919         .read_chg       = NULL,
920 };
921
922 static struct mxt_platform_data e1506_atmel_mxt_info = {
923         .x_line         = 19,
924         .y_line         = 11,
925         .x_size         = 960,
926         .y_size         = 540,
927         .blen           = 0x10,
928         .threshold      = 0x32,
929         .voltage        = 3300000,              /* 3.3V */
930         .orient         = 3,
931         .config         = e1506_config,
932         .config_length  = 168,
933         .config_crc     = E1506_MXT_CONFIG_CRC,
934         .irqflags       = IRQF_TRIGGER_FALLING,
935 /*      .read_chg       = &read_chg, */
936         .read_chg       = NULL,
937 };
938
939 static struct i2c_board_info __initdata atmel_i2c_info[] = {
940         {
941                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
942                 .platform_data = &atmel_mxt_info,
943         }
944 };
945
946 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
947         {
948                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
949                 .platform_data = &e1506_atmel_mxt_info,
950         }
951 };
952
953 /* Raydium touchscreen                     Driver data */
954 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
955         /* name         parent          rate            enabled */
956         { "sbc1",       "pll_p",        52000000,       true},
957         { NULL,         NULL,           0,              0},
958 };
959
960 static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
961         /* name         parent          rate            enabled */
962         { "extern3",    "pll_p",        41000000,       true},
963         { "clk_out_3",  "extern3",      40800000,       true},
964         { NULL,         NULL,           0,              0},
965 };
966
967 struct rm_spi_ts_platform_data rm31080ts_cardhu_data = {
968         .gpio_reset = 0,
969         .config = 0,
970 };
971
972 struct spi_board_info rm31080a_cardhu_spi_board[1] = {
973         {
974          .modalias = "rm_ts_spidev",
975          .bus_num = 0,
976          .chip_select = 0,
977          .max_speed_hz = 13 * 1000 * 1000,
978          .mode = SPI_MODE_0,
979          .platform_data = &rm31080ts_cardhu_data,
980          },
981 };
982
983 static int __init cardhu_touch_init(void)
984 {
985         struct board_info BoardInfo, DisplayBoardInfo;
986
987         tegra_get_board_info(&BoardInfo);
988         tegra_get_display_board_info(&DisplayBoardInfo);
989         if ((DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313)
990                                                 || CARDHU_DT_PLATFORM) {
991                 tegra_clk_init_from_table(spi_clk_init_table);
992                 tegra_clk_init_from_table(touch_clk_init_table);
993                 clk_enable(tegra_get_clock_by_name("clk_out_3"));
994                 rm31080ts_cardhu_data.platform_id = CARDHU_DT_PLATFORM;
995                 rm31080a_cardhu_spi_board[0].irq = gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
996                 touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI,
997                                         TOUCH_GPIO_RST_RAYDIUM_SPI,
998                                         &rm31080ts_cardhu_data,
999                                         &rm31080a_cardhu_spi_board[0],
1000                                         ARRAY_SIZE(rm31080a_cardhu_spi_board));
1001         } else {
1002                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1003                 gpio_direction_input(TEGRA_GPIO_PH4);
1004
1005                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1006                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1007                 msleep(1);
1008                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1009                 msleep(100);
1010
1011                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1012                         atmel_mxt_info.config = config_sku2000;
1013                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1014                 }
1015
1016                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1017                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1018                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1019                 } else {
1020                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1021                         i2c_register_board_info(1, atmel_i2c_info, 1);
1022                 }
1023         }
1024
1025         return 0;
1026 }
1027
1028 #if defined(CONFIG_USB_SUPPORT)
1029
1030 static void cardu_usb_hsic_postsupend(void)
1031 {
1032 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1033         baseband_xmm_set_power_status(BBXMM_PS_L2);
1034 #endif
1035 }
1036
1037 static void cardu_usb_hsic_preresume(void)
1038 {
1039 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1040         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1041 #endif
1042 }
1043
1044 static void cardu_usb_hsic_phy_ready(void)
1045 {
1046 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1047         baseband_xmm_set_power_status(BBXMM_PS_L0);
1048 #endif
1049 }
1050
1051 static void cardu_usb_hsic_phy_off(void)
1052 {
1053 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1054         baseband_xmm_set_power_status(BBXMM_PS_L3);
1055 #endif
1056 }
1057
1058 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1059         .post_suspend = cardu_usb_hsic_postsupend,
1060         .pre_resume = cardu_usb_hsic_preresume,
1061         .port_power = cardu_usb_hsic_phy_ready,
1062         .post_phy_off = cardu_usb_hsic_phy_off,
1063 };
1064
1065 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1066         .port_otg = false,
1067         .has_hostpc = true,
1068         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1069         .op_mode        = TEGRA_USB_OPMODE_HOST,
1070         .u_data.host = {
1071                 .vbus_gpio = -1,
1072                 .hot_plug = false,
1073                 .remote_wakeup_supported = false,
1074                 .power_off_on_suspend = false,
1075         },
1076         .ops = &hsic_xmm_plat_ops,
1077 };
1078 #endif
1079
1080 static int hsic_enable_gpio = -1;
1081 static int hsic_reset_gpio = -1;
1082
1083 void hsic_platform_open(void)
1084 {
1085         int reset_gpio = -1, enable_gpio = -1;
1086
1087         if (hsic_enable_gpio != -1)
1088                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1089         if (hsic_reset_gpio != -1)
1090                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1091         /* hsic enable signal deasserted, hsic reset asserted */
1092         if (!enable_gpio)
1093                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1094         if (!reset_gpio)
1095                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1096         /* keep hsic reset asserted for 1 ms */
1097         udelay(1000);
1098         /* enable (power on) hsic */
1099         if (!enable_gpio)
1100                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1101         udelay(1000);
1102         /* deassert reset */
1103         if (!reset_gpio)
1104                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1105
1106 }
1107
1108 void hsic_platform_close(void)
1109 {
1110         if (hsic_enable_gpio != -1) {
1111                 gpio_set_value(hsic_enable_gpio, 0);
1112                 gpio_free(hsic_enable_gpio);
1113         }
1114         if (hsic_reset_gpio != -1) {
1115                 gpio_set_value(hsic_reset_gpio, 0);
1116                 gpio_free(hsic_reset_gpio);
1117         }
1118 }
1119
1120 void hsic_power_on(void)
1121 {
1122         if (hsic_enable_gpio != -1) {
1123                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1124                 udelay(1000);
1125         }
1126 }
1127
1128 void hsic_power_off(void)
1129 {
1130         if (hsic_enable_gpio != -1) {
1131                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1132                 udelay(1000);
1133         }
1134 }
1135
1136 #if defined(CONFIG_USB_SUPPORT)
1137 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1138         .open = hsic_platform_open,
1139         .close = hsic_platform_close,
1140         .pre_phy_on = hsic_power_on,
1141         .post_phy_off = hsic_power_off,
1142 };
1143
1144 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1145         .port_otg = false,
1146         .has_hostpc = true,
1147         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1148         .op_mode        = TEGRA_USB_OPMODE_HOST,
1149         .u_data.host = {
1150                 .vbus_gpio = -1,
1151                 .hot_plug = false,
1152                 .remote_wakeup_supported = false,
1153                 .power_off_on_suspend = false,
1154         },
1155         .ops = &hsic_plat_ops,
1156 };
1157
1158 static struct tegra_usb_platform_data tegra_udc_pdata = {
1159         .port_otg = true,
1160         .has_hostpc = true,
1161         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1162         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1163         .u_data.dev = {
1164                 .vbus_pmu_irq = 0,
1165                 .vbus_gpio = -1,
1166                 .charging_supported = false,
1167                 .remote_wakeup_supported = false,
1168         },
1169         .u_cfg.utmi = {
1170                 .hssync_start_delay = 0,
1171                 .elastic_limit = 16,
1172                 .idle_wait_delay = 17,
1173                 .term_range_adj = 6,
1174                 .xcvr_setup = 8,
1175                 .xcvr_lsfslew = 2,
1176                 .xcvr_lsrslew = 2,
1177                 .xcvr_setup_offset = 0,
1178                 .xcvr_use_fuses = 1,
1179         },
1180 };
1181
1182 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1183         .port_otg = false,
1184         .has_hostpc = true,
1185         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1186         .op_mode        = TEGRA_USB_OPMODE_HOST,
1187         .u_data.host = {
1188                 .vbus_gpio = -1,
1189                 .hot_plug = false,
1190                 .remote_wakeup_supported = true,
1191                 .power_off_on_suspend = true,
1192         },
1193         .u_cfg.utmi = {
1194                 .hssync_start_delay = 0,
1195                 .elastic_limit = 16,
1196                 .idle_wait_delay = 17,
1197                 .term_range_adj = 6,
1198                 .xcvr_setup = 15,
1199                 .xcvr_lsfslew = 2,
1200                 .xcvr_lsrslew = 2,
1201                 .xcvr_setup_offset = 0,
1202                 .xcvr_use_fuses = 1,
1203         },
1204 };
1205
1206 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1207         .port_otg = false,
1208         .has_hostpc = true,
1209         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1210         .op_mode = TEGRA_USB_OPMODE_HOST,
1211         .u_data.host = {
1212                 .vbus_gpio = -1,
1213                 .hot_plug = true,
1214                 .remote_wakeup_supported = true,
1215                 .power_off_on_suspend = true,
1216         },
1217         .u_cfg.utmi = {
1218                 .hssync_start_delay = 0,
1219                 .elastic_limit = 16,
1220                 .idle_wait_delay = 17,
1221                 .term_range_adj = 6,
1222                 .xcvr_setup = 8,
1223                 .xcvr_lsfslew = 2,
1224                 .xcvr_lsrslew = 2,
1225                 .xcvr_setup_offset = 0,
1226                 .xcvr_use_fuses = 1,
1227         },
1228 };
1229
1230 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1231         .port_otg = true,
1232         .has_hostpc = true,
1233         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1234         .op_mode = TEGRA_USB_OPMODE_HOST,
1235         .u_data.host = {
1236                 .vbus_gpio = -1,
1237                 .hot_plug = true,
1238                 .remote_wakeup_supported = true,
1239                 .power_off_on_suspend = true,
1240         },
1241         .u_cfg.utmi = {
1242                 .hssync_start_delay = 0,
1243                 .elastic_limit = 16,
1244                 .idle_wait_delay = 17,
1245                 .term_range_adj = 6,
1246                 .xcvr_setup = 15,
1247                 .xcvr_lsfslew = 2,
1248                 .xcvr_lsrslew = 2,
1249                 .xcvr_setup_offset = 0,
1250                 .xcvr_use_fuses = 1,
1251         },
1252 };
1253
1254 static struct tegra_usb_otg_data tegra_otg_pdata = {
1255         .ehci_device = &tegra_ehci1_device,
1256         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1257 };
1258 #endif
1259
1260 #if defined(CONFIG_USB_SUPPORT)
1261 static void cardhu_usb_init(void)
1262 {
1263         struct board_info bi;
1264
1265         tegra_get_board_info(&bi);
1266
1267         /* OTG should be the first to be registered */
1268         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1269         platform_device_register(&tegra_otg_device);
1270
1271         /* setup the udc platform data */
1272         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1273
1274         if (bi.board_id == BOARD_PM267) {
1275                 hsic_enable_gpio = EN_HSIC_GPIO;
1276                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1277                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1278                 platform_device_register(&tegra_ehci2_device);
1279         } else if (bi.board_id == BOARD_E1256) {
1280                 hsic_enable_gpio = EN_HSIC_GPIO;
1281                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1282                 platform_device_register(&tegra_ehci2_device);
1283         } else if (bi.board_id == BOARD_E1186) {
1284                 tegra_ehci2_device.dev.platform_data =
1285                                                 &tegra_ehci2_hsic_xmm_pdata;
1286                 /* ehci2 registration happens in baseband-xmm-power  */
1287         } else {
1288                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1289                 platform_device_register(&tegra_ehci2_device);
1290         }
1291
1292         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1293         platform_device_register(&tegra_ehci3_device);
1294
1295 }
1296 #else
1297 static void cardhu_usb_init(void) { }
1298 #endif
1299
1300 static struct baseband_power_platform_data tegra_baseband_power_data = {
1301         .baseband_type = BASEBAND_XMM,
1302         .modem = {
1303         .xmm = {
1304                         .bb_rst = XMM_GPIO_BB_RST,
1305                         .bb_on = XMM_GPIO_BB_ON,
1306                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1307                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1308                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1309                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1310                         .hsic_device = &tegra_ehci2_device,
1311                 },
1312         },
1313 };
1314
1315 static struct platform_device tegra_baseband_power_device = {
1316         .name = "baseband_xmm_power",
1317         .id = -1,
1318         .dev = {
1319                 .platform_data = &tegra_baseband_power_data,
1320         },
1321 };
1322
1323 static struct platform_device tegra_baseband_power2_device = {
1324         .name = "baseband_xmm_power2",
1325         .id = -1,
1326         .dev = {
1327                 .platform_data = &tegra_baseband_power_data,
1328         },
1329 };
1330
1331
1332 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1333         .port_status[0] = 1,
1334         .port_status[1] = 1,
1335         .port_status[2] = 1,
1336         .use_dock_detect        = 0,
1337         .gpio           = 0,
1338 };
1339
1340 static void cardhu_pci_init(void)
1341 {
1342         struct board_info board_info;
1343
1344         tegra_get_board_info(&board_info);
1345         if (board_info.board_id == BOARD_E1291) {
1346                 cardhu_pci_platform_data.port_status[0] = 0;
1347                 cardhu_pci_platform_data.port_status[1] = 0;
1348                 cardhu_pci_platform_data.port_status[2] = 1;
1349                 cardhu_pci_platform_data.use_dock_detect = 1;
1350                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1351         }
1352         if ((board_info.board_id == BOARD_E1186) ||
1353                 (board_info.board_id == BOARD_E1187) ||
1354                 (board_info.board_id == BOARD_E1291)) {
1355                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1356                 platform_device_register(&tegra_pci_device);
1357         }
1358 }
1359
1360 static void cardhu_modem_init(void)
1361 {
1362         struct board_info board_info;
1363         int w_disable_gpio, ret;
1364
1365         tegra_get_board_info(&board_info);
1366         switch (board_info.board_id) {
1367         case BOARD_E1291:
1368         case BOARD_E1198:
1369                 if (((board_info.board_id == BOARD_E1291) &&
1370                                 (board_info.fab < BOARD_FAB_A03)) ||
1371                         ((board_info.board_id == BOARD_E1198) &&
1372                                         (board_info.fab < BOARD_FAB_A02))) {
1373                         w_disable_gpio = TEGRA_GPIO_PH5;
1374                 } else {
1375                         w_disable_gpio = TEGRA_GPIO_PDD5;
1376                 }
1377
1378                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1379                 if (ret < 0)
1380                         pr_err("%s: gpio_request failed for gpio %d\n",
1381                                 __func__, w_disable_gpio);
1382                 else
1383                         gpio_direction_input(w_disable_gpio);
1384
1385                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1386                 if (((board_info.board_id == BOARD_E1291) &&
1387                                 (board_info.fab >= BOARD_FAB_A04)) ||
1388                         ((board_info.board_id == BOARD_E1198) &&
1389                                         (board_info.fab >= BOARD_FAB_A02))) {
1390                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1391                         if (ret < 0) {
1392                                 pr_err("%s(): Error in allocating gpio "
1393                                         "TEGRA_GPIO_PH7\n", __func__);
1394                                 break;
1395                         }
1396                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1397                 }
1398                 break;
1399         case BOARD_E1186:
1400                 platform_device_register(&tegra_baseband_power_device);
1401                 platform_device_register(&tegra_baseband_power2_device);
1402                 break;
1403         default:
1404                 break;
1405         }
1406
1407 }
1408
1409 #ifdef CONFIG_SATA_AHCI_TEGRA
1410 static void cardhu_sata_init(void)
1411 {
1412         platform_device_register(&tegra_sata_device);
1413 }
1414 #else
1415 static void cardhu_sata_init(void) { }
1416 #endif
1417
1418 /* This needs to be inialized later hand */
1419 static int __init cardhu_throttle_list_init(void)
1420 {
1421         int i;
1422         for (i = 0; i < ARRAY_SIZE(throttle_list); i++)
1423                 if (balanced_throttle_register(&throttle_list[i]))
1424                         return -ENODEV;
1425
1426         return 0;
1427 }
1428 late_initcall(cardhu_throttle_list_init);
1429
1430 static void __init tegra_cardhu_init(void)
1431 {
1432         tegra_thermal_init(thermal_binds);
1433         tegra_clk_init_from_table(cardhu_clk_init_table);
1434         tegra_enable_pinmux();
1435         tegra_smmu_init();
1436         tegra_soc_device_init("cardhu");
1437         cardhu_pinmux_init();
1438         cardhu_i2c_init();
1439         cardhu_spi_init();
1440         cardhu_usb_init();
1441 #ifdef CONFIG_TEGRA_EDP_LIMITS
1442         cardhu_edp_init();
1443 #endif
1444         cardhu_uart_init();
1445         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1446         tegra_ram_console_debug_init();
1447         tegra_io_dpd_init();
1448         cardhu_sdhci_init();
1449         cardhu_regulator_init();
1450         cardhu_dtv_init();
1451         cardhu_suspend_init();
1452         cardhu_touch_init();
1453         cardhu_modem_init();
1454         cardhu_kbc_init();
1455         cardhu_scroll_init();
1456         cardhu_keys_init();
1457         cardhu_panel_init();
1458         cardhu_pmon_init();
1459         cardhu_sensors_init();
1460         cardhu_setup_bluesleep();
1461         cardhu_sata_init();
1462         cardhu_pins_state_init();
1463         cardhu_emc_init();
1464         tegra_release_bootloader_fb();
1465         cardhu_pci_init();
1466 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1467         tegra_wdt_recovery_init();
1468 #endif
1469         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1470 }
1471
1472 static void __init tegra_cardhu_dt_init(void)
1473 {
1474         tegra_cardhu_init();
1475
1476         of_platform_populate(NULL,
1477                 of_default_bus_match_table, NULL, NULL);
1478 }
1479
1480 static void __init tegra_cardhu_reserve(void)
1481 {
1482 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1483         /* support 1920X1200 with 24bpp */
1484         tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M);
1485 #else
1486         tegra_reserve(SZ_128M, SZ_8M, SZ_16M);
1487 #endif
1488 }
1489
1490 static const char *cardhu_dt_board_compat[] = {
1491         "nvidia,cardhu",
1492         NULL
1493 };
1494
1495 MACHINE_START(CARDHU, "cardhu")
1496         .atag_offset    = 0x100,
1497         .soc            = &tegra_soc_desc,
1498         .map_io         = tegra_map_common_io,
1499         .reserve        = tegra_cardhu_reserve,
1500         .init_early     = tegra30_init_early,
1501         .init_irq       = tegra_init_irq,
1502         .handle_irq     = gic_handle_irq,
1503         .timer          = &tegra_timer,
1504         .init_machine   = tegra_cardhu_dt_init,
1505         .restart        = tegra_assert_system_reset,
1506         .dt_compat      = cardhu_dt_board_compat,
1507 MACHINE_END