drivers: skin: Skin prediction algorithm
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <mach/clk.h>
49 #include <mach/iomap.h>
50 #include <mach/irqs.h>
51 #include <mach/pinmux.h>
52 #include <mach/iomap.h>
53 #include <mach/io.h>
54 #include <mach/i2s.h>
55 #include <mach/tegra_asoc_pdata.h>
56 #include <mach/tegra_wm8903_pdata.h>
57 #include <asm/mach-types.h>
58 #include <asm/mach/arch.h>
59 #include <mach/usb_phy.h>
60 #include <mach/thermal.h>
61 #include <mach/pci.h>
62
63 #include "board.h"
64 #include "clock.h"
65 #include "board-cardhu.h"
66 #include "board-touch.h"
67 #include "devices.h"
68 #include "gpio-names.h"
69 #include "fuse.h"
70 #include "pm.h"
71 #include "baseband-xmm-power.h"
72 #include "wdt-recovery.h"
73
74 static struct balanced_throttle throttle_list[] = {
75 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
76         {
77                 .id = BALANCED_THROTTLE_ID_TJ,
78                 .throt_tab_size = 10,
79                 .throt_tab = {
80                         {      0, 1000 },
81                         { 640000, 1000 },
82                         { 640000, 1000 },
83                         { 640000, 1000 },
84                         { 640000, 1000 },
85                         { 640000, 1000 },
86                         { 760000, 1000 },
87                         { 760000, 1050 },
88                         {1000000, 1050 },
89                         {1000000, 1100 },
90                 },
91         },
92 #endif
93 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
94         {
95                 .id = BALANCED_THROTTLE_ID_SKIN,
96                 .throt_tab_size = 6,
97                 .throt_tab = {
98                         { 640000, 1200 },
99                         { 640000, 1200 },
100                         { 760000, 1200 },
101                         { 760000, 1200 },
102                         {1000000, 1200 },
103                         {1000000, 1200 },
104                 },
105         },
106 #endif
107 };
108
109 /* All units are in millicelsius */
110 static struct tegra_thermal_data thermal_data = {
111         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
112         .temp_shutdown = 90000,
113
114 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
115         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
116 #endif
117 #ifdef CONFIG_TEGRA_EDP_LIMITS
118         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
119         .hysteresis_edp = 3000,
120 #endif
121 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
122         .temp_throttle = 85000,
123         .tc1 = 0,
124         .tc2 = 1,
125         .passive_delay = 2000,
126 #endif
127 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
128         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
129         .temp_throttle_skin = 43000,
130         .tc1_skin = 0,
131         .tc2_skin = 1,
132         .passive_delay_skin = 5000,
133
134         .skin_temp_offset = 9793,
135         .skin_period = 1100,
136         .skin_devs_size = 2,
137         .skin_devs = {
138                 {
139                         THERMAL_DEVICE_ID_NCT_EXT,
140                         {
141                                 2, 1, 1, 1,
142                                 1, 1, 1, 1,
143                                 1, 1, 1, 0,
144                                 1, 1, 0, 0,
145                                 0, 0, -1, -7
146                         }
147                 },
148                 {
149                         THERMAL_DEVICE_ID_NCT_INT,
150                         {
151                                 -11, -7, -5, -3,
152                                 -3, -2, -1, 0,
153                                 0, 0, 1, 1,
154                                 1, 2, 2, 3,
155                                 4, 6, 11, 18
156                         }
157                 },
158         },
159 #endif
160 };
161
162 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
163         {
164                 .name           = "bt_rfkill",
165                 .shutdown_gpio  = TEGRA_GPIO_PU0,
166                 .reset_gpio     = TEGRA_GPIO_INVALID,
167                 .type           = RFKILL_TYPE_BLUETOOTH,
168         },
169 };
170
171 static struct platform_device cardhu_bt_rfkill_device = {
172         .name = "rfkill_gpio",
173         .id             = -1,
174         .dev = {
175                 .platform_data = &cardhu_bt_rfkill_pdata,
176         },
177 };
178
179 static struct resource cardhu_bluesleep_resources[] = {
180         [0] = {
181                 .name = "gpio_host_wake",
182                         .start  = TEGRA_GPIO_PU6,
183                         .end    = TEGRA_GPIO_PU6,
184                         .flags  = IORESOURCE_IO,
185         },
186         [1] = {
187                 .name = "gpio_ext_wake",
188                         .start  = TEGRA_GPIO_PU1,
189                         .end    = TEGRA_GPIO_PU1,
190                         .flags  = IORESOURCE_IO,
191         },
192         [2] = {
193                 .name = "host_wake",
194                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
195                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
196                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
197         },
198 };
199
200 static struct platform_device cardhu_bluesleep_device = {
201         .name           = "bluesleep",
202         .id             = -1,
203         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
204         .resource       = cardhu_bluesleep_resources,
205 };
206
207 static noinline void __init cardhu_setup_bluesleep(void)
208 {
209         platform_device_register(&cardhu_bluesleep_device);
210         return;
211 }
212
213 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
214         /* name         parent          rate            enabled */
215         { "pll_m",      NULL,           0,              false},
216         { "hda",        "pll_p",        108000000,      false},
217         { "hda2codec_2x","pll_p",       48000000,       false},
218         { "pwm",        "pll_p",        3187500,        false},
219         { "blink",      "clk_32k",      32768,          true},
220         { "i2s0",       "pll_a_out0",   0,              false},
221         { "i2s1",       "pll_a_out0",   0,              false},
222         { "i2s3",       "pll_a_out0",   0,              false},
223         { "spdif_out",  "pll_a_out0",   0,              false},
224         { "d_audio",    "clk_m",        12000000,       false},
225         { "dam0",       "clk_m",        12000000,       false},
226         { "dam1",       "clk_m",        12000000,       false},
227         { "dam2",       "clk_m",        12000000,       false},
228         { "audio1",     "i2s1_sync",    0,              false},
229         { "audio3",     "i2s3_sync",    0,              false},
230         { "vi_sensor",  "pll_p",        150000000,      false},
231         { "i2c1",       "pll_p",        3200000,        false},
232         { "i2c2",       "pll_p",        3200000,        false},
233         { "i2c3",       "pll_p",        3200000,        false},
234         { "i2c4",       "pll_p",        3200000,        false},
235         { "i2c5",       "pll_p",        3200000,        false},
236         { NULL,         NULL,           0,              0},
237 };
238
239 static struct pn544_i2c_platform_data nfc_pdata = {
240         .irq_gpio = TEGRA_GPIO_PX0,
241         .ven_gpio = TEGRA_GPIO_PP3,
242         .firm_gpio = TEGRA_GPIO_PO7,
243         };
244
245 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
246         {
247                 I2C_BOARD_INFO("pn544", 0x28),
248                 .platform_data = &nfc_pdata,
249                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
250         },
251 };
252 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
253         .adapter_nr     = 0,
254         .bus_count      = 1,
255         .bus_clk_rate   = { 100000, 0 },
256         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
257         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
258         .arb_recovery = arb_lost_recovery,
259 };
260
261 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
262         .adapter_nr     = 1,
263         .bus_count      = 1,
264         .bus_clk_rate   = { 400000, 0 },
265         .is_clkon_always = true,
266         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
267         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
268         .arb_recovery = arb_lost_recovery,
269 };
270
271 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
272         .adapter_nr     = 2,
273         .bus_count      = 1,
274         .bus_clk_rate   = { 100000, 0 },
275         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
276         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
277         .arb_recovery = arb_lost_recovery,
278 };
279
280 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
281         .adapter_nr     = 3,
282         .bus_count      = 1,
283         .bus_clk_rate   = { 10000, 0 },
284         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
285         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
286         .arb_recovery = arb_lost_recovery,
287 };
288
289 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
290         .adapter_nr     = 4,
291         .bus_count      = 1,
292         .bus_clk_rate   = { 400000, 0 },
293         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
294         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
295         .arb_recovery = arb_lost_recovery,
296 };
297
298
299 #if 0
300 struct tegra_wired_jack_conf audio_wr_jack_conf = {
301         .hp_det_n = TEGRA_GPIO_PW2,
302         .en_mic_ext = TEGRA_GPIO_PX1,
303         .en_mic_int = TEGRA_GPIO_PX0,
304 };
305 #endif
306
307 static struct wm8903_platform_data cardhu_wm8903_pdata = {
308         .irq_active_low = 0,
309         .micdet_cfg = 0,
310         .micdet_delay = 100,
311         .gpio_base = CARDHU_GPIO_WM8903(0),
312         .gpio_cfg = {
313                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
314                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
315                         WM8903_GP2_DIR,
316                 0,
317                 WM8903_GPIO_NO_CONFIG,
318                 WM8903_GPIO_NO_CONFIG,
319         },
320 };
321
322 /* Equalizer filter coefs generated from the MAXIM MAX98095
323  * evkit software tool */
324 static struct max98095_eq_cfg max98095_eq_cfg[] = {
325         {
326                 .name = "FLAT",
327                 .rate = 44100,
328                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
329                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
330                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
331                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
332                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
333         },
334         {
335                 .name = "LOWPASS1K",
336                 .rate = 44100,
337                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
338                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
339                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
340                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
341                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
342         },
343         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
344                 .name = "HIBOOST",
345                 .rate = 44100,
346                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
347                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
348                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
349                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
350                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
351         },
352         { /* BASS=12dB, TREBLE=+12dB */
353                 .name = "LOUD12DB",
354                 .rate = 44100,
355                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
356                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
357                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
358                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
359                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
360         },
361         {
362                 .name = "FLAT",
363                 .rate = 16000,
364                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
365                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
366                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
367                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
368                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
369         },
370         {
371                 .name = "LOWPASS1K",
372                 .rate = 16000,
373                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
374                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
375                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
376                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
377                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
378         },
379         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
380                 .name = "HIBOOST",
381                 .rate = 16000,
382                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
383                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
384                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
385                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
386                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
387         },
388         { /* BASS=12dB, TREBLE=+12dB */
389                 .name = "LOUD12DB",
390                 .rate = 16000,
391                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
392                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
393                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
394                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
395                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
396         },
397 };
398
399 static struct max98095_pdata cardhu_max98095_pdata = {
400         /* equalizer configuration */
401         .eq_cfg = max98095_eq_cfg,
402         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
403
404         /* Biquad filter response configuration */
405         .bq_cfg = NULL,
406         .bq_cfgcnt = 0,
407
408         /* microphone configuration */
409         .digmic_left_mode = 1,
410         .digmic_right_mode = 1,
411 };
412
413 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
414         I2C_BOARD_INFO("wm8903", 0x1a),
415         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
416         .platform_data = &cardhu_wm8903_pdata,
417 };
418
419 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
420         I2C_BOARD_INFO("aic3262-codec", 0x18),
421         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
422 };
423
424 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
425         I2C_BOARD_INFO("max98095", 0x10),
426         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
427         .platform_data = &cardhu_max98095_pdata,
428 };
429
430 static void cardhu_i2c_init(void)
431 {
432         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
433         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
434         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
435         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
436         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
437
438         platform_device_register(&tegra_i2c_device5);
439         platform_device_register(&tegra_i2c_device4);
440         platform_device_register(&tegra_i2c_device3);
441         platform_device_register(&tegra_i2c_device2);
442         platform_device_register(&tegra_i2c_device1);
443
444         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
445         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
446         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
447
448         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
449 }
450
451 static struct platform_device *cardhu_uart_devices[] __initdata = {
452         &tegra_uarta_device,
453         &tegra_uartb_device,
454         &tegra_uartc_device,
455         &tegra_uartd_device,
456         &tegra_uarte_device,
457 };
458 static struct uart_clk_parent uart_parent_clk[] = {
459         [0] = {.name = "clk_m"},
460         [1] = {.name = "pll_p"},
461 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
462         [2] = {.name = "pll_m"},
463 #endif
464 };
465
466 static struct tegra_uart_platform_data cardhu_uart_pdata;
467 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
468
469 static void __init uart_debug_init(void)
470 {
471         struct board_info board_info;
472         int debug_port_id;
473
474         tegra_get_board_info(&board_info);
475
476         debug_port_id = get_tegra_uart_debug_port_id();
477         if (debug_port_id < 0) {
478                 debug_port_id = 0;
479                         /* UARTB is debug port
480                          *       for SLT - E1186/E1187/PM269
481                          *       for E1256/E1257
482                          */
483                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
484                         ((board_info.board_id == BOARD_E1186) ||
485                         (board_info.board_id == BOARD_E1187) ||
486                         (board_info.board_id == BOARD_PM269))) ||
487                         (board_info.board_id == BOARD_E1256) ||
488                         (board_info.board_id == BOARD_E1257))
489                                 debug_port_id = 1;
490         }
491
492         switch (debug_port_id) {
493         case 0:
494                 /* UARTA is the debug port. */
495                 pr_info("Selecting UARTA as the debug console\n");
496                 cardhu_uart_devices[0] = &debug_uarta_device;
497                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
498                 debug_uart_port_base = ((struct plat_serial8250_port *)(
499                         debug_uarta_device.dev.platform_data))->mapbase;
500                 break;
501
502         case 1:
503                 /* UARTB is the debug port. */
504                 pr_info("Selecting UARTB as the debug console\n");
505                 cardhu_uart_devices[1] = &debug_uartb_device;
506                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
507                 debug_uart_port_base = ((struct plat_serial8250_port *)(
508                         debug_uartb_device.dev.platform_data))->mapbase;
509                 break;
510
511         case 2:
512                 /* UARTC is the debug port. */
513                 pr_info("Selecting UARTC as the debug console\n");
514                 cardhu_uart_devices[2] = &debug_uartc_device;
515                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
516                 debug_uart_port_base = ((struct plat_serial8250_port *)(
517                         debug_uartc_device.dev.platform_data))->mapbase;
518                 break;
519
520         case 3:
521                 /* UARTD is the debug port. */
522                 pr_info("Selecting UARTD as the debug console\n");
523                 cardhu_uart_devices[3] = &debug_uartd_device;
524                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
525                 debug_uart_port_base = ((struct plat_serial8250_port *)(
526                         debug_uartd_device.dev.platform_data))->mapbase;
527                 break;
528
529         case 4:
530                 /* UARTE is the debug port. */
531                 pr_info("Selecting UARTE as the debug console\n");
532                 cardhu_uart_devices[4] = &debug_uarte_device;
533                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
534                 debug_uart_port_base = ((struct plat_serial8250_port *)(
535                         debug_uarte_device.dev.platform_data))->mapbase;
536                 break;
537
538         default:
539                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
540                 cardhu_uart_devices[0] = &debug_uarta_device;
541                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
542                 debug_uart_port_base = ((struct plat_serial8250_port *)(
543                         debug_uarta_device.dev.platform_data))->mapbase;
544                 break;
545         }
546         return;
547 }
548
549 static void __init cardhu_uart_init(void)
550 {
551         struct clk *c;
552         int i;
553
554         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
555                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
556                 if (IS_ERR_OR_NULL(c)) {
557                         pr_err("Not able to get the clock for %s\n",
558                                                 uart_parent_clk[i].name);
559                         continue;
560                 }
561                 uart_parent_clk[i].parent_clk = c;
562                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
563         }
564         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
565         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
566         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
567         cardhu_loopback_uart_pdata.parent_clk_count =
568                                                 ARRAY_SIZE(uart_parent_clk);
569         cardhu_loopback_uart_pdata.is_loopback = true;
570         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
571         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
572         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
573         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
574         /* UARTE is used for loopback test purpose */
575         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
576
577         /* Register low speed only if it is selected */
578         if (!is_tegra_debug_uartport_hs()) {
579                 uart_debug_init();
580                 /* Clock enable for the debug channel */
581                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
582                         pr_info("The debug console clock name is %s\n",
583                                                 debug_uart_clk->name);
584                         c = tegra_get_clock_by_name("pll_p");
585                         if (IS_ERR_OR_NULL(c))
586                                 pr_err("Not getting the parent clock pll_p\n");
587                         else
588                                 clk_set_parent(debug_uart_clk, c);
589
590                         clk_enable(debug_uart_clk);
591                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
592                 } else {
593                         pr_err("Not getting the clock %s for debug console\n",
594                                         debug_uart_clk->name);
595                 }
596         }
597
598         platform_add_devices(cardhu_uart_devices,
599                                 ARRAY_SIZE(cardhu_uart_devices));
600 }
601
602 static struct platform_device tegra_camera = {
603         .name = "tegra_camera",
604         .id = -1,
605 };
606
607 static struct platform_device *cardhu_spi_devices[] __initdata = {
608         &tegra_spi_device4,
609 };
610
611 static struct platform_device *touch_spi_device[] __initdata = {
612         &tegra_spi_device1,
613 };
614
615 struct spi_clk_parent spi_parent_clk[] = {
616         [0] = {.name = "pll_p"},
617 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
618         [1] = {.name = "pll_m"},
619         [2] = {.name = "clk_m"},
620 #else
621         [1] = {.name = "clk_m"},
622 #endif
623 };
624
625 static struct tegra_spi_platform_data cardhu_spi_pdata = {
626         .is_dma_based           = true,
627         .max_dma_buffer         = (16 * 1024),
628         .is_clkon_always        = false,
629         .max_rate               = 100000000,
630 };
631
632 static void __init cardhu_spi_init(void)
633 {
634         int i;
635         struct clk *c;
636         struct board_info board_info, display_board_info;
637
638         tegra_get_board_info(&board_info);
639         tegra_get_display_board_info(&display_board_info);
640
641         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
642                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
643                 if (IS_ERR_OR_NULL(c)) {
644                         pr_err("Not able to get the clock for %s\n",
645                                                 spi_parent_clk[i].name);
646                         continue;
647                 }
648                 spi_parent_clk[i].parent_clk = c;
649                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
650         }
651         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
652         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
653         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
654         platform_add_devices(cardhu_spi_devices,
655                                 ARRAY_SIZE(cardhu_spi_devices));
656
657         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
658                 platform_add_devices(touch_spi_device,
659                                 ARRAY_SIZE(touch_spi_device));
660         }
661         if (board_info.board_id == BOARD_E1198) {
662                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
663                 platform_device_register(&tegra_spi_device2);
664                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
665                 platform_device_register(&tegra_spi_slave_device1);
666         }
667 }
668
669 static void __init cardhu_dtv_init(void)
670 {
671         struct board_info board_info;
672
673         tegra_get_board_info(&board_info);
674
675         if (board_info.board_id == BOARD_E1186)
676                 platform_device_register(&tegra_dtv_device);
677 }
678
679 static struct resource tegra_rtc_resources[] = {
680         [0] = {
681                 .start = TEGRA_RTC_BASE,
682                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
683                 .flags = IORESOURCE_MEM,
684         },
685         [1] = {
686                 .start = INT_RTC,
687                 .end = INT_RTC,
688                 .flags = IORESOURCE_IRQ,
689         },
690 };
691
692 static struct platform_device tegra_rtc_device = {
693         .name = "tegra_rtc",
694         .id   = -1,
695         .resource = tegra_rtc_resources,
696         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
697 };
698
699 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
700         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
701         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
702         .gpio_hp_mute           = -1,
703         .gpio_int_mic_en        = -1,
704         .gpio_ext_mic_en        = -1,
705 };
706
707 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
708         .gpio_spkr_en           = -1,
709         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
710         .gpio_hp_mute           = -1,
711         .gpio_int_mic_en        = -1,
712         .gpio_ext_mic_en        = -1,
713 };
714
715 static struct platform_device cardhu_audio_wm8903_device = {
716         .name   = "tegra-snd-wm8903",
717         .id     = 0,
718         .dev    = {
719                 .platform_data = &cardhu_audio_wm8903_pdata,
720         },
721 };
722
723 static struct platform_device cardhu_audio_max98095_device = {
724         .name   = "tegra-snd-max98095",
725         .id     = 0,
726         .dev    = {
727                 .platform_data = &cardhu_audio_max98095_pdata,
728         },
729 };
730
731 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
732         .gpio_spkr_en           = -1,
733         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
734         .gpio_hp_mute           = -1,
735         .gpio_int_mic_en        = -1,
736         .gpio_ext_mic_en        = -1,
737         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
738         .audio_port_id          = {
739                 [HIFI_CODEC] = 0,
740                 [BASEBAND] = -1,
741                 [BT_SCO] = 3,
742         },
743         .baseband_param         = {
744                 .rate = -1,
745                 .channels = -1,
746         },
747 };
748
749 static struct platform_device cardhu_audio_aic326x_device = {
750         .name   = "tegra-snd-aic326x",
751         .id     = 0,
752         .dev    = {
753                 .platform_data  = &cardhu_audio_aic326x_pdata,
754         },
755 };
756
757 static struct platform_device *cardhu_devices[] __initdata = {
758         &tegra_pmu_device,
759         &tegra_rtc_device,
760         &tegra_udc_device,
761 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
762         &tegra_smmu_device,
763 #endif
764         &tegra_wdt_device,
765 #if defined(CONFIG_TEGRA_AVP)
766         &tegra_avp_device,
767 #endif
768         &tegra_camera,
769 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
770         &tegra_se_device,
771 #endif
772         &tegra_ahub_device,
773         &tegra_dam_device0,
774         &tegra_dam_device1,
775         &tegra_dam_device2,
776         &tegra_i2s_device0,
777         &tegra_i2s_device1,
778         &tegra_i2s_device3,
779         &tegra_spdif_device,
780         &spdif_dit_device,
781         &bluetooth_dit_device,
782         &baseband_dit_device,
783         &cardhu_bt_rfkill_device,
784         &tegra_pcm_device,
785         &cardhu_audio_wm8903_device,
786         &cardhu_audio_max98095_device,
787         &cardhu_audio_aic326x_device,
788         &tegra_hda_device,
789 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
790         &tegra_aes_device,
791 #endif
792 };
793
794 #define E1506_MXT_CONFIG_CRC 0x62F903
795 static const u8 e1506_config[] = {
796         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
797         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
798         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
799         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
800         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
801         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
802         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
803         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
804         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
806         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
808         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
809         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
810         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
811         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
812         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
813         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
814         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
815         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
817         0x00
818 };
819
820 #define MXT_CONFIG_CRC  0xD62DE8
821 static const u8 config[] = {
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
824         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
825         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
826         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
827         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
828         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
829         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
830         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
832         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
833         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
834         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
835         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
836         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
837         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
838         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
839         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
842 };
843
844 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
845 static const u8 config_sku2000[] = {
846         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
847         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
848         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
849         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
850         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
851         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
852         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
853         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
854         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
855         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
856         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
857         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
858         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
859         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
860         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
861         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
862         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
863         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
866 };
867
868 static struct mxt_platform_data atmel_mxt_info = {
869         .x_line         = 27,
870         .y_line         = 42,
871         .x_size         = 768,
872         .y_size         = 1366,
873         .blen           = 0x20,
874         .threshold      = 0x3C,
875         .voltage        = 3300000,              /* 3.3V */
876         .orient         = 5,
877         .config         = config,
878         .config_length  = 157,
879         .config_crc     = MXT_CONFIG_CRC,
880         .irqflags       = IRQF_TRIGGER_FALLING,
881 /*      .read_chg       = &read_chg, */
882         .read_chg       = NULL,
883 };
884
885 static struct mxt_platform_data e1506_atmel_mxt_info = {
886         .x_line         = 19,
887         .y_line         = 11,
888         .x_size         = 960,
889         .y_size         = 540,
890         .blen           = 0x10,
891         .threshold      = 0x32,
892         .voltage        = 3300000,              /* 3.3V */
893         .orient         = 3,
894         .config         = e1506_config,
895         .config_length  = 168,
896         .config_crc     = E1506_MXT_CONFIG_CRC,
897         .irqflags       = IRQF_TRIGGER_FALLING,
898 /*      .read_chg       = &read_chg, */
899         .read_chg       = NULL,
900 };
901
902 static struct i2c_board_info __initdata atmel_i2c_info[] = {
903         {
904                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
905                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
906                 .platform_data = &atmel_mxt_info,
907         }
908 };
909
910 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
911         {
912                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
913                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
914                 .platform_data = &e1506_atmel_mxt_info,
915         }
916 };
917
918 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
919         /* name         parent          rate            enabled */
920         { "sbc1",       "pll_p",        52000000,       true},
921         { NULL,         NULL,           0,              0},
922 };
923
924 static int __init cardhu_touch_init(void)
925 {
926         struct board_info BoardInfo, DisplayBoardInfo;
927
928         tegra_get_board_info(&BoardInfo);
929         tegra_get_display_board_info(&DisplayBoardInfo);
930         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
931                 tegra_clk_init_from_table(spi_clk_init_table);
932
933                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
934         } else {
935                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
936                 gpio_direction_input(TEGRA_GPIO_PH4);
937
938                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
939                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
940                 msleep(1);
941                 gpio_set_value(TEGRA_GPIO_PH6, 1);
942                 msleep(100);
943
944                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
945                         atmel_mxt_info.config = config_sku2000;
946                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
947                 }
948
949                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506)
950                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
951                 else
952                         i2c_register_board_info(1, atmel_i2c_info, 1);
953         }
954
955         return 0;
956 }
957
958 #if defined(CONFIG_USB_SUPPORT)
959
960 static void cardu_usb_hsic_postsupend(void)
961 {
962 #ifdef CONFIG_TEGRA_BB_XMM_POWER
963         baseband_xmm_set_power_status(BBXMM_PS_L2);
964 #endif
965 }
966
967 static void cardu_usb_hsic_preresume(void)
968 {
969 #ifdef CONFIG_TEGRA_BB_XMM_POWER
970         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
971 #endif
972 }
973
974 static void cardu_usb_hsic_phy_ready(void)
975 {
976 #ifdef CONFIG_TEGRA_BB_XMM_POWER
977         baseband_xmm_set_power_status(BBXMM_PS_L0);
978 #endif
979 }
980
981 static void cardu_usb_hsic_phy_off(void)
982 {
983 #ifdef CONFIG_TEGRA_BB_XMM_POWER
984         baseband_xmm_set_power_status(BBXMM_PS_L3);
985 #endif
986 }
987
988 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
989         .post_suspend = cardu_usb_hsic_postsupend,
990         .pre_resume = cardu_usb_hsic_preresume,
991         .port_power = cardu_usb_hsic_phy_ready,
992         .post_phy_off = cardu_usb_hsic_phy_off,
993 };
994
995 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
996         .port_otg = false,
997         .has_hostpc = true,
998         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
999         .op_mode        = TEGRA_USB_OPMODE_HOST,
1000         .u_data.host = {
1001                 .vbus_gpio = -1,
1002                 .hot_plug = false,
1003                 .remote_wakeup_supported = false,
1004                 .power_off_on_suspend = false,
1005         },
1006         .u_cfg.hsic = {
1007                 .sync_start_delay = 9,
1008                 .idle_wait_delay = 17,
1009                 .term_range_adj = 0,
1010                 .elastic_underrun_limit = 16,
1011                 .elastic_overrun_limit = 16,
1012         },
1013         .ops = &hsic_xmm_plat_ops,
1014 };
1015 #endif
1016
1017 static int hsic_enable_gpio = -1;
1018 static int hsic_reset_gpio = -1;
1019
1020 void hsic_platform_open(void)
1021 {
1022         int reset_gpio = 0, enable_gpio = 0;
1023
1024         if (hsic_enable_gpio != -1)
1025                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1026         if (hsic_reset_gpio != -1)
1027                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1028         /* hsic enable signal deasserted, hsic reset asserted */
1029         if (!enable_gpio)
1030                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1031         if (!reset_gpio)
1032                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1033         if (!enable_gpio)
1034                 tegra_gpio_enable(hsic_enable_gpio);
1035         if (!reset_gpio)
1036                 tegra_gpio_enable(hsic_reset_gpio);
1037         /* keep hsic reset asserted for 1 ms */
1038         udelay(1000);
1039         /* enable (power on) hsic */
1040         if (!enable_gpio)
1041                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1042         udelay(1000);
1043         /* deassert reset */
1044         if (!reset_gpio)
1045                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1046
1047 }
1048
1049 void hsic_platform_close(void)
1050 {
1051         if (hsic_enable_gpio != -1) {
1052                 gpio_set_value(hsic_enable_gpio, 0);
1053                 gpio_free(hsic_enable_gpio);
1054         }
1055         if (hsic_reset_gpio != -1) {
1056                 gpio_set_value(hsic_reset_gpio, 0);
1057                 gpio_free(hsic_reset_gpio);
1058         }
1059 }
1060
1061 void hsic_power_on(void)
1062 {
1063         if (hsic_enable_gpio != -1) {
1064                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1065                 udelay(1000);
1066         }
1067 }
1068
1069 void hsic_power_off(void)
1070 {
1071         if (hsic_enable_gpio != -1) {
1072                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1073                 udelay(1000);
1074         }
1075 }
1076
1077 #if defined(CONFIG_USB_SUPPORT)
1078 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1079         .open = hsic_platform_open,
1080         .close = hsic_platform_close,
1081         .pre_phy_on = hsic_power_on,
1082         .post_phy_off = hsic_power_off,
1083 };
1084
1085 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1086         .port_otg = false,
1087         .has_hostpc = true,
1088         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1089         .op_mode        = TEGRA_USB_OPMODE_HOST,
1090         .u_data.host = {
1091                 .vbus_gpio = -1,
1092                 .hot_plug = false,
1093                 .remote_wakeup_supported = false,
1094                 .power_off_on_suspend = false,
1095         },
1096         .u_cfg.hsic = {
1097                 .sync_start_delay = 9,
1098                 .idle_wait_delay = 17,
1099                 .term_range_adj = 0,
1100                 .elastic_underrun_limit = 16,
1101                 .elastic_overrun_limit = 16,
1102         },
1103         .ops = &hsic_plat_ops,
1104 };
1105
1106 static struct tegra_usb_platform_data tegra_udc_pdata = {
1107         .port_otg = true,
1108         .has_hostpc = true,
1109         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1110         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1111         .u_data.dev = {
1112                 .vbus_pmu_irq = 0,
1113                 .vbus_gpio = -1,
1114                 .charging_supported = false,
1115                 .remote_wakeup_supported = false,
1116         },
1117         .u_cfg.utmi = {
1118                 .hssync_start_delay = 0,
1119                 .elastic_limit = 16,
1120                 .idle_wait_delay = 17,
1121                 .term_range_adj = 6,
1122                 .xcvr_setup = 8,
1123                 .xcvr_lsfslew = 2,
1124                 .xcvr_lsrslew = 2,
1125                 .xcvr_setup_offset = 0,
1126                 .xcvr_use_fuses = 1,
1127         },
1128 };
1129
1130 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1131         .port_otg = false,
1132         .has_hostpc = true,
1133         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1134         .op_mode        = TEGRA_USB_OPMODE_HOST,
1135         .u_data.host = {
1136                 .vbus_gpio = -1,
1137                 .hot_plug = false,
1138                 .remote_wakeup_supported = true,
1139                 .power_off_on_suspend = true,
1140         },
1141         .u_cfg.utmi = {
1142                 .hssync_start_delay = 0,
1143                 .elastic_limit = 16,
1144                 .idle_wait_delay = 17,
1145                 .term_range_adj = 6,
1146                 .xcvr_setup = 15,
1147                 .xcvr_lsfslew = 2,
1148                 .xcvr_lsrslew = 2,
1149                 .xcvr_setup_offset = 0,
1150                 .xcvr_use_fuses = 1,
1151         },
1152 };
1153
1154 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1155         .port_otg = false,
1156         .has_hostpc = true,
1157         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1158         .op_mode = TEGRA_USB_OPMODE_HOST,
1159         .u_data.host = {
1160                 .vbus_gpio = -1,
1161                 .vbus_reg = "vdd_vbus_typea_usb",
1162                 .hot_plug = true,
1163                 .remote_wakeup_supported = true,
1164                 .power_off_on_suspend = true,
1165         },
1166         .u_cfg.utmi = {
1167                 .hssync_start_delay = 0,
1168                 .elastic_limit = 16,
1169                 .idle_wait_delay = 17,
1170                 .term_range_adj = 6,
1171                 .xcvr_setup = 8,
1172                 .xcvr_lsfslew = 2,
1173                 .xcvr_lsrslew = 2,
1174                 .xcvr_setup_offset = 0,
1175                 .xcvr_use_fuses = 1,
1176         },
1177 };
1178
1179 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1180         .port_otg = true,
1181         .has_hostpc = true,
1182         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1183         .op_mode = TEGRA_USB_OPMODE_HOST,
1184         .u_data.host = {
1185                 .vbus_gpio = -1,
1186                 .vbus_reg = "vdd_vbus_micro_usb",
1187                 .hot_plug = true,
1188                 .remote_wakeup_supported = true,
1189                 .power_off_on_suspend = true,
1190         },
1191         .u_cfg.utmi = {
1192                 .hssync_start_delay = 0,
1193                 .elastic_limit = 16,
1194                 .idle_wait_delay = 17,
1195                 .term_range_adj = 6,
1196                 .xcvr_setup = 15,
1197                 .xcvr_lsfslew = 2,
1198                 .xcvr_lsrslew = 2,
1199                 .xcvr_setup_offset = 0,
1200                 .xcvr_use_fuses = 1,
1201         },
1202 };
1203
1204 static struct tegra_usb_otg_data tegra_otg_pdata = {
1205         .ehci_device = &tegra_ehci1_device,
1206         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1207 };
1208 #endif
1209
1210 #if defined(CONFIG_USB_SUPPORT)
1211 static void cardhu_usb_init(void)
1212 {
1213         struct board_info bi;
1214
1215         tegra_get_board_info(&bi);
1216
1217         /* OTG should be the first to be registered */
1218         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1219         platform_device_register(&tegra_otg_device);
1220
1221         /* setup the udc platform data */
1222         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1223
1224         if (bi.board_id == BOARD_PM267) {
1225                 hsic_enable_gpio = EN_HSIC_GPIO;
1226                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1227                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1228                 platform_device_register(&tegra_ehci2_device);
1229         } else if (bi.board_id == BOARD_E1256) {
1230                 hsic_enable_gpio = EN_HSIC_GPIO;
1231                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1232                 platform_device_register(&tegra_ehci2_device);
1233         } else if (bi.board_id == BOARD_E1186) {
1234                 tegra_ehci2_device.dev.platform_data =
1235                                                 &tegra_ehci2_hsic_xmm_pdata;
1236                 /* ehci2 registration happens in baseband-xmm-power  */
1237         } else {
1238                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1239                 platform_device_register(&tegra_ehci2_device);
1240         }
1241
1242         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1243         platform_device_register(&tegra_ehci3_device);
1244
1245 }
1246 #else
1247 static void cardhu_usb_init(void) { }
1248 #endif
1249
1250 static struct baseband_power_platform_data tegra_baseband_power_data = {
1251         .baseband_type = BASEBAND_XMM,
1252         .modem = {
1253         .xmm = {
1254                         .bb_rst = XMM_GPIO_BB_RST,
1255                         .bb_on = XMM_GPIO_BB_ON,
1256                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1257                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1258                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1259                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1260                         .hsic_device = &tegra_ehci2_device,
1261                 },
1262         },
1263 };
1264
1265 static struct platform_device tegra_baseband_power_device = {
1266         .name = "baseband_xmm_power",
1267         .id = -1,
1268         .dev = {
1269                 .platform_data = &tegra_baseband_power_data,
1270         },
1271 };
1272
1273 static struct platform_device tegra_baseband_power2_device = {
1274         .name = "baseband_xmm_power2",
1275         .id = -1,
1276         .dev = {
1277                 .platform_data = &tegra_baseband_power_data,
1278         },
1279 };
1280
1281
1282 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1283         .port_status[0] = 1,
1284         .port_status[1] = 1,
1285         .port_status[2] = 1,
1286         .use_dock_detect        = 0,
1287         .gpio           = 0,
1288 };
1289
1290 static void cardhu_pci_init(void)
1291 {
1292         struct board_info board_info;
1293
1294         tegra_get_board_info(&board_info);
1295         if (board_info.board_id == BOARD_E1291) {
1296                 cardhu_pci_platform_data.port_status[0] = 0;
1297                 cardhu_pci_platform_data.port_status[1] = 0;
1298                 cardhu_pci_platform_data.port_status[2] = 1;
1299                 cardhu_pci_platform_data.use_dock_detect = 1;
1300                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1301         }
1302         if ((board_info.board_id == BOARD_E1186) ||
1303                 (board_info.board_id == BOARD_E1187) ||
1304                 (board_info.board_id == BOARD_E1291)) {
1305                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1306                 platform_device_register(&tegra_pci_device);
1307         }
1308 }
1309
1310 static void cardhu_modem_init(void)
1311 {
1312         struct board_info board_info;
1313         int w_disable_gpio, ret;
1314
1315         tegra_get_board_info(&board_info);
1316         switch (board_info.board_id) {
1317         case BOARD_E1291:
1318         case BOARD_E1198:
1319                 if (((board_info.board_id == BOARD_E1291) &&
1320                                 (board_info.fab < BOARD_FAB_A03)) ||
1321                         ((board_info.board_id == BOARD_E1198) &&
1322                                         (board_info.fab < BOARD_FAB_A02))) {
1323                         w_disable_gpio = TEGRA_GPIO_PH5;
1324                 } else {
1325                         w_disable_gpio = TEGRA_GPIO_PDD5;
1326                 }
1327
1328                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1329                 if (ret < 0)
1330                         pr_err("%s: gpio_request failed for gpio %d\n",
1331                                 __func__, w_disable_gpio);
1332                 else
1333                         gpio_direction_input(w_disable_gpio);
1334
1335                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1336                 if (((board_info.board_id == BOARD_E1291) &&
1337                                 (board_info.fab >= BOARD_FAB_A04)) ||
1338                         ((board_info.board_id == BOARD_E1198) &&
1339                                         (board_info.fab >= BOARD_FAB_A02))) {
1340                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1341                         if (ret < 0) {
1342                                 pr_err("%s(): Error in allocating gpio "
1343                                         "TEGRA_GPIO_PH7\n", __func__);
1344                                 break;
1345                         }
1346                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1347                 }
1348                 break;
1349         case BOARD_E1186:
1350                 platform_device_register(&tegra_baseband_power_device);
1351                 platform_device_register(&tegra_baseband_power2_device);
1352                 break;
1353         default:
1354                 break;
1355         }
1356
1357 }
1358
1359 #ifdef CONFIG_SATA_AHCI_TEGRA
1360 static void cardhu_sata_init(void)
1361 {
1362         platform_device_register(&tegra_sata_device);
1363 }
1364 #else
1365 static void cardhu_sata_init(void) { }
1366 #endif
1367
1368 static void __init tegra_cardhu_init(void)
1369 {
1370         tegra_thermal_init(&thermal_data,
1371                                 throttle_list,
1372                                 ARRAY_SIZE(throttle_list));
1373         tegra_clk_init_from_table(cardhu_clk_init_table);
1374         cardhu_pinmux_init();
1375         cardhu_i2c_init();
1376         cardhu_spi_init();
1377         cardhu_usb_init();
1378 #ifdef CONFIG_TEGRA_EDP_LIMITS
1379         cardhu_edp_init();
1380 #endif
1381         cardhu_uart_init();
1382         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1383         tegra_ram_console_debug_init();
1384         cardhu_sdhci_init();
1385         cardhu_regulator_init();
1386         cardhu_dtv_init();
1387         cardhu_suspend_init();
1388         cardhu_touch_init();
1389         cardhu_modem_init();
1390         cardhu_kbc_init();
1391         cardhu_scroll_init();
1392         cardhu_keys_init();
1393         cardhu_panel_init();
1394         cardhu_pmon_init();
1395         cardhu_sensors_init();
1396         cardhu_setup_bluesleep();
1397         cardhu_sata_init();
1398         //audio_wired_jack_init();
1399         cardhu_pins_state_init();
1400         cardhu_emc_init();
1401         tegra_release_bootloader_fb();
1402         cardhu_pci_init();
1403 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1404         tegra_wdt_recovery_init();
1405 #endif
1406 }
1407
1408 static void __init tegra_cardhu_reserve(void)
1409 {
1410 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1411         /* support 1920X1200 with 24bpp */
1412         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1413 #else
1414         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1415 #endif
1416         tegra_ram_console_debug_reserve(SZ_1M);
1417 }
1418
1419 MACHINE_START(CARDHU, "cardhu")
1420         .boot_params    = 0x80000100,
1421         .map_io         = tegra_map_common_io,
1422         .reserve        = tegra_cardhu_reserve,
1423         .init_early     = tegra_init_early,
1424         .init_irq       = tegra_init_irq,
1425         .timer          = &tegra_timer,
1426         .init_machine   = tegra_cardhu_init,
1427 MACHINE_END