ARM: Tegra: add support for persistent_ram
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43 #include <linux/of_platform.h>
44
45 #include <sound/wm8903.h>
46 #include <sound/max98095.h>
47 #include <media/tegra_dtv.h>
48
49 #include <asm/hardware/gic.h>
50
51 #include <mach/edp.h>
52 #include <mach/clk.h>
53 #include <mach/iomap.h>
54 #include <mach/irqs.h>
55 #include <mach/pinmux.h>
56 #include <mach/iomap.h>
57 #include <mach/io_dpd.h>
58 #include <mach/io.h>
59 #include <mach/i2s.h>
60 #include <mach/tegra_asoc_pdata.h>
61 #include <mach/tegra_wm8903_pdata.h>
62 #include <mach/usb_phy.h>
63 #include <mach/thermal.h>
64 #include <mach/pci.h>
65 #include <mach/gpio-tegra.h>
66 #include <mach/tegra_fiq_debugger.h>
67 #include <linux/thermal.h>
68
69 #include <asm/hardware/gic.h>
70 #include <asm/mach-types.h>
71 #include <asm/mach/arch.h>
72
73 #include "board.h"
74 #include "clock.h"
75 #include "board-cardhu.h"
76 #include "board-touch.h"
77 #include "devices.h"
78 #include "gpio-names.h"
79 #include "fuse.h"
80 #include "pm.h"
81 #include "baseband-xmm-power.h"
82 #include "wdt-recovery.h"
83 #include "common.h"
84
85 static struct balanced_throttle throttle_list[] = {
86         {
87                 .tegra_cdev = {
88                         .id = CDEV_BTHROT_ID_TJ,
89                 },
90                 .throt_tab_size = 10,
91                 .throt_tab = {
92                         {      0, 1000 },
93                         { 640000, 1000 },
94                         { 640000, 1000 },
95                         { 640000, 1000 },
96                         { 640000, 1000 },
97                         { 640000, 1000 },
98                         { 760000, 1000 },
99                         { 760000, 1050 },
100                         {1000000, 1050 },
101                         {1000000, 1100 },
102                 },
103         },
104 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
105         {
106                 .tegra_cdev = {
107                         .id = CDEV_BTHROT_ID_SKIN,
108                 },
109                 .throt_tab_size = 6,
110                 .throt_tab = {
111                         { 640000, 1200 },
112                         { 640000, 1200 },
113                         { 760000, 1200 },
114                         { 760000, 1200 },
115                         {1000000, 1200 },
116                         {1000000, 1200 },
117                 },
118         },
119 #endif
120 };
121
122 static struct tegra_thermal_bind thermal_binds[] = {
123         /* Thermal Throttling */
124         {
125                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
126                 .cdev_id = CDEV_BTHROT_ID_TJ,
127                 .type = THERMAL_TRIP_PASSIVE,
128                 .passive = {
129                         .trip_temp = 85000,
130                         .tc1 = 0,
131                         .tc2 = 1,
132                         .passive_delay = 2000,
133                 }
134         },
135         /* EDP Capping */
136         {
137                 .tdev_id = THERMAL_DEVICE_ID_NCT_EXT,
138                 .cdev_id = CDEV_EDPTABLE_ID_EDP,
139                 .type = THERMAL_TRIP_ACTIVE,
140                 .get_trip_temp = tegra_edp_get_trip_temp,
141                 .get_trip_size = tegra_edp_get_trip_size,
142         },
143 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
144         /* Skin Thermal Throttling */
145         {
146                 .tdev_id = THERMAL_DEVICE_ID_SKIN,
147                 .cdev_id = CDEV_BTHROT_ID_SKIN,
148                 .type = THERMAL_TRIP_PASSIVE,
149                 .passive = {
150                         .trip_temp = 43000,
151                         .tc1 = 10,
152                         .tc2 = 1,
153                         .passive_delay = 15000,
154                 }
155         },
156 #endif
157         {
158                 .tdev_id = THERMAL_DEVICE_ID_NULL,
159         },
160 };
161
162 static struct tegra_skin_data skin_data = {
163 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
164         .skin_device_id = THERMAL_DEVICE_ID_THERM_EST_SKIN,
165         .skin_temp_offset = 9793,
166         .skin_period = 1100,
167         .skin_devs_size = 2,
168         .skin_devs = {
169                 {
170                         THERMAL_DEVICE_ID_NCT_EXT,
171                         {
172                                 2, 1, 1, 1,
173                                 1, 1, 1, 1,
174                                 1, 1, 1, 0,
175                                 1, 1, 0, 0,
176                                 0, 0, -1, -7
177                         }
178                 },
179                 {
180                         THERMAL_DEVICE_ID_NCT_INT,
181                         {
182                                 -11, -7, -5, -3,
183                                 -3, -2, -1, 0,
184                                 0, 0, 1, 1,
185                                 1, 2, 2, 3,
186                                 4, 6, 11, 18
187                         }
188                 },
189         },
190 #else
191         .skin_device_id = THERMAL_DEVICE_ID_NULL,
192 #endif
193 };
194
195
196 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
197         {
198                 .name           = "bt_rfkill",
199                 .shutdown_gpio  = TEGRA_GPIO_PU0,
200                 .reset_gpio     = TEGRA_GPIO_INVALID,
201                 .type           = RFKILL_TYPE_BLUETOOTH,
202         },
203 };
204
205 static struct platform_device cardhu_bt_rfkill_device = {
206         .name = "rfkill_gpio",
207         .id             = -1,
208         .dev = {
209                 .platform_data = &cardhu_bt_rfkill_pdata,
210         },
211 };
212
213 static struct resource cardhu_bluesleep_resources[] = {
214         [0] = {
215                 .name = "gpio_host_wake",
216                         .start  = TEGRA_GPIO_PU6,
217                         .end    = TEGRA_GPIO_PU6,
218                         .flags  = IORESOURCE_IO,
219         },
220         [1] = {
221                 .name = "gpio_ext_wake",
222                         .start  = TEGRA_GPIO_PU1,
223                         .end    = TEGRA_GPIO_PU1,
224                         .flags  = IORESOURCE_IO,
225         },
226         [2] = {
227                 .name = "host_wake",
228                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
229         },
230 };
231
232 static struct platform_device cardhu_bluesleep_device = {
233         .name           = "bluesleep",
234         .id             = -1,
235         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
236         .resource       = cardhu_bluesleep_resources,
237 };
238
239 static noinline void __init cardhu_setup_bluesleep(void)
240 {
241         cardhu_bluesleep_resources[2].start =
242                 cardhu_bluesleep_resources[2].end =
243                         gpio_to_irq(TEGRA_GPIO_PU6);
244         platform_device_register(&cardhu_bluesleep_device);
245         return;
246 }
247
248 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
249         /* name         parent          rate            enabled */
250         { "pll_m",      NULL,           0,              false},
251         { "hda",        "pll_p",        108000000,      false},
252         { "hda2codec_2x","pll_p",       48000000,       false},
253         { "pwm",        "pll_p",        3187500,        false},
254         { "blink",      "clk_32k",      32768,          true},
255         { "i2s0",       "pll_a_out0",   0,              false},
256         { "i2s1",       "pll_a_out0",   0,              false},
257         { "i2s3",       "pll_a_out0",   0,              false},
258         { "spdif_out",  "pll_a_out0",   0,              false},
259         { "d_audio",    "clk_m",        12000000,       false},
260         { "dam0",       "clk_m",        12000000,       false},
261         { "dam1",       "clk_m",        12000000,       false},
262         { "dam2",       "clk_m",        12000000,       false},
263         { "audio1",     "i2s1_sync",    0,              false},
264         { "audio3",     "i2s3_sync",    0,              false},
265         { "vi_sensor",  "pll_p",        150000000,      false},
266         { "i2c1",       "pll_p",        3200000,        false},
267         { "i2c2",       "pll_p",        3200000,        false},
268         { "i2c3",       "pll_p",        3200000,        false},
269         { "i2c4",       "pll_p",        3200000,        false},
270         { "i2c5",       "pll_p",        3200000,        false},
271         { "vi",         "pll_p",        0,              false},
272         { NULL,         NULL,           0,              0},
273 };
274
275 static struct pn544_i2c_platform_data nfc_pdata = {
276         .irq_gpio = TEGRA_GPIO_PX0,
277         .ven_gpio = TEGRA_GPIO_PP3,
278         .firm_gpio = TEGRA_GPIO_PO7,
279         };
280
281 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
282         {
283                 I2C_BOARD_INFO("pn544", 0x28),
284                 .platform_data = &nfc_pdata,
285         },
286 };
287 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
288         .adapter_nr     = 0,
289         .bus_count      = 1,
290         .bus_clk_rate   = { 100000, 0 },
291         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
292         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
293         .arb_recovery = arb_lost_recovery,
294 };
295
296 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
297         .adapter_nr     = 1,
298         .bus_count      = 1,
299         .bus_clk_rate   = { 400000, 0 },
300         .is_clkon_always = true,
301         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
302         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
303         .arb_recovery = arb_lost_recovery,
304 };
305
306 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
307         .adapter_nr     = 2,
308         .bus_count      = 1,
309         .bus_clk_rate   = { 100000, 0 },
310         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
311         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
312         .arb_recovery = arb_lost_recovery,
313 };
314
315 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
316         .adapter_nr     = 3,
317         .bus_count      = 1,
318         .bus_clk_rate   = { 10000, 0 },
319         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
320         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
321         .arb_recovery = arb_lost_recovery,
322 };
323
324 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
325         .adapter_nr     = 4,
326         .bus_count      = 1,
327         .bus_clk_rate   = { 400000, 0 },
328         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
329         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
330         .arb_recovery = arb_lost_recovery,
331 };
332
333
334 #if 0
335 struct tegra_wired_jack_conf audio_wr_jack_conf = {
336         .hp_det_n = TEGRA_GPIO_PW2,
337         .en_mic_ext = TEGRA_GPIO_PX1,
338         .en_mic_int = TEGRA_GPIO_PX0,
339 };
340 #endif
341
342 static struct wm8903_platform_data cardhu_wm8903_pdata = {
343         .irq_active_low = 0,
344         .micdet_cfg = 0,
345         .micdet_delay = 100,
346         .gpio_base = CARDHU_GPIO_WM8903(0),
347         .gpio_cfg = {
348                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
349                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
350                         WM8903_GP2_DIR,
351                 WM8903_GPIO_CONFIG_ZERO,
352                 0,
353                 0,
354         },
355 };
356
357 /* Equalizer filter coefs generated from the MAXIM MAX98095
358  * evkit software tool */
359 static struct max98095_eq_cfg max98095_eq_cfg[] = {
360         {
361                 .name = "FLAT",
362                 .rate = 44100,
363                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
364                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
365                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
366                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
367                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
368         },
369         {
370                 .name = "LOWPASS1K",
371                 .rate = 44100,
372                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
373                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
374                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
375                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
376                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
377         },
378         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
379                 .name = "HIBOOST",
380                 .rate = 44100,
381                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
382                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
383                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
384                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
385                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
386         },
387         { /* BASS=12dB, TREBLE=+12dB */
388                 .name = "LOUD12DB",
389                 .rate = 44100,
390                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
391                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
392                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
393                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
394                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
395         },
396         {
397                 .name = "FLAT",
398                 .rate = 16000,
399                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
400                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
401                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
402                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
403                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
404         },
405         {
406                 .name = "LOWPASS1K",
407                 .rate = 16000,
408                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
409                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
410                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
411                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
412                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
413         },
414         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
415                 .name = "HIBOOST",
416                 .rate = 16000,
417                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
418                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
419                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
420                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
421                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
422         },
423         { /* BASS=12dB, TREBLE=+12dB */
424                 .name = "LOUD12DB",
425                 .rate = 16000,
426                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
427                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
428                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
429                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
430                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
431         },
432 };
433
434 static struct max98095_pdata cardhu_max98095_pdata = {
435         /* equalizer configuration */
436         .eq_cfg = max98095_eq_cfg,
437         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
438
439         /* Biquad filter response configuration */
440         .bq_cfg = NULL,
441         .bq_cfgcnt = 0,
442
443         /* microphone configuration */
444         .digmic_left_mode = 1,
445         .digmic_right_mode = 1,
446 };
447
448 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
449         I2C_BOARD_INFO("wm8903", 0x1a),
450         .platform_data = &cardhu_wm8903_pdata,
451 };
452
453 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
454         I2C_BOARD_INFO("aic3262-codec", 0x18),
455 };
456
457 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
458         I2C_BOARD_INFO("max98095", 0x10),
459         .platform_data = &cardhu_max98095_pdata,
460 };
461
462 static void cardhu_i2c_init(void)
463 {
464         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
465         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
466         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
467         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
468         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
469
470         platform_device_register(&tegra_i2c_device5);
471         platform_device_register(&tegra_i2c_device4);
472         platform_device_register(&tegra_i2c_device3);
473         platform_device_register(&tegra_i2c_device2);
474         platform_device_register(&tegra_i2c_device1);
475
476         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
477                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
478         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
479         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
480         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
481
482         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
483         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
484 }
485
486 static struct platform_device *cardhu_uart_devices[] __initdata = {
487         &tegra_uarta_device,
488         &tegra_uartb_device,
489         &tegra_uartc_device,
490         &tegra_uartd_device,
491         &tegra_uarte_device,
492 };
493 static struct uart_clk_parent uart_parent_clk[] = {
494         [0] = {.name = "clk_m"},
495         [1] = {.name = "pll_p"},
496 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
497         [2] = {.name = "pll_m"},
498 #endif
499 };
500
501 static struct tegra_uart_platform_data cardhu_uart_pdata;
502 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
503
504 static void __init uart_debug_init(void)
505 {
506         struct board_info board_info;
507         int debug_port_id;
508
509         tegra_get_board_info(&board_info);
510
511         debug_port_id = get_tegra_uart_debug_port_id();
512         if (debug_port_id < 0) {
513                 debug_port_id = 0;
514                         /* UARTB is debug port
515                          *       for SLT - E1186/E1187/PM269
516                          *       for E1256/E1257
517                          */
518                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
519                         ((board_info.board_id == BOARD_E1186) ||
520                         (board_info.board_id == BOARD_E1187) ||
521                         (board_info.board_id == BOARD_PM269))) ||
522                         (board_info.board_id == BOARD_E1256) ||
523                         (board_info.board_id == BOARD_E1257))
524                                 debug_port_id = 1;
525         }
526
527 #ifdef CONFIG_TEGRA_IRDA
528         if ((board_info.board_id == BOARD_E1186) ||
529                 (board_info.board_id == BOARD_E1198)) {
530                 if (debug_port_id == 1) {
531                         cardhu_irda_pdata.is_irda = false;
532                         pr_err("UARTB is not available for IrDA\n");
533                 }
534         }
535 #endif
536
537         switch (debug_port_id) {
538         case 0:
539                 /* UARTA is the debug port. */
540                 pr_info("Selecting UARTA as the debug console\n");
541                 cardhu_uart_devices[0] = &debug_uarta_device;
542                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
543                 debug_uart_port_base = ((struct plat_serial8250_port *)(
544                         debug_uarta_device.dev.platform_data))->mapbase;
545                 break;
546
547         case 1:
548                 /* UARTB is the debug port. */
549                 pr_info("Selecting UARTB as the debug console\n");
550                 cardhu_uart_devices[1] = &debug_uartb_device;
551                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
552                 debug_uart_port_base = ((struct plat_serial8250_port *)(
553                         debug_uartb_device.dev.platform_data))->mapbase;
554                 break;
555
556         case 2:
557                 /* UARTC is the debug port. */
558                 pr_info("Selecting UARTC as the debug console\n");
559                 cardhu_uart_devices[2] = &debug_uartc_device;
560                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
561                 debug_uart_port_base = ((struct plat_serial8250_port *)(
562                         debug_uartc_device.dev.platform_data))->mapbase;
563                 break;
564
565         case 3:
566                 /* UARTD is the debug port. */
567                 pr_info("Selecting UARTD as the debug console\n");
568                 cardhu_uart_devices[3] = &debug_uartd_device;
569                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
570                 debug_uart_port_base = ((struct plat_serial8250_port *)(
571                         debug_uartd_device.dev.platform_data))->mapbase;
572                 break;
573
574         case 4:
575                 /* UARTE is the debug port. */
576                 pr_info("Selecting UARTE as the debug console\n");
577                 cardhu_uart_devices[4] = &debug_uarte_device;
578                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
579                 debug_uart_port_base = ((struct plat_serial8250_port *)(
580                         debug_uarte_device.dev.platform_data))->mapbase;
581                 break;
582
583         default:
584                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
585                 cardhu_uart_devices[0] = &debug_uarta_device;
586                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
587                 debug_uart_port_base = ((struct plat_serial8250_port *)(
588                         debug_uarta_device.dev.platform_data))->mapbase;
589                 break;
590         }
591         return;
592 }
593
594 static void __init cardhu_uart_init(void)
595 {
596         struct clk *c;
597         int i;
598         struct board_info board_info;
599
600         tegra_get_board_info(&board_info);
601
602         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
603                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
604                 if (IS_ERR_OR_NULL(c)) {
605                         pr_err("Not able to get the clock for %s\n",
606                                                 uart_parent_clk[i].name);
607                         continue;
608                 }
609                 uart_parent_clk[i].parent_clk = c;
610                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
611         }
612         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
613         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
614         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
615         cardhu_loopback_uart_pdata.parent_clk_count =
616                                                 ARRAY_SIZE(uart_parent_clk);
617         cardhu_loopback_uart_pdata.is_loopback = true;
618         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
619         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
620         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
621         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
622         /* UARTE is used for loopback test purpose */
623         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
624
625         /* Register low speed only if it is selected */
626         if (!is_tegra_debug_uartport_hs()) {
627                 uart_debug_init();
628                 /* Clock enable for the debug channel */
629                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
630                         pr_info("The debug console clock name is %s\n",
631                                                 debug_uart_clk->name);
632                         c = tegra_get_clock_by_name("pll_p");
633                         if (IS_ERR_OR_NULL(c))
634                                 pr_err("Not getting the parent clock pll_p\n");
635                         else
636                                 clk_set_parent(debug_uart_clk, c);
637
638                         clk_enable(debug_uart_clk);
639                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
640                 } else {
641                         pr_err("Not getting the clock %s for debug console\n",
642                                         debug_uart_clk->name);
643                 }
644         }
645
646 #ifdef CONFIG_TEGRA_IRDA
647         if (((board_info.board_id == BOARD_E1186) ||
648                 (board_info.board_id == BOARD_E1198)) &&
649                         cardhu_irda_pdata.is_irda) {
650                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
651                 cardhu_irda_pdata.parent_clk_count =
652                                         ARRAY_SIZE(uart_parent_clk);
653
654                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
655         }
656 #endif
657
658         platform_add_devices(cardhu_uart_devices,
659                                 ARRAY_SIZE(cardhu_uart_devices));
660 }
661
662 static struct platform_device tegra_camera = {
663         .name = "tegra_camera",
664         .id = -1,
665 };
666
667 static struct platform_device *cardhu_spi_devices[] __initdata = {
668         &tegra_spi_device4,
669 };
670
671 static struct platform_device *touch_spi_device[] __initdata = {
672         &tegra_spi_device1,
673 };
674
675 struct spi_clk_parent spi_parent_clk[] = {
676         [0] = {.name = "pll_p"},
677 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
678         [1] = {.name = "pll_m"},
679         [2] = {.name = "clk_m"},
680 #else
681         [1] = {.name = "clk_m"},
682 #endif
683 };
684
685 static struct tegra_spi_platform_data cardhu_spi_pdata = {
686         .is_dma_based           = true,
687         .max_dma_buffer         = (16 * 1024),
688         .is_clkon_always        = false,
689         .max_rate               = 100000000,
690 };
691
692 static void __init cardhu_spi_init(void)
693 {
694         int i;
695         struct clk *c;
696         struct board_info board_info, display_board_info;
697
698         tegra_get_board_info(&board_info);
699         tegra_get_display_board_info(&display_board_info);
700
701         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
702                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
703                 if (IS_ERR_OR_NULL(c)) {
704                         pr_err("Not able to get the clock for %s\n",
705                                                 spi_parent_clk[i].name);
706                         continue;
707                 }
708                 spi_parent_clk[i].parent_clk = c;
709                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
710         }
711         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
712         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
713         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
714         platform_add_devices(cardhu_spi_devices,
715                                 ARRAY_SIZE(cardhu_spi_devices));
716
717         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
718                 platform_add_devices(touch_spi_device,
719                                 ARRAY_SIZE(touch_spi_device));
720         }
721         if (board_info.board_id == BOARD_E1198) {
722                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
723                 platform_device_register(&tegra_spi_device2);
724                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
725                 platform_device_register(&tegra_spi_slave_device1);
726         }
727 }
728
729 static void __init cardhu_dtv_init(void)
730 {
731         struct board_info board_info;
732
733         tegra_get_board_info(&board_info);
734
735         if (board_info.board_id == BOARD_E1186)
736                 platform_device_register(&tegra_dtv_device);
737 }
738
739 static struct resource tegra_rtc_resources[] = {
740         [0] = {
741                 .start = TEGRA_RTC_BASE,
742                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
743                 .flags = IORESOURCE_MEM,
744         },
745         [1] = {
746                 .start = INT_RTC,
747                 .end = INT_RTC,
748                 .flags = IORESOURCE_IRQ,
749         },
750 };
751
752 static struct platform_device tegra_rtc_device = {
753         .name = "tegra_rtc",
754         .id   = -1,
755         .resource = tegra_rtc_resources,
756         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
757 };
758
759 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
760         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
761         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
762         .gpio_hp_mute           = -1,
763         .gpio_int_mic_en        = -1,
764         .gpio_ext_mic_en        = -1,
765         .i2s_param[HIFI_CODEC]  = {
766                 .audio_port_id  = 0,
767                 .is_i2s_master  = 1,
768                 .i2s_mode       = TEGRA_DAIFMT_I2S,
769         },
770         .i2s_param[BASEBAND]    = {
771                 .audio_port_id  = -1,
772         },
773         .i2s_param[BT_SCO]      = {
774                 .audio_port_id  = 3,
775                 .is_i2s_master  = 1,
776                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
777         },
778 };
779
780 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
781         .gpio_spkr_en           = -1,
782         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
783         .gpio_hp_mute           = -1,
784         .gpio_int_mic_en        = -1,
785         .gpio_ext_mic_en        = -1,
786         .i2s_param[HIFI_CODEC]  = {
787                 .audio_port_id  = 0,
788                 .is_i2s_master  = 1,
789                 .i2s_mode       = TEGRA_DAIFMT_I2S,
790         },
791         .i2s_param[BASEBAND]    = {
792                 .audio_port_id  = -1,
793         },
794         .i2s_param[BT_SCO]      = {
795                 .audio_port_id  = 3,
796                 .is_i2s_master  = 1,
797                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
798         },
799 };
800
801 static struct platform_device cardhu_audio_wm8903_device = {
802         .name   = "tegra-snd-wm8903",
803         .id     = 0,
804         .dev    = {
805                 .platform_data = &cardhu_audio_wm8903_pdata,
806         },
807 };
808
809 static struct platform_device cardhu_audio_max98095_device = {
810         .name   = "tegra-snd-max98095",
811         .id     = 0,
812         .dev    = {
813                 .platform_data = &cardhu_audio_max98095_pdata,
814         },
815 };
816
817 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
818         .gpio_spkr_en           = -1,
819         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
820         .gpio_hp_mute           = -1,
821         .gpio_int_mic_en        = -1,
822         .gpio_ext_mic_en        = -1,
823         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
824         .i2s_param[HIFI_CODEC]  = {
825                 .audio_port_id  = 0,
826                 .is_i2s_master  = 1,
827                 .i2s_mode       = TEGRA_DAIFMT_I2S,
828                 .sample_size    = 16,
829         },
830         .i2s_param[BT_SCO]      = {
831                 .sample_size    = 16,
832                 .audio_port_id  = 3,
833                 .is_i2s_master  = 1,
834                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
835         },
836 };
837
838 static struct platform_device cardhu_audio_aic326x_device = {
839         .name   = "tegra-snd-aic326x",
840         .id     = 0,
841         .dev    = {
842                 .platform_data  = &cardhu_audio_aic326x_pdata,
843         },
844 };
845
846 static struct platform_device *cardhu_devices[] __initdata = {
847         &tegra_pmu_device,
848         &tegra_rtc_device,
849         &tegra_udc_device,
850         &tegra_wdt0_device,
851         &tegra_wdt1_device,
852         &tegra_wdt2_device,
853 #if defined(CONFIG_TEGRA_AVP)
854         &tegra_avp_device,
855 #endif
856         &tegra_camera,
857 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
858         &tegra_se_device,
859 #endif
860         &tegra_ahub_device,
861         &tegra_dam_device0,
862         &tegra_dam_device1,
863         &tegra_dam_device2,
864         &tegra_i2s_device0,
865         &tegra_i2s_device1,
866         &tegra_i2s_device3,
867         &tegra_spdif_device,
868         &spdif_dit_device,
869         &bluetooth_dit_device,
870         &baseband_dit_device,
871         &cardhu_bt_rfkill_device,
872         &tegra_pcm_device,
873         &cardhu_audio_wm8903_device,
874         &cardhu_audio_max98095_device,
875         &cardhu_audio_aic326x_device,
876         &tegra_hda_device,
877         &tegra_cec_device,
878 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
879         &tegra_aes_device,
880 #endif
881 };
882
883 #define E1506_MXT_CONFIG_CRC 0x62F903
884 static const u8 e1506_config[] = {
885         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
886         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
887         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
888         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
889         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
890         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
891         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
892         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
893         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
894         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
895         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
896         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
897         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
898         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
899         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
900         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
901         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
903         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
904         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
905         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
906         0x00
907 };
908
909 #define MXT_CONFIG_CRC  0xD62DE8
910 static const u8 config[] = {
911         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
912         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
913         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
914         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
915         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
916         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
917         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
918         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
919         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
920         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
921         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
922         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
923         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
924         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
925         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
926         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
927         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
928         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
929         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
930         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
931 };
932
933 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
934 static const u8 config_sku2000[] = {
935         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
936         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
937         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
938         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
939         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
940         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
941         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
942         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
943         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
944         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
945         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
946         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
947         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
948         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
949         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
950         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
951         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
952         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
953         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
954         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
955 };
956
957 static struct mxt_platform_data atmel_mxt_info = {
958         .x_line         = 27,
959         .y_line         = 42,
960         .x_size         = 768,
961         .y_size         = 1366,
962         .blen           = 0x20,
963         .threshold      = 0x3C,
964         .voltage        = 3300000,              /* 3.3V */
965         .orient         = 5,
966         .config         = config,
967         .config_length  = 157,
968         .config_crc     = MXT_CONFIG_CRC,
969         .irqflags       = IRQF_TRIGGER_FALLING,
970 /*      .read_chg       = &read_chg, */
971         .read_chg       = NULL,
972 };
973
974 static struct mxt_platform_data e1506_atmel_mxt_info = {
975         .x_line         = 19,
976         .y_line         = 11,
977         .x_size         = 960,
978         .y_size         = 540,
979         .blen           = 0x10,
980         .threshold      = 0x32,
981         .voltage        = 3300000,              /* 3.3V */
982         .orient         = 3,
983         .config         = e1506_config,
984         .config_length  = 168,
985         .config_crc     = E1506_MXT_CONFIG_CRC,
986         .irqflags       = IRQF_TRIGGER_FALLING,
987 /*      .read_chg       = &read_chg, */
988         .read_chg       = NULL,
989 };
990
991 static struct i2c_board_info __initdata atmel_i2c_info[] = {
992         {
993                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
994                 .platform_data = &atmel_mxt_info,
995         }
996 };
997
998 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
999         {
1000                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
1001                 .platform_data = &e1506_atmel_mxt_info,
1002         }
1003 };
1004
1005 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
1006         /* name         parent          rate            enabled */
1007         { "sbc1",       "pll_p",        52000000,       true},
1008         { NULL,         NULL,           0,              0},
1009 };
1010
1011 static int __init cardhu_touch_init(void)
1012 {
1013         struct board_info BoardInfo, DisplayBoardInfo;
1014
1015         tegra_get_board_info(&BoardInfo);
1016         tegra_get_display_board_info(&DisplayBoardInfo);
1017         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
1018                 tegra_clk_init_from_table(spi_clk_init_table);
1019
1020                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
1021         } else {
1022                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1023                 gpio_direction_input(TEGRA_GPIO_PH4);
1024
1025                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1026                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1027                 msleep(1);
1028                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1029                 msleep(100);
1030
1031                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1032                         atmel_mxt_info.config = config_sku2000;
1033                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1034                 }
1035
1036                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1037                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1038                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1039                 } else {
1040                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1041                         i2c_register_board_info(1, atmel_i2c_info, 1);
1042                 }
1043         }
1044
1045         return 0;
1046 }
1047
1048 #if defined(CONFIG_USB_SUPPORT)
1049
1050 static void cardu_usb_hsic_postsupend(void)
1051 {
1052 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1053         baseband_xmm_set_power_status(BBXMM_PS_L2);
1054 #endif
1055 }
1056
1057 static void cardu_usb_hsic_preresume(void)
1058 {
1059 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1060         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1061 #endif
1062 }
1063
1064 static void cardu_usb_hsic_phy_ready(void)
1065 {
1066 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1067         baseband_xmm_set_power_status(BBXMM_PS_L0);
1068 #endif
1069 }
1070
1071 static void cardu_usb_hsic_phy_off(void)
1072 {
1073 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1074         baseband_xmm_set_power_status(BBXMM_PS_L3);
1075 #endif
1076 }
1077
1078 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1079         .post_suspend = cardu_usb_hsic_postsupend,
1080         .pre_resume = cardu_usb_hsic_preresume,
1081         .port_power = cardu_usb_hsic_phy_ready,
1082         .post_phy_off = cardu_usb_hsic_phy_off,
1083 };
1084
1085 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1086         .port_otg = false,
1087         .has_hostpc = true,
1088         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1089         .op_mode        = TEGRA_USB_OPMODE_HOST,
1090         .u_data.host = {
1091                 .vbus_gpio = -1,
1092                 .hot_plug = false,
1093                 .remote_wakeup_supported = false,
1094                 .power_off_on_suspend = false,
1095         },
1096         .ops = &hsic_xmm_plat_ops,
1097 };
1098 #endif
1099
1100 static int hsic_enable_gpio = -1;
1101 static int hsic_reset_gpio = -1;
1102
1103 void hsic_platform_open(void)
1104 {
1105         int reset_gpio = 0, enable_gpio = 0;
1106
1107         if (hsic_enable_gpio != -1)
1108                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1109         if (hsic_reset_gpio != -1)
1110                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1111         /* hsic enable signal deasserted, hsic reset asserted */
1112         if (!enable_gpio)
1113                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1114         if (!reset_gpio)
1115                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1116         /* keep hsic reset asserted for 1 ms */
1117         udelay(1000);
1118         /* enable (power on) hsic */
1119         if (!enable_gpio)
1120                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1121         udelay(1000);
1122         /* deassert reset */
1123         if (!reset_gpio)
1124                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1125
1126 }
1127
1128 void hsic_platform_close(void)
1129 {
1130         if (hsic_enable_gpio != -1) {
1131                 gpio_set_value(hsic_enable_gpio, 0);
1132                 gpio_free(hsic_enable_gpio);
1133         }
1134         if (hsic_reset_gpio != -1) {
1135                 gpio_set_value(hsic_reset_gpio, 0);
1136                 gpio_free(hsic_reset_gpio);
1137         }
1138 }
1139
1140 void hsic_power_on(void)
1141 {
1142         if (hsic_enable_gpio != -1) {
1143                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1144                 udelay(1000);
1145         }
1146 }
1147
1148 void hsic_power_off(void)
1149 {
1150         if (hsic_enable_gpio != -1) {
1151                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1152                 udelay(1000);
1153         }
1154 }
1155
1156 #if defined(CONFIG_USB_SUPPORT)
1157 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1158         .open = hsic_platform_open,
1159         .close = hsic_platform_close,
1160         .pre_phy_on = hsic_power_on,
1161         .post_phy_off = hsic_power_off,
1162 };
1163
1164 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1165         .port_otg = false,
1166         .has_hostpc = true,
1167         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1168         .op_mode        = TEGRA_USB_OPMODE_HOST,
1169         .u_data.host = {
1170                 .vbus_gpio = -1,
1171                 .hot_plug = false,
1172                 .remote_wakeup_supported = false,
1173                 .power_off_on_suspend = false,
1174         },
1175         .ops = &hsic_plat_ops,
1176 };
1177
1178 static struct tegra_usb_platform_data tegra_udc_pdata = {
1179         .port_otg = true,
1180         .has_hostpc = true,
1181         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1182         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1183         .u_data.dev = {
1184                 .vbus_pmu_irq = 0,
1185                 .vbus_gpio = -1,
1186                 .charging_supported = false,
1187                 .remote_wakeup_supported = false,
1188         },
1189         .u_cfg.utmi = {
1190                 .hssync_start_delay = 0,
1191                 .elastic_limit = 16,
1192                 .idle_wait_delay = 17,
1193                 .term_range_adj = 6,
1194                 .xcvr_setup = 8,
1195                 .xcvr_lsfslew = 2,
1196                 .xcvr_lsrslew = 2,
1197                 .xcvr_setup_offset = 0,
1198                 .xcvr_use_fuses = 1,
1199         },
1200 };
1201
1202 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1203         .port_otg = false,
1204         .has_hostpc = true,
1205         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1206         .op_mode        = TEGRA_USB_OPMODE_HOST,
1207         .u_data.host = {
1208                 .vbus_gpio = -1,
1209                 .hot_plug = false,
1210                 .remote_wakeup_supported = true,
1211                 .power_off_on_suspend = true,
1212         },
1213         .u_cfg.utmi = {
1214                 .hssync_start_delay = 0,
1215                 .elastic_limit = 16,
1216                 .idle_wait_delay = 17,
1217                 .term_range_adj = 6,
1218                 .xcvr_setup = 15,
1219                 .xcvr_lsfslew = 2,
1220                 .xcvr_lsrslew = 2,
1221                 .xcvr_setup_offset = 0,
1222                 .xcvr_use_fuses = 1,
1223         },
1224 };
1225
1226 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1227         .port_otg = false,
1228         .has_hostpc = true,
1229         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1230         .op_mode = TEGRA_USB_OPMODE_HOST,
1231         .u_data.host = {
1232                 .vbus_gpio = -1,
1233                 .hot_plug = true,
1234                 .remote_wakeup_supported = true,
1235                 .power_off_on_suspend = true,
1236         },
1237         .u_cfg.utmi = {
1238                 .hssync_start_delay = 0,
1239                 .elastic_limit = 16,
1240                 .idle_wait_delay = 17,
1241                 .term_range_adj = 6,
1242                 .xcvr_setup = 8,
1243                 .xcvr_lsfslew = 2,
1244                 .xcvr_lsrslew = 2,
1245                 .xcvr_setup_offset = 0,
1246                 .xcvr_use_fuses = 1,
1247         },
1248 };
1249
1250 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1251         .port_otg = true,
1252         .has_hostpc = true,
1253         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1254         .op_mode = TEGRA_USB_OPMODE_HOST,
1255         .u_data.host = {
1256                 .vbus_gpio = -1,
1257                 .hot_plug = true,
1258                 .remote_wakeup_supported = true,
1259                 .power_off_on_suspend = true,
1260         },
1261         .u_cfg.utmi = {
1262                 .hssync_start_delay = 0,
1263                 .elastic_limit = 16,
1264                 .idle_wait_delay = 17,
1265                 .term_range_adj = 6,
1266                 .xcvr_setup = 15,
1267                 .xcvr_lsfslew = 2,
1268                 .xcvr_lsrslew = 2,
1269                 .xcvr_setup_offset = 0,
1270                 .xcvr_use_fuses = 1,
1271         },
1272 };
1273
1274 static struct tegra_usb_otg_data tegra_otg_pdata = {
1275         .ehci_device = &tegra_ehci1_device,
1276         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1277 };
1278 #endif
1279
1280 #if defined(CONFIG_USB_SUPPORT)
1281 static void cardhu_usb_init(void)
1282 {
1283         struct board_info bi;
1284
1285         tegra_get_board_info(&bi);
1286
1287         /* OTG should be the first to be registered */
1288         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1289         platform_device_register(&tegra_otg_device);
1290
1291         /* setup the udc platform data */
1292         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1293
1294         if (bi.board_id == BOARD_PM267) {
1295                 hsic_enable_gpio = EN_HSIC_GPIO;
1296                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1297                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1298                 platform_device_register(&tegra_ehci2_device);
1299         } else if (bi.board_id == BOARD_E1256) {
1300                 hsic_enable_gpio = EN_HSIC_GPIO;
1301                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1302                 platform_device_register(&tegra_ehci2_device);
1303         } else if (bi.board_id == BOARD_E1186) {
1304                 tegra_ehci2_device.dev.platform_data =
1305                                                 &tegra_ehci2_hsic_xmm_pdata;
1306                 /* ehci2 registration happens in baseband-xmm-power  */
1307         } else {
1308                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1309                 platform_device_register(&tegra_ehci2_device);
1310         }
1311
1312         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1313         platform_device_register(&tegra_ehci3_device);
1314
1315 }
1316 #else
1317 static void cardhu_usb_init(void) { }
1318 #endif
1319
1320 static struct baseband_power_platform_data tegra_baseband_power_data = {
1321         .baseband_type = BASEBAND_XMM,
1322         .modem = {
1323         .xmm = {
1324                         .bb_rst = XMM_GPIO_BB_RST,
1325                         .bb_on = XMM_GPIO_BB_ON,
1326                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1327                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1328                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1329                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1330                         .hsic_device = &tegra_ehci2_device,
1331                 },
1332         },
1333 };
1334
1335 static struct platform_device tegra_baseband_power_device = {
1336         .name = "baseband_xmm_power",
1337         .id = -1,
1338         .dev = {
1339                 .platform_data = &tegra_baseband_power_data,
1340         },
1341 };
1342
1343 static struct platform_device tegra_baseband_power2_device = {
1344         .name = "baseband_xmm_power2",
1345         .id = -1,
1346         .dev = {
1347                 .platform_data = &tegra_baseband_power_data,
1348         },
1349 };
1350
1351
1352 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1353         .port_status[0] = 1,
1354         .port_status[1] = 1,
1355         .port_status[2] = 1,
1356         .use_dock_detect        = 0,
1357         .gpio           = 0,
1358 };
1359
1360 static void cardhu_pci_init(void)
1361 {
1362         struct board_info board_info;
1363
1364         tegra_get_board_info(&board_info);
1365         if (board_info.board_id == BOARD_E1291) {
1366                 cardhu_pci_platform_data.port_status[0] = 0;
1367                 cardhu_pci_platform_data.port_status[1] = 0;
1368                 cardhu_pci_platform_data.port_status[2] = 1;
1369                 cardhu_pci_platform_data.use_dock_detect = 1;
1370                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1371         }
1372         if ((board_info.board_id == BOARD_E1186) ||
1373                 (board_info.board_id == BOARD_E1187) ||
1374                 (board_info.board_id == BOARD_E1291)) {
1375                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1376                 platform_device_register(&tegra_pci_device);
1377         }
1378 }
1379
1380 static void cardhu_modem_init(void)
1381 {
1382         struct board_info board_info;
1383         int w_disable_gpio, ret;
1384
1385         tegra_get_board_info(&board_info);
1386         switch (board_info.board_id) {
1387         case BOARD_E1291:
1388         case BOARD_E1198:
1389                 if (((board_info.board_id == BOARD_E1291) &&
1390                                 (board_info.fab < BOARD_FAB_A03)) ||
1391                         ((board_info.board_id == BOARD_E1198) &&
1392                                         (board_info.fab < BOARD_FAB_A02))) {
1393                         w_disable_gpio = TEGRA_GPIO_PH5;
1394                 } else {
1395                         w_disable_gpio = TEGRA_GPIO_PDD5;
1396                 }
1397
1398                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1399                 if (ret < 0)
1400                         pr_err("%s: gpio_request failed for gpio %d\n",
1401                                 __func__, w_disable_gpio);
1402                 else
1403                         gpio_direction_input(w_disable_gpio);
1404
1405                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1406                 if (((board_info.board_id == BOARD_E1291) &&
1407                                 (board_info.fab >= BOARD_FAB_A04)) ||
1408                         ((board_info.board_id == BOARD_E1198) &&
1409                                         (board_info.fab >= BOARD_FAB_A02))) {
1410                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1411                         if (ret < 0) {
1412                                 pr_err("%s(): Error in allocating gpio "
1413                                         "TEGRA_GPIO_PH7\n", __func__);
1414                                 break;
1415                         }
1416                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1417                 }
1418                 break;
1419         case BOARD_E1186:
1420                 platform_device_register(&tegra_baseband_power_device);
1421                 platform_device_register(&tegra_baseband_power2_device);
1422                 break;
1423         default:
1424                 break;
1425         }
1426
1427 }
1428
1429 #ifdef CONFIG_SATA_AHCI_TEGRA
1430 static void cardhu_sata_init(void)
1431 {
1432         platform_device_register(&tegra_sata_device);
1433 }
1434 #else
1435 static void cardhu_sata_init(void) { }
1436 #endif
1437
1438 static void __init tegra_cardhu_init(void)
1439 {
1440         tegra_thermal_init(thermal_binds,
1441                                 &skin_data,
1442                                 throttle_list,
1443                                 ARRAY_SIZE(throttle_list));
1444         tegra_clk_init_from_table(cardhu_clk_init_table);
1445         tegra_enable_pinmux();
1446         tegra_smmu_init();
1447         cardhu_pinmux_init();
1448         cardhu_i2c_init();
1449         cardhu_spi_init();
1450         cardhu_usb_init();
1451 #ifdef CONFIG_TEGRA_EDP_LIMITS
1452         cardhu_edp_init();
1453 #endif
1454         cardhu_uart_init();
1455         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1456         tegra_ram_console_debug_init();
1457         tegra_io_dpd_init();
1458         cardhu_sdhci_init();
1459         cardhu_regulator_init();
1460         cardhu_dtv_init();
1461         cardhu_suspend_init();
1462         cardhu_touch_init();
1463         cardhu_modem_init();
1464         cardhu_kbc_init();
1465         cardhu_scroll_init();
1466         cardhu_keys_init();
1467         cardhu_panel_init();
1468         cardhu_pmon_init();
1469         cardhu_sensors_init();
1470         cardhu_setup_bluesleep();
1471         cardhu_sata_init();
1472         cardhu_pins_state_init();
1473         cardhu_emc_init();
1474         tegra_release_bootloader_fb();
1475         cardhu_pci_init();
1476 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1477         tegra_wdt_recovery_init();
1478 #endif
1479         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1480 }
1481
1482 static void __init tegra_cardhu_dt_init(void)
1483 {
1484         tegra_cardhu_init();
1485
1486         of_platform_populate(NULL,
1487                 of_default_bus_match_table, NULL, NULL);
1488 }
1489
1490 static void __init tegra_cardhu_reserve(void)
1491 {
1492 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1493         /* support 1920X1200 with 24bpp */
1494         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1495 #else
1496         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1497 #endif
1498 }
1499
1500 static const char *cardhu_dt_board_compat[] = {
1501         "nvidia,cardhu",
1502         NULL
1503 };
1504
1505 MACHINE_START(CARDHU, "cardhu")
1506         .atag_offset    = 0x100,
1507         .soc            = &tegra_soc_desc,
1508         .map_io         = tegra_map_common_io,
1509         .reserve        = tegra_cardhu_reserve,
1510         .init_early     = tegra30_init_early,
1511         .init_irq       = tegra_init_irq,
1512         .handle_irq     = gic_handle_irq,
1513         .timer          = &tegra_timer,
1514         .init_machine   = tegra_cardhu_dt_init,
1515         .restart        = tegra_assert_system_reset,
1516         .dt_compat      = cardhu_dt_board_compat,
1517 MACHINE_END