fixup: gpio-tegra.h (board-cardhu.c)
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61 #include <mach/gpio-tegra.h>
62
63 #include "board.h"
64 #include "clock.h"
65 #include "board-cardhu.h"
66 #include "devices.h"
67 #include "gpio-names.h"
68 #include "fuse.h"
69 #include "pm.h"
70 #include "baseband-xmm-power.h"
71 #include "wdt-recovery.h"
72
73 /* All units are in millicelsius */
74 static struct tegra_thermal_data thermal_data = {
75         .temp_throttle = 85000,
76         .temp_shutdown = 90000,
77         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
78 #ifdef CONFIG_TEGRA_EDP_LIMITS
79         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
80         .hysteresis_edp = 3000,
81 #endif
82 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
83         .tc1 = 0,
84         .tc2 = 1,
85         .passive_delay = 2000,
86 #else
87         .hysteresis_throttle = 1000,
88 #endif
89 };
90
91 /* !!!TODO: Change for cardhu (Taken from Ventana) */
92 static struct tegra_utmip_config utmi_phy_config[] = {
93         [0] = {
94                         .hssync_start_delay = 0,
95                         .idle_wait_delay = 17,
96                         .elastic_limit = 16,
97                         .term_range_adj = 6,
98                         .xcvr_setup = 15,
99                         .xcvr_setup_offset = 0,
100                         .xcvr_use_fuses = 1,
101                         .xcvr_lsfslew = 2,
102                         .xcvr_lsrslew = 2,
103         },
104         [1] = {
105                         .hssync_start_delay = 0,
106                         .idle_wait_delay = 17,
107                         .elastic_limit = 16,
108                         .term_range_adj = 6,
109                         .xcvr_setup = 15,
110                         .xcvr_setup_offset = 0,
111                         .xcvr_use_fuses = 1,
112                         .xcvr_lsfslew = 2,
113                         .xcvr_lsrslew = 2,
114         },
115         [2] = {
116                         .hssync_start_delay = 0,
117                         .idle_wait_delay = 17,
118                         .elastic_limit = 16,
119                         .term_range_adj = 6,
120                         .xcvr_setup = 8,
121                         .xcvr_setup_offset = 0,
122                         .xcvr_use_fuses = 1,
123                         .xcvr_lsfslew = 2,
124                         .xcvr_lsrslew = 2,
125         },
126 };
127
128 static struct resource cardhu_bcm4329_rfkill_resources[] = {
129         {
130                 .name   = "bcm4329_nshutdown_gpio",
131                 .start  = TEGRA_GPIO_PU0,
132                 .end    = TEGRA_GPIO_PU0,
133                 .flags  = IORESOURCE_IO,
134         },
135 };
136
137 static struct platform_device cardhu_bcm4329_rfkill_device = {
138         .name = "bcm4329_rfkill",
139         .id             = -1,
140         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
141         .resource       = cardhu_bcm4329_rfkill_resources,
142 };
143
144 static struct resource cardhu_bluesleep_resources[] = {
145         [0] = {
146                 .name = "gpio_host_wake",
147                         .start  = TEGRA_GPIO_PU6,
148                         .end    = TEGRA_GPIO_PU6,
149                         .flags  = IORESOURCE_IO,
150         },
151         [1] = {
152                 .name = "gpio_ext_wake",
153                         .start  = TEGRA_GPIO_PU1,
154                         .end    = TEGRA_GPIO_PU1,
155                         .flags  = IORESOURCE_IO,
156         },
157         [2] = {
158                 .name = "host_wake",
159                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
160                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
161                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
162         },
163 };
164
165 static struct platform_device cardhu_bluesleep_device = {
166         .name           = "bluesleep",
167         .id             = -1,
168         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
169         .resource       = cardhu_bluesleep_resources,
170 };
171
172 static noinline void __init cardhu_setup_bluesleep(void)
173 {
174         platform_device_register(&cardhu_bluesleep_device);
175         tegra_gpio_enable(TEGRA_GPIO_PU6);
176         tegra_gpio_enable(TEGRA_GPIO_PU1);
177         return;
178 }
179
180 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
181         /* name         parent          rate            enabled */
182         { "pll_m",      NULL,           0,              false},
183         { "hda",        "pll_p",        108000000,      false},
184         { "hda2codec_2x","pll_p",       48000000,       false},
185         { "pwm",        "pll_p",        3187500,        false},
186         { "blink",      "clk_32k",      32768,          true},
187         { "i2s0",       "pll_a_out0",   0,              false},
188         { "i2s1",       "pll_a_out0",   0,              false},
189         { "i2s3",       "pll_a_out0",   0,              false},
190         { "spdif_out",  "pll_a_out0",   0,              false},
191         { "d_audio",    "clk_m",        12000000,       false},
192         { "dam0",       "clk_m",        12000000,       false},
193         { "dam1",       "clk_m",        12000000,       false},
194         { "dam2",       "clk_m",        12000000,       false},
195         { "audio1",     "i2s1_sync",    0,              false},
196         { "audio3",     "i2s3_sync",    0,              false},
197         { "vi_sensor",  "pll_p",        150000000,      false},
198         { "i2c1",       "pll_p",        3200000,        false},
199         { "i2c2",       "pll_p",        3200000,        false},
200         { "i2c3",       "pll_p",        3200000,        false},
201         { "i2c4",       "pll_p",        3200000,        false},
202         { "i2c5",       "pll_p",        3200000,        false},
203         { NULL,         NULL,           0,              0},
204 };
205
206 static struct pn544_i2c_platform_data nfc_pdata = {
207         .irq_gpio = TEGRA_GPIO_PX0,
208         .ven_gpio = TEGRA_GPIO_PP3,
209         .firm_gpio = TEGRA_GPIO_PO7,
210         };
211
212 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
213         {
214                 I2C_BOARD_INFO("pn544", 0x28),
215                 .platform_data = &nfc_pdata,
216                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
217         },
218 };
219 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
220         .adapter_nr     = 0,
221         .bus_count      = 1,
222         .bus_clk_rate   = { 100000, 0 },
223         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
224         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
225         .arb_recovery = arb_lost_recovery,
226 };
227
228 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
229         .adapter_nr     = 1,
230         .bus_count      = 1,
231         .bus_clk_rate   = { 100000, 0 },
232         .is_clkon_always = true,
233         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
234         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
235         .arb_recovery = arb_lost_recovery,
236 };
237
238 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
239         .adapter_nr     = 2,
240         .bus_count      = 1,
241         .bus_clk_rate   = { 100000, 0 },
242         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
243         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
244         .arb_recovery = arb_lost_recovery,
245 };
246
247 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
248         .adapter_nr     = 3,
249         .bus_count      = 1,
250         .bus_clk_rate   = { 100000, 0 },
251         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
252         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
253         .arb_recovery = arb_lost_recovery,
254 };
255
256 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
257         .adapter_nr     = 4,
258         .bus_count      = 1,
259         .bus_clk_rate   = { 400000, 0 },
260         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
261         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
262         .arb_recovery = arb_lost_recovery,
263 };
264
265
266 #if 0
267 struct tegra_wired_jack_conf audio_wr_jack_conf = {
268         .hp_det_n = TEGRA_GPIO_PW2,
269         .en_mic_ext = TEGRA_GPIO_PX1,
270         .en_mic_int = TEGRA_GPIO_PX0,
271 };
272 #endif
273
274 static struct wm8903_platform_data cardhu_wm8903_pdata = {
275         .irq_active_low = 0,
276         .micdet_cfg = 0,
277         .micdet_delay = 100,
278         .gpio_base = CARDHU_GPIO_WM8903(0),
279         .gpio_cfg = {
280                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
281                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
282                         WM8903_GP2_DIR,
283                 0,
284                 WM8903_GPIO_NO_CONFIG,
285                 WM8903_GPIO_NO_CONFIG,
286         },
287 };
288
289 /* Equalizer filter coefs generated from the MAXIM MAX98095
290  * evkit software tool */
291 static struct max98095_eq_cfg max98095_eq_cfg[] = {
292         {
293                 .name = "FLAT",
294                 .rate = 44100,
295                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
296                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
297                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
298                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
299                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
300         },
301         {
302                 .name = "LOWPASS1K",
303                 .rate = 44100,
304                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
305                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
306                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
307                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
308                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
309         },
310         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
311                 .name = "HIBOOST",
312                 .rate = 44100,
313                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
314                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
315                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
316                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
317                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
318         },
319         { /* BASS=12dB, TREBLE=+12dB */
320                 .name = "LOUD12DB",
321                 .rate = 44100,
322                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
323                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
324                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
325                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
326                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
327         },
328         {
329                 .name = "FLAT",
330                 .rate = 16000,
331                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
332                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
333                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
334                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
335                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
336         },
337         {
338                 .name = "LOWPASS1K",
339                 .rate = 16000,
340                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
341                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
342                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
343                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
344                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
345         },
346         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
347                 .name = "HIBOOST",
348                 .rate = 16000,
349                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
350                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
351                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
352                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
353                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
354         },
355         { /* BASS=12dB, TREBLE=+12dB */
356                 .name = "LOUD12DB",
357                 .rate = 16000,
358                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
359                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
360                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
361                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
362                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
363         },
364 };
365
366 static struct max98095_pdata cardhu_max98095_pdata = {
367         /* equalizer configuration */
368         .eq_cfg = max98095_eq_cfg,
369         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
370
371         /* Biquad filter response configuration */
372         .bq_cfg = NULL,
373         .bq_cfgcnt = 0,
374
375         /* microphone configuration */
376         .digmic_left_mode = 1,
377         .digmic_right_mode = 1,
378 };
379
380 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
381         I2C_BOARD_INFO("wm8903", 0x1a),
382         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
383         .platform_data = &cardhu_wm8903_pdata,
384 };
385
386 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
387         I2C_BOARD_INFO("aic3262-codec", 0x18),
388         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
389 };
390
391 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
392         I2C_BOARD_INFO("max98095", 0x10),
393         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
394         .platform_data = &cardhu_max98095_pdata,
395 };
396
397 static void cardhu_i2c_init(void)
398 {
399         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
400         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
401         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
402         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
403         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
404
405         platform_device_register(&tegra_i2c_device5);
406         platform_device_register(&tegra_i2c_device4);
407         platform_device_register(&tegra_i2c_device3);
408         platform_device_register(&tegra_i2c_device2);
409         platform_device_register(&tegra_i2c_device1);
410
411         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
412         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
413         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
414
415         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
416 }
417
418 static struct platform_device *cardhu_uart_devices[] __initdata = {
419         &tegra_uarta_device,
420         &tegra_uartb_device,
421         &tegra_uartc_device,
422         &tegra_uartd_device,
423         &tegra_uarte_device,
424 };
425 static struct uart_clk_parent uart_parent_clk[] = {
426         [0] = {.name = "clk_m"},
427         [1] = {.name = "pll_p"},
428 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
429         [2] = {.name = "pll_m"},
430 #endif
431 };
432
433 static struct tegra_uart_platform_data cardhu_uart_pdata;
434 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
435
436 static void __init uart_debug_init(void)
437 {
438         struct board_info board_info;
439         int debug_port_id;
440
441         tegra_get_board_info(&board_info);
442
443         debug_port_id = get_tegra_uart_debug_port_id();
444         if (debug_port_id < 0) {
445                 debug_port_id = 0;
446                         /* UARTB is debug port
447                          *       for SLT - E1186/E1187/PM269
448                          *       for E1256/E1257
449                          */
450                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
451                         ((board_info.board_id == BOARD_E1186) ||
452                         (board_info.board_id == BOARD_E1187) ||
453                         (board_info.board_id == BOARD_PM269))) ||
454                         (board_info.board_id == BOARD_E1256) ||
455                         (board_info.board_id == BOARD_E1257))
456                                 debug_port_id = 1;
457         }
458
459         switch (debug_port_id) {
460         case 0:
461                 /* UARTA is the debug port. */
462                 pr_info("Selecting UARTA as the debug console\n");
463                 cardhu_uart_devices[0] = &debug_uarta_device;
464                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
465                 debug_uart_port_base = ((struct plat_serial8250_port *)(
466                         debug_uarta_device.dev.platform_data))->mapbase;
467                 break;
468
469         case 1:
470                 /* UARTB is the debug port. */
471                 pr_info("Selecting UARTB as the debug console\n");
472                 cardhu_uart_devices[1] = &debug_uartb_device;
473                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
474                 debug_uart_port_base = ((struct plat_serial8250_port *)(
475                         debug_uartb_device.dev.platform_data))->mapbase;
476                 break;
477
478         case 2:
479                 /* UARTC is the debug port. */
480                 pr_info("Selecting UARTC as the debug console\n");
481                 cardhu_uart_devices[2] = &debug_uartc_device;
482                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
483                 debug_uart_port_base = ((struct plat_serial8250_port *)(
484                         debug_uartc_device.dev.platform_data))->mapbase;
485                 break;
486
487         case 3:
488                 /* UARTD is the debug port. */
489                 pr_info("Selecting UARTD as the debug console\n");
490                 cardhu_uart_devices[3] = &debug_uartd_device;
491                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
492                 debug_uart_port_base = ((struct plat_serial8250_port *)(
493                         debug_uartd_device.dev.platform_data))->mapbase;
494                 break;
495
496         case 4:
497                 /* UARTE is the debug port. */
498                 pr_info("Selecting UARTE as the debug console\n");
499                 cardhu_uart_devices[4] = &debug_uarte_device;
500                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
501                 debug_uart_port_base = ((struct plat_serial8250_port *)(
502                         debug_uarte_device.dev.platform_data))->mapbase;
503                 break;
504
505         default:
506                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
507                 cardhu_uart_devices[0] = &debug_uarta_device;
508                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
509                 debug_uart_port_base = ((struct plat_serial8250_port *)(
510                         debug_uarta_device.dev.platform_data))->mapbase;
511                 break;
512         }
513         return;
514 }
515
516 static void __init cardhu_uart_init(void)
517 {
518         struct clk *c;
519         int i;
520
521         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
522                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
523                 if (IS_ERR_OR_NULL(c)) {
524                         pr_err("Not able to get the clock for %s\n",
525                                                 uart_parent_clk[i].name);
526                         continue;
527                 }
528                 uart_parent_clk[i].parent_clk = c;
529                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
530         }
531         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
532         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
533         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
534         cardhu_loopback_uart_pdata.parent_clk_count =
535                                                 ARRAY_SIZE(uart_parent_clk);
536         cardhu_loopback_uart_pdata.is_loopback = true;
537         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
538         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
539         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
540         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
541         /* UARTE is used for loopback test purpose */
542         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
543
544         /* Register low speed only if it is selected */
545         if (!is_tegra_debug_uartport_hs()) {
546                 uart_debug_init();
547                 /* Clock enable for the debug channel */
548                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
549                         pr_info("The debug console clock name is %s\n",
550                                                 debug_uart_clk->name);
551                         c = tegra_get_clock_by_name("pll_p");
552                         if (IS_ERR_OR_NULL(c))
553                                 pr_err("Not getting the parent clock pll_p\n");
554                         else
555                                 clk_set_parent(debug_uart_clk, c);
556
557                         clk_enable(debug_uart_clk);
558                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
559                 } else {
560                         pr_err("Not getting the clock %s for debug console\n",
561                                         debug_uart_clk->name);
562                 }
563         }
564
565         platform_add_devices(cardhu_uart_devices,
566                                 ARRAY_SIZE(cardhu_uart_devices));
567 }
568
569 static struct platform_device tegra_camera = {
570         .name = "tegra_camera",
571         .id = -1,
572 };
573
574 static struct platform_device *cardhu_spi_devices[] __initdata = {
575         &tegra_spi_device4,
576 };
577
578 struct spi_clk_parent spi_parent_clk[] = {
579         [0] = {.name = "pll_p"},
580 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
581         [1] = {.name = "pll_m"},
582         [2] = {.name = "clk_m"},
583 #else
584         [1] = {.name = "clk_m"},
585 #endif
586 };
587
588 static struct tegra_spi_platform_data cardhu_spi_pdata = {
589         .is_dma_based           = true,
590         .max_dma_buffer         = (16 * 1024),
591         .is_clkon_always        = false,
592         .max_rate               = 100000000,
593 };
594
595 static void __init cardhu_spi_init(void)
596 {
597         int i;
598         struct clk *c;
599         struct board_info board_info;
600
601         tegra_get_board_info(&board_info);
602
603         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
604                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
605                 if (IS_ERR_OR_NULL(c)) {
606                         pr_err("Not able to get the clock for %s\n",
607                                                 spi_parent_clk[i].name);
608                         continue;
609                 }
610                 spi_parent_clk[i].parent_clk = c;
611                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
612         }
613         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
614         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
615         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
616         platform_add_devices(cardhu_spi_devices,
617                                 ARRAY_SIZE(cardhu_spi_devices));
618
619         if (board_info.board_id == BOARD_E1198) {
620                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
621                 platform_device_register(&tegra_spi_device2);
622                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
623                 platform_device_register(&tegra_spi_slave_device1);
624         }
625 }
626
627 static void __init cardhu_dtv_init(void)
628 {
629         struct board_info board_info;
630
631         tegra_get_board_info(&board_info);
632
633         if (board_info.board_id == BOARD_E1186)
634                 platform_device_register(&tegra_dtv_device);
635 }
636
637 static struct resource tegra_rtc_resources[] = {
638         [0] = {
639                 .start = TEGRA_RTC_BASE,
640                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
641                 .flags = IORESOURCE_MEM,
642         },
643         [1] = {
644                 .start = INT_RTC,
645                 .end = INT_RTC,
646                 .flags = IORESOURCE_IRQ,
647         },
648 };
649
650 static struct platform_device tegra_rtc_device = {
651         .name = "tegra_rtc",
652         .id   = -1,
653         .resource = tegra_rtc_resources,
654         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
655 };
656
657 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
658         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
659         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
660         .gpio_hp_mute           = -1,
661         .gpio_int_mic_en        = -1,
662         .gpio_ext_mic_en        = -1,
663 };
664
665 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
666         .gpio_spkr_en           = -1,
667         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
668         .gpio_hp_mute           = -1,
669         .gpio_int_mic_en        = -1,
670         .gpio_ext_mic_en        = -1,
671 };
672
673 static struct platform_device cardhu_audio_wm8903_device = {
674         .name   = "tegra-snd-wm8903",
675         .id     = 0,
676         .dev    = {
677                 .platform_data = &cardhu_audio_wm8903_pdata,
678         },
679 };
680
681 static struct platform_device cardhu_audio_max98095_device = {
682         .name   = "tegra-snd-max98095",
683         .id     = 0,
684         .dev    = {
685                 .platform_data = &cardhu_audio_max98095_pdata,
686         },
687 };
688
689 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
690         .gpio_spkr_en           = -1,
691         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
692         .gpio_hp_mute           = -1,
693         .gpio_int_mic_en        = -1,
694         .gpio_ext_mic_en        = -1,
695 };
696
697 static struct platform_device cardhu_audio_aic326x_device = {
698         .name   = "tegra-snd-aic326x",
699         .id     = 0,
700         .dev    = {
701                 .platform_data  = &cardhu_audio_aic326x_pdata,
702         },
703 };
704
705 static struct platform_device *cardhu_devices[] __initdata = {
706         &tegra_pmu_device,
707         &tegra_rtc_device,
708         &tegra_udc_device,
709 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
710         &tegra_smmu_device,
711 #endif
712         &tegra_wdt_device,
713 #if defined(CONFIG_TEGRA_AVP)
714         &tegra_avp_device,
715 #endif
716         &tegra_camera,
717 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
718         &tegra_se_device,
719 #endif
720         &tegra_ahub_device,
721         &tegra_dam_device0,
722         &tegra_dam_device1,
723         &tegra_dam_device2,
724         &tegra_i2s_device0,
725         &tegra_i2s_device1,
726         &tegra_i2s_device3,
727         &tegra_spdif_device,
728         &spdif_dit_device,
729         &bluetooth_dit_device,
730         &baseband_dit_device,
731         &cardhu_bcm4329_rfkill_device,
732         &tegra_pcm_device,
733         &cardhu_audio_wm8903_device,
734         &cardhu_audio_max98095_device,
735         &cardhu_audio_aic326x_device,
736         &tegra_hda_device,
737 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
738         &tegra_aes_device,
739 #endif
740 };
741
742 #define MXT_CONFIG_CRC  0xD62DE8
743 static const u8 config[] = {
744         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
745         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
746         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
747         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
748         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
749         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
750         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
751         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
752         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
753         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
754         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
755         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
756         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
757         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
758         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
759         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
760         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
762         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
763         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
764 };
765
766 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
767 static const u8 config_sku2000[] = {
768         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
769         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
770         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
771         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
772         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
773         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
774         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
775         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
776         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
777         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
778         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
779         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
780         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
781         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
782         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
783         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
784         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
786         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
788 };
789
790 static struct mxt_platform_data atmel_mxt_info = {
791         .x_line         = 27,
792         .y_line         = 42,
793         .x_size         = 768,
794         .y_size         = 1366,
795         .blen           = 0x20,
796         .threshold      = 0x3C,
797         .voltage        = 3300000,              /* 3.3V */
798         .orient         = 5,
799         .config         = config,
800         .config_length  = 157,
801         .config_crc     = MXT_CONFIG_CRC,
802         .irqflags       = IRQF_TRIGGER_FALLING,
803 /*      .read_chg       = &read_chg, */
804         .read_chg       = NULL,
805 };
806
807 static struct i2c_board_info __initdata atmel_i2c_info[] = {
808         {
809                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
810                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
811                 .platform_data = &atmel_mxt_info,
812         }
813 };
814
815 static int __init cardhu_touch_init(void)
816 {
817         struct board_info BoardInfo;
818
819         tegra_gpio_enable(TEGRA_GPIO_PH4);
820         tegra_gpio_enable(TEGRA_GPIO_PH6);
821
822         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
823         gpio_direction_input(TEGRA_GPIO_PH4);
824
825         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
826         gpio_direction_output(TEGRA_GPIO_PH6, 0);
827         msleep(1);
828         gpio_set_value(TEGRA_GPIO_PH6, 1);
829         msleep(100);
830
831         tegra_get_board_info(&BoardInfo);
832         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
833                 atmel_mxt_info.config = config_sku2000;
834                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
835         }
836
837         i2c_register_board_info(1, atmel_i2c_info, 1);
838
839         return 0;
840 }
841
842 static struct tegra_uhsic_config uhsic_phy_config = {
843         .enable_gpio = EN_HSIC_GPIO,
844         .reset_gpio = -1,
845         .sync_start_delay = 9,
846         .idle_wait_delay = 17,
847         .term_range_adj = 0,
848         .elastic_underrun_limit = 16,
849         .elastic_overrun_limit = 16,
850 };
851
852 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
853         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
854         .phy_config = &uhsic_phy_config,
855         .operating_mode = TEGRA_USB_HOST,
856         .power_down_on_bus_suspend = 1,
857         .default_enable = true,
858 };
859
860 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
861         [0] = {
862                         .phy_config = &utmi_phy_config[0],
863                         .operating_mode = TEGRA_USB_HOST,
864                         .power_down_on_bus_suspend = 1,
865                         .default_enable = true,
866         },
867         [1] = {
868                         .phy_config = &utmi_phy_config[1],
869                         .operating_mode = TEGRA_USB_HOST,
870                         .power_down_on_bus_suspend = 1,
871                         .default_enable = true,
872         },
873         [2] = {
874                         .phy_config = &utmi_phy_config[2],
875                         .operating_mode = TEGRA_USB_HOST,
876                         .power_down_on_bus_suspend = 1,
877                         .hotplug = 1,
878                         .default_enable = true,
879         },
880 };
881
882 static struct tegra_otg_platform_data tegra_otg_pdata = {
883         .ehci_device = &tegra_ehci1_device,
884         .ehci_pdata = &tegra_ehci_pdata[0],
885 };
886
887 #ifdef CONFIG_USB_SUPPORT
888 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
889         [0] = {
890                         .instance = 0,
891                         .vbus_gpio = -1,
892                         .vbus_reg_supply = "vdd_vbus_micro_usb",
893         },
894         [1] = {
895                         .instance = 1,
896                         .vbus_gpio = -1,
897         },
898         [2] = {
899                         .instance = 2,
900                         .vbus_gpio = -1,
901                         .vbus_reg_supply = "vdd_vbus_typea_usb",
902         },
903 };
904
905 static int cardhu_usb_hsic_postsupend(void)
906 {
907 #ifdef CONFIG_TEGRA_BB_XMM_POWER
908         baseband_xmm_set_power_status(BBXMM_PS_L2);
909 #endif
910         return 0;
911 }
912
913 static int cardhu_usb_hsic_preresume(void)
914 {
915 #ifdef CONFIG_TEGRA_BB_XMM_POWER
916         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
917 #endif
918         return 0;
919 }
920
921 static int cardhu_usb_hsic_phy_ready(void)
922 {
923 #ifdef CONFIG_TEGRA_BB_XMM_POWER
924         baseband_xmm_set_power_status(BBXMM_PS_L0);
925 #endif
926         return 0;
927 }
928
929 static int cardhu_usb_hsic_phy_off(void)
930 {
931 #ifdef CONFIG_TEGRA_BB_XMM_POWER
932         baseband_xmm_set_power_status(BBXMM_PS_L3);
933 #endif
934         return 0;
935 }
936
937 static void cardhu_usb_init(void)
938 {
939         struct board_info bi;
940
941         tegra_get_board_info(&bi);
942
943         tegra_usb_phy_init(tegra_usb_phy_pdata,
944                         ARRAY_SIZE(tegra_usb_phy_pdata));
945
946         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
947         platform_device_register(&tegra_otg_device);
948         if (bi.board_id == BOARD_PM267) {
949                 uhsic_phy_config.reset_gpio =
950                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
951                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
952                 platform_device_register(&tegra_ehci2_device);
953         } else if (bi.board_id == BOARD_E1256) {
954                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
955                 platform_device_register(&tegra_ehci2_device);
956         } else if (bi.board_id == BOARD_E1186) {
957                 /* for baseband devices do not switch off phy during suspend */
958                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
959                 uhsic_phy_config.postsuspend = cardhu_usb_hsic_postsupend;
960                 uhsic_phy_config.preresume = cardhu_usb_hsic_preresume;
961                 uhsic_phy_config.usb_phy_ready = cardhu_usb_hsic_phy_ready;
962                 uhsic_phy_config.post_phy_off = cardhu_usb_hsic_phy_off;
963                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
964                 /* baseband registration happens in baseband-xmm-power  */
965         } else {
966                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
967                 platform_device_register(&tegra_ehci2_device);
968         }
969
970         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
971         platform_device_register(&tegra_ehci3_device);
972
973 }
974 #else
975 static void cardhu_usb_init(void) { }
976 #endif
977
978 static void cardhu_gps_init(void)
979 {
980         tegra_gpio_enable(TEGRA_GPIO_PU2);
981         tegra_gpio_enable(TEGRA_GPIO_PU3);
982 }
983
984 static void cardhu_nfc_init(void)
985 {
986         tegra_gpio_enable(TEGRA_GPIO_PX0);
987         tegra_gpio_enable(TEGRA_GPIO_PP3);
988         tegra_gpio_enable(TEGRA_GPIO_PO7);
989 }
990
991 static struct baseband_power_platform_data tegra_baseband_power_data = {
992         .baseband_type = BASEBAND_XMM,
993         .modem = {
994         .xmm = {
995                         .bb_rst = XMM_GPIO_BB_RST,
996                         .bb_on = XMM_GPIO_BB_ON,
997                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
998                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
999                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1000                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1001                         .hsic_device = &tegra_ehci2_device,
1002                 },
1003         },
1004 };
1005
1006 static struct platform_device tegra_baseband_power_device = {
1007         .name = "baseband_xmm_power",
1008         .id = -1,
1009         .dev = {
1010                 .platform_data = &tegra_baseband_power_data,
1011         },
1012 };
1013
1014 static struct platform_device tegra_baseband_power2_device = {
1015         .name = "baseband_xmm_power2",
1016         .id = -1,
1017         .dev = {
1018                 .platform_data = &tegra_baseband_power_data,
1019         },
1020 };
1021
1022
1023 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1024         .port_status[0] = 1,
1025         .port_status[1] = 1,
1026         .port_status[2] = 1,
1027         .use_dock_detect        = 0,
1028         .gpio           = 0,
1029 };
1030
1031 static void cardhu_pci_init(void)
1032 {
1033         struct board_info board_info;
1034
1035         tegra_get_board_info(&board_info);
1036         if (board_info.board_id == BOARD_E1291) {
1037                 cardhu_pci_platform_data.port_status[0] = 0;
1038                 cardhu_pci_platform_data.port_status[1] = 0;
1039                 cardhu_pci_platform_data.port_status[2] = 1;
1040                 cardhu_pci_platform_data.use_dock_detect = 1;
1041                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1042         }
1043         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1044         platform_device_register(&tegra_pci_device);
1045 }
1046
1047 static void cardhu_modem_init(void)
1048 {
1049         struct board_info board_info;
1050         int w_disable_gpio, ret;
1051
1052         tegra_get_board_info(&board_info);
1053         switch (board_info.board_id) {
1054         case BOARD_E1291:
1055         case BOARD_E1198:
1056                 if (((board_info.board_id == BOARD_E1291) &&
1057                                 (board_info.fab < BOARD_FAB_A03)) ||
1058                         ((board_info.board_id == BOARD_E1198) &&
1059                                         (board_info.fab < BOARD_FAB_A02))) {
1060                         w_disable_gpio = TEGRA_GPIO_PH5;
1061                 } else {
1062                         w_disable_gpio = TEGRA_GPIO_PDD5;
1063                 }
1064                 tegra_gpio_enable(w_disable_gpio);
1065                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1066                 if (ret < 0)
1067                         pr_err("%s: gpio_request failed for gpio %d\n",
1068                                 __func__, w_disable_gpio);
1069                 else
1070                         gpio_direction_input(w_disable_gpio);
1071
1072                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1073                 if (((board_info.board_id == BOARD_E1291) &&
1074                                 (board_info.fab >= BOARD_FAB_A04)) ||
1075                         ((board_info.board_id == BOARD_E1198) &&
1076                                         (board_info.fab >= BOARD_FAB_A02))) {
1077                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1078                         if (ret < 0) {
1079                                 pr_err("%s(): Error in allocating gpio "
1080                                         "TEGRA_GPIO_PH7\n", __func__);
1081                                 break;
1082                         }
1083                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1084                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1085                 }
1086                 break;
1087         case BOARD_E1186:
1088                 tegra_gpio_enable(
1089                         tegra_baseband_power_data.modem.xmm.bb_rst);
1090                 tegra_gpio_enable(
1091                         tegra_baseband_power_data.modem.xmm.bb_on);
1092                 tegra_gpio_enable(
1093                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1094                 tegra_gpio_enable(
1095                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1096                 tegra_gpio_enable(
1097                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1098                 tegra_gpio_enable(
1099                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1100                 platform_device_register(&tegra_baseband_power_device);
1101                 platform_device_register(&tegra_baseband_power2_device);
1102                 break;
1103         default:
1104                 break;
1105         }
1106
1107 }
1108
1109 #ifdef CONFIG_SATA_AHCI_TEGRA
1110 static void cardhu_sata_init(void)
1111 {
1112         platform_device_register(&tegra_sata_device);
1113 }
1114 #else
1115 static void cardhu_sata_init(void) { }
1116 #endif
1117
1118 static void __init tegra_cardhu_init(void)
1119 {
1120         tegra_thermal_init(&thermal_data);
1121         tegra_clk_init_from_table(cardhu_clk_init_table);
1122         cardhu_pinmux_init();
1123         cardhu_i2c_init();
1124         cardhu_spi_init();
1125         cardhu_usb_init();
1126 #ifdef CONFIG_TEGRA_EDP_LIMITS
1127         cardhu_edp_init();
1128 #endif
1129         cardhu_uart_init();
1130         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1131         tegra_ram_console_debug_init();
1132         cardhu_sdhci_init();
1133         cardhu_regulator_init();
1134         cardhu_dtv_init();
1135         cardhu_suspend_init();
1136         cardhu_touch_init();
1137         cardhu_gps_init();
1138         cardhu_modem_init();
1139         cardhu_kbc_init();
1140         cardhu_scroll_init();
1141         cardhu_keys_init();
1142         cardhu_panel_init();
1143         cardhu_pmon_init();
1144         cardhu_sensors_init();
1145         cardhu_setup_bluesleep();
1146         cardhu_sata_init();
1147         //audio_wired_jack_init();
1148         cardhu_pins_state_init();
1149         cardhu_emc_init();
1150         tegra_release_bootloader_fb();
1151         cardhu_nfc_init();
1152         cardhu_pci_init();
1153 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1154         tegra_wdt_recovery_init();
1155 #endif
1156 }
1157
1158 static void __init tegra_cardhu_reserve(void)
1159 {
1160 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1161         /* support 1920X1200 with 24bpp */
1162         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1163 #else
1164         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1165 #endif
1166         tegra_ram_console_debug_reserve(SZ_1M);
1167 }
1168
1169 MACHINE_START(CARDHU, "cardhu")
1170         .boot_params    = 0x80000100,
1171         .map_io         = tegra_map_common_io,
1172         .reserve        = tegra_cardhu_reserve,
1173         .init_early     = tegra_init_early,
1174         .init_irq       = tegra_init_irq,
1175         .timer          = &tegra_timer,
1176         .init_machine   = tegra_cardhu_init,
1177 MACHINE_END