arm: tegra: cardhu: move VI to PLL_P
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/clk.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/iomap.h>
55 #include <mach/io.h>
56 #include <mach/i2s.h>
57 #include <mach/tegra_asoc_pdata.h>
58 #include <mach/tegra_wm8903_pdata.h>
59 #include <mach/usb_phy.h>
60 #include <mach/thermal.h>
61 #include <mach/pci.h>
62 #include <mach/gpio-tegra.h>
63 #include <mach/tegra_fiq_debugger.h>
64
65 #include <asm/hardware/gic.h>
66 #include <asm/mach-types.h>
67 #include <asm/mach/arch.h>
68
69 #include "board.h"
70 #include "clock.h"
71 #include "board-cardhu.h"
72 #include "board-touch.h"
73 #include "devices.h"
74 #include "gpio-names.h"
75 #include "fuse.h"
76 #include "pm.h"
77 #include "baseband-xmm-power.h"
78 #include "wdt-recovery.h"
79 #include "common.h"
80
81 static struct balanced_throttle throttle_list[] = {
82 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
83         {
84                 .id = BALANCED_THROTTLE_ID_TJ,
85                 .throt_tab_size = 10,
86                 .throt_tab = {
87                         {      0, 1000 },
88                         { 640000, 1000 },
89                         { 640000, 1000 },
90                         { 640000, 1000 },
91                         { 640000, 1000 },
92                         { 640000, 1000 },
93                         { 760000, 1000 },
94                         { 760000, 1050 },
95                         {1000000, 1050 },
96                         {1000000, 1100 },
97                 },
98         },
99 #endif
100 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
101         {
102                 .id = BALANCED_THROTTLE_ID_SKIN,
103                 .throt_tab_size = 6,
104                 .throt_tab = {
105                         { 640000, 1200 },
106                         { 640000, 1200 },
107                         { 760000, 1200 },
108                         { 760000, 1200 },
109                         {1000000, 1200 },
110                         {1000000, 1200 },
111                 },
112         },
113 #endif
114 };
115
116 /* All units are in millicelsius */
117 static struct tegra_thermal_data thermal_data = {
118         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
119         .temp_shutdown = 90000,
120
121 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
122         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
123 #endif
124 #ifdef CONFIG_TEGRA_EDP_LIMITS
125         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
126         .hysteresis_edp = 3000,
127 #endif
128 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
129         .temp_throttle = 85000,
130         .tc1 = 0,
131         .tc2 = 1,
132         .passive_delay = 2000,
133 #endif
134 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
135         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
136         .temp_throttle_skin = 43000,
137         .tc1_skin = 0,
138         .tc2_skin = 1,
139         .passive_delay_skin = 5000,
140
141         .skin_temp_offset = 9793,
142         .skin_period = 1100,
143         .skin_devs_size = 2,
144         .skin_devs = {
145                 {
146                         THERMAL_DEVICE_ID_NCT_EXT,
147                         {
148                                 2, 1, 1, 1,
149                                 1, 1, 1, 1,
150                                 1, 1, 1, 0,
151                                 1, 1, 0, 0,
152                                 0, 0, -1, -7
153                         }
154                 },
155                 {
156                         THERMAL_DEVICE_ID_NCT_INT,
157                         {
158                                 -11, -7, -5, -3,
159                                 -3, -2, -1, 0,
160                                 0, 0, 1, 1,
161                                 1, 2, 2, 3,
162                                 4, 6, 11, 18
163                         }
164                 },
165         },
166 #endif
167 };
168
169 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
170         {
171                 .name           = "bt_rfkill",
172                 .shutdown_gpio  = TEGRA_GPIO_PU0,
173                 .reset_gpio     = TEGRA_GPIO_INVALID,
174                 .type           = RFKILL_TYPE_BLUETOOTH,
175         },
176 };
177
178 static struct platform_device cardhu_bt_rfkill_device = {
179         .name = "rfkill_gpio",
180         .id             = -1,
181         .dev = {
182                 .platform_data = &cardhu_bt_rfkill_pdata,
183         },
184 };
185
186 static struct resource cardhu_bluesleep_resources[] = {
187         [0] = {
188                 .name = "gpio_host_wake",
189                         .start  = TEGRA_GPIO_PU6,
190                         .end    = TEGRA_GPIO_PU6,
191                         .flags  = IORESOURCE_IO,
192         },
193         [1] = {
194                 .name = "gpio_ext_wake",
195                         .start  = TEGRA_GPIO_PU1,
196                         .end    = TEGRA_GPIO_PU1,
197                         .flags  = IORESOURCE_IO,
198         },
199         [2] = {
200                 .name = "host_wake",
201                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
202         },
203 };
204
205 static struct platform_device cardhu_bluesleep_device = {
206         .name           = "bluesleep",
207         .id             = -1,
208         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
209         .resource       = cardhu_bluesleep_resources,
210 };
211
212 static noinline void __init cardhu_setup_bluesleep(void)
213 {
214         cardhu_bluesleep_resources[2].start =
215                 cardhu_bluesleep_resources[2].end =
216                         gpio_to_irq(TEGRA_GPIO_PU6);
217         platform_device_register(&cardhu_bluesleep_device);
218         return;
219 }
220
221 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
222         /* name         parent          rate            enabled */
223         { "pll_m",      NULL,           0,              false},
224         { "hda",        "pll_p",        108000000,      false},
225         { "hda2codec_2x","pll_p",       48000000,       false},
226         { "pwm",        "pll_p",        3187500,        false},
227         { "blink",      "clk_32k",      32768,          true},
228         { "i2s0",       "pll_a_out0",   0,              false},
229         { "i2s1",       "pll_a_out0",   0,              false},
230         { "i2s3",       "pll_a_out0",   0,              false},
231         { "spdif_out",  "pll_a_out0",   0,              false},
232         { "d_audio",    "clk_m",        12000000,       false},
233         { "dam0",       "clk_m",        12000000,       false},
234         { "dam1",       "clk_m",        12000000,       false},
235         { "dam2",       "clk_m",        12000000,       false},
236         { "audio1",     "i2s1_sync",    0,              false},
237         { "audio3",     "i2s3_sync",    0,              false},
238         { "vi_sensor",  "pll_p",        150000000,      false},
239         { "i2c1",       "pll_p",        3200000,        false},
240         { "i2c2",       "pll_p",        3200000,        false},
241         { "i2c3",       "pll_p",        3200000,        false},
242         { "i2c4",       "pll_p",        3200000,        false},
243         { "i2c5",       "pll_p",        3200000,        false},
244         { "vi",         "pll_p",        0,              false},
245         { NULL,         NULL,           0,              0},
246 };
247
248 static struct pn544_i2c_platform_data nfc_pdata = {
249         .irq_gpio = TEGRA_GPIO_PX0,
250         .ven_gpio = TEGRA_GPIO_PP3,
251         .firm_gpio = TEGRA_GPIO_PO7,
252         };
253
254 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
255         {
256                 I2C_BOARD_INFO("pn544", 0x28),
257                 .platform_data = &nfc_pdata,
258         },
259 };
260 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
261         .adapter_nr     = 0,
262         .bus_count      = 1,
263         .bus_clk_rate   = { 100000, 0 },
264         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
265         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
266         .arb_recovery = arb_lost_recovery,
267 };
268
269 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
270         .adapter_nr     = 1,
271         .bus_count      = 1,
272         .bus_clk_rate   = { 400000, 0 },
273         .is_clkon_always = true,
274         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
275         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
276         .arb_recovery = arb_lost_recovery,
277 };
278
279 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
280         .adapter_nr     = 2,
281         .bus_count      = 1,
282         .bus_clk_rate   = { 100000, 0 },
283         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
284         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
285         .arb_recovery = arb_lost_recovery,
286 };
287
288 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
289         .adapter_nr     = 3,
290         .bus_count      = 1,
291         .bus_clk_rate   = { 10000, 0 },
292         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
293         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
294         .arb_recovery = arb_lost_recovery,
295 };
296
297 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
298         .adapter_nr     = 4,
299         .bus_count      = 1,
300         .bus_clk_rate   = { 400000, 0 },
301         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
302         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
303         .arb_recovery = arb_lost_recovery,
304 };
305
306
307 #if 0
308 struct tegra_wired_jack_conf audio_wr_jack_conf = {
309         .hp_det_n = TEGRA_GPIO_PW2,
310         .en_mic_ext = TEGRA_GPIO_PX1,
311         .en_mic_int = TEGRA_GPIO_PX0,
312 };
313 #endif
314
315 static struct wm8903_platform_data cardhu_wm8903_pdata = {
316         .irq_active_low = 0,
317         .micdet_cfg = 0,
318         .micdet_delay = 100,
319         .gpio_base = CARDHU_GPIO_WM8903(0),
320         .gpio_cfg = {
321                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
322                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
323                         WM8903_GP2_DIR,
324                 WM8903_GPIO_CONFIG_ZERO,
325                 0,
326                 0,
327         },
328 };
329
330 /* Equalizer filter coefs generated from the MAXIM MAX98095
331  * evkit software tool */
332 static struct max98095_eq_cfg max98095_eq_cfg[] = {
333         {
334                 .name = "FLAT",
335                 .rate = 44100,
336                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
337                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
338                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
339                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
340                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
341         },
342         {
343                 .name = "LOWPASS1K",
344                 .rate = 44100,
345                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
346                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
347                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
348                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
349                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
350         },
351         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
352                 .name = "HIBOOST",
353                 .rate = 44100,
354                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
355                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
356                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
357                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
358                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
359         },
360         { /* BASS=12dB, TREBLE=+12dB */
361                 .name = "LOUD12DB",
362                 .rate = 44100,
363                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
364                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
365                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
366                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
367                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
368         },
369         {
370                 .name = "FLAT",
371                 .rate = 16000,
372                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
373                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
374                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
375                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
376                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
377         },
378         {
379                 .name = "LOWPASS1K",
380                 .rate = 16000,
381                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
382                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
383                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
384                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
385                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
386         },
387         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
388                 .name = "HIBOOST",
389                 .rate = 16000,
390                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
391                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
392                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
393                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
394                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
395         },
396         { /* BASS=12dB, TREBLE=+12dB */
397                 .name = "LOUD12DB",
398                 .rate = 16000,
399                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
400                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
401                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
402                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
403                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
404         },
405 };
406
407 static struct max98095_pdata cardhu_max98095_pdata = {
408         /* equalizer configuration */
409         .eq_cfg = max98095_eq_cfg,
410         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
411
412         /* Biquad filter response configuration */
413         .bq_cfg = NULL,
414         .bq_cfgcnt = 0,
415
416         /* microphone configuration */
417         .digmic_left_mode = 1,
418         .digmic_right_mode = 1,
419 };
420
421 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
422         I2C_BOARD_INFO("wm8903", 0x1a),
423         .platform_data = &cardhu_wm8903_pdata,
424 };
425
426 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
427         I2C_BOARD_INFO("aic3262-codec", 0x18),
428 };
429
430 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
431         I2C_BOARD_INFO("max98095", 0x10),
432         .platform_data = &cardhu_max98095_pdata,
433 };
434
435 static void cardhu_i2c_init(void)
436 {
437         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
438         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
439         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
440         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
441         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
442
443         platform_device_register(&tegra_i2c_device5);
444         platform_device_register(&tegra_i2c_device4);
445         platform_device_register(&tegra_i2c_device3);
446         platform_device_register(&tegra_i2c_device2);
447         platform_device_register(&tegra_i2c_device1);
448
449         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
450                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
451         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
452         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
453         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
454
455         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
456         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
457 }
458
459 static struct platform_device *cardhu_uart_devices[] __initdata = {
460         &tegra_uarta_device,
461         &tegra_uartb_device,
462         &tegra_uartc_device,
463         &tegra_uartd_device,
464         &tegra_uarte_device,
465 };
466 static struct uart_clk_parent uart_parent_clk[] = {
467         [0] = {.name = "clk_m"},
468         [1] = {.name = "pll_p"},
469 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
470         [2] = {.name = "pll_m"},
471 #endif
472 };
473
474 static struct tegra_uart_platform_data cardhu_uart_pdata;
475 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
476
477 static void __init uart_debug_init(void)
478 {
479         struct board_info board_info;
480         int debug_port_id;
481
482         tegra_get_board_info(&board_info);
483
484         debug_port_id = get_tegra_uart_debug_port_id();
485         if (debug_port_id < 0) {
486                 debug_port_id = 0;
487                         /* UARTB is debug port
488                          *       for SLT - E1186/E1187/PM269
489                          *       for E1256/E1257
490                          */
491                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
492                         ((board_info.board_id == BOARD_E1186) ||
493                         (board_info.board_id == BOARD_E1187) ||
494                         (board_info.board_id == BOARD_PM269))) ||
495                         (board_info.board_id == BOARD_E1256) ||
496                         (board_info.board_id == BOARD_E1257))
497                                 debug_port_id = 1;
498         }
499
500         switch (debug_port_id) {
501         case 0:
502                 /* UARTA is the debug port. */
503                 pr_info("Selecting UARTA as the debug console\n");
504                 cardhu_uart_devices[0] = &debug_uarta_device;
505                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
506                 debug_uart_port_base = ((struct plat_serial8250_port *)(
507                         debug_uarta_device.dev.platform_data))->mapbase;
508                 break;
509
510         case 1:
511                 /* UARTB is the debug port. */
512                 pr_info("Selecting UARTB as the debug console\n");
513                 cardhu_uart_devices[1] = &debug_uartb_device;
514                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
515                 debug_uart_port_base = ((struct plat_serial8250_port *)(
516                         debug_uartb_device.dev.platform_data))->mapbase;
517                 break;
518
519         case 2:
520                 /* UARTC is the debug port. */
521                 pr_info("Selecting UARTC as the debug console\n");
522                 cardhu_uart_devices[2] = &debug_uartc_device;
523                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
524                 debug_uart_port_base = ((struct plat_serial8250_port *)(
525                         debug_uartc_device.dev.platform_data))->mapbase;
526                 break;
527
528         case 3:
529                 /* UARTD is the debug port. */
530                 pr_info("Selecting UARTD as the debug console\n");
531                 cardhu_uart_devices[3] = &debug_uartd_device;
532                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
533                 debug_uart_port_base = ((struct plat_serial8250_port *)(
534                         debug_uartd_device.dev.platform_data))->mapbase;
535                 break;
536
537         case 4:
538                 /* UARTE is the debug port. */
539                 pr_info("Selecting UARTE as the debug console\n");
540                 cardhu_uart_devices[4] = &debug_uarte_device;
541                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
542                 debug_uart_port_base = ((struct plat_serial8250_port *)(
543                         debug_uarte_device.dev.platform_data))->mapbase;
544                 break;
545
546         default:
547                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
548                 cardhu_uart_devices[0] = &debug_uarta_device;
549                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
550                 debug_uart_port_base = ((struct plat_serial8250_port *)(
551                         debug_uarta_device.dev.platform_data))->mapbase;
552                 break;
553         }
554         return;
555 }
556
557 static void __init cardhu_uart_init(void)
558 {
559         struct clk *c;
560         int i;
561
562         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
563                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
564                 if (IS_ERR_OR_NULL(c)) {
565                         pr_err("Not able to get the clock for %s\n",
566                                                 uart_parent_clk[i].name);
567                         continue;
568                 }
569                 uart_parent_clk[i].parent_clk = c;
570                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
571         }
572         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
573         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
574         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
575         cardhu_loopback_uart_pdata.parent_clk_count =
576                                                 ARRAY_SIZE(uart_parent_clk);
577         cardhu_loopback_uart_pdata.is_loopback = true;
578         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
579         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
580         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
581         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
582         /* UARTE is used for loopback test purpose */
583         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
584
585         /* Register low speed only if it is selected */
586         if (!is_tegra_debug_uartport_hs()) {
587                 uart_debug_init();
588                 /* Clock enable for the debug channel */
589                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
590                         pr_info("The debug console clock name is %s\n",
591                                                 debug_uart_clk->name);
592                         c = tegra_get_clock_by_name("pll_p");
593                         if (IS_ERR_OR_NULL(c))
594                                 pr_err("Not getting the parent clock pll_p\n");
595                         else
596                                 clk_set_parent(debug_uart_clk, c);
597
598                         clk_enable(debug_uart_clk);
599                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
600                 } else {
601                         pr_err("Not getting the clock %s for debug console\n",
602                                         debug_uart_clk->name);
603                 }
604         }
605
606         platform_add_devices(cardhu_uart_devices,
607                                 ARRAY_SIZE(cardhu_uart_devices));
608 }
609
610 static struct platform_device tegra_camera = {
611         .name = "tegra_camera",
612         .id = -1,
613 };
614
615 static struct platform_device *cardhu_spi_devices[] __initdata = {
616         &tegra_spi_device4,
617 };
618
619 static struct platform_device *touch_spi_device[] __initdata = {
620         &tegra_spi_device1,
621 };
622
623 struct spi_clk_parent spi_parent_clk[] = {
624         [0] = {.name = "pll_p"},
625 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
626         [1] = {.name = "pll_m"},
627         [2] = {.name = "clk_m"},
628 #else
629         [1] = {.name = "clk_m"},
630 #endif
631 };
632
633 static struct tegra_spi_platform_data cardhu_spi_pdata = {
634         .is_dma_based           = true,
635         .max_dma_buffer         = (16 * 1024),
636         .is_clkon_always        = false,
637         .max_rate               = 100000000,
638 };
639
640 static void __init cardhu_spi_init(void)
641 {
642         int i;
643         struct clk *c;
644         struct board_info board_info, display_board_info;
645
646         tegra_get_board_info(&board_info);
647         tegra_get_display_board_info(&display_board_info);
648
649         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
650                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
651                 if (IS_ERR_OR_NULL(c)) {
652                         pr_err("Not able to get the clock for %s\n",
653                                                 spi_parent_clk[i].name);
654                         continue;
655                 }
656                 spi_parent_clk[i].parent_clk = c;
657                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
658         }
659         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
660         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
661         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
662         platform_add_devices(cardhu_spi_devices,
663                                 ARRAY_SIZE(cardhu_spi_devices));
664
665         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
666                 platform_add_devices(touch_spi_device,
667                                 ARRAY_SIZE(touch_spi_device));
668         }
669         if (board_info.board_id == BOARD_E1198) {
670                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
671                 platform_device_register(&tegra_spi_device2);
672                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
673                 platform_device_register(&tegra_spi_slave_device1);
674         }
675 }
676
677 static void __init cardhu_dtv_init(void)
678 {
679         struct board_info board_info;
680
681         tegra_get_board_info(&board_info);
682
683         if (board_info.board_id == BOARD_E1186)
684                 platform_device_register(&tegra_dtv_device);
685 }
686
687 static struct resource tegra_rtc_resources[] = {
688         [0] = {
689                 .start = TEGRA_RTC_BASE,
690                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
691                 .flags = IORESOURCE_MEM,
692         },
693         [1] = {
694                 .start = INT_RTC,
695                 .end = INT_RTC,
696                 .flags = IORESOURCE_IRQ,
697         },
698 };
699
700 static struct platform_device tegra_rtc_device = {
701         .name = "tegra_rtc",
702         .id   = -1,
703         .resource = tegra_rtc_resources,
704         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
705 };
706
707 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
708         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
709         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
710         .gpio_hp_mute           = -1,
711         .gpio_int_mic_en        = -1,
712         .gpio_ext_mic_en        = -1,
713 };
714
715 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
716         .gpio_spkr_en           = -1,
717         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
718         .gpio_hp_mute           = -1,
719         .gpio_int_mic_en        = -1,
720         .gpio_ext_mic_en        = -1,
721 };
722
723 static struct platform_device cardhu_audio_wm8903_device = {
724         .name   = "tegra-snd-wm8903",
725         .id     = 0,
726         .dev    = {
727                 .platform_data = &cardhu_audio_wm8903_pdata,
728         },
729 };
730
731 static struct platform_device cardhu_audio_max98095_device = {
732         .name   = "tegra-snd-max98095",
733         .id     = 0,
734         .dev    = {
735                 .platform_data = &cardhu_audio_max98095_pdata,
736         },
737 };
738
739 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
740         .gpio_spkr_en           = -1,
741         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
742         .gpio_hp_mute           = -1,
743         .gpio_int_mic_en        = -1,
744         .gpio_ext_mic_en        = -1,
745         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
746         .audio_port_id          = {
747                 [HIFI_CODEC] = 0,
748                 [BASEBAND] = -1,
749                 [BT_SCO] = 3,
750         },
751         .baseband_param         = {
752                 .rate = -1,
753                 .channels = -1,
754         },
755 };
756
757 static struct platform_device cardhu_audio_aic326x_device = {
758         .name   = "tegra-snd-aic326x",
759         .id     = 0,
760         .dev    = {
761                 .platform_data  = &cardhu_audio_aic326x_pdata,
762         },
763 };
764
765 static struct platform_device *cardhu_devices[] __initdata = {
766         &tegra_pmu_device,
767         &tegra_rtc_device,
768         &tegra_udc_device,
769 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
770         &tegra_smmu_device,
771 #endif
772         &tegra_wdt0_device,
773         &tegra_wdt1_device,
774         &tegra_wdt2_device,
775 #if defined(CONFIG_TEGRA_AVP)
776         &tegra_avp_device,
777 #endif
778         &tegra_camera,
779 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
780         &tegra_se_device,
781 #endif
782         &tegra_ahub_device,
783         &tegra_dam_device0,
784         &tegra_dam_device1,
785         &tegra_dam_device2,
786         &tegra_i2s_device0,
787         &tegra_i2s_device1,
788         &tegra_i2s_device3,
789         &tegra_spdif_device,
790         &spdif_dit_device,
791         &bluetooth_dit_device,
792         &baseband_dit_device,
793         &cardhu_bt_rfkill_device,
794         &tegra_pcm_device,
795         &cardhu_audio_wm8903_device,
796         &cardhu_audio_max98095_device,
797         &cardhu_audio_aic326x_device,
798         &tegra_hda_device,
799         &tegra_cec_device,
800 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
801         &tegra_aes_device,
802 #endif
803 };
804
805 #define E1506_MXT_CONFIG_CRC 0x62F903
806 static const u8 e1506_config[] = {
807         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
809         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
810         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
811         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
812         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
813         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
814         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
815         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
817         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
818         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
819         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
820         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
821         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
824         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
825         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
826         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
827         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
828         0x00
829 };
830
831 #define MXT_CONFIG_CRC  0xD62DE8
832 static const u8 config[] = {
833         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
835         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
836         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
837         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
838         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
839         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
843         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
844         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
845         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
846         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
847         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
851         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
852         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
853 };
854
855 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
856 static const u8 config_sku2000[] = {
857         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
858         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
859         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
860         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
861         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
862         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
863         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
864         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
868         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
869         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
870         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
871         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
875         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
876         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
877 };
878
879 static struct mxt_platform_data atmel_mxt_info = {
880         .x_line         = 27,
881         .y_line         = 42,
882         .x_size         = 768,
883         .y_size         = 1366,
884         .blen           = 0x20,
885         .threshold      = 0x3C,
886         .voltage        = 3300000,              /* 3.3V */
887         .orient         = 5,
888         .config         = config,
889         .config_length  = 157,
890         .config_crc     = MXT_CONFIG_CRC,
891         .irqflags       = IRQF_TRIGGER_FALLING,
892 /*      .read_chg       = &read_chg, */
893         .read_chg       = NULL,
894 };
895
896 static struct mxt_platform_data e1506_atmel_mxt_info = {
897         .x_line         = 19,
898         .y_line         = 11,
899         .x_size         = 960,
900         .y_size         = 540,
901         .blen           = 0x10,
902         .threshold      = 0x32,
903         .voltage        = 3300000,              /* 3.3V */
904         .orient         = 3,
905         .config         = e1506_config,
906         .config_length  = 168,
907         .config_crc     = E1506_MXT_CONFIG_CRC,
908         .irqflags       = IRQF_TRIGGER_FALLING,
909 /*      .read_chg       = &read_chg, */
910         .read_chg       = NULL,
911 };
912
913 static struct i2c_board_info __initdata atmel_i2c_info[] = {
914         {
915                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
916                 .platform_data = &atmel_mxt_info,
917         }
918 };
919
920 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
921         {
922                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
923                 .platform_data = &e1506_atmel_mxt_info,
924         }
925 };
926
927 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
928         /* name         parent          rate            enabled */
929         { "sbc1",       "pll_p",        52000000,       true},
930         { NULL,         NULL,           0,              0},
931 };
932
933 static int __init cardhu_touch_init(void)
934 {
935         struct board_info BoardInfo, DisplayBoardInfo;
936
937         tegra_get_board_info(&BoardInfo);
938         tegra_get_display_board_info(&DisplayBoardInfo);
939         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
940                 tegra_clk_init_from_table(spi_clk_init_table);
941
942                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
943         } else {
944                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
945                 gpio_direction_input(TEGRA_GPIO_PH4);
946
947                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
948                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
949                 msleep(1);
950                 gpio_set_value(TEGRA_GPIO_PH6, 1);
951                 msleep(100);
952
953                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
954                         atmel_mxt_info.config = config_sku2000;
955                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
956                 }
957
958                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
959                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
960                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
961                 } else {
962                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
963                         i2c_register_board_info(1, atmel_i2c_info, 1);
964                 }
965         }
966
967         return 0;
968 }
969
970 #if defined(CONFIG_USB_SUPPORT)
971
972 static void cardu_usb_hsic_postsupend(void)
973 {
974 #ifdef CONFIG_TEGRA_BB_XMM_POWER
975         baseband_xmm_set_power_status(BBXMM_PS_L2);
976 #endif
977 }
978
979 static void cardu_usb_hsic_preresume(void)
980 {
981 #ifdef CONFIG_TEGRA_BB_XMM_POWER
982         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
983 #endif
984 }
985
986 static void cardu_usb_hsic_phy_ready(void)
987 {
988 #ifdef CONFIG_TEGRA_BB_XMM_POWER
989         baseband_xmm_set_power_status(BBXMM_PS_L0);
990 #endif
991 }
992
993 static void cardu_usb_hsic_phy_off(void)
994 {
995 #ifdef CONFIG_TEGRA_BB_XMM_POWER
996         baseband_xmm_set_power_status(BBXMM_PS_L3);
997 #endif
998 }
999
1000 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1001         .post_suspend = cardu_usb_hsic_postsupend,
1002         .pre_resume = cardu_usb_hsic_preresume,
1003         .port_power = cardu_usb_hsic_phy_ready,
1004         .post_phy_off = cardu_usb_hsic_phy_off,
1005 };
1006
1007 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1008         .port_otg = false,
1009         .has_hostpc = true,
1010         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1011         .op_mode        = TEGRA_USB_OPMODE_HOST,
1012         .u_data.host = {
1013                 .vbus_gpio = -1,
1014                 .hot_plug = false,
1015                 .remote_wakeup_supported = false,
1016                 .power_off_on_suspend = false,
1017         },
1018         .u_cfg.hsic = {
1019                 .sync_start_delay = 9,
1020                 .idle_wait_delay = 17,
1021                 .term_range_adj = 0,
1022                 .elastic_underrun_limit = 16,
1023                 .elastic_overrun_limit = 16,
1024         },
1025         .ops = &hsic_xmm_plat_ops,
1026 };
1027 #endif
1028
1029 static int hsic_enable_gpio = -1;
1030 static int hsic_reset_gpio = -1;
1031
1032 void hsic_platform_open(void)
1033 {
1034         int reset_gpio = 0, enable_gpio = 0;
1035
1036         if (hsic_enable_gpio != -1)
1037                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1038         if (hsic_reset_gpio != -1)
1039                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1040         /* hsic enable signal deasserted, hsic reset asserted */
1041         if (!enable_gpio)
1042                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1043         if (!reset_gpio)
1044                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1045         if (!enable_gpio)
1046                 tegra_gpio_enable(hsic_enable_gpio);
1047         if (!reset_gpio)
1048                 tegra_gpio_enable(hsic_reset_gpio);
1049         /* keep hsic reset asserted for 1 ms */
1050         udelay(1000);
1051         /* enable (power on) hsic */
1052         if (!enable_gpio)
1053                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1054         udelay(1000);
1055         /* deassert reset */
1056         if (!reset_gpio)
1057                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1058
1059 }
1060
1061 void hsic_platform_close(void)
1062 {
1063         if (hsic_enable_gpio != -1) {
1064                 gpio_set_value(hsic_enable_gpio, 0);
1065                 gpio_free(hsic_enable_gpio);
1066         }
1067         if (hsic_reset_gpio != -1) {
1068                 gpio_set_value(hsic_reset_gpio, 0);
1069                 gpio_free(hsic_reset_gpio);
1070         }
1071 }
1072
1073 void hsic_power_on(void)
1074 {
1075         if (hsic_enable_gpio != -1) {
1076                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1077                 udelay(1000);
1078         }
1079 }
1080
1081 void hsic_power_off(void)
1082 {
1083         if (hsic_enable_gpio != -1) {
1084                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1085                 udelay(1000);
1086         }
1087 }
1088
1089 #if defined(CONFIG_USB_SUPPORT)
1090 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1091         .open = hsic_platform_open,
1092         .close = hsic_platform_close,
1093         .pre_phy_on = hsic_power_on,
1094         .post_phy_off = hsic_power_off,
1095 };
1096
1097 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1098         .port_otg = false,
1099         .has_hostpc = true,
1100         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1101         .op_mode        = TEGRA_USB_OPMODE_HOST,
1102         .u_data.host = {
1103                 .vbus_gpio = -1,
1104                 .hot_plug = false,
1105                 .remote_wakeup_supported = false,
1106                 .power_off_on_suspend = false,
1107         },
1108         .u_cfg.hsic = {
1109                 .sync_start_delay = 9,
1110                 .idle_wait_delay = 17,
1111                 .term_range_adj = 0,
1112                 .elastic_underrun_limit = 16,
1113                 .elastic_overrun_limit = 16,
1114         },
1115         .ops = &hsic_plat_ops,
1116 };
1117
1118 static struct tegra_usb_platform_data tegra_udc_pdata = {
1119         .port_otg = true,
1120         .has_hostpc = true,
1121         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1122         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1123         .u_data.dev = {
1124                 .vbus_pmu_irq = 0,
1125                 .vbus_gpio = -1,
1126                 .charging_supported = false,
1127                 .remote_wakeup_supported = false,
1128         },
1129         .u_cfg.utmi = {
1130                 .hssync_start_delay = 0,
1131                 .elastic_limit = 16,
1132                 .idle_wait_delay = 17,
1133                 .term_range_adj = 6,
1134                 .xcvr_setup = 8,
1135                 .xcvr_lsfslew = 2,
1136                 .xcvr_lsrslew = 2,
1137                 .xcvr_setup_offset = 0,
1138                 .xcvr_use_fuses = 1,
1139         },
1140 };
1141
1142 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1143         .port_otg = false,
1144         .has_hostpc = true,
1145         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1146         .op_mode        = TEGRA_USB_OPMODE_HOST,
1147         .u_data.host = {
1148                 .vbus_gpio = -1,
1149                 .hot_plug = false,
1150                 .remote_wakeup_supported = true,
1151                 .power_off_on_suspend = true,
1152         },
1153         .u_cfg.utmi = {
1154                 .hssync_start_delay = 0,
1155                 .elastic_limit = 16,
1156                 .idle_wait_delay = 17,
1157                 .term_range_adj = 6,
1158                 .xcvr_setup = 15,
1159                 .xcvr_lsfslew = 2,
1160                 .xcvr_lsrslew = 2,
1161                 .xcvr_setup_offset = 0,
1162                 .xcvr_use_fuses = 1,
1163         },
1164 };
1165
1166 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1167         .port_otg = false,
1168         .has_hostpc = true,
1169         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1170         .op_mode = TEGRA_USB_OPMODE_HOST,
1171         .u_data.host = {
1172                 .vbus_gpio = -1,
1173                 .vbus_reg = "vdd_vbus_typea_usb",
1174                 .hot_plug = true,
1175                 .remote_wakeup_supported = true,
1176                 .power_off_on_suspend = true,
1177         },
1178         .u_cfg.utmi = {
1179                 .hssync_start_delay = 0,
1180                 .elastic_limit = 16,
1181                 .idle_wait_delay = 17,
1182                 .term_range_adj = 6,
1183                 .xcvr_setup = 8,
1184                 .xcvr_lsfslew = 2,
1185                 .xcvr_lsrslew = 2,
1186                 .xcvr_setup_offset = 0,
1187                 .xcvr_use_fuses = 1,
1188         },
1189 };
1190
1191 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1192         .port_otg = true,
1193         .has_hostpc = true,
1194         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1195         .op_mode = TEGRA_USB_OPMODE_HOST,
1196         .u_data.host = {
1197                 .vbus_gpio = -1,
1198                 .vbus_reg = "vdd_vbus_micro_usb",
1199                 .hot_plug = true,
1200                 .remote_wakeup_supported = true,
1201                 .power_off_on_suspend = true,
1202         },
1203         .u_cfg.utmi = {
1204                 .hssync_start_delay = 0,
1205                 .elastic_limit = 16,
1206                 .idle_wait_delay = 17,
1207                 .term_range_adj = 6,
1208                 .xcvr_setup = 15,
1209                 .xcvr_lsfslew = 2,
1210                 .xcvr_lsrslew = 2,
1211                 .xcvr_setup_offset = 0,
1212                 .xcvr_use_fuses = 1,
1213         },
1214 };
1215
1216 static struct tegra_usb_otg_data tegra_otg_pdata = {
1217         .ehci_device = &tegra_ehci1_device,
1218         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1219 };
1220 #endif
1221
1222 #if defined(CONFIG_USB_SUPPORT)
1223 static void cardhu_usb_init(void)
1224 {
1225         struct board_info bi;
1226
1227         tegra_get_board_info(&bi);
1228
1229         /* OTG should be the first to be registered */
1230         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1231         platform_device_register(&tegra_otg_device);
1232
1233         /* setup the udc platform data */
1234         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1235
1236         if (bi.board_id == BOARD_PM267) {
1237                 hsic_enable_gpio = EN_HSIC_GPIO;
1238                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1239                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1240                 platform_device_register(&tegra_ehci2_device);
1241         } else if (bi.board_id == BOARD_E1256) {
1242                 hsic_enable_gpio = EN_HSIC_GPIO;
1243                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1244                 platform_device_register(&tegra_ehci2_device);
1245         } else if (bi.board_id == BOARD_E1186) {
1246                 tegra_ehci2_device.dev.platform_data =
1247                                                 &tegra_ehci2_hsic_xmm_pdata;
1248                 /* ehci2 registration happens in baseband-xmm-power  */
1249         } else {
1250                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1251                 platform_device_register(&tegra_ehci2_device);
1252         }
1253
1254         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1255         platform_device_register(&tegra_ehci3_device);
1256
1257 }
1258 #else
1259 static void cardhu_usb_init(void) { }
1260 #endif
1261
1262 static struct baseband_power_platform_data tegra_baseband_power_data = {
1263         .baseband_type = BASEBAND_XMM,
1264         .modem = {
1265         .xmm = {
1266                         .bb_rst = XMM_GPIO_BB_RST,
1267                         .bb_on = XMM_GPIO_BB_ON,
1268                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1269                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1270                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1271                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1272                         .hsic_device = &tegra_ehci2_device,
1273                 },
1274         },
1275 };
1276
1277 static struct platform_device tegra_baseband_power_device = {
1278         .name = "baseband_xmm_power",
1279         .id = -1,
1280         .dev = {
1281                 .platform_data = &tegra_baseband_power_data,
1282         },
1283 };
1284
1285 static struct platform_device tegra_baseband_power2_device = {
1286         .name = "baseband_xmm_power2",
1287         .id = -1,
1288         .dev = {
1289                 .platform_data = &tegra_baseband_power_data,
1290         },
1291 };
1292
1293
1294 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1295         .port_status[0] = 1,
1296         .port_status[1] = 1,
1297         .port_status[2] = 1,
1298         .use_dock_detect        = 0,
1299         .gpio           = 0,
1300 };
1301
1302 static void cardhu_pci_init(void)
1303 {
1304         struct board_info board_info;
1305
1306         tegra_get_board_info(&board_info);
1307         if (board_info.board_id == BOARD_E1291) {
1308                 cardhu_pci_platform_data.port_status[0] = 0;
1309                 cardhu_pci_platform_data.port_status[1] = 0;
1310                 cardhu_pci_platform_data.port_status[2] = 1;
1311                 cardhu_pci_platform_data.use_dock_detect = 1;
1312                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1313         }
1314         if ((board_info.board_id == BOARD_E1186) ||
1315                 (board_info.board_id == BOARD_E1187) ||
1316                 (board_info.board_id == BOARD_E1291)) {
1317                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1318                 platform_device_register(&tegra_pci_device);
1319         }
1320 }
1321
1322 static void cardhu_modem_init(void)
1323 {
1324         struct board_info board_info;
1325         int w_disable_gpio, ret;
1326
1327         tegra_get_board_info(&board_info);
1328         switch (board_info.board_id) {
1329         case BOARD_E1291:
1330         case BOARD_E1198:
1331                 if (((board_info.board_id == BOARD_E1291) &&
1332                                 (board_info.fab < BOARD_FAB_A03)) ||
1333                         ((board_info.board_id == BOARD_E1198) &&
1334                                         (board_info.fab < BOARD_FAB_A02))) {
1335                         w_disable_gpio = TEGRA_GPIO_PH5;
1336                 } else {
1337                         w_disable_gpio = TEGRA_GPIO_PDD5;
1338                 }
1339
1340                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1341                 if (ret < 0)
1342                         pr_err("%s: gpio_request failed for gpio %d\n",
1343                                 __func__, w_disable_gpio);
1344                 else
1345                         gpio_direction_input(w_disable_gpio);
1346
1347                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1348                 if (((board_info.board_id == BOARD_E1291) &&
1349                                 (board_info.fab >= BOARD_FAB_A04)) ||
1350                         ((board_info.board_id == BOARD_E1198) &&
1351                                         (board_info.fab >= BOARD_FAB_A02))) {
1352                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1353                         if (ret < 0) {
1354                                 pr_err("%s(): Error in allocating gpio "
1355                                         "TEGRA_GPIO_PH7\n", __func__);
1356                                 break;
1357                         }
1358                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1359                 }
1360                 break;
1361         case BOARD_E1186:
1362                 platform_device_register(&tegra_baseband_power_device);
1363                 platform_device_register(&tegra_baseband_power2_device);
1364                 break;
1365         default:
1366                 break;
1367         }
1368
1369 }
1370
1371 #ifdef CONFIG_SATA_AHCI_TEGRA
1372 static void cardhu_sata_init(void)
1373 {
1374         platform_device_register(&tegra_sata_device);
1375 }
1376 #else
1377 static void cardhu_sata_init(void) { }
1378 #endif
1379
1380 static void __init tegra_cardhu_init(void)
1381 {
1382         tegra_thermal_init(&thermal_data,
1383                                 throttle_list,
1384                                 ARRAY_SIZE(throttle_list));
1385         tegra_clk_init_from_table(cardhu_clk_init_table);
1386         tegra_enable_pinmux();
1387         cardhu_pinmux_init();
1388         cardhu_i2c_init();
1389         cardhu_spi_init();
1390         cardhu_usb_init();
1391 #ifdef CONFIG_TEGRA_EDP_LIMITS
1392         cardhu_edp_init();
1393 #endif
1394         cardhu_uart_init();
1395         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1396         tegra_ram_console_debug_init();
1397         cardhu_sdhci_init();
1398         cardhu_regulator_init();
1399         cardhu_dtv_init();
1400         cardhu_suspend_init();
1401         cardhu_touch_init();
1402         cardhu_modem_init();
1403         cardhu_kbc_init();
1404         cardhu_scroll_init();
1405         cardhu_keys_init();
1406         cardhu_panel_init();
1407         cardhu_pmon_init();
1408         cardhu_sensors_init();
1409         cardhu_setup_bluesleep();
1410         cardhu_sata_init();
1411         //audio_wired_jack_init();
1412         cardhu_pins_state_init();
1413         cardhu_emc_init();
1414         tegra_release_bootloader_fb();
1415         cardhu_pci_init();
1416 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1417         tegra_wdt_recovery_init();
1418 #endif
1419         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1420 }
1421
1422 static void __init tegra_cardhu_reserve(void)
1423 {
1424 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1425         /* support 1920X1200 with 24bpp */
1426         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1427 #else
1428         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1429 #endif
1430         tegra_ram_console_debug_reserve(SZ_1M);
1431 }
1432
1433 MACHINE_START(CARDHU, "cardhu")
1434         .atag_offset    = 0x100,
1435         .soc            = &tegra_soc_desc,
1436         .map_io         = tegra_map_common_io,
1437         .reserve        = tegra_cardhu_reserve,
1438         .init_early     = tegra30_init_early,
1439         .init_irq       = tegra_init_irq,
1440         .handle_irq     = gic_handle_irq,
1441         .timer          = &tegra_timer,
1442         .init_machine   = tegra_cardhu_init,
1443         .restart        = tegra_assert_system_reset,
1444 MACHINE_END