ARM: tegra: resolve compilation time warnings
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "board-touch.h"
66 #include "devices.h"
67 #include "gpio-names.h"
68 #include "fuse.h"
69 #include "pm.h"
70 #include "baseband-xmm-power.h"
71 #include "wdt-recovery.h"
72
73 /* All units are in millicelsius */
74 static struct tegra_thermal_data thermal_data = {
75         .temp_shutdown = 90000,
76         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
77 #ifdef CONFIG_TEGRA_EDP_LIMITS
78         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
79         .hysteresis_edp = 3000,
80 #endif
81 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
82         .temp_throttle = 85000,
83         .tc1 = 0,
84         .tc2 = 1,
85         .passive_delay = 2000,
86 #endif
87 };
88
89 static struct resource cardhu_bcm4329_rfkill_resources[] = {
90         {
91                 .name   = "bcm4329_nshutdown_gpio",
92                 .start  = TEGRA_GPIO_PU0,
93                 .end    = TEGRA_GPIO_PU0,
94                 .flags  = IORESOURCE_IO,
95         },
96 };
97
98 static struct platform_device cardhu_bcm4329_rfkill_device = {
99         .name = "bcm4329_rfkill",
100         .id             = -1,
101         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
102         .resource       = cardhu_bcm4329_rfkill_resources,
103 };
104
105 static struct resource cardhu_bluesleep_resources[] = {
106         [0] = {
107                 .name = "gpio_host_wake",
108                         .start  = TEGRA_GPIO_PU6,
109                         .end    = TEGRA_GPIO_PU6,
110                         .flags  = IORESOURCE_IO,
111         },
112         [1] = {
113                 .name = "gpio_ext_wake",
114                         .start  = TEGRA_GPIO_PU1,
115                         .end    = TEGRA_GPIO_PU1,
116                         .flags  = IORESOURCE_IO,
117         },
118         [2] = {
119                 .name = "host_wake",
120                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
121                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
122                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
123         },
124 };
125
126 static struct platform_device cardhu_bluesleep_device = {
127         .name           = "bluesleep",
128         .id             = -1,
129         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
130         .resource       = cardhu_bluesleep_resources,
131 };
132
133 static noinline void __init cardhu_setup_bluesleep(void)
134 {
135         platform_device_register(&cardhu_bluesleep_device);
136         return;
137 }
138
139 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
140         /* name         parent          rate            enabled */
141         { "pll_m",      NULL,           0,              false},
142         { "hda",        "pll_p",        108000000,      false},
143         { "hda2codec_2x","pll_p",       48000000,       false},
144         { "pwm",        "pll_p",        3187500,        false},
145         { "blink",      "clk_32k",      32768,          true},
146         { "i2s0",       "pll_a_out0",   0,              false},
147         { "i2s1",       "pll_a_out0",   0,              false},
148         { "i2s3",       "pll_a_out0",   0,              false},
149         { "spdif_out",  "pll_a_out0",   0,              false},
150         { "d_audio",    "clk_m",        12000000,       false},
151         { "dam0",       "clk_m",        12000000,       false},
152         { "dam1",       "clk_m",        12000000,       false},
153         { "dam2",       "clk_m",        12000000,       false},
154         { "audio1",     "i2s1_sync",    0,              false},
155         { "audio3",     "i2s3_sync",    0,              false},
156         { "vi_sensor",  "pll_p",        150000000,      false},
157         { "i2c1",       "pll_p",        3200000,        false},
158         { "i2c2",       "pll_p",        3200000,        false},
159         { "i2c3",       "pll_p",        3200000,        false},
160         { "i2c4",       "pll_p",        3200000,        false},
161         { "i2c5",       "pll_p",        3200000,        false},
162         { NULL,         NULL,           0,              0},
163 };
164
165 static struct pn544_i2c_platform_data nfc_pdata = {
166         .irq_gpio = TEGRA_GPIO_PX0,
167         .ven_gpio = TEGRA_GPIO_PP3,
168         .firm_gpio = TEGRA_GPIO_PO7,
169         };
170
171 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
172         {
173                 I2C_BOARD_INFO("pn544", 0x28),
174                 .platform_data = &nfc_pdata,
175                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
176         },
177 };
178 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
179         .adapter_nr     = 0,
180         .bus_count      = 1,
181         .bus_clk_rate   = { 100000, 0 },
182         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
183         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
184         .arb_recovery = arb_lost_recovery,
185 };
186
187 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
188         .adapter_nr     = 1,
189         .bus_count      = 1,
190         .bus_clk_rate   = { 400000, 0 },
191         .is_clkon_always = true,
192         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
193         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
194         .arb_recovery = arb_lost_recovery,
195 };
196
197 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
198         .adapter_nr     = 2,
199         .bus_count      = 1,
200         .bus_clk_rate   = { 100000, 0 },
201         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
202         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
203         .arb_recovery = arb_lost_recovery,
204 };
205
206 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
207         .adapter_nr     = 3,
208         .bus_count      = 1,
209         .bus_clk_rate   = { 10000, 0 },
210         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
211         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
212         .arb_recovery = arb_lost_recovery,
213 };
214
215 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
216         .adapter_nr     = 4,
217         .bus_count      = 1,
218         .bus_clk_rate   = { 400000, 0 },
219         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
220         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
221         .arb_recovery = arb_lost_recovery,
222 };
223
224
225 #if 0
226 struct tegra_wired_jack_conf audio_wr_jack_conf = {
227         .hp_det_n = TEGRA_GPIO_PW2,
228         .en_mic_ext = TEGRA_GPIO_PX1,
229         .en_mic_int = TEGRA_GPIO_PX0,
230 };
231 #endif
232
233 static struct wm8903_platform_data cardhu_wm8903_pdata = {
234         .irq_active_low = 0,
235         .micdet_cfg = 0,
236         .micdet_delay = 100,
237         .gpio_base = CARDHU_GPIO_WM8903(0),
238         .gpio_cfg = {
239                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
240                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
241                         WM8903_GP2_DIR,
242                 0,
243                 WM8903_GPIO_NO_CONFIG,
244                 WM8903_GPIO_NO_CONFIG,
245         },
246 };
247
248 /* Equalizer filter coefs generated from the MAXIM MAX98095
249  * evkit software tool */
250 static struct max98095_eq_cfg max98095_eq_cfg[] = {
251         {
252                 .name = "FLAT",
253                 .rate = 44100,
254                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
255                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
256                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
257                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
258                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
259         },
260         {
261                 .name = "LOWPASS1K",
262                 .rate = 44100,
263                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
264                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
265                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
266                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
267                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
268         },
269         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
270                 .name = "HIBOOST",
271                 .rate = 44100,
272                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
273                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
274                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
275                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
276                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
277         },
278         { /* BASS=12dB, TREBLE=+12dB */
279                 .name = "LOUD12DB",
280                 .rate = 44100,
281                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
282                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
283                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
284                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
285                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
286         },
287         {
288                 .name = "FLAT",
289                 .rate = 16000,
290                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
291                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
292                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
293                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
294                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
295         },
296         {
297                 .name = "LOWPASS1K",
298                 .rate = 16000,
299                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
300                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
301                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
302                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
303                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
304         },
305         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
306                 .name = "HIBOOST",
307                 .rate = 16000,
308                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
309                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
310                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
311                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
312                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
313         },
314         { /* BASS=12dB, TREBLE=+12dB */
315                 .name = "LOUD12DB",
316                 .rate = 16000,
317                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
318                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
319                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
320                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
321                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
322         },
323 };
324
325 static struct max98095_pdata cardhu_max98095_pdata = {
326         /* equalizer configuration */
327         .eq_cfg = max98095_eq_cfg,
328         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
329
330         /* Biquad filter response configuration */
331         .bq_cfg = NULL,
332         .bq_cfgcnt = 0,
333
334         /* microphone configuration */
335         .digmic_left_mode = 1,
336         .digmic_right_mode = 1,
337 };
338
339 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
340         I2C_BOARD_INFO("wm8903", 0x1a),
341         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
342         .platform_data = &cardhu_wm8903_pdata,
343 };
344
345 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
346         I2C_BOARD_INFO("aic3262-codec", 0x18),
347         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
348 };
349
350 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
351         I2C_BOARD_INFO("max98095", 0x10),
352         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
353         .platform_data = &cardhu_max98095_pdata,
354 };
355
356 static void cardhu_i2c_init(void)
357 {
358         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
359         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
360         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
361         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
362         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
363
364         platform_device_register(&tegra_i2c_device5);
365         platform_device_register(&tegra_i2c_device4);
366         platform_device_register(&tegra_i2c_device3);
367         platform_device_register(&tegra_i2c_device2);
368         platform_device_register(&tegra_i2c_device1);
369
370         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
371         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
372         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
373
374         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
375 }
376
377 static struct platform_device *cardhu_uart_devices[] __initdata = {
378         &tegra_uarta_device,
379         &tegra_uartb_device,
380         &tegra_uartc_device,
381         &tegra_uartd_device,
382         &tegra_uarte_device,
383 };
384 static struct uart_clk_parent uart_parent_clk[] = {
385         [0] = {.name = "clk_m"},
386         [1] = {.name = "pll_p"},
387 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
388         [2] = {.name = "pll_m"},
389 #endif
390 };
391
392 static struct tegra_uart_platform_data cardhu_uart_pdata;
393 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
394
395 static void __init uart_debug_init(void)
396 {
397         struct board_info board_info;
398         int debug_port_id;
399
400         tegra_get_board_info(&board_info);
401
402         debug_port_id = get_tegra_uart_debug_port_id();
403         if (debug_port_id < 0) {
404                 debug_port_id = 0;
405                         /* UARTB is debug port
406                          *       for SLT - E1186/E1187/PM269
407                          *       for E1256/E1257
408                          */
409                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
410                         ((board_info.board_id == BOARD_E1186) ||
411                         (board_info.board_id == BOARD_E1187) ||
412                         (board_info.board_id == BOARD_PM269))) ||
413                         (board_info.board_id == BOARD_E1256) ||
414                         (board_info.board_id == BOARD_E1257))
415                                 debug_port_id = 1;
416         }
417
418         switch (debug_port_id) {
419         case 0:
420                 /* UARTA is the debug port. */
421                 pr_info("Selecting UARTA as the debug console\n");
422                 cardhu_uart_devices[0] = &debug_uarta_device;
423                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
424                 debug_uart_port_base = ((struct plat_serial8250_port *)(
425                         debug_uarta_device.dev.platform_data))->mapbase;
426                 break;
427
428         case 1:
429                 /* UARTB is the debug port. */
430                 pr_info("Selecting UARTB as the debug console\n");
431                 cardhu_uart_devices[1] = &debug_uartb_device;
432                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
433                 debug_uart_port_base = ((struct plat_serial8250_port *)(
434                         debug_uartb_device.dev.platform_data))->mapbase;
435                 break;
436
437         case 2:
438                 /* UARTC is the debug port. */
439                 pr_info("Selecting UARTC as the debug console\n");
440                 cardhu_uart_devices[2] = &debug_uartc_device;
441                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
442                 debug_uart_port_base = ((struct plat_serial8250_port *)(
443                         debug_uartc_device.dev.platform_data))->mapbase;
444                 break;
445
446         case 3:
447                 /* UARTD is the debug port. */
448                 pr_info("Selecting UARTD as the debug console\n");
449                 cardhu_uart_devices[3] = &debug_uartd_device;
450                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
451                 debug_uart_port_base = ((struct plat_serial8250_port *)(
452                         debug_uartd_device.dev.platform_data))->mapbase;
453                 break;
454
455         case 4:
456                 /* UARTE is the debug port. */
457                 pr_info("Selecting UARTE as the debug console\n");
458                 cardhu_uart_devices[4] = &debug_uarte_device;
459                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
460                 debug_uart_port_base = ((struct plat_serial8250_port *)(
461                         debug_uarte_device.dev.platform_data))->mapbase;
462                 break;
463
464         default:
465                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
466                 cardhu_uart_devices[0] = &debug_uarta_device;
467                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
468                 debug_uart_port_base = ((struct plat_serial8250_port *)(
469                         debug_uarta_device.dev.platform_data))->mapbase;
470                 break;
471         }
472         return;
473 }
474
475 static void __init cardhu_uart_init(void)
476 {
477         struct clk *c;
478         int i;
479
480         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
481                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
482                 if (IS_ERR_OR_NULL(c)) {
483                         pr_err("Not able to get the clock for %s\n",
484                                                 uart_parent_clk[i].name);
485                         continue;
486                 }
487                 uart_parent_clk[i].parent_clk = c;
488                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
489         }
490         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
491         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
492         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
493         cardhu_loopback_uart_pdata.parent_clk_count =
494                                                 ARRAY_SIZE(uart_parent_clk);
495         cardhu_loopback_uart_pdata.is_loopback = true;
496         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
497         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
498         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
499         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
500         /* UARTE is used for loopback test purpose */
501         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
502
503         /* Register low speed only if it is selected */
504         if (!is_tegra_debug_uartport_hs()) {
505                 uart_debug_init();
506                 /* Clock enable for the debug channel */
507                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
508                         pr_info("The debug console clock name is %s\n",
509                                                 debug_uart_clk->name);
510                         c = tegra_get_clock_by_name("pll_p");
511                         if (IS_ERR_OR_NULL(c))
512                                 pr_err("Not getting the parent clock pll_p\n");
513                         else
514                                 clk_set_parent(debug_uart_clk, c);
515
516                         clk_enable(debug_uart_clk);
517                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
518                 } else {
519                         pr_err("Not getting the clock %s for debug console\n",
520                                         debug_uart_clk->name);
521                 }
522         }
523
524         platform_add_devices(cardhu_uart_devices,
525                                 ARRAY_SIZE(cardhu_uart_devices));
526 }
527
528 static struct platform_device tegra_camera = {
529         .name = "tegra_camera",
530         .id = -1,
531 };
532
533 static struct platform_device *cardhu_spi_devices[] __initdata = {
534         &tegra_spi_device4,
535 };
536
537 static struct platform_device *touch_spi_device[] __initdata = {
538         &tegra_spi_device1,
539 };
540
541 struct spi_clk_parent spi_parent_clk[] = {
542         [0] = {.name = "pll_p"},
543 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
544         [1] = {.name = "pll_m"},
545         [2] = {.name = "clk_m"},
546 #else
547         [1] = {.name = "clk_m"},
548 #endif
549 };
550
551 static struct tegra_spi_platform_data cardhu_spi_pdata = {
552         .is_dma_based           = true,
553         .max_dma_buffer         = (16 * 1024),
554         .is_clkon_always        = false,
555         .max_rate               = 100000000,
556 };
557
558 static void __init cardhu_spi_init(void)
559 {
560         int i;
561         struct clk *c;
562         struct board_info board_info, display_board_info;
563
564         tegra_get_board_info(&board_info);
565         tegra_get_display_board_info(&display_board_info);
566
567         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
568                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
569                 if (IS_ERR_OR_NULL(c)) {
570                         pr_err("Not able to get the clock for %s\n",
571                                                 spi_parent_clk[i].name);
572                         continue;
573                 }
574                 spi_parent_clk[i].parent_clk = c;
575                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
576         }
577         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
578         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
579         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
580         platform_add_devices(cardhu_spi_devices,
581                                 ARRAY_SIZE(cardhu_spi_devices));
582
583         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
584                 platform_add_devices(touch_spi_device,
585                                 ARRAY_SIZE(touch_spi_device));
586         }
587         if (board_info.board_id == BOARD_E1198) {
588                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
589                 platform_device_register(&tegra_spi_device2);
590                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
591                 platform_device_register(&tegra_spi_slave_device1);
592         }
593 }
594
595 static void __init cardhu_dtv_init(void)
596 {
597         struct board_info board_info;
598
599         tegra_get_board_info(&board_info);
600
601         if (board_info.board_id == BOARD_E1186)
602                 platform_device_register(&tegra_dtv_device);
603 }
604
605 static struct resource tegra_rtc_resources[] = {
606         [0] = {
607                 .start = TEGRA_RTC_BASE,
608                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
609                 .flags = IORESOURCE_MEM,
610         },
611         [1] = {
612                 .start = INT_RTC,
613                 .end = INT_RTC,
614                 .flags = IORESOURCE_IRQ,
615         },
616 };
617
618 static struct platform_device tegra_rtc_device = {
619         .name = "tegra_rtc",
620         .id   = -1,
621         .resource = tegra_rtc_resources,
622         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
623 };
624
625 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
626         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
627         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
628         .gpio_hp_mute           = -1,
629         .gpio_int_mic_en        = -1,
630         .gpio_ext_mic_en        = -1,
631 };
632
633 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
634         .gpio_spkr_en           = -1,
635         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
636         .gpio_hp_mute           = -1,
637         .gpio_int_mic_en        = -1,
638         .gpio_ext_mic_en        = -1,
639 };
640
641 static struct platform_device cardhu_audio_wm8903_device = {
642         .name   = "tegra-snd-wm8903",
643         .id     = 0,
644         .dev    = {
645                 .platform_data = &cardhu_audio_wm8903_pdata,
646         },
647 };
648
649 static struct platform_device cardhu_audio_max98095_device = {
650         .name   = "tegra-snd-max98095",
651         .id     = 0,
652         .dev    = {
653                 .platform_data = &cardhu_audio_max98095_pdata,
654         },
655 };
656
657 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
658         .gpio_spkr_en           = -1,
659         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
660         .gpio_hp_mute           = -1,
661         .gpio_int_mic_en        = -1,
662         .gpio_ext_mic_en        = -1,
663         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
664         .audio_port_id          = {
665                 [HIFI_CODEC] = 0,
666                 [BASEBAND] = -1,
667                 [BT_SCO] = 3,
668         },
669         .baseband_param         = {
670                 .rate = -1,
671                 .channels = -1,
672         },
673 };
674
675 static struct platform_device cardhu_audio_aic326x_device = {
676         .name   = "tegra-snd-aic326x",
677         .id     = 0,
678         .dev    = {
679                 .platform_data  = &cardhu_audio_aic326x_pdata,
680         },
681 };
682
683 static struct platform_device *cardhu_devices[] __initdata = {
684         &tegra_pmu_device,
685         &tegra_rtc_device,
686         &tegra_udc_device,
687 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
688         &tegra_smmu_device,
689 #endif
690         &tegra_wdt_device,
691 #if defined(CONFIG_TEGRA_AVP)
692         &tegra_avp_device,
693 #endif
694         &tegra_camera,
695 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
696         &tegra_se_device,
697 #endif
698         &tegra_ahub_device,
699         &tegra_dam_device0,
700         &tegra_dam_device1,
701         &tegra_dam_device2,
702         &tegra_i2s_device0,
703         &tegra_i2s_device1,
704         &tegra_i2s_device3,
705         &tegra_spdif_device,
706         &spdif_dit_device,
707         &bluetooth_dit_device,
708         &baseband_dit_device,
709         &cardhu_bcm4329_rfkill_device,
710         &tegra_pcm_device,
711         &cardhu_audio_wm8903_device,
712         &cardhu_audio_max98095_device,
713         &cardhu_audio_aic326x_device,
714         &tegra_hda_device,
715 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
716         &tegra_aes_device,
717 #endif
718 };
719
720 #define E1506_MXT_CONFIG_CRC 0x62F903
721 static const u8 e1506_config[] = {
722         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
723         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
724         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
725         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
726         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
727         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
728         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
729         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
730         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
731         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
732         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
733         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
734         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
735         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
736         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
737         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
738         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
739         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
740         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
742         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
743         0x00
744 };
745
746 #define MXT_CONFIG_CRC  0xD62DE8
747 static const u8 config[] = {
748         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
749         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
750         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
751         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
752         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
753         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
754         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
755         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
756         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
757         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
758         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
759         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
760         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
761         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
762         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
763         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
764         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
766         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
767         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
768 };
769
770 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
771 static const u8 config_sku2000[] = {
772         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
773         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
774         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
775         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
776         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
777         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
778         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
779         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
780         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
781         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
782         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
783         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
784         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
785         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
786         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
787         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
788         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
789         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
790         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
791         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
792 };
793
794 static struct mxt_platform_data atmel_mxt_info = {
795         .x_line         = 27,
796         .y_line         = 42,
797         .x_size         = 768,
798         .y_size         = 1366,
799         .blen           = 0x20,
800         .threshold      = 0x3C,
801         .voltage        = 3300000,              /* 3.3V */
802         .orient         = 5,
803         .config         = config,
804         .config_length  = 157,
805         .config_crc     = MXT_CONFIG_CRC,
806         .irqflags       = IRQF_TRIGGER_FALLING,
807 /*      .read_chg       = &read_chg, */
808         .read_chg       = NULL,
809 };
810
811 static struct mxt_platform_data e1506_atmel_mxt_info = {
812         .x_line         = 19,
813         .y_line         = 11,
814         .x_size         = 960,
815         .y_size         = 540,
816         .blen           = 0x10,
817         .threshold      = 0x32,
818         .voltage        = 3300000,              /* 3.3V */
819         .orient         = 3,
820         .config         = e1506_config,
821         .config_length  = 168,
822         .config_crc     = E1506_MXT_CONFIG_CRC,
823         .irqflags       = IRQF_TRIGGER_FALLING,
824 /*      .read_chg       = &read_chg, */
825         .read_chg       = NULL,
826 };
827
828 static struct i2c_board_info __initdata atmel_i2c_info[] = {
829         {
830                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
831                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
832                 .platform_data = &atmel_mxt_info,
833         }
834 };
835
836 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
837         {
838                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
839                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
840                 .platform_data = &e1506_atmel_mxt_info,
841         }
842 };
843
844 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
845         /* name         parent          rate            enabled */
846         { "sbc1",       "pll_p",        52000000,       true},
847         { NULL,         NULL,           0,              0},
848 };
849
850 static int __init cardhu_touch_init(void)
851 {
852         struct board_info BoardInfo, DisplayBoardInfo;
853
854         tegra_get_board_info(&BoardInfo);
855         tegra_get_display_board_info(&DisplayBoardInfo);
856         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
857                 tegra_clk_init_from_table(spi_clk_init_table);
858
859                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
860         } else {
861                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
862                 gpio_direction_input(TEGRA_GPIO_PH4);
863
864                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
865                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
866                 msleep(1);
867                 gpio_set_value(TEGRA_GPIO_PH6, 1);
868                 msleep(100);
869
870                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
871                         atmel_mxt_info.config = config_sku2000;
872                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
873                 }
874
875                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506)
876                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
877                 else
878                         i2c_register_board_info(1, atmel_i2c_info, 1);
879         }
880
881         return 0;
882 }
883
884 #if defined(CONFIG_USB_SUPPORT)
885
886 static void cardu_usb_hsic_postsupend(void)
887 {
888 #ifdef CONFIG_TEGRA_BB_XMM_POWER
889         baseband_xmm_set_power_status(BBXMM_PS_L2);
890 #endif
891 }
892
893 static void cardu_usb_hsic_preresume(void)
894 {
895 #ifdef CONFIG_TEGRA_BB_XMM_POWER
896         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
897 #endif
898 }
899
900 static void cardu_usb_hsic_phy_ready(void)
901 {
902 #ifdef CONFIG_TEGRA_BB_XMM_POWER
903         baseband_xmm_set_power_status(BBXMM_PS_L0);
904 #endif
905 }
906
907 static void cardu_usb_hsic_phy_off(void)
908 {
909 #ifdef CONFIG_TEGRA_BB_XMM_POWER
910         baseband_xmm_set_power_status(BBXMM_PS_L3);
911 #endif
912 }
913
914 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
915         .post_suspend = cardu_usb_hsic_postsupend,
916         .pre_resume = cardu_usb_hsic_preresume,
917         .port_power = cardu_usb_hsic_phy_ready,
918         .post_phy_off = cardu_usb_hsic_phy_off,
919 };
920
921 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
922         .port_otg = false,
923         .has_hostpc = true,
924         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
925         .op_mode        = TEGRA_USB_OPMODE_HOST,
926         .u_data.host = {
927                 .vbus_gpio = -1,
928                 .hot_plug = false,
929                 .remote_wakeup_supported = false,
930                 .power_off_on_suspend = false,
931         },
932         .u_cfg.hsic = {
933                 .sync_start_delay = 9,
934                 .idle_wait_delay = 17,
935                 .term_range_adj = 0,
936                 .elastic_underrun_limit = 16,
937                 .elastic_overrun_limit = 16,
938         },
939         .ops = &hsic_xmm_plat_ops,
940 };
941 #endif
942
943 static int hsic_enable_gpio = -1;
944 static int hsic_reset_gpio = -1;
945
946 void hsic_platform_open(void)
947 {
948         int reset_gpio = 0, enable_gpio = 0;
949
950         if (hsic_enable_gpio != -1)
951                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
952         if (hsic_reset_gpio != -1)
953                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
954         /* hsic enable signal deasserted, hsic reset asserted */
955         if (!enable_gpio)
956                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
957         if (!reset_gpio)
958                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
959         if (!enable_gpio)
960                 tegra_gpio_enable(hsic_enable_gpio);
961         if (!reset_gpio)
962                 tegra_gpio_enable(hsic_reset_gpio);
963         /* keep hsic reset asserted for 1 ms */
964         udelay(1000);
965         /* enable (power on) hsic */
966         if (!enable_gpio)
967                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
968         udelay(1000);
969         /* deassert reset */
970         if (!reset_gpio)
971                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
972
973 }
974
975 void hsic_platform_close(void)
976 {
977         if (hsic_enable_gpio != -1) {
978                 gpio_set_value(hsic_enable_gpio, 0);
979                 gpio_free(hsic_enable_gpio);
980         }
981         if (hsic_reset_gpio != -1) {
982                 gpio_set_value(hsic_reset_gpio, 0);
983                 gpio_free(hsic_reset_gpio);
984         }
985 }
986
987 void hsic_power_on(void)
988 {
989         if (hsic_enable_gpio != -1) {
990                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
991                 udelay(1000);
992         }
993 }
994
995 void hsic_power_off(void)
996 {
997         if (hsic_enable_gpio != -1) {
998                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
999                 udelay(1000);
1000         }
1001 }
1002
1003 #if defined(CONFIG_USB_SUPPORT)
1004 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1005         .open = hsic_platform_open,
1006         .close = hsic_platform_close,
1007         .pre_phy_on = hsic_power_on,
1008         .post_phy_off = hsic_power_off,
1009 };
1010
1011 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1012         .port_otg = false,
1013         .has_hostpc = true,
1014         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1015         .op_mode        = TEGRA_USB_OPMODE_HOST,
1016         .u_data.host = {
1017                 .vbus_gpio = -1,
1018                 .hot_plug = false,
1019                 .remote_wakeup_supported = false,
1020                 .power_off_on_suspend = false,
1021         },
1022         .u_cfg.hsic = {
1023                 .sync_start_delay = 9,
1024                 .idle_wait_delay = 17,
1025                 .term_range_adj = 0,
1026                 .elastic_underrun_limit = 16,
1027                 .elastic_overrun_limit = 16,
1028         },
1029         .ops = &hsic_plat_ops,
1030 };
1031
1032 static struct tegra_usb_platform_data tegra_udc_pdata = {
1033         .port_otg = true,
1034         .has_hostpc = true,
1035         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1036         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1037         .u_data.dev = {
1038                 .vbus_pmu_irq = 0,
1039                 .vbus_gpio = -1,
1040                 .charging_supported = false,
1041                 .remote_wakeup_supported = false,
1042         },
1043         .u_cfg.utmi = {
1044                 .hssync_start_delay = 0,
1045                 .elastic_limit = 16,
1046                 .idle_wait_delay = 17,
1047                 .term_range_adj = 6,
1048                 .xcvr_setup = 8,
1049                 .xcvr_lsfslew = 2,
1050                 .xcvr_lsrslew = 2,
1051                 .xcvr_setup_offset = 0,
1052                 .xcvr_use_fuses = 1,
1053         },
1054 };
1055
1056 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1057         .port_otg = false,
1058         .has_hostpc = true,
1059         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1060         .op_mode        = TEGRA_USB_OPMODE_HOST,
1061         .u_data.host = {
1062                 .vbus_gpio = -1,
1063                 .hot_plug = false,
1064                 .remote_wakeup_supported = true,
1065                 .power_off_on_suspend = true,
1066         },
1067         .u_cfg.utmi = {
1068                 .hssync_start_delay = 0,
1069                 .elastic_limit = 16,
1070                 .idle_wait_delay = 17,
1071                 .term_range_adj = 6,
1072                 .xcvr_setup = 15,
1073                 .xcvr_lsfslew = 2,
1074                 .xcvr_lsrslew = 2,
1075                 .xcvr_setup_offset = 0,
1076                 .xcvr_use_fuses = 1,
1077         },
1078 };
1079
1080 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1081         .port_otg = false,
1082         .has_hostpc = true,
1083         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1084         .op_mode = TEGRA_USB_OPMODE_HOST,
1085         .u_data.host = {
1086                 .vbus_gpio = -1,
1087                 .vbus_reg = "vdd_vbus_typea_usb",
1088                 .hot_plug = true,
1089                 .remote_wakeup_supported = true,
1090                 .power_off_on_suspend = true,
1091         },
1092         .u_cfg.utmi = {
1093                 .hssync_start_delay = 0,
1094                 .elastic_limit = 16,
1095                 .idle_wait_delay = 17,
1096                 .term_range_adj = 6,
1097                 .xcvr_setup = 8,
1098                 .xcvr_lsfslew = 2,
1099                 .xcvr_lsrslew = 2,
1100                 .xcvr_setup_offset = 0,
1101                 .xcvr_use_fuses = 1,
1102         },
1103 };
1104
1105 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1106         .port_otg = true,
1107         .has_hostpc = true,
1108         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1109         .op_mode = TEGRA_USB_OPMODE_HOST,
1110         .u_data.host = {
1111                 .vbus_gpio = -1,
1112                 .vbus_reg = "vdd_vbus_micro_usb",
1113                 .hot_plug = true,
1114                 .remote_wakeup_supported = true,
1115                 .power_off_on_suspend = true,
1116         },
1117         .u_cfg.utmi = {
1118                 .hssync_start_delay = 0,
1119                 .elastic_limit = 16,
1120                 .idle_wait_delay = 17,
1121                 .term_range_adj = 6,
1122                 .xcvr_setup = 15,
1123                 .xcvr_lsfslew = 2,
1124                 .xcvr_lsrslew = 2,
1125                 .xcvr_setup_offset = 0,
1126                 .xcvr_use_fuses = 1,
1127         },
1128 };
1129
1130 static struct tegra_usb_otg_data tegra_otg_pdata = {
1131         .ehci_device = &tegra_ehci1_device,
1132         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1133 };
1134 #endif
1135
1136 #if defined(CONFIG_USB_SUPPORT)
1137 static void cardhu_usb_init(void)
1138 {
1139         struct board_info bi;
1140
1141         tegra_get_board_info(&bi);
1142
1143         /* OTG should be the first to be registered */
1144         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1145         platform_device_register(&tegra_otg_device);
1146
1147         /* setup the udc platform data */
1148         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1149
1150         if (bi.board_id == BOARD_PM267) {
1151                 hsic_enable_gpio = EN_HSIC_GPIO;
1152                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1153                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1154                 platform_device_register(&tegra_ehci2_device);
1155         } else if (bi.board_id == BOARD_E1256) {
1156                 hsic_enable_gpio = EN_HSIC_GPIO;
1157                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1158                 platform_device_register(&tegra_ehci2_device);
1159         } else if (bi.board_id == BOARD_E1186) {
1160                 tegra_ehci2_device.dev.platform_data =
1161                                                 &tegra_ehci2_hsic_xmm_pdata;
1162                 /* ehci2 registration happens in baseband-xmm-power  */
1163         } else {
1164                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1165                 platform_device_register(&tegra_ehci2_device);
1166         }
1167
1168         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1169         platform_device_register(&tegra_ehci3_device);
1170
1171 }
1172 #else
1173 static void cardhu_usb_init(void) { }
1174 #endif
1175
1176 static struct baseband_power_platform_data tegra_baseband_power_data = {
1177         .baseband_type = BASEBAND_XMM,
1178         .modem = {
1179         .xmm = {
1180                         .bb_rst = XMM_GPIO_BB_RST,
1181                         .bb_on = XMM_GPIO_BB_ON,
1182                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1183                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1184                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1185                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1186                         .hsic_device = &tegra_ehci2_device,
1187                 },
1188         },
1189 };
1190
1191 static struct platform_device tegra_baseband_power_device = {
1192         .name = "baseband_xmm_power",
1193         .id = -1,
1194         .dev = {
1195                 .platform_data = &tegra_baseband_power_data,
1196         },
1197 };
1198
1199 static struct platform_device tegra_baseband_power2_device = {
1200         .name = "baseband_xmm_power2",
1201         .id = -1,
1202         .dev = {
1203                 .platform_data = &tegra_baseband_power_data,
1204         },
1205 };
1206
1207
1208 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1209         .port_status[0] = 1,
1210         .port_status[1] = 1,
1211         .port_status[2] = 1,
1212         .use_dock_detect        = 0,
1213         .gpio           = 0,
1214 };
1215
1216 static void cardhu_pci_init(void)
1217 {
1218         struct board_info board_info;
1219
1220         tegra_get_board_info(&board_info);
1221         if (board_info.board_id == BOARD_E1291) {
1222                 cardhu_pci_platform_data.port_status[0] = 0;
1223                 cardhu_pci_platform_data.port_status[1] = 0;
1224                 cardhu_pci_platform_data.port_status[2] = 1;
1225                 cardhu_pci_platform_data.use_dock_detect = 1;
1226                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1227         }
1228         if ((board_info.board_id == BOARD_E1186) ||
1229                 (board_info.board_id == BOARD_E1187) ||
1230                 (board_info.board_id == BOARD_E1291)) {
1231                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1232                 platform_device_register(&tegra_pci_device);
1233         }
1234 }
1235
1236 static void cardhu_modem_init(void)
1237 {
1238         struct board_info board_info;
1239         int w_disable_gpio, ret;
1240
1241         tegra_get_board_info(&board_info);
1242         switch (board_info.board_id) {
1243         case BOARD_E1291:
1244         case BOARD_E1198:
1245                 if (((board_info.board_id == BOARD_E1291) &&
1246                                 (board_info.fab < BOARD_FAB_A03)) ||
1247                         ((board_info.board_id == BOARD_E1198) &&
1248                                         (board_info.fab < BOARD_FAB_A02))) {
1249                         w_disable_gpio = TEGRA_GPIO_PH5;
1250                 } else {
1251                         w_disable_gpio = TEGRA_GPIO_PDD5;
1252                 }
1253
1254                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1255                 if (ret < 0)
1256                         pr_err("%s: gpio_request failed for gpio %d\n",
1257                                 __func__, w_disable_gpio);
1258                 else
1259                         gpio_direction_input(w_disable_gpio);
1260
1261                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1262                 if (((board_info.board_id == BOARD_E1291) &&
1263                                 (board_info.fab >= BOARD_FAB_A04)) ||
1264                         ((board_info.board_id == BOARD_E1198) &&
1265                                         (board_info.fab >= BOARD_FAB_A02))) {
1266                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1267                         if (ret < 0) {
1268                                 pr_err("%s(): Error in allocating gpio "
1269                                         "TEGRA_GPIO_PH7\n", __func__);
1270                                 break;
1271                         }
1272                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1273                 }
1274                 break;
1275         case BOARD_E1186:
1276                 platform_device_register(&tegra_baseband_power_device);
1277                 platform_device_register(&tegra_baseband_power2_device);
1278                 break;
1279         default:
1280                 break;
1281         }
1282
1283 }
1284
1285 #ifdef CONFIG_SATA_AHCI_TEGRA
1286 static void cardhu_sata_init(void)
1287 {
1288         platform_device_register(&tegra_sata_device);
1289 }
1290 #else
1291 static void cardhu_sata_init(void) { }
1292 #endif
1293
1294 static void __init tegra_cardhu_init(void)
1295 {
1296         tegra_thermal_init(&thermal_data);
1297         tegra_clk_init_from_table(cardhu_clk_init_table);
1298         cardhu_pinmux_init();
1299         cardhu_i2c_init();
1300         cardhu_spi_init();
1301         cardhu_usb_init();
1302 #ifdef CONFIG_TEGRA_EDP_LIMITS
1303         cardhu_edp_init();
1304 #endif
1305         cardhu_uart_init();
1306         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1307         tegra_ram_console_debug_init();
1308         cardhu_sdhci_init();
1309         cardhu_regulator_init();
1310         cardhu_dtv_init();
1311         cardhu_suspend_init();
1312         cardhu_touch_init();
1313         cardhu_modem_init();
1314         cardhu_kbc_init();
1315         cardhu_scroll_init();
1316         cardhu_keys_init();
1317         cardhu_panel_init();
1318         cardhu_pmon_init();
1319         cardhu_sensors_init();
1320         cardhu_setup_bluesleep();
1321         cardhu_sata_init();
1322         //audio_wired_jack_init();
1323         cardhu_pins_state_init();
1324         cardhu_emc_init();
1325         tegra_release_bootloader_fb();
1326         cardhu_pci_init();
1327 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1328         tegra_wdt_recovery_init();
1329 #endif
1330 }
1331
1332 static void __init tegra_cardhu_reserve(void)
1333 {
1334 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1335         /* support 1920X1200 with 24bpp */
1336         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1337 #else
1338         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1339 #endif
1340         tegra_ram_console_debug_reserve(SZ_1M);
1341 }
1342
1343 MACHINE_START(CARDHU, "cardhu")
1344         .boot_params    = 0x80000100,
1345         .map_io         = tegra_map_common_io,
1346         .reserve        = tegra_cardhu_reserve,
1347         .init_early     = tegra_init_early,
1348         .init_irq       = tegra_init_irq,
1349         .timer          = &tegra_timer,
1350         .init_machine   = tegra_cardhu_init,
1351 MACHINE_END