arm: tegra: use rfkill-gpio driver to register bluetooth rfkill
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/clk.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/iomap.h>
55 #include <mach/io.h>
56 #include <mach/i2s.h>
57 #include <mach/tegra_asoc_pdata.h>
58 #include <mach/tegra_wm8903_pdata.h>
59 #include <mach/usb_phy.h>
60 #include <mach/thermal.h>
61 #include <mach/pci.h>
62 #include <mach/gpio-tegra.h>
63
64 #include <asm/hardware/gic.h>
65 #include <asm/mach-types.h>
66 #include <asm/mach/arch.h>
67
68 #include "board.h"
69 #include "clock.h"
70 #include "board-cardhu.h"
71 #include "board-touch.h"
72 #include "devices.h"
73 #include "gpio-names.h"
74 #include "fuse.h"
75 #include "pm.h"
76 #include "baseband-xmm-power.h"
77 #include "wdt-recovery.h"
78 #include "common.h"
79
80 /* All units are in millicelsius */
81 static struct tegra_thermal_data thermal_data = {
82         .temp_shutdown = 90000,
83         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
84 #ifdef CONFIG_TEGRA_EDP_LIMITS
85         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
86         .hysteresis_edp = 3000,
87 #endif
88 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
89         .temp_throttle = 85000,
90         .tc1 = 0,
91         .tc2 = 1,
92         .passive_delay = 2000,
93 #endif
94 };
95
96 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
97         {
98                 .name           = "bt_rfkill",
99                 .shutdown_gpio  = TEGRA_GPIO_PU0,
100                 .reset_gpio     = TEGRA_GPIO_INVALID,
101                 .type           = RFKILL_TYPE_BLUETOOTH,
102         },
103 };
104
105 static struct platform_device cardhu_bt_rfkill_device = {
106         .name = "rfkill_gpio",
107         .id             = -1,
108         .dev = {
109                 .platform_data = &cardhu_bt_rfkill_pdata,
110         },
111 };
112
113 static struct resource cardhu_bluesleep_resources[] = {
114         [0] = {
115                 .name = "gpio_host_wake",
116                         .start  = TEGRA_GPIO_PU6,
117                         .end    = TEGRA_GPIO_PU6,
118                         .flags  = IORESOURCE_IO,
119         },
120         [1] = {
121                 .name = "gpio_ext_wake",
122                         .start  = TEGRA_GPIO_PU1,
123                         .end    = TEGRA_GPIO_PU1,
124                         .flags  = IORESOURCE_IO,
125         },
126         [2] = {
127                 .name = "host_wake",
128                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
129         },
130 };
131
132 static struct platform_device cardhu_bluesleep_device = {
133         .name           = "bluesleep",
134         .id             = -1,
135         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
136         .resource       = cardhu_bluesleep_resources,
137 };
138
139 static noinline void __init cardhu_setup_bluesleep(void)
140 {
141         cardhu_bluesleep_resources[2].start =
142                 cardhu_bluesleep_resources[2].end =
143                         gpio_to_irq(TEGRA_GPIO_PU6);
144         platform_device_register(&cardhu_bluesleep_device);
145         return;
146 }
147
148 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
149         /* name         parent          rate            enabled */
150         { "pll_m",      NULL,           0,              false},
151         { "hda",        "pll_p",        108000000,      false},
152         { "hda2codec_2x","pll_p",       48000000,       false},
153         { "pwm",        "pll_p",        3187500,        false},
154         { "blink",      "clk_32k",      32768,          true},
155         { "i2s0",       "pll_a_out0",   0,              false},
156         { "i2s1",       "pll_a_out0",   0,              false},
157         { "i2s3",       "pll_a_out0",   0,              false},
158         { "spdif_out",  "pll_a_out0",   0,              false},
159         { "d_audio",    "clk_m",        12000000,       false},
160         { "dam0",       "clk_m",        12000000,       false},
161         { "dam1",       "clk_m",        12000000,       false},
162         { "dam2",       "clk_m",        12000000,       false},
163         { "audio1",     "i2s1_sync",    0,              false},
164         { "audio3",     "i2s3_sync",    0,              false},
165         { "vi_sensor",  "pll_p",        150000000,      false},
166         { "i2c1",       "pll_p",        3200000,        false},
167         { "i2c2",       "pll_p",        3200000,        false},
168         { "i2c3",       "pll_p",        3200000,        false},
169         { "i2c4",       "pll_p",        3200000,        false},
170         { "i2c5",       "pll_p",        3200000,        false},
171         { NULL,         NULL,           0,              0},
172 };
173
174 static struct pn544_i2c_platform_data nfc_pdata = {
175         .irq_gpio = TEGRA_GPIO_PX0,
176         .ven_gpio = TEGRA_GPIO_PP3,
177         .firm_gpio = TEGRA_GPIO_PO7,
178         };
179
180 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
181         {
182                 I2C_BOARD_INFO("pn544", 0x28),
183                 .platform_data = &nfc_pdata,
184         },
185 };
186 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
187         .adapter_nr     = 0,
188         .bus_count      = 1,
189         .bus_clk_rate   = { 100000, 0 },
190         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
191         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
192         .arb_recovery = arb_lost_recovery,
193 };
194
195 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
196         .adapter_nr     = 1,
197         .bus_count      = 1,
198         .bus_clk_rate   = { 400000, 0 },
199         .is_clkon_always = true,
200         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
201         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
202         .arb_recovery = arb_lost_recovery,
203 };
204
205 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
206         .adapter_nr     = 2,
207         .bus_count      = 1,
208         .bus_clk_rate   = { 100000, 0 },
209         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
210         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
211         .arb_recovery = arb_lost_recovery,
212 };
213
214 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
215         .adapter_nr     = 3,
216         .bus_count      = 1,
217         .bus_clk_rate   = { 10000, 0 },
218         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
219         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
220         .arb_recovery = arb_lost_recovery,
221 };
222
223 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
224         .adapter_nr     = 4,
225         .bus_count      = 1,
226         .bus_clk_rate   = { 400000, 0 },
227         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
228         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
229         .arb_recovery = arb_lost_recovery,
230 };
231
232
233 #if 0
234 struct tegra_wired_jack_conf audio_wr_jack_conf = {
235         .hp_det_n = TEGRA_GPIO_PW2,
236         .en_mic_ext = TEGRA_GPIO_PX1,
237         .en_mic_int = TEGRA_GPIO_PX0,
238 };
239 #endif
240
241 static struct wm8903_platform_data cardhu_wm8903_pdata = {
242         .irq_active_low = 0,
243         .micdet_cfg = 0,
244         .micdet_delay = 100,
245         .gpio_base = CARDHU_GPIO_WM8903(0),
246         .gpio_cfg = {
247                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
248                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
249                         WM8903_GP2_DIR,
250                 WM8903_GPIO_CONFIG_ZERO,
251                 0,
252                 0,
253         },
254 };
255
256 /* Equalizer filter coefs generated from the MAXIM MAX98095
257  * evkit software tool */
258 static struct max98095_eq_cfg max98095_eq_cfg[] = {
259         {
260                 .name = "FLAT",
261                 .rate = 44100,
262                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
263                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
264                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
265                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
266                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
267         },
268         {
269                 .name = "LOWPASS1K",
270                 .rate = 44100,
271                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
272                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
273                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
274                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
275                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
276         },
277         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
278                 .name = "HIBOOST",
279                 .rate = 44100,
280                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
281                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
282                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
283                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
284                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
285         },
286         { /* BASS=12dB, TREBLE=+12dB */
287                 .name = "LOUD12DB",
288                 .rate = 44100,
289                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
290                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
291                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
292                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
293                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
294         },
295         {
296                 .name = "FLAT",
297                 .rate = 16000,
298                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
299                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
300                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
301                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
302                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
303         },
304         {
305                 .name = "LOWPASS1K",
306                 .rate = 16000,
307                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
308                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
309                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
310                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
311                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
312         },
313         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
314                 .name = "HIBOOST",
315                 .rate = 16000,
316                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
317                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
318                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
319                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
320                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
321         },
322         { /* BASS=12dB, TREBLE=+12dB */
323                 .name = "LOUD12DB",
324                 .rate = 16000,
325                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
326                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
327                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
328                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
329                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
330         },
331 };
332
333 static struct max98095_pdata cardhu_max98095_pdata = {
334         /* equalizer configuration */
335         .eq_cfg = max98095_eq_cfg,
336         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
337
338         /* Biquad filter response configuration */
339         .bq_cfg = NULL,
340         .bq_cfgcnt = 0,
341
342         /* microphone configuration */
343         .digmic_left_mode = 1,
344         .digmic_right_mode = 1,
345 };
346
347 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
348         I2C_BOARD_INFO("wm8903", 0x1a),
349         .platform_data = &cardhu_wm8903_pdata,
350 };
351
352 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
353         I2C_BOARD_INFO("aic3262-codec", 0x18),
354 };
355
356 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
357         I2C_BOARD_INFO("max98095", 0x10),
358         .platform_data = &cardhu_max98095_pdata,
359 };
360
361 static void cardhu_i2c_init(void)
362 {
363         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
364         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
365         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
366         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
367         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
368
369         platform_device_register(&tegra_i2c_device5);
370         platform_device_register(&tegra_i2c_device4);
371         platform_device_register(&tegra_i2c_device3);
372         platform_device_register(&tegra_i2c_device2);
373         platform_device_register(&tegra_i2c_device1);
374
375         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
376                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
377         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
378         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
379         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
380
381         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
382         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
383 }
384
385 static struct platform_device *cardhu_uart_devices[] __initdata = {
386         &tegra_uarta_device,
387         &tegra_uartb_device,
388         &tegra_uartc_device,
389         &tegra_uartd_device,
390         &tegra_uarte_device,
391 };
392 static struct uart_clk_parent uart_parent_clk[] = {
393         [0] = {.name = "clk_m"},
394         [1] = {.name = "pll_p"},
395 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
396         [2] = {.name = "pll_m"},
397 #endif
398 };
399
400 static struct tegra_uart_platform_data cardhu_uart_pdata;
401 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
402
403 static void __init uart_debug_init(void)
404 {
405         struct board_info board_info;
406         int debug_port_id;
407
408         tegra_get_board_info(&board_info);
409
410         debug_port_id = get_tegra_uart_debug_port_id();
411         if (debug_port_id < 0) {
412                 debug_port_id = 0;
413                         /* UARTB is debug port
414                          *       for SLT - E1186/E1187/PM269
415                          *       for E1256/E1257
416                          */
417                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
418                         ((board_info.board_id == BOARD_E1186) ||
419                         (board_info.board_id == BOARD_E1187) ||
420                         (board_info.board_id == BOARD_PM269))) ||
421                         (board_info.board_id == BOARD_E1256) ||
422                         (board_info.board_id == BOARD_E1257))
423                                 debug_port_id = 1;
424         }
425
426         switch (debug_port_id) {
427         case 0:
428                 /* UARTA is the debug port. */
429                 pr_info("Selecting UARTA as the debug console\n");
430                 cardhu_uart_devices[0] = &debug_uarta_device;
431                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
432                 debug_uart_port_base = ((struct plat_serial8250_port *)(
433                         debug_uarta_device.dev.platform_data))->mapbase;
434                 break;
435
436         case 1:
437                 /* UARTB is the debug port. */
438                 pr_info("Selecting UARTB as the debug console\n");
439                 cardhu_uart_devices[1] = &debug_uartb_device;
440                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
441                 debug_uart_port_base = ((struct plat_serial8250_port *)(
442                         debug_uartb_device.dev.platform_data))->mapbase;
443                 break;
444
445         case 2:
446                 /* UARTC is the debug port. */
447                 pr_info("Selecting UARTC as the debug console\n");
448                 cardhu_uart_devices[2] = &debug_uartc_device;
449                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
450                 debug_uart_port_base = ((struct plat_serial8250_port *)(
451                         debug_uartc_device.dev.platform_data))->mapbase;
452                 break;
453
454         case 3:
455                 /* UARTD is the debug port. */
456                 pr_info("Selecting UARTD as the debug console\n");
457                 cardhu_uart_devices[3] = &debug_uartd_device;
458                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
459                 debug_uart_port_base = ((struct plat_serial8250_port *)(
460                         debug_uartd_device.dev.platform_data))->mapbase;
461                 break;
462
463         case 4:
464                 /* UARTE is the debug port. */
465                 pr_info("Selecting UARTE as the debug console\n");
466                 cardhu_uart_devices[4] = &debug_uarte_device;
467                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
468                 debug_uart_port_base = ((struct plat_serial8250_port *)(
469                         debug_uarte_device.dev.platform_data))->mapbase;
470                 break;
471
472         default:
473                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
474                 cardhu_uart_devices[0] = &debug_uarta_device;
475                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
476                 debug_uart_port_base = ((struct plat_serial8250_port *)(
477                         debug_uarta_device.dev.platform_data))->mapbase;
478                 break;
479         }
480         return;
481 }
482
483 static void __init cardhu_uart_init(void)
484 {
485         struct clk *c;
486         int i;
487
488         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
489                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
490                 if (IS_ERR_OR_NULL(c)) {
491                         pr_err("Not able to get the clock for %s\n",
492                                                 uart_parent_clk[i].name);
493                         continue;
494                 }
495                 uart_parent_clk[i].parent_clk = c;
496                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
497         }
498         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
499         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
500         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
501         cardhu_loopback_uart_pdata.parent_clk_count =
502                                                 ARRAY_SIZE(uart_parent_clk);
503         cardhu_loopback_uart_pdata.is_loopback = true;
504         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
505         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
506         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
507         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
508         /* UARTE is used for loopback test purpose */
509         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
510
511         /* Register low speed only if it is selected */
512         if (!is_tegra_debug_uartport_hs()) {
513                 uart_debug_init();
514                 /* Clock enable for the debug channel */
515                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
516                         pr_info("The debug console clock name is %s\n",
517                                                 debug_uart_clk->name);
518                         c = tegra_get_clock_by_name("pll_p");
519                         if (IS_ERR_OR_NULL(c))
520                                 pr_err("Not getting the parent clock pll_p\n");
521                         else
522                                 clk_set_parent(debug_uart_clk, c);
523
524                         clk_enable(debug_uart_clk);
525                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
526                 } else {
527                         pr_err("Not getting the clock %s for debug console\n",
528                                         debug_uart_clk->name);
529                 }
530         }
531
532         platform_add_devices(cardhu_uart_devices,
533                                 ARRAY_SIZE(cardhu_uart_devices));
534 }
535
536 static struct platform_device tegra_camera = {
537         .name = "tegra_camera",
538         .id = -1,
539 };
540
541 static struct platform_device *cardhu_spi_devices[] __initdata = {
542         &tegra_spi_device4,
543 };
544
545 static struct platform_device *touch_spi_device[] __initdata = {
546         &tegra_spi_device1,
547 };
548
549 struct spi_clk_parent spi_parent_clk[] = {
550         [0] = {.name = "pll_p"},
551 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
552         [1] = {.name = "pll_m"},
553         [2] = {.name = "clk_m"},
554 #else
555         [1] = {.name = "clk_m"},
556 #endif
557 };
558
559 static struct tegra_spi_platform_data cardhu_spi_pdata = {
560         .is_dma_based           = true,
561         .max_dma_buffer         = (16 * 1024),
562         .is_clkon_always        = false,
563         .max_rate               = 100000000,
564 };
565
566 static void __init cardhu_spi_init(void)
567 {
568         int i;
569         struct clk *c;
570         struct board_info board_info, display_board_info;
571
572         tegra_get_board_info(&board_info);
573         tegra_get_display_board_info(&display_board_info);
574
575         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
576                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
577                 if (IS_ERR_OR_NULL(c)) {
578                         pr_err("Not able to get the clock for %s\n",
579                                                 spi_parent_clk[i].name);
580                         continue;
581                 }
582                 spi_parent_clk[i].parent_clk = c;
583                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
584         }
585         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
586         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
587         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
588         platform_add_devices(cardhu_spi_devices,
589                                 ARRAY_SIZE(cardhu_spi_devices));
590
591         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
592                 platform_add_devices(touch_spi_device,
593                                 ARRAY_SIZE(touch_spi_device));
594         }
595         if (board_info.board_id == BOARD_E1198) {
596                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
597                 platform_device_register(&tegra_spi_device2);
598                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
599                 platform_device_register(&tegra_spi_slave_device1);
600         }
601 }
602
603 static void __init cardhu_dtv_init(void)
604 {
605         struct board_info board_info;
606
607         tegra_get_board_info(&board_info);
608
609         if (board_info.board_id == BOARD_E1186)
610                 platform_device_register(&tegra_dtv_device);
611 }
612
613 static struct resource tegra_rtc_resources[] = {
614         [0] = {
615                 .start = TEGRA_RTC_BASE,
616                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
617                 .flags = IORESOURCE_MEM,
618         },
619         [1] = {
620                 .start = INT_RTC,
621                 .end = INT_RTC,
622                 .flags = IORESOURCE_IRQ,
623         },
624 };
625
626 static struct platform_device tegra_rtc_device = {
627         .name = "tegra_rtc",
628         .id   = -1,
629         .resource = tegra_rtc_resources,
630         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
631 };
632
633 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
634         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
635         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
636         .gpio_hp_mute           = -1,
637         .gpio_int_mic_en        = -1,
638         .gpio_ext_mic_en        = -1,
639 };
640
641 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
642         .gpio_spkr_en           = -1,
643         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
644         .gpio_hp_mute           = -1,
645         .gpio_int_mic_en        = -1,
646         .gpio_ext_mic_en        = -1,
647 };
648
649 static struct platform_device cardhu_audio_wm8903_device = {
650         .name   = "tegra-snd-wm8903",
651         .id     = 0,
652         .dev    = {
653                 .platform_data = &cardhu_audio_wm8903_pdata,
654         },
655 };
656
657 static struct platform_device cardhu_audio_max98095_device = {
658         .name   = "tegra-snd-max98095",
659         .id     = 0,
660         .dev    = {
661                 .platform_data = &cardhu_audio_max98095_pdata,
662         },
663 };
664
665 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
666         .gpio_spkr_en           = -1,
667         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
668         .gpio_hp_mute           = -1,
669         .gpio_int_mic_en        = -1,
670         .gpio_ext_mic_en        = -1,
671         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
672         .audio_port_id          = {
673                 [HIFI_CODEC] = 0,
674                 [BASEBAND] = -1,
675                 [BT_SCO] = 3,
676         },
677         .baseband_param         = {
678                 .rate = -1,
679                 .channels = -1,
680         },
681 };
682
683 static struct platform_device cardhu_audio_aic326x_device = {
684         .name   = "tegra-snd-aic326x",
685         .id     = 0,
686         .dev    = {
687                 .platform_data  = &cardhu_audio_aic326x_pdata,
688         },
689 };
690
691 static struct platform_device *cardhu_devices[] __initdata = {
692         &tegra_pmu_device,
693         &tegra_rtc_device,
694         &tegra_udc_device,
695 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
696         &tegra_smmu_device,
697 #endif
698         &tegra_wdt_device,
699 #if defined(CONFIG_TEGRA_AVP)
700         &tegra_avp_device,
701 #endif
702         &tegra_camera,
703 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
704         &tegra_se_device,
705 #endif
706         &tegra_ahub_device,
707         &tegra_dam_device0,
708         &tegra_dam_device1,
709         &tegra_dam_device2,
710         &tegra_i2s_device0,
711         &tegra_i2s_device1,
712         &tegra_i2s_device3,
713         &tegra_spdif_device,
714         &spdif_dit_device,
715         &bluetooth_dit_device,
716         &baseband_dit_device,
717         &cardhu_bt_rfkill_device,
718         &tegra_pcm_device,
719         &cardhu_audio_wm8903_device,
720         &cardhu_audio_max98095_device,
721         &cardhu_audio_aic326x_device,
722         &tegra_hda_device,
723 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
724         &tegra_aes_device,
725 #endif
726 };
727
728 #define E1506_MXT_CONFIG_CRC 0x62F903
729 static const u8 e1506_config[] = {
730         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
731         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
732         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
733         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
734         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
735         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
736         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
737         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
738         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
739         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
740         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
742         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
743         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
744         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
745         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
746         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
747         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
748         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
749         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
750         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
751         0x00
752 };
753
754 #define MXT_CONFIG_CRC  0xD62DE8
755 static const u8 config[] = {
756         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
757         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
758         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
759         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
760         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
761         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
762         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
763         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
764         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
766         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
767         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
768         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
769         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
770         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
771         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
772         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
773         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
774         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
775         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
776 };
777
778 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
779 static const u8 config_sku2000[] = {
780         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
781         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
782         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
783         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
784         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
785         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
786         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
787         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
788         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
789         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
790         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
791         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
792         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
793         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
794         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
795         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
796         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
797         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
798         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
799         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
800 };
801
802 static struct mxt_platform_data atmel_mxt_info = {
803         .x_line         = 27,
804         .y_line         = 42,
805         .x_size         = 768,
806         .y_size         = 1366,
807         .blen           = 0x20,
808         .threshold      = 0x3C,
809         .voltage        = 3300000,              /* 3.3V */
810         .orient         = 5,
811         .config         = config,
812         .config_length  = 157,
813         .config_crc     = MXT_CONFIG_CRC,
814         .irqflags       = IRQF_TRIGGER_FALLING,
815 /*      .read_chg       = &read_chg, */
816         .read_chg       = NULL,
817 };
818
819 static struct mxt_platform_data e1506_atmel_mxt_info = {
820         .x_line         = 19,
821         .y_line         = 11,
822         .x_size         = 960,
823         .y_size         = 540,
824         .blen           = 0x10,
825         .threshold      = 0x32,
826         .voltage        = 3300000,              /* 3.3V */
827         .orient         = 3,
828         .config         = e1506_config,
829         .config_length  = 168,
830         .config_crc     = E1506_MXT_CONFIG_CRC,
831         .irqflags       = IRQF_TRIGGER_FALLING,
832 /*      .read_chg       = &read_chg, */
833         .read_chg       = NULL,
834 };
835
836 static struct i2c_board_info __initdata atmel_i2c_info[] = {
837         {
838                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
839                 .platform_data = &atmel_mxt_info,
840         }
841 };
842
843 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
844         {
845                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
846                 .platform_data = &e1506_atmel_mxt_info,
847         }
848 };
849
850 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
851         /* name         parent          rate            enabled */
852         { "sbc1",       "pll_p",        52000000,       true},
853         { NULL,         NULL,           0,              0},
854 };
855
856 static int __init cardhu_touch_init(void)
857 {
858         struct board_info BoardInfo, DisplayBoardInfo;
859
860         tegra_get_board_info(&BoardInfo);
861         tegra_get_display_board_info(&DisplayBoardInfo);
862         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
863                 tegra_clk_init_from_table(spi_clk_init_table);
864
865                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
866         } else {
867                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
868                 gpio_direction_input(TEGRA_GPIO_PH4);
869
870                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
871                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
872                 msleep(1);
873                 gpio_set_value(TEGRA_GPIO_PH6, 1);
874                 msleep(100);
875
876                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
877                         atmel_mxt_info.config = config_sku2000;
878                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
879                 }
880
881                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
882                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
883                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
884                 } else {
885                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
886                         i2c_register_board_info(1, atmel_i2c_info, 1);
887                 }
888         }
889
890         return 0;
891 }
892
893 #if defined(CONFIG_USB_SUPPORT)
894
895 static void cardu_usb_hsic_postsupend(void)
896 {
897 #ifdef CONFIG_TEGRA_BB_XMM_POWER
898         baseband_xmm_set_power_status(BBXMM_PS_L2);
899 #endif
900 }
901
902 static void cardu_usb_hsic_preresume(void)
903 {
904 #ifdef CONFIG_TEGRA_BB_XMM_POWER
905         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
906 #endif
907 }
908
909 static void cardu_usb_hsic_phy_ready(void)
910 {
911 #ifdef CONFIG_TEGRA_BB_XMM_POWER
912         baseband_xmm_set_power_status(BBXMM_PS_L0);
913 #endif
914 }
915
916 static void cardu_usb_hsic_phy_off(void)
917 {
918 #ifdef CONFIG_TEGRA_BB_XMM_POWER
919         baseband_xmm_set_power_status(BBXMM_PS_L3);
920 #endif
921 }
922
923 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
924         .post_suspend = cardu_usb_hsic_postsupend,
925         .pre_resume = cardu_usb_hsic_preresume,
926         .port_power = cardu_usb_hsic_phy_ready,
927         .post_phy_off = cardu_usb_hsic_phy_off,
928 };
929
930 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
931         .port_otg = false,
932         .has_hostpc = true,
933         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
934         .op_mode        = TEGRA_USB_OPMODE_HOST,
935         .u_data.host = {
936                 .vbus_gpio = -1,
937                 .hot_plug = false,
938                 .remote_wakeup_supported = false,
939                 .power_off_on_suspend = false,
940         },
941         .u_cfg.hsic = {
942                 .sync_start_delay = 9,
943                 .idle_wait_delay = 17,
944                 .term_range_adj = 0,
945                 .elastic_underrun_limit = 16,
946                 .elastic_overrun_limit = 16,
947         },
948         .ops = &hsic_xmm_plat_ops,
949 };
950 #endif
951
952 static int hsic_enable_gpio = -1;
953 static int hsic_reset_gpio = -1;
954
955 void hsic_platform_open(void)
956 {
957         int reset_gpio = 0, enable_gpio = 0;
958
959         if (hsic_enable_gpio != -1)
960                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
961         if (hsic_reset_gpio != -1)
962                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
963         /* hsic enable signal deasserted, hsic reset asserted */
964         if (!enable_gpio)
965                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
966         if (!reset_gpio)
967                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
968         if (!enable_gpio)
969                 tegra_gpio_enable(hsic_enable_gpio);
970         if (!reset_gpio)
971                 tegra_gpio_enable(hsic_reset_gpio);
972         /* keep hsic reset asserted for 1 ms */
973         udelay(1000);
974         /* enable (power on) hsic */
975         if (!enable_gpio)
976                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
977         udelay(1000);
978         /* deassert reset */
979         if (!reset_gpio)
980                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
981
982 }
983
984 void hsic_platform_close(void)
985 {
986         if (hsic_enable_gpio != -1) {
987                 gpio_set_value(hsic_enable_gpio, 0);
988                 gpio_free(hsic_enable_gpio);
989         }
990         if (hsic_reset_gpio != -1) {
991                 gpio_set_value(hsic_reset_gpio, 0);
992                 gpio_free(hsic_reset_gpio);
993         }
994 }
995
996 void hsic_power_on(void)
997 {
998         if (hsic_enable_gpio != -1) {
999                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1000                 udelay(1000);
1001         }
1002 }
1003
1004 void hsic_power_off(void)
1005 {
1006         if (hsic_enable_gpio != -1) {
1007                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1008                 udelay(1000);
1009         }
1010 }
1011
1012 #if defined(CONFIG_USB_SUPPORT)
1013 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1014         .open = hsic_platform_open,
1015         .close = hsic_platform_close,
1016         .pre_phy_on = hsic_power_on,
1017         .post_phy_off = hsic_power_off,
1018 };
1019
1020 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1021         .port_otg = false,
1022         .has_hostpc = true,
1023         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1024         .op_mode        = TEGRA_USB_OPMODE_HOST,
1025         .u_data.host = {
1026                 .vbus_gpio = -1,
1027                 .hot_plug = false,
1028                 .remote_wakeup_supported = false,
1029                 .power_off_on_suspend = false,
1030         },
1031         .u_cfg.hsic = {
1032                 .sync_start_delay = 9,
1033                 .idle_wait_delay = 17,
1034                 .term_range_adj = 0,
1035                 .elastic_underrun_limit = 16,
1036                 .elastic_overrun_limit = 16,
1037         },
1038         .ops = &hsic_plat_ops,
1039 };
1040
1041 static struct tegra_usb_platform_data tegra_udc_pdata = {
1042         .port_otg = true,
1043         .has_hostpc = true,
1044         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1045         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1046         .u_data.dev = {
1047                 .vbus_pmu_irq = 0,
1048                 .vbus_gpio = -1,
1049                 .charging_supported = false,
1050                 .remote_wakeup_supported = false,
1051         },
1052         .u_cfg.utmi = {
1053                 .hssync_start_delay = 0,
1054                 .elastic_limit = 16,
1055                 .idle_wait_delay = 17,
1056                 .term_range_adj = 6,
1057                 .xcvr_setup = 8,
1058                 .xcvr_lsfslew = 2,
1059                 .xcvr_lsrslew = 2,
1060                 .xcvr_setup_offset = 0,
1061                 .xcvr_use_fuses = 1,
1062         },
1063 };
1064
1065 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1066         .port_otg = false,
1067         .has_hostpc = true,
1068         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1069         .op_mode        = TEGRA_USB_OPMODE_HOST,
1070         .u_data.host = {
1071                 .vbus_gpio = -1,
1072                 .hot_plug = false,
1073                 .remote_wakeup_supported = true,
1074                 .power_off_on_suspend = true,
1075         },
1076         .u_cfg.utmi = {
1077                 .hssync_start_delay = 0,
1078                 .elastic_limit = 16,
1079                 .idle_wait_delay = 17,
1080                 .term_range_adj = 6,
1081                 .xcvr_setup = 15,
1082                 .xcvr_lsfslew = 2,
1083                 .xcvr_lsrslew = 2,
1084                 .xcvr_setup_offset = 0,
1085                 .xcvr_use_fuses = 1,
1086         },
1087 };
1088
1089 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1090         .port_otg = false,
1091         .has_hostpc = true,
1092         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1093         .op_mode = TEGRA_USB_OPMODE_HOST,
1094         .u_data.host = {
1095                 .vbus_gpio = -1,
1096                 .vbus_reg = "vdd_vbus_typea_usb",
1097                 .hot_plug = true,
1098                 .remote_wakeup_supported = true,
1099                 .power_off_on_suspend = true,
1100         },
1101         .u_cfg.utmi = {
1102                 .hssync_start_delay = 0,
1103                 .elastic_limit = 16,
1104                 .idle_wait_delay = 17,
1105                 .term_range_adj = 6,
1106                 .xcvr_setup = 8,
1107                 .xcvr_lsfslew = 2,
1108                 .xcvr_lsrslew = 2,
1109                 .xcvr_setup_offset = 0,
1110                 .xcvr_use_fuses = 1,
1111         },
1112 };
1113
1114 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1115         .port_otg = true,
1116         .has_hostpc = true,
1117         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1118         .op_mode = TEGRA_USB_OPMODE_HOST,
1119         .u_data.host = {
1120                 .vbus_gpio = -1,
1121                 .vbus_reg = "vdd_vbus_micro_usb",
1122                 .hot_plug = true,
1123                 .remote_wakeup_supported = true,
1124                 .power_off_on_suspend = true,
1125         },
1126         .u_cfg.utmi = {
1127                 .hssync_start_delay = 0,
1128                 .elastic_limit = 16,
1129                 .idle_wait_delay = 17,
1130                 .term_range_adj = 6,
1131                 .xcvr_setup = 15,
1132                 .xcvr_lsfslew = 2,
1133                 .xcvr_lsrslew = 2,
1134                 .xcvr_setup_offset = 0,
1135                 .xcvr_use_fuses = 1,
1136         },
1137 };
1138
1139 static struct tegra_usb_otg_data tegra_otg_pdata = {
1140         .ehci_device = &tegra_ehci1_device,
1141         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1142 };
1143 #endif
1144
1145 #if defined(CONFIG_USB_SUPPORT)
1146 static void cardhu_usb_init(void)
1147 {
1148         struct board_info bi;
1149
1150         tegra_get_board_info(&bi);
1151
1152         /* OTG should be the first to be registered */
1153         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1154         platform_device_register(&tegra_otg_device);
1155
1156         /* setup the udc platform data */
1157         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1158
1159         if (bi.board_id == BOARD_PM267) {
1160                 hsic_enable_gpio = EN_HSIC_GPIO;
1161                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1162                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1163                 platform_device_register(&tegra_ehci2_device);
1164         } else if (bi.board_id == BOARD_E1256) {
1165                 hsic_enable_gpio = EN_HSIC_GPIO;
1166                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1167                 platform_device_register(&tegra_ehci2_device);
1168         } else if (bi.board_id == BOARD_E1186) {
1169                 tegra_ehci2_device.dev.platform_data =
1170                                                 &tegra_ehci2_hsic_xmm_pdata;
1171                 /* ehci2 registration happens in baseband-xmm-power  */
1172         } else {
1173                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1174                 platform_device_register(&tegra_ehci2_device);
1175         }
1176
1177         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1178         platform_device_register(&tegra_ehci3_device);
1179
1180 }
1181 #else
1182 static void cardhu_usb_init(void) { }
1183 #endif
1184
1185 static struct baseband_power_platform_data tegra_baseband_power_data = {
1186         .baseband_type = BASEBAND_XMM,
1187         .modem = {
1188         .xmm = {
1189                         .bb_rst = XMM_GPIO_BB_RST,
1190                         .bb_on = XMM_GPIO_BB_ON,
1191                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1192                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1193                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1194                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1195                         .hsic_device = &tegra_ehci2_device,
1196                 },
1197         },
1198 };
1199
1200 static struct platform_device tegra_baseband_power_device = {
1201         .name = "baseband_xmm_power",
1202         .id = -1,
1203         .dev = {
1204                 .platform_data = &tegra_baseband_power_data,
1205         },
1206 };
1207
1208 static struct platform_device tegra_baseband_power2_device = {
1209         .name = "baseband_xmm_power2",
1210         .id = -1,
1211         .dev = {
1212                 .platform_data = &tegra_baseband_power_data,
1213         },
1214 };
1215
1216
1217 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1218         .port_status[0] = 1,
1219         .port_status[1] = 1,
1220         .port_status[2] = 1,
1221         .use_dock_detect        = 0,
1222         .gpio           = 0,
1223 };
1224
1225 static void cardhu_pci_init(void)
1226 {
1227         struct board_info board_info;
1228
1229         tegra_get_board_info(&board_info);
1230         if (board_info.board_id == BOARD_E1291) {
1231                 cardhu_pci_platform_data.port_status[0] = 0;
1232                 cardhu_pci_platform_data.port_status[1] = 0;
1233                 cardhu_pci_platform_data.port_status[2] = 1;
1234                 cardhu_pci_platform_data.use_dock_detect = 1;
1235                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1236         }
1237         if ((board_info.board_id == BOARD_E1186) ||
1238                 (board_info.board_id == BOARD_E1187) ||
1239                 (board_info.board_id == BOARD_E1291)) {
1240                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1241                 platform_device_register(&tegra_pci_device);
1242         }
1243 }
1244
1245 static void cardhu_modem_init(void)
1246 {
1247         struct board_info board_info;
1248         int w_disable_gpio, ret;
1249
1250         tegra_get_board_info(&board_info);
1251         switch (board_info.board_id) {
1252         case BOARD_E1291:
1253         case BOARD_E1198:
1254                 if (((board_info.board_id == BOARD_E1291) &&
1255                                 (board_info.fab < BOARD_FAB_A03)) ||
1256                         ((board_info.board_id == BOARD_E1198) &&
1257                                         (board_info.fab < BOARD_FAB_A02))) {
1258                         w_disable_gpio = TEGRA_GPIO_PH5;
1259                 } else {
1260                         w_disable_gpio = TEGRA_GPIO_PDD5;
1261                 }
1262
1263                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1264                 if (ret < 0)
1265                         pr_err("%s: gpio_request failed for gpio %d\n",
1266                                 __func__, w_disable_gpio);
1267                 else
1268                         gpio_direction_input(w_disable_gpio);
1269
1270                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1271                 if (((board_info.board_id == BOARD_E1291) &&
1272                                 (board_info.fab >= BOARD_FAB_A04)) ||
1273                         ((board_info.board_id == BOARD_E1198) &&
1274                                         (board_info.fab >= BOARD_FAB_A02))) {
1275                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1276                         if (ret < 0) {
1277                                 pr_err("%s(): Error in allocating gpio "
1278                                         "TEGRA_GPIO_PH7\n", __func__);
1279                                 break;
1280                         }
1281                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1282                 }
1283                 break;
1284         case BOARD_E1186:
1285                 platform_device_register(&tegra_baseband_power_device);
1286                 platform_device_register(&tegra_baseband_power2_device);
1287                 break;
1288         default:
1289                 break;
1290         }
1291
1292 }
1293
1294 #ifdef CONFIG_SATA_AHCI_TEGRA
1295 static void cardhu_sata_init(void)
1296 {
1297         platform_device_register(&tegra_sata_device);
1298 }
1299 #else
1300 static void cardhu_sata_init(void) { }
1301 #endif
1302
1303 static void __init tegra_cardhu_init(void)
1304 {
1305         tegra_thermal_init(&thermal_data);
1306         tegra_clk_init_from_table(cardhu_clk_init_table);
1307         tegra_enable_pinmux();
1308         cardhu_pinmux_init();
1309         cardhu_i2c_init();
1310         cardhu_spi_init();
1311         cardhu_usb_init();
1312 #ifdef CONFIG_TEGRA_EDP_LIMITS
1313         cardhu_edp_init();
1314 #endif
1315         cardhu_uart_init();
1316         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1317         tegra_ram_console_debug_init();
1318         cardhu_sdhci_init();
1319         cardhu_regulator_init();
1320         cardhu_dtv_init();
1321         cardhu_suspend_init();
1322         cardhu_touch_init();
1323         cardhu_modem_init();
1324         cardhu_kbc_init();
1325         cardhu_scroll_init();
1326         cardhu_keys_init();
1327         cardhu_panel_init();
1328         cardhu_pmon_init();
1329         cardhu_sensors_init();
1330         cardhu_setup_bluesleep();
1331         cardhu_sata_init();
1332         //audio_wired_jack_init();
1333         cardhu_pins_state_init();
1334         cardhu_emc_init();
1335         tegra_release_bootloader_fb();
1336         cardhu_pci_init();
1337 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1338         tegra_wdt_recovery_init();
1339 #endif
1340 }
1341
1342 static void __init tegra_cardhu_reserve(void)
1343 {
1344 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1345         /* support 1920X1200 with 24bpp */
1346         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1347 #else
1348         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1349 #endif
1350         tegra_ram_console_debug_reserve(SZ_1M);
1351 }
1352
1353 MACHINE_START(CARDHU, "cardhu")
1354         .atag_offset    = 0x100,
1355         .soc            = &tegra_soc_desc,
1356         .map_io         = tegra_map_common_io,
1357         .reserve        = tegra_cardhu_reserve,
1358         .init_early     = tegra30_init_early,
1359         .init_irq       = tegra_init_irq,
1360         .handle_irq     = gic_handle_irq,
1361         .timer          = &tegra_timer,
1362         .init_machine   = tegra_cardhu_init,
1363         .restart        = tegra_assert_system_reset,
1364 MACHINE_END