arm: tegra: cardhu: HSIC config change for xmm modem
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "devices.h"
66 #include "gpio-names.h"
67 #include "fuse.h"
68 #include "pm.h"
69 #include "baseband-xmm-power.h"
70 #include "wdt-recovery.h"
71
72 static unsigned long ramconsole_start;
73 static unsigned long ramconsole_size;
74
75 /* All units are in millicelsius */
76 static struct tegra_thermal_data thermal_data = {
77         .temp_throttle = 85000,
78         .temp_shutdown = 90000,
79         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
80 #ifdef CONFIG_TEGRA_EDP_LIMITS
81         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
82         .hysteresis_edp = 3000,
83 #endif
84 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
85         .tc1 = 0,
86         .tc2 = 1,
87         .passive_delay = 2000,
88 #else
89         .hysteresis_throttle = 1000,
90 #endif
91 };
92
93 /* !!!TODO: Change for cardhu (Taken from Ventana) */
94 static struct tegra_utmip_config utmi_phy_config[] = {
95         [0] = {
96                         .hssync_start_delay = 0,
97                         .idle_wait_delay = 17,
98                         .elastic_limit = 16,
99                         .term_range_adj = 6,
100                         .xcvr_setup = 15,
101                         .xcvr_setup_offset = 0,
102                         .xcvr_use_fuses = 1,
103                         .xcvr_lsfslew = 2,
104                         .xcvr_lsrslew = 2,
105         },
106         [1] = {
107                         .hssync_start_delay = 0,
108                         .idle_wait_delay = 17,
109                         .elastic_limit = 16,
110                         .term_range_adj = 6,
111                         .xcvr_setup = 15,
112                         .xcvr_setup_offset = 0,
113                         .xcvr_use_fuses = 1,
114                         .xcvr_lsfslew = 2,
115                         .xcvr_lsrslew = 2,
116         },
117         [2] = {
118                         .hssync_start_delay = 0,
119                         .idle_wait_delay = 17,
120                         .elastic_limit = 16,
121                         .term_range_adj = 6,
122                         .xcvr_setup = 8,
123                         .xcvr_setup_offset = 0,
124                         .xcvr_use_fuses = 1,
125                         .xcvr_lsfslew = 2,
126                         .xcvr_lsrslew = 2,
127         },
128 };
129
130 #ifdef CONFIG_BCM4329_RFKILL
131 static struct resource cardhu_bcm4329_rfkill_resources[] = {
132         {
133                 .name   = "bcm4329_nshutdown_gpio",
134                 .start  = TEGRA_GPIO_PU0,
135                 .end    = TEGRA_GPIO_PU0,
136                 .flags  = IORESOURCE_IO,
137         },
138 };
139
140 static struct platform_device cardhu_bcm4329_rfkill_device = {
141         .name = "bcm4329_rfkill",
142         .id             = -1,
143         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
144         .resource       = cardhu_bcm4329_rfkill_resources,
145 };
146
147 static noinline void __init cardhu_bt_rfkill(void)
148 {
149         platform_device_register(&cardhu_bcm4329_rfkill_device);
150
151         return;
152 }
153 #else
154 static inline void cardhu_bt_rfkill(void) { }
155 #endif
156
157 #ifdef CONFIG_BT_BLUESLEEP
158 static noinline void __init tegra_setup_bluesleep(void)
159 {
160         struct platform_device *pdev = NULL;
161         struct resource *res;
162
163         pdev = platform_device_alloc("bluesleep", 0);
164         if (!pdev) {
165                 pr_err("unable to allocate platform device for bluesleep");
166                 return;
167         }
168
169         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
170         if (!res) {
171                 pr_err("unable to allocate resource for bluesleep\n");
172                 goto err_free_dev;
173         }
174
175         res[0].name   = "gpio_host_wake";
176         res[0].start  = TEGRA_GPIO_PU6;
177         res[0].end    = TEGRA_GPIO_PU6;
178         res[0].flags  = IORESOURCE_IO;
179
180         res[1].name   = "gpio_ext_wake";
181         res[1].start  = TEGRA_GPIO_PU1;
182         res[1].end    = TEGRA_GPIO_PU1;
183         res[1].flags  = IORESOURCE_IO;
184
185         res[2].name   = "host_wake";
186         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
187         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
188         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
189
190         if (platform_device_add_resources(pdev, res, 3)) {
191                 pr_err("unable to add resources to bluesleep device\n");
192                 goto err_free_res;
193         }
194
195         if (platform_device_add(pdev)) {
196                 pr_err("unable to add bluesleep device\n");
197                 goto err_free_res;
198         }
199         tegra_gpio_enable(TEGRA_GPIO_PU6);
200         tegra_gpio_enable(TEGRA_GPIO_PU1);
201
202 return;
203
204 err_free_res:
205         kfree(res);
206 err_free_dev:
207         platform_device_put(pdev);
208         return;
209 }
210 #else
211 static inline void tegra_setup_bluesleep(void) { }
212 #endif
213
214 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
215         /* name         parent          rate            enabled */
216         { "pll_m",      NULL,           0,              false},
217         { "hda",        "pll_p",        108000000,      false},
218         { "hda2codec_2x","pll_p",       48000000,       false},
219         { "pwm",        "pll_p",        3187500,        false},
220         { "blink",      "clk_32k",      32768,          true},
221         { "i2s0",       "pll_a_out0",   0,              false},
222         { "i2s1",       "pll_a_out0",   0,              false},
223         { "i2s3",       "pll_a_out0",   0,              false},
224         { "spdif_out",  "pll_a_out0",   0,              false},
225         { "d_audio",    "clk_m",        12000000,       false},
226         { "dam0",       "clk_m",        12000000,       false},
227         { "dam1",       "clk_m",        12000000,       false},
228         { "dam2",       "clk_m",        12000000,       false},
229         { "audio1",     "i2s1_sync",    0,              false},
230         { "audio3",     "i2s3_sync",    0,              false},
231         { "vi_sensor",  "pll_p",        150000000,      false},
232         { "i2c1",       "pll_p",        3200000,        false},
233         { "i2c2",       "pll_p",        3200000,        false},
234         { "i2c3",       "pll_p",        3200000,        false},
235         { "i2c4",       "pll_p",        3200000,        false},
236         { "i2c5",       "pll_p",        3200000,        false},
237         { NULL,         NULL,           0,              0},
238 };
239
240 static struct pn544_i2c_platform_data nfc_pdata = {
241         .irq_gpio = TEGRA_GPIO_PX0,
242         .ven_gpio = TEGRA_GPIO_PP3,
243         .firm_gpio = TEGRA_GPIO_PO7,
244         };
245
246 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
247         {
248                 I2C_BOARD_INFO("pn544", 0x28),
249                 .platform_data = &nfc_pdata,
250                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
251         },
252 };
253 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
254         .adapter_nr     = 0,
255         .bus_count      = 1,
256         .bus_clk_rate   = { 100000, 0 },
257         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
258         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
259         .arb_recovery = arb_lost_recovery,
260 };
261
262 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
263         .adapter_nr     = 1,
264         .bus_count      = 1,
265         .bus_clk_rate   = { 100000, 0 },
266         .is_clkon_always = true,
267         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
268         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
269         .arb_recovery = arb_lost_recovery,
270 };
271
272 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
273         .adapter_nr     = 2,
274         .bus_count      = 1,
275         .bus_clk_rate   = { 100000, 0 },
276         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
277         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
278         .arb_recovery = arb_lost_recovery,
279 };
280
281 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
282         .adapter_nr     = 3,
283         .bus_count      = 1,
284         .bus_clk_rate   = { 100000, 0 },
285         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
286         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
287         .arb_recovery = arb_lost_recovery,
288 };
289
290 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
291         .adapter_nr     = 4,
292         .bus_count      = 1,
293         .bus_clk_rate   = { 400000, 0 },
294         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
295         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
296         .arb_recovery = arb_lost_recovery,
297 };
298
299
300 #if 0
301 struct tegra_wired_jack_conf audio_wr_jack_conf = {
302         .hp_det_n = TEGRA_GPIO_PW2,
303         .en_mic_ext = TEGRA_GPIO_PX1,
304         .en_mic_int = TEGRA_GPIO_PX0,
305 };
306 #endif
307
308 static struct wm8903_platform_data cardhu_wm8903_pdata = {
309         .irq_active_low = 0,
310         .micdet_cfg = 0,
311         .micdet_delay = 100,
312         .gpio_base = CARDHU_GPIO_WM8903(0),
313         .gpio_cfg = {
314                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
315                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
316                         WM8903_GP2_DIR,
317                 0,
318                 WM8903_GPIO_NO_CONFIG,
319                 WM8903_GPIO_NO_CONFIG,
320         },
321 };
322
323 /* Equalizer filter coefs generated from the MAXIM MAX98095
324  * evkit software tool */
325 static struct max98095_eq_cfg max98095_eq_cfg[] = {
326         {
327                 .name = "FLAT",
328                 .rate = 44100,
329                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
330                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
331                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
332                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
333                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
334         },
335         {
336                 .name = "LOWPASS1K",
337                 .rate = 44100,
338                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
339                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
340                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
341                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
342                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
343         },
344         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
345                 .name = "HIBOOST",
346                 .rate = 44100,
347                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
348                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
349                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
350                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
351                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
352         },
353         { /* BASS=12dB, TREBLE=+12dB */
354                 .name = "LOUD12DB",
355                 .rate = 44100,
356                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
357                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
358                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
359                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
360                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
361         },
362         {
363                 .name = "FLAT",
364                 .rate = 16000,
365                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
366                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
367                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
368                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
369                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
370         },
371         {
372                 .name = "LOWPASS1K",
373                 .rate = 16000,
374                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
375                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
376                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
377                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
378                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
379         },
380         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
381                 .name = "HIBOOST",
382                 .rate = 16000,
383                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
384                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
385                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
386                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
387                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
388         },
389         { /* BASS=12dB, TREBLE=+12dB */
390                 .name = "LOUD12DB",
391                 .rate = 16000,
392                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
393                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
394                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
395                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
396                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
397         },
398 };
399
400 static struct max98095_pdata cardhu_max98095_pdata = {
401         /* equalizer configuration */
402         .eq_cfg = max98095_eq_cfg,
403         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
404
405         /* Biquad filter response configuration */
406         .bq_cfg = NULL,
407         .bq_cfgcnt = 0,
408
409         /* microphone configuration */
410         .digmic_left_mode = 1,
411         .digmic_right_mode = 1,
412 };
413
414 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
415         I2C_BOARD_INFO("wm8903", 0x1a),
416         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
417         .platform_data = &cardhu_wm8903_pdata,
418 };
419
420 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
421         I2C_BOARD_INFO("aic3262-codec", 0x18),
422         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
423 };
424
425 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
426         I2C_BOARD_INFO("max98095", 0x10),
427         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
428         .platform_data = &cardhu_max98095_pdata,
429 };
430
431 static void cardhu_i2c_init(void)
432 {
433         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
434         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
435         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
436         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
437         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
438
439         platform_device_register(&tegra_i2c_device5);
440         platform_device_register(&tegra_i2c_device4);
441         platform_device_register(&tegra_i2c_device3);
442         platform_device_register(&tegra_i2c_device2);
443         platform_device_register(&tegra_i2c_device1);
444
445         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
446         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
447         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
448
449         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
450 }
451
452 static struct platform_device *cardhu_uart_devices[] __initdata = {
453         &tegra_uarta_device,
454         &tegra_uartb_device,
455         &tegra_uartc_device,
456         &tegra_uartd_device,
457         &tegra_uarte_device,
458 };
459 static struct uart_clk_parent uart_parent_clk[] = {
460         [0] = {.name = "clk_m"},
461         [1] = {.name = "pll_p"},
462 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
463         [2] = {.name = "pll_m"},
464 #endif
465 };
466
467 static struct tegra_uart_platform_data cardhu_uart_pdata;
468 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
469
470 static void __init uart_debug_init(void)
471 {
472         struct board_info board_info;
473         int debug_port_id;
474
475         tegra_get_board_info(&board_info);
476
477         debug_port_id = get_tegra_uart_debug_port_id();
478         if (debug_port_id < 0) {
479                 debug_port_id = 0;
480                         /* UARTB is debug port
481                          *       for SLT - E1186/E1187/PM269
482                          *       for E1256/E1257
483                          */
484                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
485                         ((board_info.board_id == BOARD_E1186) ||
486                         (board_info.board_id == BOARD_E1187) ||
487                         (board_info.board_id == BOARD_PM269))) ||
488                         (board_info.board_id == BOARD_E1256) ||
489                         (board_info.board_id == BOARD_E1257))
490                                 debug_port_id = 1;
491         }
492
493         switch (debug_port_id) {
494         case 0:
495                 /* UARTA is the debug port. */
496                 pr_info("Selecting UARTA as the debug console\n");
497                 cardhu_uart_devices[0] = &debug_uarta_device;
498                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
499                 debug_uart_port_base = ((struct plat_serial8250_port *)(
500                         debug_uarta_device.dev.platform_data))->mapbase;
501                 break;
502
503         case 1:
504                 /* UARTB is the debug port. */
505                 pr_info("Selecting UARTB as the debug console\n");
506                 cardhu_uart_devices[1] = &debug_uartb_device;
507                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
508                 debug_uart_port_base = ((struct plat_serial8250_port *)(
509                         debug_uartb_device.dev.platform_data))->mapbase;
510                 break;
511
512         case 2:
513                 /* UARTC is the debug port. */
514                 pr_info("Selecting UARTC as the debug console\n");
515                 cardhu_uart_devices[2] = &debug_uartc_device;
516                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
517                 debug_uart_port_base = ((struct plat_serial8250_port *)(
518                         debug_uartc_device.dev.platform_data))->mapbase;
519                 break;
520
521         case 3:
522                 /* UARTD is the debug port. */
523                 pr_info("Selecting UARTD as the debug console\n");
524                 cardhu_uart_devices[3] = &debug_uartd_device;
525                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
526                 debug_uart_port_base = ((struct plat_serial8250_port *)(
527                         debug_uartd_device.dev.platform_data))->mapbase;
528                 break;
529
530         case 4:
531                 /* UARTE is the debug port. */
532                 pr_info("Selecting UARTE as the debug console\n");
533                 cardhu_uart_devices[4] = &debug_uarte_device;
534                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
535                 debug_uart_port_base = ((struct plat_serial8250_port *)(
536                         debug_uarte_device.dev.platform_data))->mapbase;
537                 break;
538
539         default:
540                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
541                 cardhu_uart_devices[0] = &debug_uarta_device;
542                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
543                 debug_uart_port_base = ((struct plat_serial8250_port *)(
544                         debug_uarta_device.dev.platform_data))->mapbase;
545                 break;
546         }
547         return;
548 }
549
550 static void __init cardhu_uart_init(void)
551 {
552         struct clk *c;
553         int i;
554
555         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
556                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
557                 if (IS_ERR_OR_NULL(c)) {
558                         pr_err("Not able to get the clock for %s\n",
559                                                 uart_parent_clk[i].name);
560                         continue;
561                 }
562                 uart_parent_clk[i].parent_clk = c;
563                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
564         }
565         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
566         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
567         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
568         cardhu_loopback_uart_pdata.parent_clk_count =
569                                                 ARRAY_SIZE(uart_parent_clk);
570         cardhu_loopback_uart_pdata.is_loopback = true;
571         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
572         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
573         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
574         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
575         /* UARTE is used for loopback test purpose */
576         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
577
578         /* Register low speed only if it is selected */
579         if (!is_tegra_debug_uartport_hs()) {
580                 uart_debug_init();
581                 /* Clock enable for the debug channel */
582                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
583                         pr_info("The debug console clock name is %s\n",
584                                                 debug_uart_clk->name);
585                         c = tegra_get_clock_by_name("pll_p");
586                         if (IS_ERR_OR_NULL(c))
587                                 pr_err("Not getting the parent clock pll_p\n");
588                         else
589                                 clk_set_parent(debug_uart_clk, c);
590
591                         clk_enable(debug_uart_clk);
592                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
593                 } else {
594                         pr_err("Not getting the clock %s for debug console\n",
595                                         debug_uart_clk->name);
596                 }
597         }
598
599         platform_add_devices(cardhu_uart_devices,
600                                 ARRAY_SIZE(cardhu_uart_devices));
601 }
602
603 static struct platform_device tegra_camera = {
604         .name = "tegra_camera",
605         .id = -1,
606 };
607
608 static struct platform_device *cardhu_spi_devices[] __initdata = {
609         &tegra_spi_device4,
610 };
611
612 struct spi_clk_parent spi_parent_clk[] = {
613         [0] = {.name = "pll_p"},
614 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
615         [1] = {.name = "pll_m"},
616         [2] = {.name = "clk_m"},
617 #else
618         [1] = {.name = "clk_m"},
619 #endif
620 };
621
622 static struct tegra_spi_platform_data cardhu_spi_pdata = {
623         .is_dma_based           = true,
624         .max_dma_buffer         = (16 * 1024),
625         .is_clkon_always        = false,
626         .max_rate               = 100000000,
627 };
628
629 static void __init cardhu_spi_init(void)
630 {
631         int i;
632         struct clk *c;
633         struct board_info board_info;
634
635         tegra_get_board_info(&board_info);
636
637         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
638                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
639                 if (IS_ERR_OR_NULL(c)) {
640                         pr_err("Not able to get the clock for %s\n",
641                                                 spi_parent_clk[i].name);
642                         continue;
643                 }
644                 spi_parent_clk[i].parent_clk = c;
645                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
646         }
647         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
648         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
649         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
650         platform_add_devices(cardhu_spi_devices,
651                                 ARRAY_SIZE(cardhu_spi_devices));
652
653         if (board_info.board_id == BOARD_E1198) {
654                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
655                 platform_device_register(&tegra_spi_device2);
656                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
657                 platform_device_register(&tegra_spi_slave_device1);
658         }
659 }
660
661 static void __init cardhu_dtv_init(void)
662 {
663         struct board_info board_info;
664
665         tegra_get_board_info(&board_info);
666
667         if (board_info.board_id == BOARD_E1186)
668                 platform_device_register(&tegra_dtv_device);
669 }
670
671 static struct resource tegra_rtc_resources[] = {
672         [0] = {
673                 .start = TEGRA_RTC_BASE,
674                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
675                 .flags = IORESOURCE_MEM,
676         },
677         [1] = {
678                 .start = INT_RTC,
679                 .end = INT_RTC,
680                 .flags = IORESOURCE_IRQ,
681         },
682 };
683
684 static struct platform_device tegra_rtc_device = {
685         .name = "tegra_rtc",
686         .id   = -1,
687         .resource = tegra_rtc_resources,
688         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
689 };
690
691 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
692         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
693         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
694         .gpio_hp_mute           = -1,
695         .gpio_int_mic_en        = -1,
696         .gpio_ext_mic_en        = -1,
697 };
698
699 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
700         .gpio_spkr_en           = -1,
701         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
702         .gpio_hp_mute           = -1,
703         .gpio_int_mic_en        = -1,
704         .gpio_ext_mic_en        = -1,
705 };
706
707 static struct platform_device cardhu_audio_wm8903_device = {
708         .name   = "tegra-snd-wm8903",
709         .id     = 0,
710         .dev    = {
711                 .platform_data = &cardhu_audio_wm8903_pdata,
712         },
713 };
714
715 static struct platform_device cardhu_audio_max98095_device = {
716         .name   = "tegra-snd-max98095",
717         .id     = 0,
718         .dev    = {
719                 .platform_data = &cardhu_audio_max98095_pdata,
720         },
721 };
722
723 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
724         .gpio_spkr_en           = -1,
725         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
726         .gpio_hp_mute           = -1,
727         .gpio_int_mic_en        = -1,
728         .gpio_ext_mic_en        = -1,
729 };
730
731 static struct platform_device cardhu_audio_aic326x_device = {
732         .name   = "tegra-snd-aic326x",
733         .id     = 0,
734         .dev    = {
735                 .platform_data  = &cardhu_audio_aic326x_pdata,
736         },
737 };
738
739 static struct resource ram_console_resources[] = {
740         {
741                 .flags = IORESOURCE_MEM,
742         },
743 };
744
745 static struct platform_device ram_console_device = {
746         .name           = "ram_console",
747         .id             = -1,
748         .num_resources  = ARRAY_SIZE(ram_console_resources),
749         .resource       = ram_console_resources,
750 };
751
752 static struct platform_device *cardhu_devices[] __initdata = {
753         &tegra_pmu_device,
754         &tegra_rtc_device,
755         &tegra_udc_device,
756 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
757         &tegra_smmu_device,
758 #endif
759         &tegra_wdt_device,
760 #if defined(CONFIG_TEGRA_AVP)
761         &tegra_avp_device,
762 #endif
763         &tegra_camera,
764 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
765         &tegra_se_device,
766 #endif
767         &tegra_ahub_device,
768         &tegra_dam_device0,
769         &tegra_dam_device1,
770         &tegra_dam_device2,
771         &tegra_i2s_device0,
772         &tegra_i2s_device1,
773         &tegra_i2s_device3,
774         &tegra_spdif_device,
775         &spdif_dit_device,
776         &bluetooth_dit_device,
777         &baseband_dit_device,
778         &tegra_pcm_device,
779         &cardhu_audio_wm8903_device,
780         &cardhu_audio_max98095_device,
781         &cardhu_audio_aic326x_device,
782         &tegra_hda_device,
783 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
784         &tegra_aes_device,
785 #endif
786         &ram_console_device,
787 };
788
789 #define MXT_CONFIG_CRC  0xD62DE8
790 static const u8 config[] = {
791         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
792         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
793         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
794         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
795         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
796         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
797         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
798         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
799         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
800         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
801         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
802         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
803         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
804         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
805         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
806         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
809         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
810         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
811 };
812
813 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
814 static const u8 config_sku2000[] = {
815         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
817         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
818         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
819         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
820         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
821         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
824         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
825         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
826         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
827         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
828         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
829         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
830         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
831         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
832         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
833         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
835 };
836
837 static struct mxt_platform_data atmel_mxt_info = {
838         .x_line         = 27,
839         .y_line         = 42,
840         .x_size         = 768,
841         .y_size         = 1366,
842         .blen           = 0x20,
843         .threshold      = 0x3C,
844         .voltage        = 3300000,              /* 3.3V */
845         .orient         = 5,
846         .config         = config,
847         .config_length  = 157,
848         .config_crc     = MXT_CONFIG_CRC,
849         .irqflags       = IRQF_TRIGGER_FALLING,
850 /*      .read_chg       = &read_chg, */
851         .read_chg       = NULL,
852 };
853
854 static struct i2c_board_info __initdata atmel_i2c_info[] = {
855         {
856                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
857                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
858                 .platform_data = &atmel_mxt_info,
859         }
860 };
861
862 static int __init cardhu_touch_init(void)
863 {
864         struct board_info BoardInfo;
865
866         tegra_gpio_enable(TEGRA_GPIO_PH4);
867         tegra_gpio_enable(TEGRA_GPIO_PH6);
868
869         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
870         gpio_direction_input(TEGRA_GPIO_PH4);
871
872         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
873         gpio_direction_output(TEGRA_GPIO_PH6, 0);
874         msleep(1);
875         gpio_set_value(TEGRA_GPIO_PH6, 1);
876         msleep(100);
877
878         tegra_get_board_info(&BoardInfo);
879         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
880                 atmel_mxt_info.config = config_sku2000;
881                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
882         }
883
884         i2c_register_board_info(1, atmel_i2c_info, 1);
885
886         return 0;
887 }
888
889 static struct tegra_uhsic_config uhsic_phy_config = {
890         .enable_gpio = EN_HSIC_GPIO,
891         .reset_gpio = -1,
892         .sync_start_delay = 9,
893         .idle_wait_delay = 17,
894         .term_range_adj = 0,
895         .elastic_underrun_limit = 16,
896         .elastic_overrun_limit = 16,
897 };
898
899 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
900         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
901         .phy_config = &uhsic_phy_config,
902         .operating_mode = TEGRA_USB_HOST,
903         .power_down_on_bus_suspend = 1,
904         .default_enable = true,
905 };
906
907 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
908         [0] = {
909                         .phy_config = &utmi_phy_config[0],
910                         .operating_mode = TEGRA_USB_HOST,
911                         .power_down_on_bus_suspend = 1,
912                         .default_enable = true,
913         },
914         [1] = {
915                         .phy_config = &utmi_phy_config[1],
916                         .operating_mode = TEGRA_USB_HOST,
917                         .power_down_on_bus_suspend = 1,
918                         .default_enable = true,
919         },
920         [2] = {
921                         .phy_config = &utmi_phy_config[2],
922                         .operating_mode = TEGRA_USB_HOST,
923                         .power_down_on_bus_suspend = 1,
924                         .hotplug = 1,
925                         .default_enable = true,
926         },
927 };
928
929 static struct tegra_otg_platform_data tegra_otg_pdata = {
930         .ehci_device = &tegra_ehci1_device,
931         .ehci_pdata = &tegra_ehci_pdata[0],
932 };
933
934 #ifdef CONFIG_USB_SUPPORT
935 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
936         [0] = {
937                         .instance = 0,
938                         .vbus_gpio = -1,
939                         .vbus_reg_supply = "vdd_vbus_micro_usb",
940         },
941         [1] = {
942                         .instance = 1,
943                         .vbus_gpio = -1,
944         },
945         [2] = {
946                         .instance = 2,
947                         .vbus_gpio = -1,
948                         .vbus_reg_supply = "vdd_vbus_typea_usb",
949         },
950 };
951
952 static int cardu_usb_hsic_postsupend(void)
953 {
954         baseband_xmm_set_power_status(BBXMM_PS_L2);
955         return 0;
956 }
957
958 static int cardu_usb_hsic_preresume(void)
959 {
960         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
961         return 0;
962 }
963
964 static void cardhu_usb_init(void)
965 {
966         struct board_info bi;
967
968         tegra_get_board_info(&bi);
969
970         tegra_usb_phy_init(tegra_usb_phy_pdata,
971                         ARRAY_SIZE(tegra_usb_phy_pdata));
972
973         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
974         platform_device_register(&tegra_otg_device);
975         if (bi.board_id == BOARD_PM267) {
976                 uhsic_phy_config.reset_gpio =
977                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
978                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
979                 platform_device_register(&tegra_ehci2_device);
980         } else if (bi.board_id == BOARD_E1256) {
981                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
982                 platform_device_register(&tegra_ehci2_device);
983         } else if (bi.board_id == BOARD_E1186) {
984                 /* for baseband devices do not switch off phy during suspend */
985                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
986                 uhsic_phy_config.postsuspend = cardu_usb_hsic_postsupend;
987                 uhsic_phy_config.preresume = cardu_usb_hsic_preresume;
988                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
989                 /* baseband registration happens in baseband-xmm-power  */
990         } else {
991                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
992                 platform_device_register(&tegra_ehci2_device);
993         }
994
995         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
996         platform_device_register(&tegra_ehci3_device);
997
998 }
999 #else
1000 static void cardhu_usb_init(void) { }
1001 #endif
1002
1003 static void cardhu_gps_init(void)
1004 {
1005         tegra_gpio_enable(TEGRA_GPIO_PU2);
1006         tegra_gpio_enable(TEGRA_GPIO_PU3);
1007 }
1008
1009 static void cardhu_nfc_init(void)
1010 {
1011         tegra_gpio_enable(TEGRA_GPIO_PX0);
1012         tegra_gpio_enable(TEGRA_GPIO_PP3);
1013         tegra_gpio_enable(TEGRA_GPIO_PO7);
1014 }
1015
1016 static struct baseband_power_platform_data tegra_baseband_power_data = {
1017         .baseband_type = BASEBAND_XMM,
1018         .modem = {
1019         .xmm = {
1020                         .bb_rst = XMM_GPIO_BB_RST,
1021                         .bb_on = XMM_GPIO_BB_ON,
1022                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1023                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1024                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1025                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1026                         .hsic_device = &tegra_ehci2_device,
1027                 },
1028         },
1029 };
1030
1031 static struct platform_device tegra_baseband_power_device = {
1032         .name = "baseband_xmm_power",
1033         .id = -1,
1034         .dev = {
1035                 .platform_data = &tegra_baseband_power_data,
1036         },
1037 };
1038
1039 static struct platform_device tegra_baseband_power2_device = {
1040         .name = "baseband_xmm_power2",
1041         .id = -1,
1042         .dev = {
1043                 .platform_data = &tegra_baseband_power_data,
1044         },
1045 };
1046
1047
1048 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1049         .port_status[0] = 1,
1050         .port_status[1] = 1,
1051         .port_status[2] = 1,
1052         .use_dock_detect        = 0,
1053         .gpio           = 0,
1054 };
1055
1056 static void cardhu_pci_init(void)
1057 {
1058         struct board_info board_info;
1059
1060         tegra_get_board_info(&board_info);
1061         if (board_info.board_id == BOARD_E1291) {
1062                 cardhu_pci_platform_data.port_status[0] = 0;
1063                 cardhu_pci_platform_data.port_status[1] = 0;
1064                 cardhu_pci_platform_data.port_status[2] = 1;
1065                 cardhu_pci_platform_data.use_dock_detect = 1;
1066                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1067         }
1068         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1069         platform_device_register(&tegra_pci_device);
1070 }
1071
1072 static void cardhu_modem_init(void)
1073 {
1074         struct board_info board_info;
1075         int w_disable_gpio, ret;
1076
1077         tegra_get_board_info(&board_info);
1078         switch (board_info.board_id) {
1079         case BOARD_E1291:
1080         case BOARD_E1198:
1081                 if (((board_info.board_id == BOARD_E1291) &&
1082                                 (board_info.fab < BOARD_FAB_A03)) ||
1083                         ((board_info.board_id == BOARD_E1198) &&
1084                                         (board_info.fab < BOARD_FAB_A02))) {
1085                         w_disable_gpio = TEGRA_GPIO_PH5;
1086                 } else {
1087                         w_disable_gpio = TEGRA_GPIO_PDD5;
1088                 }
1089                 tegra_gpio_enable(w_disable_gpio);
1090                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1091                 if (ret < 0)
1092                         pr_err("%s: gpio_request failed for gpio %d\n",
1093                                 __func__, w_disable_gpio);
1094                 else
1095                         gpio_direction_input(w_disable_gpio);
1096
1097                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1098                 if (((board_info.board_id == BOARD_E1291) &&
1099                                 (board_info.fab >= BOARD_FAB_A04)) ||
1100                         ((board_info.board_id == BOARD_E1198) &&
1101                                         (board_info.fab >= BOARD_FAB_A02))) {
1102                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1103                         if (ret < 0) {
1104                                 pr_err("%s(): Error in allocating gpio "
1105                                         "TEGRA_GPIO_PH7\n", __func__);
1106                                 break;
1107                         }
1108                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1109                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1110                 }
1111                 break;
1112         case BOARD_E1186:
1113                 tegra_gpio_enable(
1114                         tegra_baseband_power_data.modem.xmm.bb_rst);
1115                 tegra_gpio_enable(
1116                         tegra_baseband_power_data.modem.xmm.bb_on);
1117                 tegra_gpio_enable(
1118                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1119                 tegra_gpio_enable(
1120                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1121                 tegra_gpio_enable(
1122                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1123                 tegra_gpio_enable(
1124                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1125                 platform_device_register(&tegra_baseband_power_device);
1126                 platform_device_register(&tegra_baseband_power2_device);
1127                 break;
1128         default:
1129                 break;
1130         }
1131
1132 }
1133
1134 #ifdef CONFIG_SATA_AHCI_TEGRA
1135 static void cardhu_sata_init(void)
1136 {
1137         platform_device_register(&tegra_sata_device);
1138 }
1139 #else
1140 static void cardhu_sata_init(void) { }
1141 #endif
1142
1143 static void cardhu_ramconsole_init(void)
1144 {
1145         struct resource *res;
1146         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
1147         res->start = ramconsole_start;
1148         res->end = res->start + ramconsole_size - 1;
1149 }
1150
1151 static void __init tegra_cardhu_init(void)
1152 {
1153         tegra_thermal_init(&thermal_data);
1154         tegra_clk_init_from_table(cardhu_clk_init_table);
1155         cardhu_pinmux_init();
1156         cardhu_i2c_init();
1157         cardhu_spi_init();
1158         cardhu_usb_init();
1159 #ifdef CONFIG_TEGRA_EDP_LIMITS
1160         cardhu_edp_init();
1161 #endif
1162         cardhu_uart_init();
1163         cardhu_ramconsole_init();
1164         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1165         cardhu_sdhci_init();
1166         cardhu_regulator_init();
1167         cardhu_dtv_init();
1168         cardhu_suspend_init();
1169         cardhu_touch_init();
1170         cardhu_gps_init();
1171         cardhu_modem_init();
1172         cardhu_kbc_init();
1173         cardhu_scroll_init();
1174         cardhu_keys_init();
1175         cardhu_panel_init();
1176         cardhu_pmon_init();
1177         cardhu_sensors_init();
1178         cardhu_bt_rfkill();
1179         tegra_setup_bluesleep();
1180         cardhu_sata_init();
1181         //audio_wired_jack_init();
1182         cardhu_pins_state_init();
1183         cardhu_emc_init();
1184         tegra_release_bootloader_fb();
1185         cardhu_nfc_init();
1186         cardhu_pci_init();
1187 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1188         tegra_wdt_recovery_init();
1189 #endif
1190 }
1191
1192 static void __init tegra_cardhu_reserve(void)
1193 {
1194         long ret;
1195         ramconsole_size = SZ_1M;
1196         ramconsole_start = memblock_end_of_DRAM() - ramconsole_size;
1197         ret = memblock_remove(ramconsole_start, ramconsole_size);
1198         if (ret) {
1199                 ramconsole_size = 0;
1200                 pr_err("Failed to reserve memory block for ram console\n");
1201         }
1202
1203 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1204         /* support 1920X1200 with 24bpp */
1205         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1206 #else
1207         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1208 #endif
1209 }
1210
1211 MACHINE_START(CARDHU, "cardhu")
1212         .boot_params    = 0x80000100,
1213         .map_io         = tegra_map_common_io,
1214         .reserve        = tegra_cardhu_reserve,
1215         .init_early     = tegra_init_early,
1216         .init_irq       = tegra_init_irq,
1217         .timer          = &tegra_timer,
1218         .init_machine   = tegra_cardhu_init,
1219 MACHINE_END