ARM: tegra: fiq_dbg: Enable FIQ serial debug
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <mach/clk.h>
49 #include <mach/iomap.h>
50 #include <mach/irqs.h>
51 #include <mach/pinmux.h>
52 #include <mach/iomap.h>
53 #include <mach/io.h>
54 #include <mach/i2s.h>
55 #include <mach/tegra_asoc_pdata.h>
56 #include <mach/tegra_wm8903_pdata.h>
57 #include <asm/mach-types.h>
58 #include <asm/mach/arch.h>
59 #include <mach/usb_phy.h>
60 #include <mach/thermal.h>
61 #include <mach/pci.h>
62 #include <mach/tegra_fiq_debugger.h>
63
64 #include "board.h"
65 #include "clock.h"
66 #include "board-cardhu.h"
67 #include "board-touch.h"
68 #include "devices.h"
69 #include "gpio-names.h"
70 #include "fuse.h"
71 #include "pm.h"
72 #include "baseband-xmm-power.h"
73 #include "wdt-recovery.h"
74
75 static struct balanced_throttle throttle_list[] = {
76 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
77         {
78                 .id = BALANCED_THROTTLE_ID_TJ,
79                 .throt_tab_size = 10,
80                 .throt_tab = {
81                         {      0, 1000 },
82                         { 640000, 1000 },
83                         { 640000, 1000 },
84                         { 640000, 1000 },
85                         { 640000, 1000 },
86                         { 640000, 1000 },
87                         { 760000, 1000 },
88                         { 760000, 1050 },
89                         {1000000, 1050 },
90                         {1000000, 1100 },
91                 },
92         },
93 #endif
94 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
95         {
96                 .id = BALANCED_THROTTLE_ID_SKIN,
97                 .throt_tab_size = 6,
98                 .throt_tab = {
99                         { 640000, 1200 },
100                         { 640000, 1200 },
101                         { 760000, 1200 },
102                         { 760000, 1200 },
103                         {1000000, 1200 },
104                         {1000000, 1200 },
105                 },
106         },
107 #endif
108 };
109
110 /* All units are in millicelsius */
111 static struct tegra_thermal_data thermal_data = {
112         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
113         .temp_shutdown = 90000,
114
115 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
116         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
117 #endif
118 #ifdef CONFIG_TEGRA_EDP_LIMITS
119         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
120         .hysteresis_edp = 3000,
121 #endif
122 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
123         .temp_throttle = 85000,
124         .tc1 = 0,
125         .tc2 = 1,
126         .passive_delay = 2000,
127 #endif
128 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
129         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
130         .temp_throttle_skin = 43000,
131         .tc1_skin = 0,
132         .tc2_skin = 1,
133         .passive_delay_skin = 5000,
134
135         .skin_temp_offset = 9793,
136         .skin_period = 1100,
137         .skin_devs_size = 2,
138         .skin_devs = {
139                 {
140                         THERMAL_DEVICE_ID_NCT_EXT,
141                         {
142                                 2, 1, 1, 1,
143                                 1, 1, 1, 1,
144                                 1, 1, 1, 0,
145                                 1, 1, 0, 0,
146                                 0, 0, -1, -7
147                         }
148                 },
149                 {
150                         THERMAL_DEVICE_ID_NCT_INT,
151                         {
152                                 -11, -7, -5, -3,
153                                 -3, -2, -1, 0,
154                                 0, 0, 1, 1,
155                                 1, 2, 2, 3,
156                                 4, 6, 11, 18
157                         }
158                 },
159         },
160 #endif
161 };
162
163 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
164         {
165                 .name           = "bt_rfkill",
166                 .shutdown_gpio  = TEGRA_GPIO_PU0,
167                 .reset_gpio     = TEGRA_GPIO_INVALID,
168                 .type           = RFKILL_TYPE_BLUETOOTH,
169         },
170 };
171
172 static struct platform_device cardhu_bt_rfkill_device = {
173         .name = "rfkill_gpio",
174         .id             = -1,
175         .dev = {
176                 .platform_data = &cardhu_bt_rfkill_pdata,
177         },
178 };
179
180 static struct resource cardhu_bluesleep_resources[] = {
181         [0] = {
182                 .name = "gpio_host_wake",
183                         .start  = TEGRA_GPIO_PU6,
184                         .end    = TEGRA_GPIO_PU6,
185                         .flags  = IORESOURCE_IO,
186         },
187         [1] = {
188                 .name = "gpio_ext_wake",
189                         .start  = TEGRA_GPIO_PU1,
190                         .end    = TEGRA_GPIO_PU1,
191                         .flags  = IORESOURCE_IO,
192         },
193         [2] = {
194                 .name = "host_wake",
195                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
196                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
197                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
198         },
199 };
200
201 static struct platform_device cardhu_bluesleep_device = {
202         .name           = "bluesleep",
203         .id             = -1,
204         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
205         .resource       = cardhu_bluesleep_resources,
206 };
207
208 static noinline void __init cardhu_setup_bluesleep(void)
209 {
210         platform_device_register(&cardhu_bluesleep_device);
211         return;
212 }
213
214 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
215         /* name         parent          rate            enabled */
216         { "pll_m",      NULL,           0,              false},
217         { "hda",        "pll_p",        108000000,      false},
218         { "hda2codec_2x","pll_p",       48000000,       false},
219         { "pwm",        "pll_p",        3187500,        false},
220         { "blink",      "clk_32k",      32768,          true},
221         { "i2s0",       "pll_a_out0",   0,              false},
222         { "i2s1",       "pll_a_out0",   0,              false},
223         { "i2s3",       "pll_a_out0",   0,              false},
224         { "spdif_out",  "pll_a_out0",   0,              false},
225         { "d_audio",    "clk_m",        12000000,       false},
226         { "dam0",       "clk_m",        12000000,       false},
227         { "dam1",       "clk_m",        12000000,       false},
228         { "dam2",       "clk_m",        12000000,       false},
229         { "audio1",     "i2s1_sync",    0,              false},
230         { "audio3",     "i2s3_sync",    0,              false},
231         { "vi_sensor",  "pll_p",        150000000,      false},
232         { "i2c1",       "pll_p",        3200000,        false},
233         { "i2c2",       "pll_p",        3200000,        false},
234         { "i2c3",       "pll_p",        3200000,        false},
235         { "i2c4",       "pll_p",        3200000,        false},
236         { "i2c5",       "pll_p",        3200000,        false},
237         { NULL,         NULL,           0,              0},
238 };
239
240 static struct pn544_i2c_platform_data nfc_pdata = {
241         .irq_gpio = TEGRA_GPIO_PX0,
242         .ven_gpio = TEGRA_GPIO_PP3,
243         .firm_gpio = TEGRA_GPIO_PO7,
244         };
245
246 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
247         {
248                 I2C_BOARD_INFO("pn544", 0x28),
249                 .platform_data = &nfc_pdata,
250                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
251         },
252 };
253 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
254         .adapter_nr     = 0,
255         .bus_count      = 1,
256         .bus_clk_rate   = { 100000, 0 },
257         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
258         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
259         .arb_recovery = arb_lost_recovery,
260 };
261
262 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
263         .adapter_nr     = 1,
264         .bus_count      = 1,
265         .bus_clk_rate   = { 400000, 0 },
266         .is_clkon_always = true,
267         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
268         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
269         .arb_recovery = arb_lost_recovery,
270 };
271
272 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
273         .adapter_nr     = 2,
274         .bus_count      = 1,
275         .bus_clk_rate   = { 100000, 0 },
276         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
277         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
278         .arb_recovery = arb_lost_recovery,
279 };
280
281 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
282         .adapter_nr     = 3,
283         .bus_count      = 1,
284         .bus_clk_rate   = { 10000, 0 },
285         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
286         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
287         .arb_recovery = arb_lost_recovery,
288 };
289
290 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
291         .adapter_nr     = 4,
292         .bus_count      = 1,
293         .bus_clk_rate   = { 400000, 0 },
294         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
295         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
296         .arb_recovery = arb_lost_recovery,
297 };
298
299
300 #if 0
301 struct tegra_wired_jack_conf audio_wr_jack_conf = {
302         .hp_det_n = TEGRA_GPIO_PW2,
303         .en_mic_ext = TEGRA_GPIO_PX1,
304         .en_mic_int = TEGRA_GPIO_PX0,
305 };
306 #endif
307
308 static struct wm8903_platform_data cardhu_wm8903_pdata = {
309         .irq_active_low = 0,
310         .micdet_cfg = 0,
311         .micdet_delay = 100,
312         .gpio_base = CARDHU_GPIO_WM8903(0),
313         .gpio_cfg = {
314                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
315                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
316                         WM8903_GP2_DIR,
317                 0,
318                 WM8903_GPIO_NO_CONFIG,
319                 WM8903_GPIO_NO_CONFIG,
320         },
321 };
322
323 /* Equalizer filter coefs generated from the MAXIM MAX98095
324  * evkit software tool */
325 static struct max98095_eq_cfg max98095_eq_cfg[] = {
326         {
327                 .name = "FLAT",
328                 .rate = 44100,
329                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
330                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
331                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
332                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
333                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
334         },
335         {
336                 .name = "LOWPASS1K",
337                 .rate = 44100,
338                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
339                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
340                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
341                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
342                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
343         },
344         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
345                 .name = "HIBOOST",
346                 .rate = 44100,
347                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
348                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
349                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
350                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
351                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
352         },
353         { /* BASS=12dB, TREBLE=+12dB */
354                 .name = "LOUD12DB",
355                 .rate = 44100,
356                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
357                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
358                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
359                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
360                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
361         },
362         {
363                 .name = "FLAT",
364                 .rate = 16000,
365                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
366                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
367                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
368                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
369                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
370         },
371         {
372                 .name = "LOWPASS1K",
373                 .rate = 16000,
374                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
375                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
376                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
377                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
378                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
379         },
380         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
381                 .name = "HIBOOST",
382                 .rate = 16000,
383                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
384                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
385                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
386                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
387                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
388         },
389         { /* BASS=12dB, TREBLE=+12dB */
390                 .name = "LOUD12DB",
391                 .rate = 16000,
392                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
393                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
394                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
395                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
396                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
397         },
398 };
399
400 static struct max98095_pdata cardhu_max98095_pdata = {
401         /* equalizer configuration */
402         .eq_cfg = max98095_eq_cfg,
403         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
404
405         /* Biquad filter response configuration */
406         .bq_cfg = NULL,
407         .bq_cfgcnt = 0,
408
409         /* microphone configuration */
410         .digmic_left_mode = 1,
411         .digmic_right_mode = 1,
412 };
413
414 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
415         I2C_BOARD_INFO("wm8903", 0x1a),
416         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
417         .platform_data = &cardhu_wm8903_pdata,
418 };
419
420 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
421         I2C_BOARD_INFO("aic3262-codec", 0x18),
422         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
423 };
424
425 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
426         I2C_BOARD_INFO("max98095", 0x10),
427         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
428         .platform_data = &cardhu_max98095_pdata,
429 };
430
431 static void cardhu_i2c_init(void)
432 {
433         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
434         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
435         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
436         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
437         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
438
439         platform_device_register(&tegra_i2c_device5);
440         platform_device_register(&tegra_i2c_device4);
441         platform_device_register(&tegra_i2c_device3);
442         platform_device_register(&tegra_i2c_device2);
443         platform_device_register(&tegra_i2c_device1);
444
445         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
446         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
447         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
448
449         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
450 }
451
452 static struct platform_device *cardhu_uart_devices[] __initdata = {
453         &tegra_uarta_device,
454         &tegra_uartb_device,
455         &tegra_uartc_device,
456         &tegra_uartd_device,
457         &tegra_uarte_device,
458 };
459 static struct uart_clk_parent uart_parent_clk[] = {
460         [0] = {.name = "clk_m"},
461         [1] = {.name = "pll_p"},
462 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
463         [2] = {.name = "pll_m"},
464 #endif
465 };
466
467 static struct tegra_uart_platform_data cardhu_uart_pdata;
468 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
469
470 static void __init uart_debug_init(void)
471 {
472         struct board_info board_info;
473         int debug_port_id;
474
475         tegra_get_board_info(&board_info);
476
477         debug_port_id = get_tegra_uart_debug_port_id();
478         if (debug_port_id < 0) {
479                 debug_port_id = 0;
480                         /* UARTB is debug port
481                          *       for SLT - E1186/E1187/PM269
482                          *       for E1256/E1257
483                          */
484                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
485                         ((board_info.board_id == BOARD_E1186) ||
486                         (board_info.board_id == BOARD_E1187) ||
487                         (board_info.board_id == BOARD_PM269))) ||
488                         (board_info.board_id == BOARD_E1256) ||
489                         (board_info.board_id == BOARD_E1257))
490                                 debug_port_id = 1;
491         }
492
493         switch (debug_port_id) {
494         case 0:
495                 /* UARTA is the debug port. */
496                 pr_info("Selecting UARTA as the debug console\n");
497                 cardhu_uart_devices[0] = &debug_uarta_device;
498                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
499                 debug_uart_port_base = ((struct plat_serial8250_port *)(
500                         debug_uarta_device.dev.platform_data))->mapbase;
501                 break;
502
503         case 1:
504                 /* UARTB is the debug port. */
505                 pr_info("Selecting UARTB as the debug console\n");
506                 cardhu_uart_devices[1] = &debug_uartb_device;
507                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
508                 debug_uart_port_base = ((struct plat_serial8250_port *)(
509                         debug_uartb_device.dev.platform_data))->mapbase;
510                 break;
511
512         case 2:
513                 /* UARTC is the debug port. */
514                 pr_info("Selecting UARTC as the debug console\n");
515                 cardhu_uart_devices[2] = &debug_uartc_device;
516                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
517                 debug_uart_port_base = ((struct plat_serial8250_port *)(
518                         debug_uartc_device.dev.platform_data))->mapbase;
519                 break;
520
521         case 3:
522                 /* UARTD is the debug port. */
523                 pr_info("Selecting UARTD as the debug console\n");
524                 cardhu_uart_devices[3] = &debug_uartd_device;
525                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
526                 debug_uart_port_base = ((struct plat_serial8250_port *)(
527                         debug_uartd_device.dev.platform_data))->mapbase;
528                 break;
529
530         case 4:
531                 /* UARTE is the debug port. */
532                 pr_info("Selecting UARTE as the debug console\n");
533                 cardhu_uart_devices[4] = &debug_uarte_device;
534                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
535                 debug_uart_port_base = ((struct plat_serial8250_port *)(
536                         debug_uarte_device.dev.platform_data))->mapbase;
537                 break;
538
539         default:
540                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
541                 cardhu_uart_devices[0] = &debug_uarta_device;
542                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
543                 debug_uart_port_base = ((struct plat_serial8250_port *)(
544                         debug_uarta_device.dev.platform_data))->mapbase;
545                 break;
546         }
547         return;
548 }
549
550 static void __init cardhu_uart_init(void)
551 {
552         struct clk *c;
553         int i;
554
555         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
556                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
557                 if (IS_ERR_OR_NULL(c)) {
558                         pr_err("Not able to get the clock for %s\n",
559                                                 uart_parent_clk[i].name);
560                         continue;
561                 }
562                 uart_parent_clk[i].parent_clk = c;
563                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
564         }
565         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
566         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
567         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
568         cardhu_loopback_uart_pdata.parent_clk_count =
569                                                 ARRAY_SIZE(uart_parent_clk);
570         cardhu_loopback_uart_pdata.is_loopback = true;
571         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
572         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
573         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
574         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
575         /* UARTE is used for loopback test purpose */
576         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
577
578         /* Register low speed only if it is selected */
579         if (!is_tegra_debug_uartport_hs()) {
580                 uart_debug_init();
581                 /* Clock enable for the debug channel */
582                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
583                         pr_info("The debug console clock name is %s\n",
584                                                 debug_uart_clk->name);
585                         c = tegra_get_clock_by_name("pll_p");
586                         if (IS_ERR_OR_NULL(c))
587                                 pr_err("Not getting the parent clock pll_p\n");
588                         else
589                                 clk_set_parent(debug_uart_clk, c);
590
591                         clk_enable(debug_uart_clk);
592                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
593                 } else {
594                         pr_err("Not getting the clock %s for debug console\n",
595                                         debug_uart_clk->name);
596                 }
597         }
598
599         platform_add_devices(cardhu_uart_devices,
600                                 ARRAY_SIZE(cardhu_uart_devices));
601 }
602
603 static struct platform_device tegra_camera = {
604         .name = "tegra_camera",
605         .id = -1,
606 };
607
608 static struct platform_device *cardhu_spi_devices[] __initdata = {
609         &tegra_spi_device4,
610 };
611
612 static struct platform_device *touch_spi_device[] __initdata = {
613         &tegra_spi_device1,
614 };
615
616 struct spi_clk_parent spi_parent_clk[] = {
617         [0] = {.name = "pll_p"},
618 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
619         [1] = {.name = "pll_m"},
620         [2] = {.name = "clk_m"},
621 #else
622         [1] = {.name = "clk_m"},
623 #endif
624 };
625
626 static struct tegra_spi_platform_data cardhu_spi_pdata = {
627         .is_dma_based           = true,
628         .max_dma_buffer         = (16 * 1024),
629         .is_clkon_always        = false,
630         .max_rate               = 100000000,
631 };
632
633 static void __init cardhu_spi_init(void)
634 {
635         int i;
636         struct clk *c;
637         struct board_info board_info, display_board_info;
638
639         tegra_get_board_info(&board_info);
640         tegra_get_display_board_info(&display_board_info);
641
642         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
643                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
644                 if (IS_ERR_OR_NULL(c)) {
645                         pr_err("Not able to get the clock for %s\n",
646                                                 spi_parent_clk[i].name);
647                         continue;
648                 }
649                 spi_parent_clk[i].parent_clk = c;
650                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
651         }
652         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
653         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
654         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
655         platform_add_devices(cardhu_spi_devices,
656                                 ARRAY_SIZE(cardhu_spi_devices));
657
658         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
659                 platform_add_devices(touch_spi_device,
660                                 ARRAY_SIZE(touch_spi_device));
661         }
662         if (board_info.board_id == BOARD_E1198) {
663                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
664                 platform_device_register(&tegra_spi_device2);
665                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
666                 platform_device_register(&tegra_spi_slave_device1);
667         }
668 }
669
670 static void __init cardhu_dtv_init(void)
671 {
672         struct board_info board_info;
673
674         tegra_get_board_info(&board_info);
675
676         if (board_info.board_id == BOARD_E1186)
677                 platform_device_register(&tegra_dtv_device);
678 }
679
680 static struct resource tegra_rtc_resources[] = {
681         [0] = {
682                 .start = TEGRA_RTC_BASE,
683                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
684                 .flags = IORESOURCE_MEM,
685         },
686         [1] = {
687                 .start = INT_RTC,
688                 .end = INT_RTC,
689                 .flags = IORESOURCE_IRQ,
690         },
691 };
692
693 static struct platform_device tegra_rtc_device = {
694         .name = "tegra_rtc",
695         .id   = -1,
696         .resource = tegra_rtc_resources,
697         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
698 };
699
700 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
701         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
702         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
703         .gpio_hp_mute           = -1,
704         .gpio_int_mic_en        = -1,
705         .gpio_ext_mic_en        = -1,
706 };
707
708 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
709         .gpio_spkr_en           = -1,
710         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
711         .gpio_hp_mute           = -1,
712         .gpio_int_mic_en        = -1,
713         .gpio_ext_mic_en        = -1,
714 };
715
716 static struct platform_device cardhu_audio_wm8903_device = {
717         .name   = "tegra-snd-wm8903",
718         .id     = 0,
719         .dev    = {
720                 .platform_data = &cardhu_audio_wm8903_pdata,
721         },
722 };
723
724 static struct platform_device cardhu_audio_max98095_device = {
725         .name   = "tegra-snd-max98095",
726         .id     = 0,
727         .dev    = {
728                 .platform_data = &cardhu_audio_max98095_pdata,
729         },
730 };
731
732 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
733         .gpio_spkr_en           = -1,
734         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
735         .gpio_hp_mute           = -1,
736         .gpio_int_mic_en        = -1,
737         .gpio_ext_mic_en        = -1,
738         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
739         .audio_port_id          = {
740                 [HIFI_CODEC] = 0,
741                 [BASEBAND] = -1,
742                 [BT_SCO] = 3,
743         },
744         .baseband_param         = {
745                 .rate = -1,
746                 .channels = -1,
747         },
748 };
749
750 static struct platform_device cardhu_audio_aic326x_device = {
751         .name   = "tegra-snd-aic326x",
752         .id     = 0,
753         .dev    = {
754                 .platform_data  = &cardhu_audio_aic326x_pdata,
755         },
756 };
757
758 static struct platform_device *cardhu_devices[] __initdata = {
759         &tegra_pmu_device,
760         &tegra_rtc_device,
761         &tegra_udc_device,
762 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
763         &tegra_smmu_device,
764 #endif
765         &tegra_wdt0_device,
766         &tegra_wdt1_device,
767         &tegra_wdt2_device,
768 #if defined(CONFIG_TEGRA_AVP)
769         &tegra_avp_device,
770 #endif
771         &tegra_camera,
772 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
773         &tegra_se_device,
774 #endif
775         &tegra_ahub_device,
776         &tegra_dam_device0,
777         &tegra_dam_device1,
778         &tegra_dam_device2,
779         &tegra_i2s_device0,
780         &tegra_i2s_device1,
781         &tegra_i2s_device3,
782         &tegra_spdif_device,
783         &spdif_dit_device,
784         &bluetooth_dit_device,
785         &baseband_dit_device,
786         &cardhu_bt_rfkill_device,
787         &tegra_pcm_device,
788         &cardhu_audio_wm8903_device,
789         &cardhu_audio_max98095_device,
790         &cardhu_audio_aic326x_device,
791         &tegra_hda_device,
792         &tegra_cec_device,
793 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
794         &tegra_aes_device,
795 #endif
796 };
797
798 #define E1506_MXT_CONFIG_CRC 0x62F903
799 static const u8 e1506_config[] = {
800         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
801         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
802         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
803         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
804         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
805         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
806         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
808         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
809         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
810         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
811         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
812         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
813         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
814         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
815         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
817         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
818         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
819         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
820         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
821         0x00
822 };
823
824 #define MXT_CONFIG_CRC  0xD62DE8
825 static const u8 config[] = {
826         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
827         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
828         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
829         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
830         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
831         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
832         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
833         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
835         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
836         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
837         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
838         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
839         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
840         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
843         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
844         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
845         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
846 };
847
848 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
849 static const u8 config_sku2000[] = {
850         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
852         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
853         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
854         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
855         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
856         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
857         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
858         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
859         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
860         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
861         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
862         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
863         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
864         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
868         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
869         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
870 };
871
872 static struct mxt_platform_data atmel_mxt_info = {
873         .x_line         = 27,
874         .y_line         = 42,
875         .x_size         = 768,
876         .y_size         = 1366,
877         .blen           = 0x20,
878         .threshold      = 0x3C,
879         .voltage        = 3300000,              /* 3.3V */
880         .orient         = 5,
881         .config         = config,
882         .config_length  = 157,
883         .config_crc     = MXT_CONFIG_CRC,
884         .irqflags       = IRQF_TRIGGER_FALLING,
885 /*      .read_chg       = &read_chg, */
886         .read_chg       = NULL,
887 };
888
889 static struct mxt_platform_data e1506_atmel_mxt_info = {
890         .x_line         = 19,
891         .y_line         = 11,
892         .x_size         = 960,
893         .y_size         = 540,
894         .blen           = 0x10,
895         .threshold      = 0x32,
896         .voltage        = 3300000,              /* 3.3V */
897         .orient         = 3,
898         .config         = e1506_config,
899         .config_length  = 168,
900         .config_crc     = E1506_MXT_CONFIG_CRC,
901         .irqflags       = IRQF_TRIGGER_FALLING,
902 /*      .read_chg       = &read_chg, */
903         .read_chg       = NULL,
904 };
905
906 static struct i2c_board_info __initdata atmel_i2c_info[] = {
907         {
908                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
909                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
910                 .platform_data = &atmel_mxt_info,
911         }
912 };
913
914 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
915         {
916                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
917                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
918                 .platform_data = &e1506_atmel_mxt_info,
919         }
920 };
921
922 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
923         /* name         parent          rate            enabled */
924         { "sbc1",       "pll_p",        52000000,       true},
925         { NULL,         NULL,           0,              0},
926 };
927
928 static int __init cardhu_touch_init(void)
929 {
930         struct board_info BoardInfo, DisplayBoardInfo;
931
932         tegra_get_board_info(&BoardInfo);
933         tegra_get_display_board_info(&DisplayBoardInfo);
934         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
935                 tegra_clk_init_from_table(spi_clk_init_table);
936
937                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
938         } else {
939                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
940                 gpio_direction_input(TEGRA_GPIO_PH4);
941
942                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
943                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
944                 msleep(1);
945                 gpio_set_value(TEGRA_GPIO_PH6, 1);
946                 msleep(100);
947
948                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
949                         atmel_mxt_info.config = config_sku2000;
950                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
951                 }
952
953                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506)
954                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
955                 else
956                         i2c_register_board_info(1, atmel_i2c_info, 1);
957         }
958
959         return 0;
960 }
961
962 #if defined(CONFIG_USB_SUPPORT)
963
964 static void cardu_usb_hsic_postsupend(void)
965 {
966 #ifdef CONFIG_TEGRA_BB_XMM_POWER
967         baseband_xmm_set_power_status(BBXMM_PS_L2);
968 #endif
969 }
970
971 static void cardu_usb_hsic_preresume(void)
972 {
973 #ifdef CONFIG_TEGRA_BB_XMM_POWER
974         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
975 #endif
976 }
977
978 static void cardu_usb_hsic_phy_ready(void)
979 {
980 #ifdef CONFIG_TEGRA_BB_XMM_POWER
981         baseband_xmm_set_power_status(BBXMM_PS_L0);
982 #endif
983 }
984
985 static void cardu_usb_hsic_phy_off(void)
986 {
987 #ifdef CONFIG_TEGRA_BB_XMM_POWER
988         baseband_xmm_set_power_status(BBXMM_PS_L3);
989 #endif
990 }
991
992 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
993         .post_suspend = cardu_usb_hsic_postsupend,
994         .pre_resume = cardu_usb_hsic_preresume,
995         .port_power = cardu_usb_hsic_phy_ready,
996         .post_phy_off = cardu_usb_hsic_phy_off,
997 };
998
999 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1000         .port_otg = false,
1001         .has_hostpc = true,
1002         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1003         .op_mode        = TEGRA_USB_OPMODE_HOST,
1004         .u_data.host = {
1005                 .vbus_gpio = -1,
1006                 .hot_plug = false,
1007                 .remote_wakeup_supported = false,
1008                 .power_off_on_suspend = false,
1009         },
1010         .u_cfg.hsic = {
1011                 .sync_start_delay = 9,
1012                 .idle_wait_delay = 17,
1013                 .term_range_adj = 0,
1014                 .elastic_underrun_limit = 16,
1015                 .elastic_overrun_limit = 16,
1016         },
1017         .ops = &hsic_xmm_plat_ops,
1018 };
1019 #endif
1020
1021 static int hsic_enable_gpio = -1;
1022 static int hsic_reset_gpio = -1;
1023
1024 void hsic_platform_open(void)
1025 {
1026         int reset_gpio = 0, enable_gpio = 0;
1027
1028         if (hsic_enable_gpio != -1)
1029                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1030         if (hsic_reset_gpio != -1)
1031                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1032         /* hsic enable signal deasserted, hsic reset asserted */
1033         if (!enable_gpio)
1034                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1035         if (!reset_gpio)
1036                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1037         if (!enable_gpio)
1038                 tegra_gpio_enable(hsic_enable_gpio);
1039         if (!reset_gpio)
1040                 tegra_gpio_enable(hsic_reset_gpio);
1041         /* keep hsic reset asserted for 1 ms */
1042         udelay(1000);
1043         /* enable (power on) hsic */
1044         if (!enable_gpio)
1045                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1046         udelay(1000);
1047         /* deassert reset */
1048         if (!reset_gpio)
1049                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1050
1051 }
1052
1053 void hsic_platform_close(void)
1054 {
1055         if (hsic_enable_gpio != -1) {
1056                 gpio_set_value(hsic_enable_gpio, 0);
1057                 gpio_free(hsic_enable_gpio);
1058         }
1059         if (hsic_reset_gpio != -1) {
1060                 gpio_set_value(hsic_reset_gpio, 0);
1061                 gpio_free(hsic_reset_gpio);
1062         }
1063 }
1064
1065 void hsic_power_on(void)
1066 {
1067         if (hsic_enable_gpio != -1) {
1068                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1069                 udelay(1000);
1070         }
1071 }
1072
1073 void hsic_power_off(void)
1074 {
1075         if (hsic_enable_gpio != -1) {
1076                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1077                 udelay(1000);
1078         }
1079 }
1080
1081 #if defined(CONFIG_USB_SUPPORT)
1082 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1083         .open = hsic_platform_open,
1084         .close = hsic_platform_close,
1085         .pre_phy_on = hsic_power_on,
1086         .post_phy_off = hsic_power_off,
1087 };
1088
1089 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1090         .port_otg = false,
1091         .has_hostpc = true,
1092         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1093         .op_mode        = TEGRA_USB_OPMODE_HOST,
1094         .u_data.host = {
1095                 .vbus_gpio = -1,
1096                 .hot_plug = false,
1097                 .remote_wakeup_supported = false,
1098                 .power_off_on_suspend = false,
1099         },
1100         .u_cfg.hsic = {
1101                 .sync_start_delay = 9,
1102                 .idle_wait_delay = 17,
1103                 .term_range_adj = 0,
1104                 .elastic_underrun_limit = 16,
1105                 .elastic_overrun_limit = 16,
1106         },
1107         .ops = &hsic_plat_ops,
1108 };
1109
1110 static struct tegra_usb_platform_data tegra_udc_pdata = {
1111         .port_otg = true,
1112         .has_hostpc = true,
1113         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1114         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1115         .u_data.dev = {
1116                 .vbus_pmu_irq = 0,
1117                 .vbus_gpio = -1,
1118                 .charging_supported = false,
1119                 .remote_wakeup_supported = false,
1120         },
1121         .u_cfg.utmi = {
1122                 .hssync_start_delay = 0,
1123                 .elastic_limit = 16,
1124                 .idle_wait_delay = 17,
1125                 .term_range_adj = 6,
1126                 .xcvr_setup = 8,
1127                 .xcvr_lsfslew = 2,
1128                 .xcvr_lsrslew = 2,
1129                 .xcvr_setup_offset = 0,
1130                 .xcvr_use_fuses = 1,
1131         },
1132 };
1133
1134 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1135         .port_otg = false,
1136         .has_hostpc = true,
1137         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1138         .op_mode        = TEGRA_USB_OPMODE_HOST,
1139         .u_data.host = {
1140                 .vbus_gpio = -1,
1141                 .hot_plug = false,
1142                 .remote_wakeup_supported = true,
1143                 .power_off_on_suspend = true,
1144         },
1145         .u_cfg.utmi = {
1146                 .hssync_start_delay = 0,
1147                 .elastic_limit = 16,
1148                 .idle_wait_delay = 17,
1149                 .term_range_adj = 6,
1150                 .xcvr_setup = 15,
1151                 .xcvr_lsfslew = 2,
1152                 .xcvr_lsrslew = 2,
1153                 .xcvr_setup_offset = 0,
1154                 .xcvr_use_fuses = 1,
1155         },
1156 };
1157
1158 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1159         .port_otg = false,
1160         .has_hostpc = true,
1161         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1162         .op_mode = TEGRA_USB_OPMODE_HOST,
1163         .u_data.host = {
1164                 .vbus_gpio = -1,
1165                 .vbus_reg = "vdd_vbus_typea_usb",
1166                 .hot_plug = true,
1167                 .remote_wakeup_supported = true,
1168                 .power_off_on_suspend = true,
1169         },
1170         .u_cfg.utmi = {
1171                 .hssync_start_delay = 0,
1172                 .elastic_limit = 16,
1173                 .idle_wait_delay = 17,
1174                 .term_range_adj = 6,
1175                 .xcvr_setup = 8,
1176                 .xcvr_lsfslew = 2,
1177                 .xcvr_lsrslew = 2,
1178                 .xcvr_setup_offset = 0,
1179                 .xcvr_use_fuses = 1,
1180         },
1181 };
1182
1183 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1184         .port_otg = true,
1185         .has_hostpc = true,
1186         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1187         .op_mode = TEGRA_USB_OPMODE_HOST,
1188         .u_data.host = {
1189                 .vbus_gpio = -1,
1190                 .vbus_reg = "vdd_vbus_micro_usb",
1191                 .hot_plug = true,
1192                 .remote_wakeup_supported = true,
1193                 .power_off_on_suspend = true,
1194         },
1195         .u_cfg.utmi = {
1196                 .hssync_start_delay = 0,
1197                 .elastic_limit = 16,
1198                 .idle_wait_delay = 17,
1199                 .term_range_adj = 6,
1200                 .xcvr_setup = 15,
1201                 .xcvr_lsfslew = 2,
1202                 .xcvr_lsrslew = 2,
1203                 .xcvr_setup_offset = 0,
1204                 .xcvr_use_fuses = 1,
1205         },
1206 };
1207
1208 static struct tegra_usb_otg_data tegra_otg_pdata = {
1209         .ehci_device = &tegra_ehci1_device,
1210         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1211 };
1212 #endif
1213
1214 #if defined(CONFIG_USB_SUPPORT)
1215 static void cardhu_usb_init(void)
1216 {
1217         struct board_info bi;
1218
1219         tegra_get_board_info(&bi);
1220
1221         /* OTG should be the first to be registered */
1222         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1223         platform_device_register(&tegra_otg_device);
1224
1225         /* setup the udc platform data */
1226         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1227
1228         if (bi.board_id == BOARD_PM267) {
1229                 hsic_enable_gpio = EN_HSIC_GPIO;
1230                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1231                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1232                 platform_device_register(&tegra_ehci2_device);
1233         } else if (bi.board_id == BOARD_E1256) {
1234                 hsic_enable_gpio = EN_HSIC_GPIO;
1235                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1236                 platform_device_register(&tegra_ehci2_device);
1237         } else if (bi.board_id == BOARD_E1186) {
1238                 tegra_ehci2_device.dev.platform_data =
1239                                                 &tegra_ehci2_hsic_xmm_pdata;
1240                 /* ehci2 registration happens in baseband-xmm-power  */
1241         } else {
1242                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1243                 platform_device_register(&tegra_ehci2_device);
1244         }
1245
1246         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1247         platform_device_register(&tegra_ehci3_device);
1248
1249 }
1250 #else
1251 static void cardhu_usb_init(void) { }
1252 #endif
1253
1254 static struct baseband_power_platform_data tegra_baseband_power_data = {
1255         .baseband_type = BASEBAND_XMM,
1256         .modem = {
1257         .xmm = {
1258                         .bb_rst = XMM_GPIO_BB_RST,
1259                         .bb_on = XMM_GPIO_BB_ON,
1260                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1261                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1262                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1263                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1264                         .hsic_device = &tegra_ehci2_device,
1265                 },
1266         },
1267 };
1268
1269 static struct platform_device tegra_baseband_power_device = {
1270         .name = "baseband_xmm_power",
1271         .id = -1,
1272         .dev = {
1273                 .platform_data = &tegra_baseband_power_data,
1274         },
1275 };
1276
1277 static struct platform_device tegra_baseband_power2_device = {
1278         .name = "baseband_xmm_power2",
1279         .id = -1,
1280         .dev = {
1281                 .platform_data = &tegra_baseband_power_data,
1282         },
1283 };
1284
1285
1286 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1287         .port_status[0] = 1,
1288         .port_status[1] = 1,
1289         .port_status[2] = 1,
1290         .use_dock_detect        = 0,
1291         .gpio           = 0,
1292 };
1293
1294 static void cardhu_pci_init(void)
1295 {
1296         struct board_info board_info;
1297
1298         tegra_get_board_info(&board_info);
1299         if (board_info.board_id == BOARD_E1291) {
1300                 cardhu_pci_platform_data.port_status[0] = 0;
1301                 cardhu_pci_platform_data.port_status[1] = 0;
1302                 cardhu_pci_platform_data.port_status[2] = 1;
1303                 cardhu_pci_platform_data.use_dock_detect = 1;
1304                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1305         }
1306         if ((board_info.board_id == BOARD_E1186) ||
1307                 (board_info.board_id == BOARD_E1187) ||
1308                 (board_info.board_id == BOARD_E1291)) {
1309                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1310                 platform_device_register(&tegra_pci_device);
1311         }
1312 }
1313
1314 static void cardhu_modem_init(void)
1315 {
1316         struct board_info board_info;
1317         int w_disable_gpio, ret;
1318
1319         tegra_get_board_info(&board_info);
1320         switch (board_info.board_id) {
1321         case BOARD_E1291:
1322         case BOARD_E1198:
1323                 if (((board_info.board_id == BOARD_E1291) &&
1324                                 (board_info.fab < BOARD_FAB_A03)) ||
1325                         ((board_info.board_id == BOARD_E1198) &&
1326                                         (board_info.fab < BOARD_FAB_A02))) {
1327                         w_disable_gpio = TEGRA_GPIO_PH5;
1328                 } else {
1329                         w_disable_gpio = TEGRA_GPIO_PDD5;
1330                 }
1331
1332                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1333                 if (ret < 0)
1334                         pr_err("%s: gpio_request failed for gpio %d\n",
1335                                 __func__, w_disable_gpio);
1336                 else
1337                         gpio_direction_input(w_disable_gpio);
1338
1339                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1340                 if (((board_info.board_id == BOARD_E1291) &&
1341                                 (board_info.fab >= BOARD_FAB_A04)) ||
1342                         ((board_info.board_id == BOARD_E1198) &&
1343                                         (board_info.fab >= BOARD_FAB_A02))) {
1344                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1345                         if (ret < 0) {
1346                                 pr_err("%s(): Error in allocating gpio "
1347                                         "TEGRA_GPIO_PH7\n", __func__);
1348                                 break;
1349                         }
1350                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1351                 }
1352                 break;
1353         case BOARD_E1186:
1354                 platform_device_register(&tegra_baseband_power_device);
1355                 platform_device_register(&tegra_baseband_power2_device);
1356                 break;
1357         default:
1358                 break;
1359         }
1360
1361 }
1362
1363 #ifdef CONFIG_SATA_AHCI_TEGRA
1364 static void cardhu_sata_init(void)
1365 {
1366         platform_device_register(&tegra_sata_device);
1367 }
1368 #else
1369 static void cardhu_sata_init(void) { }
1370 #endif
1371
1372 static void __init tegra_cardhu_init(void)
1373 {
1374         tegra_thermal_init(&thermal_data,
1375                                 throttle_list,
1376                                 ARRAY_SIZE(throttle_list));
1377         tegra_clk_init_from_table(cardhu_clk_init_table);
1378         cardhu_pinmux_init();
1379         cardhu_i2c_init();
1380         cardhu_spi_init();
1381         cardhu_usb_init();
1382 #ifdef CONFIG_TEGRA_EDP_LIMITS
1383         cardhu_edp_init();
1384 #endif
1385         cardhu_uart_init();
1386         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1387         tegra_ram_console_debug_init();
1388         cardhu_sdhci_init();
1389         cardhu_regulator_init();
1390         cardhu_dtv_init();
1391         cardhu_suspend_init();
1392         cardhu_touch_init();
1393         cardhu_modem_init();
1394         cardhu_kbc_init();
1395         cardhu_scroll_init();
1396         cardhu_keys_init();
1397         cardhu_panel_init();
1398         cardhu_pmon_init();
1399         cardhu_sensors_init();
1400         cardhu_setup_bluesleep();
1401         cardhu_sata_init();
1402         //audio_wired_jack_init();
1403         cardhu_pins_state_init();
1404         cardhu_emc_init();
1405         tegra_release_bootloader_fb();
1406         cardhu_pci_init();
1407 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1408         tegra_wdt_recovery_init();
1409 #endif
1410         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1411 }
1412
1413 static void __init tegra_cardhu_reserve(void)
1414 {
1415 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1416         /* support 1920X1200 with 24bpp */
1417         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1418 #else
1419         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1420 #endif
1421         tegra_ram_console_debug_reserve(SZ_1M);
1422 }
1423
1424 MACHINE_START(CARDHU, "cardhu")
1425         .boot_params    = 0x80000100,
1426         .map_io         = tegra_map_common_io,
1427         .reserve        = tegra_cardhu_reserve,
1428         .init_early     = tegra_init_early,
1429         .init_irq       = tegra_init_irq,
1430         .timer          = &tegra_timer,
1431         .init_machine   = tegra_cardhu_init,
1432 MACHINE_END