arm: tegra: update thermal sensor configurations
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/spi-tegra.h>
40 #include <linux/nfc/pn544.h>
41
42 #include <sound/wm8903.h>
43 #include <sound/max98095.h>
44 #include <media/tegra_dtv.h>
45
46 #include <mach/clk.h>
47 #include <mach/iomap.h>
48 #include <mach/irqs.h>
49 #include <mach/pinmux.h>
50 #include <mach/iomap.h>
51 #include <mach/io.h>
52 #include <mach/i2s.h>
53 #include <mach/tegra_asoc_pdata.h>
54 #include <mach/tegra_wm8903_pdata.h>
55 #include <asm/mach-types.h>
56 #include <asm/mach/arch.h>
57 #include <mach/usb_phy.h>
58 #include <mach/thermal.h>
59 #include <mach/pci.h>
60
61 #include "board.h"
62 #include "clock.h"
63 #include "board-cardhu.h"
64 #include "devices.h"
65 #include "gpio-names.h"
66 #include "fuse.h"
67 #include "pm.h"
68 #include "baseband-xmm-power.h"
69 #include "wdt-recovery.h"
70
71 /* All units are in millicelsius */
72 static struct tegra_thermal_data thermal_data = {
73         .temp_throttle = 85000,
74         .temp_shutdown = 90000,
75         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
76 #ifdef CONFIG_TEGRA_EDP_LIMITS
77         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
78         .hysteresis_edp = 3000,
79 #endif
80 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
81         .tc1 = 0,
82         .tc2 = 1,
83         .passive_delay = 2000,
84 #else
85         .hysteresis_throttle = 1000,
86 #endif
87 };
88
89 /* !!!TODO: Change for cardhu (Taken from Ventana) */
90 static struct tegra_utmip_config utmi_phy_config[] = {
91         [0] = {
92                         .hssync_start_delay = 0,
93                         .idle_wait_delay = 17,
94                         .elastic_limit = 16,
95                         .term_range_adj = 6,
96                         .xcvr_setup = 15,
97                         .xcvr_setup_offset = 0,
98                         .xcvr_use_fuses = 1,
99                         .xcvr_lsfslew = 2,
100                         .xcvr_lsrslew = 2,
101         },
102         [1] = {
103                         .hssync_start_delay = 0,
104                         .idle_wait_delay = 17,
105                         .elastic_limit = 16,
106                         .term_range_adj = 6,
107                         .xcvr_setup = 15,
108                         .xcvr_setup_offset = 0,
109                         .xcvr_use_fuses = 1,
110                         .xcvr_lsfslew = 2,
111                         .xcvr_lsrslew = 2,
112         },
113         [2] = {
114                         .hssync_start_delay = 0,
115                         .idle_wait_delay = 17,
116                         .elastic_limit = 16,
117                         .term_range_adj = 6,
118                         .xcvr_setup = 8,
119                         .xcvr_setup_offset = 0,
120                         .xcvr_use_fuses = 1,
121                         .xcvr_lsfslew = 2,
122                         .xcvr_lsrslew = 2,
123         },
124 };
125
126 #ifdef CONFIG_BCM4329_RFKILL
127 static struct resource cardhu_bcm4329_rfkill_resources[] = {
128         {
129                 .name   = "bcm4329_nshutdown_gpio",
130                 .start  = TEGRA_GPIO_PU0,
131                 .end    = TEGRA_GPIO_PU0,
132                 .flags  = IORESOURCE_IO,
133         },
134 };
135
136 static struct platform_device cardhu_bcm4329_rfkill_device = {
137         .name = "bcm4329_rfkill",
138         .id             = -1,
139         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
140         .resource       = cardhu_bcm4329_rfkill_resources,
141 };
142
143 static noinline void __init cardhu_bt_rfkill(void)
144 {
145         platform_device_register(&cardhu_bcm4329_rfkill_device);
146
147         return;
148 }
149 #else
150 static inline void cardhu_bt_rfkill(void) { }
151 #endif
152
153 #ifdef CONFIG_BT_BLUESLEEP
154 static noinline void __init tegra_setup_bluesleep(void)
155 {
156         struct platform_device *pdev = NULL;
157         struct resource *res;
158
159         pdev = platform_device_alloc("bluesleep", 0);
160         if (!pdev) {
161                 pr_err("unable to allocate platform device for bluesleep");
162                 return;
163         }
164
165         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
166         if (!res) {
167                 pr_err("unable to allocate resource for bluesleep\n");
168                 goto err_free_dev;
169         }
170
171         res[0].name   = "gpio_host_wake";
172         res[0].start  = TEGRA_GPIO_PU6;
173         res[0].end    = TEGRA_GPIO_PU6;
174         res[0].flags  = IORESOURCE_IO;
175
176         res[1].name   = "gpio_ext_wake";
177         res[1].start  = TEGRA_GPIO_PU1;
178         res[1].end    = TEGRA_GPIO_PU1;
179         res[1].flags  = IORESOURCE_IO;
180
181         res[2].name   = "host_wake";
182         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
183         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
184         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
185
186         if (platform_device_add_resources(pdev, res, 3)) {
187                 pr_err("unable to add resources to bluesleep device\n");
188                 goto err_free_res;
189         }
190
191         if (platform_device_add(pdev)) {
192                 pr_err("unable to add bluesleep device\n");
193                 goto err_free_res;
194         }
195         tegra_gpio_enable(TEGRA_GPIO_PU6);
196         tegra_gpio_enable(TEGRA_GPIO_PU1);
197
198 return;
199
200 err_free_res:
201         kfree(res);
202 err_free_dev:
203         platform_device_put(pdev);
204         return;
205 }
206 #else
207 static inline void tegra_setup_bluesleep(void) { }
208 #endif
209
210 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
211         /* name         parent          rate            enabled */
212         { "pll_m",      NULL,           0,              false},
213         { "hda",        "pll_p",        108000000,      false},
214         { "hda2codec_2x","pll_p",       48000000,       false},
215         { "pwm",        "pll_p",        3187500,        false},
216         { "blink",      "clk_32k",      32768,          true},
217         { "i2s0",       "pll_a_out0",   0,              false},
218         { "i2s1",       "pll_a_out0",   0,              false},
219         { "i2s3",       "pll_a_out0",   0,              false},
220         { "spdif_out",  "pll_a_out0",   0,              false},
221         { "d_audio",    "clk_m",        12000000,       false},
222         { "dam0",       "clk_m",        12000000,       false},
223         { "dam1",       "clk_m",        12000000,       false},
224         { "dam2",       "clk_m",        12000000,       false},
225         { "audio1",     "i2s1_sync",    0,              false},
226         { "audio3",     "i2s3_sync",    0,              false},
227         { "vi_sensor",  "pll_p",        150000000,      false},
228         { "i2c1",       "pll_p",        3200000,        false},
229         { "i2c2",       "pll_p",        3200000,        false},
230         { "i2c3",       "pll_p",        3200000,        false},
231         { "i2c4",       "pll_p",        3200000,        false},
232         { "i2c5",       "pll_p",        3200000,        false},
233         { NULL,         NULL,           0,              0},
234 };
235
236 static struct pn544_i2c_platform_data nfc_pdata = {
237         .irq_gpio = TEGRA_GPIO_PX0,
238         .ven_gpio = TEGRA_GPIO_PP3,
239         .firm_gpio = TEGRA_GPIO_PO7,
240         };
241
242 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
243         {
244                 I2C_BOARD_INFO("pn544", 0x28),
245                 .platform_data = &nfc_pdata,
246                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
247         },
248 };
249 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
250         .adapter_nr     = 0,
251         .bus_count      = 1,
252         .bus_clk_rate   = { 100000, 0 },
253         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
254         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
255         .arb_recovery = arb_lost_recovery,
256 };
257
258 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
259         .adapter_nr     = 1,
260         .bus_count      = 1,
261         .bus_clk_rate   = { 100000, 0 },
262         .is_clkon_always = true,
263         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
264         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
265         .arb_recovery = arb_lost_recovery,
266 };
267
268 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
269         .adapter_nr     = 2,
270         .bus_count      = 1,
271         .bus_clk_rate   = { 100000, 0 },
272         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
273         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
274         .arb_recovery = arb_lost_recovery,
275 };
276
277 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
278         .adapter_nr     = 3,
279         .bus_count      = 1,
280         .bus_clk_rate   = { 100000, 0 },
281         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
282         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
283         .arb_recovery = arb_lost_recovery,
284 };
285
286 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
287         .adapter_nr     = 4,
288         .bus_count      = 1,
289         .bus_clk_rate   = { 400000, 0 },
290         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
291         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
292         .arb_recovery = arb_lost_recovery,
293 };
294
295
296 #if 0
297 struct tegra_wired_jack_conf audio_wr_jack_conf = {
298         .hp_det_n = TEGRA_GPIO_PW2,
299         .en_mic_ext = TEGRA_GPIO_PX1,
300         .en_mic_int = TEGRA_GPIO_PX0,
301 };
302 #endif
303
304 static struct wm8903_platform_data cardhu_wm8903_pdata = {
305         .irq_active_low = 0,
306         .micdet_cfg = 0,
307         .micdet_delay = 100,
308         .gpio_base = CARDHU_GPIO_WM8903(0),
309         .gpio_cfg = {
310                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
311                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
312                         WM8903_GP2_DIR,
313                 0,
314                 WM8903_GPIO_NO_CONFIG,
315                 WM8903_GPIO_NO_CONFIG,
316         },
317 };
318
319 /* Equalizer filter coefs generated from the MAXIM MAX98095
320  * evkit software tool */
321 static struct max98095_eq_cfg max98095_eq_cfg[] = {
322         {
323                 .name = "FLAT",
324                 .rate = 44100,
325                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
326                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
327                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
328                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
329                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
330         },
331         {
332                 .name = "LOWPASS1K",
333                 .rate = 44100,
334                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
335                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
336                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
337                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
338                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
339         },
340         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
341                 .name = "HIBOOST",
342                 .rate = 44100,
343                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
344                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
345                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
346                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
347                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
348         },
349         { /* BASS=12dB, TREBLE=+12dB */
350                 .name = "LOUD12DB",
351                 .rate = 44100,
352                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
353                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
354                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
355                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
356                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
357         },
358         {
359                 .name = "FLAT",
360                 .rate = 16000,
361                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
362                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
363                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
364                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
365                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
366         },
367         {
368                 .name = "LOWPASS1K",
369                 .rate = 16000,
370                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
371                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
372                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
373                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
374                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
375         },
376         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
377                 .name = "HIBOOST",
378                 .rate = 16000,
379                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
380                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
381                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
382                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
383                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
384         },
385         { /* BASS=12dB, TREBLE=+12dB */
386                 .name = "LOUD12DB",
387                 .rate = 16000,
388                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
389                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
390                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
391                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
392                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
393         },
394 };
395
396 static struct max98095_pdata cardhu_max98095_pdata = {
397         /* equalizer configuration */
398         .eq_cfg = max98095_eq_cfg,
399         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
400
401         /* Biquad filter response configuration */
402         .bq_cfg = NULL,
403         .bq_cfgcnt = 0,
404
405         /* microphone configuration */
406         .digmic_left_mode = 1,
407         .digmic_right_mode = 1,
408 };
409
410 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
411         I2C_BOARD_INFO("wm8903", 0x1a),
412         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
413         .platform_data = &cardhu_wm8903_pdata,
414 };
415
416 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
417         I2C_BOARD_INFO("aic3262-codec", 0x18),
418         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
419 };
420
421 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
422         I2C_BOARD_INFO("max98095", 0x10),
423         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
424         .platform_data = &cardhu_max98095_pdata,
425 };
426
427 static void cardhu_i2c_init(void)
428 {
429         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
430         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
431         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
432         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
433         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
434
435         platform_device_register(&tegra_i2c_device5);
436         platform_device_register(&tegra_i2c_device4);
437         platform_device_register(&tegra_i2c_device3);
438         platform_device_register(&tegra_i2c_device2);
439         platform_device_register(&tegra_i2c_device1);
440
441         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
442         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
443         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
444
445         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
446 }
447
448 static struct platform_device *cardhu_uart_devices[] __initdata = {
449         &tegra_uarta_device,
450         &tegra_uartb_device,
451         &tegra_uartc_device,
452         &tegra_uartd_device,
453         &tegra_uarte_device,
454 };
455 static struct uart_clk_parent uart_parent_clk[] = {
456         [0] = {.name = "clk_m"},
457         [1] = {.name = "pll_p"},
458 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
459         [2] = {.name = "pll_m"},
460 #endif
461 };
462
463 static struct tegra_uart_platform_data cardhu_uart_pdata;
464 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
465
466 static void __init uart_debug_init(void)
467 {
468         struct board_info board_info;
469         int debug_port_id;
470
471         tegra_get_board_info(&board_info);
472
473         debug_port_id = get_tegra_uart_debug_port_id();
474         if (debug_port_id < 0) {
475                 debug_port_id = 0;
476                         /* UARTB is debug port
477                          *       for SLT - E1186/E1187/PM269
478                          *       for E1256/E1257
479                          */
480                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
481                         ((board_info.board_id == BOARD_E1186) ||
482                         (board_info.board_id == BOARD_E1187) ||
483                         (board_info.board_id == BOARD_PM269))) ||
484                         (board_info.board_id == BOARD_E1256) ||
485                         (board_info.board_id == BOARD_E1257))
486                                 debug_port_id = 1;
487         }
488
489         switch (debug_port_id) {
490         case 0:
491                 /* UARTA is the debug port. */
492                 pr_info("Selecting UARTA as the debug console\n");
493                 cardhu_uart_devices[0] = &debug_uarta_device;
494                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
495                 debug_uart_port_base = ((struct plat_serial8250_port *)(
496                         debug_uarta_device.dev.platform_data))->mapbase;
497                 break;
498
499         case 1:
500                 /* UARTB is the debug port. */
501                 pr_info("Selecting UARTB as the debug console\n");
502                 cardhu_uart_devices[1] = &debug_uartb_device;
503                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
504                 debug_uart_port_base = ((struct plat_serial8250_port *)(
505                         debug_uartb_device.dev.platform_data))->mapbase;
506                 break;
507
508         case 2:
509                 /* UARTC is the debug port. */
510                 pr_info("Selecting UARTC as the debug console\n");
511                 cardhu_uart_devices[2] = &debug_uartc_device;
512                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
513                 debug_uart_port_base = ((struct plat_serial8250_port *)(
514                         debug_uartc_device.dev.platform_data))->mapbase;
515                 break;
516
517         case 3:
518                 /* UARTD is the debug port. */
519                 pr_info("Selecting UARTD as the debug console\n");
520                 cardhu_uart_devices[3] = &debug_uartd_device;
521                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
522                 debug_uart_port_base = ((struct plat_serial8250_port *)(
523                         debug_uartd_device.dev.platform_data))->mapbase;
524                 break;
525
526         case 4:
527                 /* UARTE is the debug port. */
528                 pr_info("Selecting UARTE as the debug console\n");
529                 cardhu_uart_devices[4] = &debug_uarte_device;
530                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
531                 debug_uart_port_base = ((struct plat_serial8250_port *)(
532                         debug_uarte_device.dev.platform_data))->mapbase;
533                 break;
534
535         default:
536                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
537                 cardhu_uart_devices[0] = &debug_uarta_device;
538                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
539                 debug_uart_port_base = ((struct plat_serial8250_port *)(
540                         debug_uarta_device.dev.platform_data))->mapbase;
541                 break;
542         }
543         return;
544 }
545
546 static void __init cardhu_uart_init(void)
547 {
548         struct clk *c;
549         int i;
550
551         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
552                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
553                 if (IS_ERR_OR_NULL(c)) {
554                         pr_err("Not able to get the clock for %s\n",
555                                                 uart_parent_clk[i].name);
556                         continue;
557                 }
558                 uart_parent_clk[i].parent_clk = c;
559                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
560         }
561         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
562         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
563         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
564         cardhu_loopback_uart_pdata.parent_clk_count =
565                                                 ARRAY_SIZE(uart_parent_clk);
566         cardhu_loopback_uart_pdata.is_loopback = true;
567         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
568         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
569         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
570         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
571         /* UARTE is used for loopback test purpose */
572         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
573
574         /* Register low speed only if it is selected */
575         if (!is_tegra_debug_uartport_hs()) {
576                 uart_debug_init();
577                 /* Clock enable for the debug channel */
578                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
579                         pr_info("The debug console clock name is %s\n",
580                                                 debug_uart_clk->name);
581                         c = tegra_get_clock_by_name("pll_p");
582                         if (IS_ERR_OR_NULL(c))
583                                 pr_err("Not getting the parent clock pll_p\n");
584                         else
585                                 clk_set_parent(debug_uart_clk, c);
586
587                         clk_enable(debug_uart_clk);
588                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
589                 } else {
590                         pr_err("Not getting the clock %s for debug console\n",
591                                         debug_uart_clk->name);
592                 }
593         }
594
595         platform_add_devices(cardhu_uart_devices,
596                                 ARRAY_SIZE(cardhu_uart_devices));
597 }
598
599 static struct platform_device tegra_camera = {
600         .name = "tegra_camera",
601         .id = -1,
602 };
603
604 static struct platform_device *cardhu_spi_devices[] __initdata = {
605         &tegra_spi_device4,
606 };
607
608 struct spi_clk_parent spi_parent_clk[] = {
609         [0] = {.name = "pll_p"},
610 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
611         [1] = {.name = "pll_m"},
612         [2] = {.name = "clk_m"},
613 #else
614         [1] = {.name = "clk_m"},
615 #endif
616 };
617
618 static struct tegra_spi_platform_data cardhu_spi_pdata = {
619         .is_dma_based           = true,
620         .max_dma_buffer         = (16 * 1024),
621         .is_clkon_always        = false,
622         .max_rate               = 100000000,
623 };
624
625 static void __init cardhu_spi_init(void)
626 {
627         int i;
628         struct clk *c;
629         struct board_info board_info;
630
631         tegra_get_board_info(&board_info);
632
633         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
634                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
635                 if (IS_ERR_OR_NULL(c)) {
636                         pr_err("Not able to get the clock for %s\n",
637                                                 spi_parent_clk[i].name);
638                         continue;
639                 }
640                 spi_parent_clk[i].parent_clk = c;
641                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
642         }
643         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
644         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
645         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
646         platform_add_devices(cardhu_spi_devices,
647                                 ARRAY_SIZE(cardhu_spi_devices));
648
649         if (board_info.board_id == BOARD_E1198) {
650                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
651                 platform_device_register(&tegra_spi_device2);
652                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
653                 platform_device_register(&tegra_spi_slave_device1);
654         }
655 }
656
657 static void __init cardhu_dtv_init(void)
658 {
659         struct board_info board_info;
660
661         tegra_get_board_info(&board_info);
662
663         if (board_info.board_id == BOARD_E1186)
664                 platform_device_register(&tegra_dtv_device);
665 }
666
667 static struct resource tegra_rtc_resources[] = {
668         [0] = {
669                 .start = TEGRA_RTC_BASE,
670                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
671                 .flags = IORESOURCE_MEM,
672         },
673         [1] = {
674                 .start = INT_RTC,
675                 .end = INT_RTC,
676                 .flags = IORESOURCE_IRQ,
677         },
678 };
679
680 static struct platform_device tegra_rtc_device = {
681         .name = "tegra_rtc",
682         .id   = -1,
683         .resource = tegra_rtc_resources,
684         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
685 };
686
687 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
688         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
689         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
690         .gpio_hp_mute           = -1,
691         .gpio_int_mic_en        = -1,
692         .gpio_ext_mic_en        = -1,
693 };
694
695 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
696         .gpio_spkr_en           = -1,
697         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
698         .gpio_hp_mute           = -1,
699         .gpio_int_mic_en        = -1,
700         .gpio_ext_mic_en        = -1,
701 };
702
703 static struct platform_device cardhu_audio_wm8903_device = {
704         .name   = "tegra-snd-wm8903",
705         .id     = 0,
706         .dev    = {
707                 .platform_data = &cardhu_audio_wm8903_pdata,
708         },
709 };
710
711 static struct platform_device cardhu_audio_max98095_device = {
712         .name   = "tegra-snd-max98095",
713         .id     = 0,
714         .dev    = {
715                 .platform_data = &cardhu_audio_max98095_pdata,
716         },
717 };
718
719 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
720         .gpio_spkr_en           = -1,
721         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
722         .gpio_hp_mute           = -1,
723         .gpio_int_mic_en        = -1,
724         .gpio_ext_mic_en        = -1,
725 };
726
727 static struct platform_device cardhu_audio_aic326x_device = {
728         .name   = "tegra-snd-aic326x",
729         .id     = 0,
730         .dev    = {
731                 .platform_data  = &cardhu_audio_aic326x_pdata,
732         },
733 };
734
735 static struct platform_device *cardhu_devices[] __initdata = {
736         &tegra_pmu_device,
737         &tegra_rtc_device,
738         &tegra_udc_device,
739 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
740         &tegra_smmu_device,
741 #endif
742         &tegra_wdt_device,
743 #if defined(CONFIG_TEGRA_AVP)
744         &tegra_avp_device,
745 #endif
746         &tegra_camera,
747 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
748         &tegra_se_device,
749 #endif
750         &tegra_ahub_device,
751         &tegra_dam_device0,
752         &tegra_dam_device1,
753         &tegra_dam_device2,
754         &tegra_i2s_device0,
755         &tegra_i2s_device1,
756         &tegra_i2s_device3,
757         &tegra_spdif_device,
758         &spdif_dit_device,
759         &bluetooth_dit_device,
760         &baseband_dit_device,
761         &tegra_pcm_device,
762         &cardhu_audio_wm8903_device,
763         &cardhu_audio_max98095_device,
764         &cardhu_audio_aic326x_device,
765         &tegra_hda_device,
766 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
767         &tegra_aes_device,
768 #endif
769 };
770
771 #define MXT_CONFIG_CRC  0xD62DE8
772 static const u8 config[] = {
773         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
774         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
775         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
776         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
777         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
778         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
779         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
780         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
781         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
782         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
783         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
784         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
785         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
786         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
787         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
788         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
789         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
790         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
791         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
792         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
793 };
794
795 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
796 static const u8 config_sku2000[] = {
797         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
798         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
799         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
800         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
801         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
802         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
803         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
804         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
806         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
808         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
809         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
810         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
811         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
812         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
813         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
814         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
815         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
816         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
817 };
818
819 static struct mxt_platform_data atmel_mxt_info = {
820         .x_line         = 27,
821         .y_line         = 42,
822         .x_size         = 768,
823         .y_size         = 1366,
824         .blen           = 0x20,
825         .threshold      = 0x3C,
826         .voltage        = 3300000,              /* 3.3V */
827         .orient         = 5,
828         .config         = config,
829         .config_length  = 157,
830         .config_crc     = MXT_CONFIG_CRC,
831         .irqflags       = IRQF_TRIGGER_FALLING,
832 /*      .read_chg       = &read_chg, */
833         .read_chg       = NULL,
834 };
835
836 static struct i2c_board_info __initdata atmel_i2c_info[] = {
837         {
838                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
839                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
840                 .platform_data = &atmel_mxt_info,
841         }
842 };
843
844 static int __init cardhu_touch_init(void)
845 {
846         struct board_info BoardInfo;
847
848         tegra_gpio_enable(TEGRA_GPIO_PH4);
849         tegra_gpio_enable(TEGRA_GPIO_PH6);
850
851         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
852         gpio_direction_input(TEGRA_GPIO_PH4);
853
854         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
855         gpio_direction_output(TEGRA_GPIO_PH6, 0);
856         msleep(1);
857         gpio_set_value(TEGRA_GPIO_PH6, 1);
858         msleep(100);
859
860         tegra_get_board_info(&BoardInfo);
861         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
862                 atmel_mxt_info.config = config_sku2000;
863                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
864         }
865
866         i2c_register_board_info(1, atmel_i2c_info, 1);
867
868         return 0;
869 }
870
871 static struct tegra_uhsic_config uhsic_phy_config = {
872         .enable_gpio = EN_HSIC_GPIO,
873         .reset_gpio = -1,
874         .sync_start_delay = 9,
875         .idle_wait_delay = 17,
876         .term_range_adj = 0,
877         .elastic_underrun_limit = 16,
878         .elastic_overrun_limit = 16,
879 };
880
881 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
882         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
883         .phy_config = &uhsic_phy_config,
884         .operating_mode = TEGRA_USB_HOST,
885         .power_down_on_bus_suspend = 1,
886         .default_enable = true,
887 };
888
889 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
890         [0] = {
891                         .phy_config = &utmi_phy_config[0],
892                         .operating_mode = TEGRA_USB_HOST,
893                         .power_down_on_bus_suspend = 1,
894                         .default_enable = true,
895         },
896         [1] = {
897                         .phy_config = &utmi_phy_config[1],
898                         .operating_mode = TEGRA_USB_HOST,
899                         .power_down_on_bus_suspend = 1,
900                         .default_enable = true,
901         },
902         [2] = {
903                         .phy_config = &utmi_phy_config[2],
904                         .operating_mode = TEGRA_USB_HOST,
905                         .power_down_on_bus_suspend = 1,
906                         .hotplug = 1,
907                         .default_enable = true,
908         },
909 };
910
911 static struct tegra_otg_platform_data tegra_otg_pdata = {
912         .ehci_device = &tegra_ehci1_device,
913         .ehci_pdata = &tegra_ehci_pdata[0],
914 };
915
916 #ifdef CONFIG_USB_SUPPORT
917 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
918         [0] = {
919                         .instance = 0,
920                         .vbus_gpio = -1,
921                         .vbus_reg_supply = "vdd_vbus_micro_usb",
922         },
923         [1] = {
924                         .instance = 1,
925                         .vbus_gpio = -1,
926         },
927         [2] = {
928                         .instance = 2,
929                         .vbus_gpio = -1,
930                         .vbus_reg_supply = "vdd_vbus_typea_usb",
931         },
932 };
933
934 static void cardhu_usb_init(void)
935 {
936         struct board_info bi;
937
938         tegra_get_board_info(&bi);
939
940         tegra_usb_phy_init(tegra_usb_phy_pdata,
941                         ARRAY_SIZE(tegra_usb_phy_pdata));
942
943         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
944         platform_device_register(&tegra_otg_device);
945         if (bi.board_id == BOARD_PM267) {
946                 uhsic_phy_config.reset_gpio =
947                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
948                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
949                 platform_device_register(&tegra_ehci2_device);
950         } else if (bi.board_id == BOARD_E1256) {
951                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
952                 platform_device_register(&tegra_ehci2_device);
953         } else if (bi.board_id == BOARD_E1186) {
954                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
955                 /* baseband registration happens in baseband-xmm-power  */
956         } else {
957                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
958                 platform_device_register(&tegra_ehci2_device);
959         }
960
961         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
962         platform_device_register(&tegra_ehci3_device);
963
964 }
965 #else
966 static void cardhu_usb_init(void) { }
967 #endif
968
969 static void cardhu_gps_init(void)
970 {
971         tegra_gpio_enable(TEGRA_GPIO_PU2);
972         tegra_gpio_enable(TEGRA_GPIO_PU3);
973 }
974
975 static void cardhu_nfc_init(void)
976 {
977         tegra_gpio_enable(TEGRA_GPIO_PX0);
978         tegra_gpio_enable(TEGRA_GPIO_PP3);
979         tegra_gpio_enable(TEGRA_GPIO_PO7);
980 }
981
982 static struct baseband_power_platform_data tegra_baseband_power_data = {
983         .baseband_type = BASEBAND_XMM,
984         .modem = {
985         .xmm = {
986                         .bb_rst = XMM_GPIO_BB_RST,
987                         .bb_on = XMM_GPIO_BB_ON,
988                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
989                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
990                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
991                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
992                         .hsic_device = &tegra_ehci2_device,
993                 },
994         },
995 };
996
997 static struct platform_device tegra_baseband_power_device = {
998         .name = "baseband_xmm_power",
999         .id = -1,
1000         .dev = {
1001                 .platform_data = &tegra_baseband_power_data,
1002         },
1003 };
1004
1005 static struct platform_device tegra_baseband_power2_device = {
1006         .name = "baseband_xmm_power2",
1007         .id = -1,
1008         .dev = {
1009                 .platform_data = &tegra_baseband_power_data,
1010         },
1011 };
1012
1013
1014 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1015         .port_status[0] = 1,
1016         .port_status[1] = 1,
1017         .port_status[2] = 1,
1018         .use_dock_detect        = 0,
1019         .gpio           = 0,
1020 };
1021
1022 static void cardhu_pci_init(void)
1023 {
1024         struct board_info board_info;
1025
1026         tegra_get_board_info(&board_info);
1027         if (board_info.board_id == BOARD_E1291) {
1028                 cardhu_pci_platform_data.port_status[0] = 0;
1029                 cardhu_pci_platform_data.port_status[1] = 0;
1030                 cardhu_pci_platform_data.port_status[2] = 1;
1031                 cardhu_pci_platform_data.use_dock_detect = 1;
1032                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1033         }
1034         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1035         platform_device_register(&tegra_pci_device);
1036 }
1037
1038 static void cardhu_modem_init(void)
1039 {
1040         struct board_info board_info;
1041         int w_disable_gpio, ret;
1042
1043         tegra_get_board_info(&board_info);
1044         switch (board_info.board_id) {
1045         case BOARD_E1291:
1046         case BOARD_E1198:
1047                 if (((board_info.board_id == BOARD_E1291) &&
1048                                 (board_info.fab < BOARD_FAB_A03)) ||
1049                         ((board_info.board_id == BOARD_E1198) &&
1050                                         (board_info.fab < BOARD_FAB_A02))) {
1051                         w_disable_gpio = TEGRA_GPIO_PH5;
1052                 } else {
1053                         w_disable_gpio = TEGRA_GPIO_PDD5;
1054                 }
1055                 tegra_gpio_enable(w_disable_gpio);
1056                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1057                 if (ret < 0)
1058                         pr_err("%s: gpio_request failed for gpio %d\n",
1059                                 __func__, w_disable_gpio);
1060                 else
1061                         gpio_direction_input(w_disable_gpio);
1062
1063                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1064                 if (((board_info.board_id == BOARD_E1291) &&
1065                                 (board_info.fab >= BOARD_FAB_A04)) ||
1066                         ((board_info.board_id == BOARD_E1198) &&
1067                                         (board_info.fab >= BOARD_FAB_A02))) {
1068                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1069                         if (ret < 0) {
1070                                 pr_err("%s(): Error in allocating gpio "
1071                                         "TEGRA_GPIO_PH7\n", __func__);
1072                                 break;
1073                         }
1074                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1075                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1076                 }
1077                 break;
1078         case BOARD_E1186:
1079                 tegra_gpio_enable(
1080                         tegra_baseband_power_data.modem.xmm.bb_rst);
1081                 tegra_gpio_enable(
1082                         tegra_baseband_power_data.modem.xmm.bb_on);
1083                 tegra_gpio_enable(
1084                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1085                 tegra_gpio_enable(
1086                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1087                 tegra_gpio_enable(
1088                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1089                 tegra_gpio_enable(
1090                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1091                 platform_device_register(&tegra_baseband_power_device);
1092                 platform_device_register(&tegra_baseband_power2_device);
1093                 break;
1094         default:
1095                 break;
1096         }
1097
1098 }
1099
1100 #ifdef CONFIG_SATA_AHCI_TEGRA
1101 static void cardhu_sata_init(void)
1102 {
1103         platform_device_register(&tegra_sata_device);
1104 }
1105 #else
1106 static void cardhu_sata_init(void) { }
1107 #endif
1108
1109 static void __init tegra_cardhu_init(void)
1110 {
1111         tegra_thermal_init(&thermal_data);
1112         tegra_clk_init_from_table(cardhu_clk_init_table);
1113         cardhu_pinmux_init();
1114         cardhu_i2c_init();
1115         cardhu_spi_init();
1116         cardhu_usb_init();
1117 #ifdef CONFIG_TEGRA_EDP_LIMITS
1118         cardhu_edp_init();
1119 #endif
1120         cardhu_uart_init();
1121         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1122         cardhu_sdhci_init();
1123         cardhu_regulator_init();
1124         cardhu_dtv_init();
1125         cardhu_suspend_init();
1126         cardhu_touch_init();
1127         cardhu_gps_init();
1128         cardhu_modem_init();
1129         cardhu_kbc_init();
1130         cardhu_scroll_init();
1131         cardhu_keys_init();
1132         cardhu_panel_init();
1133         cardhu_pmon_init();
1134         cardhu_sensors_init();
1135         cardhu_bt_rfkill();
1136         tegra_setup_bluesleep();
1137         cardhu_sata_init();
1138         //audio_wired_jack_init();
1139         cardhu_pins_state_init();
1140         cardhu_emc_init();
1141         tegra_release_bootloader_fb();
1142         cardhu_nfc_init();
1143         cardhu_pci_init();
1144 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1145         tegra_wdt_recovery_init();
1146 #endif
1147 }
1148
1149 static void __init tegra_cardhu_reserve(void)
1150 {
1151 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1152         /* support 1920X1200 with 24bpp */
1153         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1154 #else
1155         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1156 #endif
1157 }
1158
1159 MACHINE_START(CARDHU, "cardhu")
1160         .boot_params    = 0x80000100,
1161         .map_io         = tegra_map_common_io,
1162         .reserve        = tegra_cardhu_reserve,
1163         .init_early     = tegra_init_early,
1164         .init_irq       = tegra_init_irq,
1165         .timer          = &tegra_timer,
1166         .init_machine   = tegra_cardhu_init,
1167 MACHINE_END