arm: tegra: cardhu: cleanup ram console
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "devices.h"
66 #include "gpio-names.h"
67 #include "fuse.h"
68 #include "pm.h"
69 #include "baseband-xmm-power.h"
70 #include "wdt-recovery.h"
71
72 /* All units are in millicelsius */
73 static struct tegra_thermal_data thermal_data = {
74         .temp_throttle = 85000,
75         .temp_shutdown = 90000,
76         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
77 #ifdef CONFIG_TEGRA_EDP_LIMITS
78         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
79         .hysteresis_edp = 3000,
80 #endif
81 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
82         .tc1 = 0,
83         .tc2 = 1,
84         .passive_delay = 2000,
85 #else
86         .hysteresis_throttle = 1000,
87 #endif
88 };
89
90 /* !!!TODO: Change for cardhu (Taken from Ventana) */
91 static struct tegra_utmip_config utmi_phy_config[] = {
92         [0] = {
93                         .hssync_start_delay = 0,
94                         .idle_wait_delay = 17,
95                         .elastic_limit = 16,
96                         .term_range_adj = 6,
97                         .xcvr_setup = 15,
98                         .xcvr_setup_offset = 0,
99                         .xcvr_use_fuses = 1,
100                         .xcvr_lsfslew = 2,
101                         .xcvr_lsrslew = 2,
102         },
103         [1] = {
104                         .hssync_start_delay = 0,
105                         .idle_wait_delay = 17,
106                         .elastic_limit = 16,
107                         .term_range_adj = 6,
108                         .xcvr_setup = 15,
109                         .xcvr_setup_offset = 0,
110                         .xcvr_use_fuses = 1,
111                         .xcvr_lsfslew = 2,
112                         .xcvr_lsrslew = 2,
113         },
114         [2] = {
115                         .hssync_start_delay = 0,
116                         .idle_wait_delay = 17,
117                         .elastic_limit = 16,
118                         .term_range_adj = 6,
119                         .xcvr_setup = 8,
120                         .xcvr_setup_offset = 0,
121                         .xcvr_use_fuses = 1,
122                         .xcvr_lsfslew = 2,
123                         .xcvr_lsrslew = 2,
124         },
125 };
126
127 #ifdef CONFIG_BCM4329_RFKILL
128 static struct resource cardhu_bcm4329_rfkill_resources[] = {
129         {
130                 .name   = "bcm4329_nshutdown_gpio",
131                 .start  = TEGRA_GPIO_PU0,
132                 .end    = TEGRA_GPIO_PU0,
133                 .flags  = IORESOURCE_IO,
134         },
135 };
136
137 static struct platform_device cardhu_bcm4329_rfkill_device = {
138         .name = "bcm4329_rfkill",
139         .id             = -1,
140         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
141         .resource       = cardhu_bcm4329_rfkill_resources,
142 };
143
144 static noinline void __init cardhu_bt_rfkill(void)
145 {
146         platform_device_register(&cardhu_bcm4329_rfkill_device);
147
148         return;
149 }
150 #else
151 static inline void cardhu_bt_rfkill(void) { }
152 #endif
153
154 #ifdef CONFIG_BT_BLUESLEEP
155 static noinline void __init tegra_setup_bluesleep(void)
156 {
157         struct platform_device *pdev = NULL;
158         struct resource *res;
159
160         pdev = platform_device_alloc("bluesleep", 0);
161         if (!pdev) {
162                 pr_err("unable to allocate platform device for bluesleep");
163                 return;
164         }
165
166         res = kzalloc(sizeof(struct resource) * 3, GFP_KERNEL);
167         if (!res) {
168                 pr_err("unable to allocate resource for bluesleep\n");
169                 goto err_free_dev;
170         }
171
172         res[0].name   = "gpio_host_wake";
173         res[0].start  = TEGRA_GPIO_PU6;
174         res[0].end    = TEGRA_GPIO_PU6;
175         res[0].flags  = IORESOURCE_IO;
176
177         res[1].name   = "gpio_ext_wake";
178         res[1].start  = TEGRA_GPIO_PU1;
179         res[1].end    = TEGRA_GPIO_PU1;
180         res[1].flags  = IORESOURCE_IO;
181
182         res[2].name   = "host_wake";
183         res[2].start  = gpio_to_irq(TEGRA_GPIO_PU6);
184         res[2].end    = gpio_to_irq(TEGRA_GPIO_PU6);
185         res[2].flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE ;
186
187         if (platform_device_add_resources(pdev, res, 3)) {
188                 pr_err("unable to add resources to bluesleep device\n");
189                 goto err_free_res;
190         }
191
192         if (platform_device_add(pdev)) {
193                 pr_err("unable to add bluesleep device\n");
194                 goto err_free_res;
195         }
196         tegra_gpio_enable(TEGRA_GPIO_PU6);
197         tegra_gpio_enable(TEGRA_GPIO_PU1);
198
199 return;
200
201 err_free_res:
202         kfree(res);
203 err_free_dev:
204         platform_device_put(pdev);
205         return;
206 }
207 #else
208 static inline void tegra_setup_bluesleep(void) { }
209 #endif
210
211 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
212         /* name         parent          rate            enabled */
213         { "pll_m",      NULL,           0,              false},
214         { "hda",        "pll_p",        108000000,      false},
215         { "hda2codec_2x","pll_p",       48000000,       false},
216         { "pwm",        "pll_p",        3187500,        false},
217         { "blink",      "clk_32k",      32768,          true},
218         { "i2s0",       "pll_a_out0",   0,              false},
219         { "i2s1",       "pll_a_out0",   0,              false},
220         { "i2s3",       "pll_a_out0",   0,              false},
221         { "spdif_out",  "pll_a_out0",   0,              false},
222         { "d_audio",    "clk_m",        12000000,       false},
223         { "dam0",       "clk_m",        12000000,       false},
224         { "dam1",       "clk_m",        12000000,       false},
225         { "dam2",       "clk_m",        12000000,       false},
226         { "audio1",     "i2s1_sync",    0,              false},
227         { "audio3",     "i2s3_sync",    0,              false},
228         { "sdmmc3",     "clk_m",        12000000,       true},
229         { "vi_sensor",  "pll_p",        150000000,      false},
230         { "i2c1",       "pll_p",        3200000,        false},
231         { "i2c2",       "pll_p",        3200000,        false},
232         { "i2c3",       "pll_p",        3200000,        false},
233         { "i2c4",       "pll_p",        3200000,        false},
234         { "i2c5",       "pll_p",        3200000,        false},
235         { NULL,         NULL,           0,              0},
236 };
237
238 static struct pn544_i2c_platform_data nfc_pdata = {
239         .irq_gpio = TEGRA_GPIO_PX0,
240         .ven_gpio = TEGRA_GPIO_PP3,
241         .firm_gpio = TEGRA_GPIO_PO7,
242         };
243
244 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
245         {
246                 I2C_BOARD_INFO("pn544", 0x28),
247                 .platform_data = &nfc_pdata,
248                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
249         },
250 };
251 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
252         .adapter_nr     = 0,
253         .bus_count      = 1,
254         .bus_clk_rate   = { 100000, 0 },
255         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
256         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
257         .arb_recovery = arb_lost_recovery,
258 };
259
260 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
261         .adapter_nr     = 1,
262         .bus_count      = 1,
263         .bus_clk_rate   = { 100000, 0 },
264         .is_clkon_always = true,
265         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
266         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
267         .arb_recovery = arb_lost_recovery,
268 };
269
270 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
271         .adapter_nr     = 2,
272         .bus_count      = 1,
273         .bus_clk_rate   = { 100000, 0 },
274         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
275         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
276         .arb_recovery = arb_lost_recovery,
277 };
278
279 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
280         .adapter_nr     = 3,
281         .bus_count      = 1,
282         .bus_clk_rate   = { 100000, 0 },
283         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
284         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
285         .arb_recovery = arb_lost_recovery,
286 };
287
288 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
289         .adapter_nr     = 4,
290         .bus_count      = 1,
291         .bus_clk_rate   = { 400000, 0 },
292         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
293         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
294         .arb_recovery = arb_lost_recovery,
295 };
296
297
298 #if 0
299 struct tegra_wired_jack_conf audio_wr_jack_conf = {
300         .hp_det_n = TEGRA_GPIO_PW2,
301         .en_mic_ext = TEGRA_GPIO_PX1,
302         .en_mic_int = TEGRA_GPIO_PX0,
303 };
304 #endif
305
306 static struct wm8903_platform_data cardhu_wm8903_pdata = {
307         .irq_active_low = 0,
308         .micdet_cfg = 0,
309         .micdet_delay = 100,
310         .gpio_base = CARDHU_GPIO_WM8903(0),
311         .gpio_cfg = {
312                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
313                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
314                         WM8903_GP2_DIR,
315                 0,
316                 WM8903_GPIO_NO_CONFIG,
317                 WM8903_GPIO_NO_CONFIG,
318         },
319 };
320
321 /* Equalizer filter coefs generated from the MAXIM MAX98095
322  * evkit software tool */
323 static struct max98095_eq_cfg max98095_eq_cfg[] = {
324         {
325                 .name = "FLAT",
326                 .rate = 44100,
327                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
328                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
329                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
330                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
331                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
332         },
333         {
334                 .name = "LOWPASS1K",
335                 .rate = 44100,
336                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
337                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
338                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
339                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
340                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
341         },
342         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
343                 .name = "HIBOOST",
344                 .rate = 44100,
345                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
346                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
347                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
348                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
349                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
350         },
351         { /* BASS=12dB, TREBLE=+12dB */
352                 .name = "LOUD12DB",
353                 .rate = 44100,
354                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
355                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
356                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
357                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
358                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
359         },
360         {
361                 .name = "FLAT",
362                 .rate = 16000,
363                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
364                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
365                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
366                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
367                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
368         },
369         {
370                 .name = "LOWPASS1K",
371                 .rate = 16000,
372                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
373                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
374                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
375                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
376                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
377         },
378         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
379                 .name = "HIBOOST",
380                 .rate = 16000,
381                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
382                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
383                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
384                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
385                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
386         },
387         { /* BASS=12dB, TREBLE=+12dB */
388                 .name = "LOUD12DB",
389                 .rate = 16000,
390                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
391                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
392                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
393                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
394                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
395         },
396 };
397
398 static struct max98095_pdata cardhu_max98095_pdata = {
399         /* equalizer configuration */
400         .eq_cfg = max98095_eq_cfg,
401         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
402
403         /* Biquad filter response configuration */
404         .bq_cfg = NULL,
405         .bq_cfgcnt = 0,
406
407         /* microphone configuration */
408         .digmic_left_mode = 1,
409         .digmic_right_mode = 1,
410 };
411
412 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
413         I2C_BOARD_INFO("wm8903", 0x1a),
414         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
415         .platform_data = &cardhu_wm8903_pdata,
416 };
417
418 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
419         I2C_BOARD_INFO("aic3262-codec", 0x18),
420         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
421 };
422
423 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
424         I2C_BOARD_INFO("max98095", 0x10),
425         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
426         .platform_data = &cardhu_max98095_pdata,
427 };
428
429 static void cardhu_i2c_init(void)
430 {
431         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
432         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
433         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
434         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
435         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
436
437         platform_device_register(&tegra_i2c_device5);
438         platform_device_register(&tegra_i2c_device4);
439         platform_device_register(&tegra_i2c_device3);
440         platform_device_register(&tegra_i2c_device2);
441         platform_device_register(&tegra_i2c_device1);
442
443         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
444         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
445         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
446
447         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
448 }
449
450 static struct platform_device *cardhu_uart_devices[] __initdata = {
451         &tegra_uarta_device,
452         &tegra_uartb_device,
453         &tegra_uartc_device,
454         &tegra_uartd_device,
455         &tegra_uarte_device,
456 };
457 static struct uart_clk_parent uart_parent_clk[] = {
458         [0] = {.name = "clk_m"},
459         [1] = {.name = "pll_p"},
460 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
461         [2] = {.name = "pll_m"},
462 #endif
463 };
464
465 static struct tegra_uart_platform_data cardhu_uart_pdata;
466 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
467
468 static void __init uart_debug_init(void)
469 {
470         struct board_info board_info;
471         int debug_port_id;
472
473         tegra_get_board_info(&board_info);
474
475         debug_port_id = get_tegra_uart_debug_port_id();
476         if (debug_port_id < 0) {
477                 debug_port_id = 0;
478                         /* UARTB is debug port
479                          *       for SLT - E1186/E1187/PM269
480                          *       for E1256/E1257
481                          */
482                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
483                         ((board_info.board_id == BOARD_E1186) ||
484                         (board_info.board_id == BOARD_E1187) ||
485                         (board_info.board_id == BOARD_PM269))) ||
486                         (board_info.board_id == BOARD_E1256) ||
487                         (board_info.board_id == BOARD_E1257))
488                                 debug_port_id = 1;
489         }
490
491         switch (debug_port_id) {
492         case 0:
493                 /* UARTA is the debug port. */
494                 pr_info("Selecting UARTA as the debug console\n");
495                 cardhu_uart_devices[0] = &debug_uarta_device;
496                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
497                 debug_uart_port_base = ((struct plat_serial8250_port *)(
498                         debug_uarta_device.dev.platform_data))->mapbase;
499                 break;
500
501         case 1:
502                 /* UARTB is the debug port. */
503                 pr_info("Selecting UARTB as the debug console\n");
504                 cardhu_uart_devices[1] = &debug_uartb_device;
505                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
506                 debug_uart_port_base = ((struct plat_serial8250_port *)(
507                         debug_uartb_device.dev.platform_data))->mapbase;
508                 break;
509
510         case 2:
511                 /* UARTC is the debug port. */
512                 pr_info("Selecting UARTC as the debug console\n");
513                 cardhu_uart_devices[2] = &debug_uartc_device;
514                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
515                 debug_uart_port_base = ((struct plat_serial8250_port *)(
516                         debug_uartc_device.dev.platform_data))->mapbase;
517                 break;
518
519         case 3:
520                 /* UARTD is the debug port. */
521                 pr_info("Selecting UARTD as the debug console\n");
522                 cardhu_uart_devices[3] = &debug_uartd_device;
523                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
524                 debug_uart_port_base = ((struct plat_serial8250_port *)(
525                         debug_uartd_device.dev.platform_data))->mapbase;
526                 break;
527
528         case 4:
529                 /* UARTE is the debug port. */
530                 pr_info("Selecting UARTE as the debug console\n");
531                 cardhu_uart_devices[4] = &debug_uarte_device;
532                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
533                 debug_uart_port_base = ((struct plat_serial8250_port *)(
534                         debug_uarte_device.dev.platform_data))->mapbase;
535                 break;
536
537         default:
538                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
539                 cardhu_uart_devices[0] = &debug_uarta_device;
540                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
541                 debug_uart_port_base = ((struct plat_serial8250_port *)(
542                         debug_uarta_device.dev.platform_data))->mapbase;
543                 break;
544         }
545         return;
546 }
547
548 static void __init cardhu_uart_init(void)
549 {
550         struct clk *c;
551         int i;
552
553         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
554                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
555                 if (IS_ERR_OR_NULL(c)) {
556                         pr_err("Not able to get the clock for %s\n",
557                                                 uart_parent_clk[i].name);
558                         continue;
559                 }
560                 uart_parent_clk[i].parent_clk = c;
561                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
562         }
563         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
564         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
565         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
566         cardhu_loopback_uart_pdata.parent_clk_count =
567                                                 ARRAY_SIZE(uart_parent_clk);
568         cardhu_loopback_uart_pdata.is_loopback = true;
569         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
570         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
571         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
572         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
573         /* UARTE is used for loopback test purpose */
574         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
575
576         /* Register low speed only if it is selected */
577         if (!is_tegra_debug_uartport_hs()) {
578                 uart_debug_init();
579                 /* Clock enable for the debug channel */
580                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
581                         pr_info("The debug console clock name is %s\n",
582                                                 debug_uart_clk->name);
583                         c = tegra_get_clock_by_name("pll_p");
584                         if (IS_ERR_OR_NULL(c))
585                                 pr_err("Not getting the parent clock pll_p\n");
586                         else
587                                 clk_set_parent(debug_uart_clk, c);
588
589                         clk_enable(debug_uart_clk);
590                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
591                 } else {
592                         pr_err("Not getting the clock %s for debug console\n",
593                                         debug_uart_clk->name);
594                 }
595         }
596
597         platform_add_devices(cardhu_uart_devices,
598                                 ARRAY_SIZE(cardhu_uart_devices));
599 }
600
601 static struct platform_device tegra_camera = {
602         .name = "tegra_camera",
603         .id = -1,
604 };
605
606 static struct platform_device *cardhu_spi_devices[] __initdata = {
607         &tegra_spi_device4,
608 };
609
610 struct spi_clk_parent spi_parent_clk[] = {
611         [0] = {.name = "pll_p"},
612 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
613         [1] = {.name = "pll_m"},
614         [2] = {.name = "clk_m"},
615 #else
616         [1] = {.name = "clk_m"},
617 #endif
618 };
619
620 static struct tegra_spi_platform_data cardhu_spi_pdata = {
621         .is_dma_based           = true,
622         .max_dma_buffer         = (16 * 1024),
623         .is_clkon_always        = false,
624         .max_rate               = 100000000,
625 };
626
627 static void __init cardhu_spi_init(void)
628 {
629         int i;
630         struct clk *c;
631         struct board_info board_info;
632
633         tegra_get_board_info(&board_info);
634
635         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
636                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
637                 if (IS_ERR_OR_NULL(c)) {
638                         pr_err("Not able to get the clock for %s\n",
639                                                 spi_parent_clk[i].name);
640                         continue;
641                 }
642                 spi_parent_clk[i].parent_clk = c;
643                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
644         }
645         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
646         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
647         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
648         platform_add_devices(cardhu_spi_devices,
649                                 ARRAY_SIZE(cardhu_spi_devices));
650
651         if (board_info.board_id == BOARD_E1198) {
652                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
653                 platform_device_register(&tegra_spi_device2);
654                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
655                 platform_device_register(&tegra_spi_slave_device1);
656         }
657 }
658
659 static void __init cardhu_dtv_init(void)
660 {
661         struct board_info board_info;
662
663         tegra_get_board_info(&board_info);
664
665         if (board_info.board_id == BOARD_E1186)
666                 platform_device_register(&tegra_dtv_device);
667 }
668
669 static struct resource tegra_rtc_resources[] = {
670         [0] = {
671                 .start = TEGRA_RTC_BASE,
672                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
673                 .flags = IORESOURCE_MEM,
674         },
675         [1] = {
676                 .start = INT_RTC,
677                 .end = INT_RTC,
678                 .flags = IORESOURCE_IRQ,
679         },
680 };
681
682 static struct platform_device tegra_rtc_device = {
683         .name = "tegra_rtc",
684         .id   = -1,
685         .resource = tegra_rtc_resources,
686         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
687 };
688
689 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
690         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
691         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
692         .gpio_hp_mute           = -1,
693         .gpio_int_mic_en        = -1,
694         .gpio_ext_mic_en        = -1,
695 };
696
697 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
698         .gpio_spkr_en           = -1,
699         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
700         .gpio_hp_mute           = -1,
701         .gpio_int_mic_en        = -1,
702         .gpio_ext_mic_en        = -1,
703 };
704
705 static struct platform_device cardhu_audio_wm8903_device = {
706         .name   = "tegra-snd-wm8903",
707         .id     = 0,
708         .dev    = {
709                 .platform_data = &cardhu_audio_wm8903_pdata,
710         },
711 };
712
713 static struct platform_device cardhu_audio_max98095_device = {
714         .name   = "tegra-snd-max98095",
715         .id     = 0,
716         .dev    = {
717                 .platform_data = &cardhu_audio_max98095_pdata,
718         },
719 };
720
721 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
722         .gpio_spkr_en           = -1,
723         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
724         .gpio_hp_mute           = -1,
725         .gpio_int_mic_en        = -1,
726         .gpio_ext_mic_en        = -1,
727 };
728
729 static struct platform_device cardhu_audio_aic326x_device = {
730         .name   = "tegra-snd-aic326x",
731         .id     = 0,
732         .dev    = {
733                 .platform_data  = &cardhu_audio_aic326x_pdata,
734         },
735 };
736
737 static struct resource ram_console_resources[] = {
738         {
739                 .flags = IORESOURCE_MEM,
740         },
741 };
742
743 static struct platform_device ram_console_device = {
744         .name           = "ram_console",
745         .id             = -1,
746         .num_resources  = ARRAY_SIZE(ram_console_resources),
747         .resource       = ram_console_resources,
748 };
749
750 static struct platform_device *cardhu_devices[] __initdata = {
751         &tegra_pmu_device,
752         &tegra_rtc_device,
753         &tegra_udc_device,
754 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
755         &tegra_smmu_device,
756 #endif
757         &tegra_wdt_device,
758 #if defined(CONFIG_TEGRA_AVP)
759         &tegra_avp_device,
760 #endif
761         &tegra_camera,
762 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
763         &tegra_se_device,
764 #endif
765         &tegra_ahub_device,
766         &tegra_dam_device0,
767         &tegra_dam_device1,
768         &tegra_dam_device2,
769         &tegra_i2s_device0,
770         &tegra_i2s_device1,
771         &tegra_i2s_device3,
772         &tegra_spdif_device,
773         &spdif_dit_device,
774         &bluetooth_dit_device,
775         &baseband_dit_device,
776         &tegra_pcm_device,
777         &cardhu_audio_wm8903_device,
778         &cardhu_audio_max98095_device,
779         &cardhu_audio_aic326x_device,
780         &tegra_hda_device,
781 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
782         &tegra_aes_device,
783 #endif
784         &ram_console_device,
785 };
786
787 #define MXT_CONFIG_CRC  0xD62DE8
788 static const u8 config[] = {
789         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
790         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
791         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
792         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
793         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
794         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
795         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
796         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
797         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
798         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
799         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
800         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
801         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
802         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
803         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
804         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
805         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
806         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
807         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
808         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
809 };
810
811 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
812 static const u8 config_sku2000[] = {
813         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
814         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
815         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
816         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
817         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
818         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
819         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
820         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
821         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
824         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
825         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
826         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
827         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
828         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
829         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
830         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
831         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
832         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
833 };
834
835 static struct mxt_platform_data atmel_mxt_info = {
836         .x_line         = 27,
837         .y_line         = 42,
838         .x_size         = 768,
839         .y_size         = 1366,
840         .blen           = 0x20,
841         .threshold      = 0x3C,
842         .voltage        = 3300000,              /* 3.3V */
843         .orient         = 5,
844         .config         = config,
845         .config_length  = 157,
846         .config_crc     = MXT_CONFIG_CRC,
847         .irqflags       = IRQF_TRIGGER_FALLING,
848 /*      .read_chg       = &read_chg, */
849         .read_chg       = NULL,
850 };
851
852 static struct i2c_board_info __initdata atmel_i2c_info[] = {
853         {
854                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
855                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
856                 .platform_data = &atmel_mxt_info,
857         }
858 };
859
860 static int __init cardhu_touch_init(void)
861 {
862         struct board_info BoardInfo;
863
864         tegra_gpio_enable(TEGRA_GPIO_PH4);
865         tegra_gpio_enable(TEGRA_GPIO_PH6);
866
867         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
868         gpio_direction_input(TEGRA_GPIO_PH4);
869
870         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
871         gpio_direction_output(TEGRA_GPIO_PH6, 0);
872         msleep(1);
873         gpio_set_value(TEGRA_GPIO_PH6, 1);
874         msleep(100);
875
876         tegra_get_board_info(&BoardInfo);
877         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
878                 atmel_mxt_info.config = config_sku2000;
879                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
880         }
881
882         i2c_register_board_info(1, atmel_i2c_info, 1);
883
884         return 0;
885 }
886
887 static struct tegra_uhsic_config uhsic_phy_config = {
888         .enable_gpio = EN_HSIC_GPIO,
889         .reset_gpio = -1,
890         .sync_start_delay = 9,
891         .idle_wait_delay = 17,
892         .term_range_adj = 0,
893         .elastic_underrun_limit = 16,
894         .elastic_overrun_limit = 16,
895 };
896
897 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
898         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
899         .phy_config = &uhsic_phy_config,
900         .operating_mode = TEGRA_USB_HOST,
901         .power_down_on_bus_suspend = 1,
902         .default_enable = true,
903 };
904
905 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
906         [0] = {
907                         .phy_config = &utmi_phy_config[0],
908                         .operating_mode = TEGRA_USB_HOST,
909                         .power_down_on_bus_suspend = 1,
910                         .default_enable = true,
911         },
912         [1] = {
913                         .phy_config = &utmi_phy_config[1],
914                         .operating_mode = TEGRA_USB_HOST,
915                         .power_down_on_bus_suspend = 1,
916                         .default_enable = true,
917         },
918         [2] = {
919                         .phy_config = &utmi_phy_config[2],
920                         .operating_mode = TEGRA_USB_HOST,
921                         .power_down_on_bus_suspend = 1,
922                         .hotplug = 1,
923                         .default_enable = true,
924         },
925 };
926
927 static struct tegra_otg_platform_data tegra_otg_pdata = {
928         .ehci_device = &tegra_ehci1_device,
929         .ehci_pdata = &tegra_ehci_pdata[0],
930 };
931
932 #ifdef CONFIG_USB_SUPPORT
933 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
934         [0] = {
935                         .instance = 0,
936                         .vbus_gpio = -1,
937                         .vbus_reg_supply = "vdd_vbus_micro_usb",
938         },
939         [1] = {
940                         .instance = 1,
941                         .vbus_gpio = -1,
942         },
943         [2] = {
944                         .instance = 2,
945                         .vbus_gpio = -1,
946                         .vbus_reg_supply = "vdd_vbus_typea_usb",
947         },
948 };
949
950 static int cardu_usb_hsic_postsupend(void)
951 {
952         baseband_xmm_set_power_status(BBXMM_PS_L2);
953         return 0;
954 }
955
956 static int cardu_usb_hsic_preresume(void)
957 {
958         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
959         return 0;
960 }
961
962 static void cardhu_usb_init(void)
963 {
964         struct board_info bi;
965
966         tegra_get_board_info(&bi);
967
968         tegra_usb_phy_init(tegra_usb_phy_pdata,
969                         ARRAY_SIZE(tegra_usb_phy_pdata));
970
971         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
972         platform_device_register(&tegra_otg_device);
973         if (bi.board_id == BOARD_PM267) {
974                 uhsic_phy_config.reset_gpio =
975                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
976                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
977                 platform_device_register(&tegra_ehci2_device);
978         } else if (bi.board_id == BOARD_E1256) {
979                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
980                 platform_device_register(&tegra_ehci2_device);
981         } else if (bi.board_id == BOARD_E1186) {
982                 /* for baseband devices do not switch off phy during suspend */
983                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
984                 uhsic_phy_config.postsuspend = cardu_usb_hsic_postsupend;
985                 uhsic_phy_config.preresume = cardu_usb_hsic_preresume;
986                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
987                 /* baseband registration happens in baseband-xmm-power  */
988         } else {
989                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
990                 platform_device_register(&tegra_ehci2_device);
991         }
992
993         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
994         platform_device_register(&tegra_ehci3_device);
995
996 }
997 #else
998 static void cardhu_usb_init(void) { }
999 #endif
1000
1001 static void cardhu_gps_init(void)
1002 {
1003         tegra_gpio_enable(TEGRA_GPIO_PU2);
1004         tegra_gpio_enable(TEGRA_GPIO_PU3);
1005 }
1006
1007 static void cardhu_nfc_init(void)
1008 {
1009         tegra_gpio_enable(TEGRA_GPIO_PX0);
1010         tegra_gpio_enable(TEGRA_GPIO_PP3);
1011         tegra_gpio_enable(TEGRA_GPIO_PO7);
1012 }
1013
1014 static struct baseband_power_platform_data tegra_baseband_power_data = {
1015         .baseband_type = BASEBAND_XMM,
1016         .modem = {
1017         .xmm = {
1018                         .bb_rst = XMM_GPIO_BB_RST,
1019                         .bb_on = XMM_GPIO_BB_ON,
1020                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1021                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1022                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1023                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1024                         .hsic_device = &tegra_ehci2_device,
1025                 },
1026         },
1027 };
1028
1029 static struct platform_device tegra_baseband_power_device = {
1030         .name = "baseband_xmm_power",
1031         .id = -1,
1032         .dev = {
1033                 .platform_data = &tegra_baseband_power_data,
1034         },
1035 };
1036
1037 static struct platform_device tegra_baseband_power2_device = {
1038         .name = "baseband_xmm_power2",
1039         .id = -1,
1040         .dev = {
1041                 .platform_data = &tegra_baseband_power_data,
1042         },
1043 };
1044
1045
1046 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1047         .port_status[0] = 1,
1048         .port_status[1] = 1,
1049         .port_status[2] = 1,
1050         .use_dock_detect        = 0,
1051         .gpio           = 0,
1052 };
1053
1054 static void cardhu_pci_init(void)
1055 {
1056         struct board_info board_info;
1057
1058         tegra_get_board_info(&board_info);
1059         if (board_info.board_id == BOARD_E1291) {
1060                 cardhu_pci_platform_data.port_status[0] = 0;
1061                 cardhu_pci_platform_data.port_status[1] = 0;
1062                 cardhu_pci_platform_data.port_status[2] = 1;
1063                 cardhu_pci_platform_data.use_dock_detect = 1;
1064                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1065         }
1066         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1067         platform_device_register(&tegra_pci_device);
1068 }
1069
1070 static void cardhu_modem_init(void)
1071 {
1072         struct board_info board_info;
1073         int w_disable_gpio, ret;
1074
1075         tegra_get_board_info(&board_info);
1076         switch (board_info.board_id) {
1077         case BOARD_E1291:
1078         case BOARD_E1198:
1079                 if (((board_info.board_id == BOARD_E1291) &&
1080                                 (board_info.fab < BOARD_FAB_A03)) ||
1081                         ((board_info.board_id == BOARD_E1198) &&
1082                                         (board_info.fab < BOARD_FAB_A02))) {
1083                         w_disable_gpio = TEGRA_GPIO_PH5;
1084                 } else {
1085                         w_disable_gpio = TEGRA_GPIO_PDD5;
1086                 }
1087                 tegra_gpio_enable(w_disable_gpio);
1088                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1089                 if (ret < 0)
1090                         pr_err("%s: gpio_request failed for gpio %d\n",
1091                                 __func__, w_disable_gpio);
1092                 else
1093                         gpio_direction_input(w_disable_gpio);
1094
1095                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1096                 if (((board_info.board_id == BOARD_E1291) &&
1097                                 (board_info.fab >= BOARD_FAB_A04)) ||
1098                         ((board_info.board_id == BOARD_E1198) &&
1099                                         (board_info.fab >= BOARD_FAB_A02))) {
1100                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1101                         if (ret < 0) {
1102                                 pr_err("%s(): Error in allocating gpio "
1103                                         "TEGRA_GPIO_PH7\n", __func__);
1104                                 break;
1105                         }
1106                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1107                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1108                 }
1109                 break;
1110         case BOARD_E1186:
1111                 tegra_gpio_enable(
1112                         tegra_baseband_power_data.modem.xmm.bb_rst);
1113                 tegra_gpio_enable(
1114                         tegra_baseband_power_data.modem.xmm.bb_on);
1115                 tegra_gpio_enable(
1116                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1117                 tegra_gpio_enable(
1118                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1119                 tegra_gpio_enable(
1120                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1121                 tegra_gpio_enable(
1122                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1123                 platform_device_register(&tegra_baseband_power_device);
1124                 platform_device_register(&tegra_baseband_power2_device);
1125                 break;
1126         default:
1127                 break;
1128         }
1129
1130 }
1131
1132 #ifdef CONFIG_SATA_AHCI_TEGRA
1133 static void cardhu_sata_init(void)
1134 {
1135         platform_device_register(&tegra_sata_device);
1136 }
1137 #else
1138 static void cardhu_sata_init(void) { }
1139 #endif
1140
1141 static void __init tegra_cardhu_init(void)
1142 {
1143         tegra_thermal_init(&thermal_data);
1144         tegra_clk_init_from_table(cardhu_clk_init_table);
1145         cardhu_pinmux_init();
1146         cardhu_i2c_init();
1147         cardhu_spi_init();
1148         cardhu_usb_init();
1149 #ifdef CONFIG_TEGRA_EDP_LIMITS
1150         cardhu_edp_init();
1151 #endif
1152         cardhu_uart_init();
1153         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1154         cardhu_sdhci_init();
1155         cardhu_regulator_init();
1156         cardhu_dtv_init();
1157         cardhu_suspend_init();
1158         cardhu_touch_init();
1159         cardhu_gps_init();
1160         cardhu_modem_init();
1161         cardhu_kbc_init();
1162         cardhu_scroll_init();
1163         cardhu_keys_init();
1164         cardhu_panel_init();
1165         cardhu_pmon_init();
1166         cardhu_sensors_init();
1167         cardhu_bt_rfkill();
1168         tegra_setup_bluesleep();
1169         cardhu_sata_init();
1170         //audio_wired_jack_init();
1171         cardhu_pins_state_init();
1172         cardhu_emc_init();
1173         tegra_release_bootloader_fb();
1174         cardhu_nfc_init();
1175         cardhu_pci_init();
1176 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1177         tegra_wdt_recovery_init();
1178 #endif
1179 }
1180
1181 static void __init cardhu_ramconsole_reserve(unsigned long size)
1182 {
1183         struct resource *res;
1184         long ret;
1185
1186         res = platform_get_resource(&ram_console_device, IORESOURCE_MEM, 0);
1187         if (!res) {
1188                 pr_err("Failed to find memory resource for ram console\n");
1189                 return;
1190         }
1191         res->start = memblock_end_of_DRAM() - size;
1192         res->end = res->start + size - 1;
1193         ret = memblock_remove(res->start, size);
1194         if (ret) {
1195                 ram_console_device.resource = NULL;
1196                 ram_console_device.num_resources = 0;
1197                 pr_err("Failed to reserve memory block for ram console\n");
1198         }
1199 }
1200
1201 static void __init tegra_cardhu_reserve(void)
1202 {
1203 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1204         /* support 1920X1200 with 24bpp */
1205         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1206 #else
1207         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1208 #endif
1209         cardhu_ramconsole_reserve(SZ_1M);
1210 }
1211
1212 MACHINE_START(CARDHU, "cardhu")
1213         .boot_params    = 0x80000100,
1214         .map_io         = tegra_map_common_io,
1215         .reserve        = tegra_cardhu_reserve,
1216         .init_early     = tegra_init_early,
1217         .init_irq       = tegra_init_irq,
1218         .timer          = &tegra_timer,
1219         .init_machine   = tegra_cardhu_init,
1220 MACHINE_END