arm: tegra: cardhu: enable touchscreen for E1506 panel
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <asm/hardware/gic.h>
48
49 #include <mach/clk.h>
50 #include <mach/iomap.h>
51 #include <mach/irqs.h>
52 #include <mach/pinmux.h>
53 #include <mach/iomap.h>
54 #include <mach/io.h>
55 #include <mach/i2s.h>
56 #include <mach/tegra_asoc_pdata.h>
57 #include <mach/tegra_wm8903_pdata.h>
58 #include <asm/mach-types.h>
59 #include <asm/mach/arch.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/gpio-tegra.h>
64
65 #include "board.h"
66 #include "clock.h"
67 #include "board-cardhu.h"
68 #include "board-touch.h"
69 #include "devices.h"
70 #include "gpio-names.h"
71 #include "fuse.h"
72 #include "pm.h"
73 #include "baseband-xmm-power.h"
74 #include "wdt-recovery.h"
75
76 /* All units are in millicelsius */
77 static struct tegra_thermal_data thermal_data = {
78         .temp_shutdown = 90000,
79         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
80 #ifdef CONFIG_TEGRA_EDP_LIMITS
81         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
82         .hysteresis_edp = 3000,
83 #endif
84 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
85         .temp_throttle = 85000,
86         .tc1 = 0,
87         .tc2 = 1,
88         .passive_delay = 2000,
89 #endif
90 };
91
92 static struct resource cardhu_bcm4329_rfkill_resources[] = {
93         {
94                 .name   = "bcm4329_nshutdown_gpio",
95                 .start  = TEGRA_GPIO_PU0,
96                 .end    = TEGRA_GPIO_PU0,
97                 .flags  = IORESOURCE_IO,
98         },
99 };
100
101 static struct platform_device cardhu_bcm4329_rfkill_device = {
102         .name = "bcm4329_rfkill",
103         .id             = -1,
104         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
105         .resource       = cardhu_bcm4329_rfkill_resources,
106 };
107
108 static struct resource cardhu_bluesleep_resources[] = {
109         [0] = {
110                 .name = "gpio_host_wake",
111                         .start  = TEGRA_GPIO_PU6,
112                         .end    = TEGRA_GPIO_PU6,
113                         .flags  = IORESOURCE_IO,
114         },
115         [1] = {
116                 .name = "gpio_ext_wake",
117                         .start  = TEGRA_GPIO_PU1,
118                         .end    = TEGRA_GPIO_PU1,
119                         .flags  = IORESOURCE_IO,
120         },
121         [2] = {
122                 .name = "host_wake",
123                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
124         },
125 };
126
127 static struct platform_device cardhu_bluesleep_device = {
128         .name           = "bluesleep",
129         .id             = -1,
130         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
131         .resource       = cardhu_bluesleep_resources,
132 };
133
134 static noinline void __init cardhu_setup_bluesleep(void)
135 {
136         cardhu_bluesleep_resources[2].start =
137                 cardhu_bluesleep_resources[2].end =
138                         gpio_to_irq(TEGRA_GPIO_PU6);
139         platform_device_register(&cardhu_bluesleep_device);
140         return;
141 }
142
143 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
144         /* name         parent          rate            enabled */
145         { "pll_m",      NULL,           0,              false},
146         { "hda",        "pll_p",        108000000,      false},
147         { "hda2codec_2x","pll_p",       48000000,       false},
148         { "pwm",        "pll_p",        3187500,        false},
149         { "blink",      "clk_32k",      32768,          true},
150         { "i2s0",       "pll_a_out0",   0,              false},
151         { "i2s1",       "pll_a_out0",   0,              false},
152         { "i2s3",       "pll_a_out0",   0,              false},
153         { "spdif_out",  "pll_a_out0",   0,              false},
154         { "d_audio",    "clk_m",        12000000,       false},
155         { "dam0",       "clk_m",        12000000,       false},
156         { "dam1",       "clk_m",        12000000,       false},
157         { "dam2",       "clk_m",        12000000,       false},
158         { "audio1",     "i2s1_sync",    0,              false},
159         { "audio3",     "i2s3_sync",    0,              false},
160         { "vi_sensor",  "pll_p",        150000000,      false},
161         { "i2c1",       "pll_p",        3200000,        false},
162         { "i2c2",       "pll_p",        3200000,        false},
163         { "i2c3",       "pll_p",        3200000,        false},
164         { "i2c4",       "pll_p",        3200000,        false},
165         { "i2c5",       "pll_p",        3200000,        false},
166         { NULL,         NULL,           0,              0},
167 };
168
169 static struct pn544_i2c_platform_data nfc_pdata = {
170         .irq_gpio = TEGRA_GPIO_PX0,
171         .ven_gpio = TEGRA_GPIO_PP3,
172         .firm_gpio = TEGRA_GPIO_PO7,
173         };
174
175 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
176         {
177                 I2C_BOARD_INFO("pn544", 0x28),
178                 .platform_data = &nfc_pdata,
179         },
180 };
181 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
182         .adapter_nr     = 0,
183         .bus_count      = 1,
184         .bus_clk_rate   = { 100000, 0 },
185         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
186         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
187         .arb_recovery = arb_lost_recovery,
188 };
189
190 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
191         .adapter_nr     = 1,
192         .bus_count      = 1,
193         .bus_clk_rate   = { 400000, 0 },
194         .is_clkon_always = true,
195         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
196         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
197         .arb_recovery = arb_lost_recovery,
198 };
199
200 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
201         .adapter_nr     = 2,
202         .bus_count      = 1,
203         .bus_clk_rate   = { 100000, 0 },
204         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
205         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
206         .arb_recovery = arb_lost_recovery,
207 };
208
209 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
210         .adapter_nr     = 3,
211         .bus_count      = 1,
212         .bus_clk_rate   = { 10000, 0 },
213         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
214         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
215         .arb_recovery = arb_lost_recovery,
216 };
217
218 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
219         .adapter_nr     = 4,
220         .bus_count      = 1,
221         .bus_clk_rate   = { 400000, 0 },
222         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
223         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
224         .arb_recovery = arb_lost_recovery,
225 };
226
227
228 #if 0
229 struct tegra_wired_jack_conf audio_wr_jack_conf = {
230         .hp_det_n = TEGRA_GPIO_PW2,
231         .en_mic_ext = TEGRA_GPIO_PX1,
232         .en_mic_int = TEGRA_GPIO_PX0,
233 };
234 #endif
235
236 static struct wm8903_platform_data cardhu_wm8903_pdata = {
237         .irq_active_low = 0,
238         .micdet_cfg = 0,
239         .micdet_delay = 100,
240         .gpio_base = CARDHU_GPIO_WM8903(0),
241         .gpio_cfg = {
242                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
243                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
244                         WM8903_GP2_DIR,
245                 WM8903_GPIO_CONFIG_ZERO,
246                 0,
247                 0,
248         },
249 };
250
251 /* Equalizer filter coefs generated from the MAXIM MAX98095
252  * evkit software tool */
253 static struct max98095_eq_cfg max98095_eq_cfg[] = {
254         {
255                 .name = "FLAT",
256                 .rate = 44100,
257                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
258                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
259                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
260                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
261                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
262         },
263         {
264                 .name = "LOWPASS1K",
265                 .rate = 44100,
266                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
267                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
268                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
269                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
270                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
271         },
272         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
273                 .name = "HIBOOST",
274                 .rate = 44100,
275                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
276                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
277                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
278                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
279                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
280         },
281         { /* BASS=12dB, TREBLE=+12dB */
282                 .name = "LOUD12DB",
283                 .rate = 44100,
284                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
285                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
286                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
287                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
288                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
289         },
290         {
291                 .name = "FLAT",
292                 .rate = 16000,
293                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
294                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
295                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
296                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
297                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
298         },
299         {
300                 .name = "LOWPASS1K",
301                 .rate = 16000,
302                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
303                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
304                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
305                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
306                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
307         },
308         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
309                 .name = "HIBOOST",
310                 .rate = 16000,
311                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
312                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
313                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
314                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
315                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
316         },
317         { /* BASS=12dB, TREBLE=+12dB */
318                 .name = "LOUD12DB",
319                 .rate = 16000,
320                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
321                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
322                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
323                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
324                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
325         },
326 };
327
328 static struct max98095_pdata cardhu_max98095_pdata = {
329         /* equalizer configuration */
330         .eq_cfg = max98095_eq_cfg,
331         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
332
333         /* Biquad filter response configuration */
334         .bq_cfg = NULL,
335         .bq_cfgcnt = 0,
336
337         /* microphone configuration */
338         .digmic_left_mode = 1,
339         .digmic_right_mode = 1,
340 };
341
342 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
343         I2C_BOARD_INFO("wm8903", 0x1a),
344         .platform_data = &cardhu_wm8903_pdata,
345 };
346
347 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
348         I2C_BOARD_INFO("aic3262-codec", 0x18),
349 };
350
351 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
352         I2C_BOARD_INFO("max98095", 0x10),
353         .platform_data = &cardhu_max98095_pdata,
354 };
355
356 static void cardhu_i2c_init(void)
357 {
358         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
359         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
360         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
361         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
362         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
363
364         platform_device_register(&tegra_i2c_device5);
365         platform_device_register(&tegra_i2c_device4);
366         platform_device_register(&tegra_i2c_device3);
367         platform_device_register(&tegra_i2c_device2);
368         platform_device_register(&tegra_i2c_device1);
369
370         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
371                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
372         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
373         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
374         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
375
376         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
377         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
378 }
379
380 static struct platform_device *cardhu_uart_devices[] __initdata = {
381         &tegra_uarta_device,
382         &tegra_uartb_device,
383         &tegra_uartc_device,
384         &tegra_uartd_device,
385         &tegra_uarte_device,
386 };
387 static struct uart_clk_parent uart_parent_clk[] = {
388         [0] = {.name = "clk_m"},
389         [1] = {.name = "pll_p"},
390 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
391         [2] = {.name = "pll_m"},
392 #endif
393 };
394
395 static struct tegra_uart_platform_data cardhu_uart_pdata;
396 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
397
398 static void __init uart_debug_init(void)
399 {
400         struct board_info board_info;
401         int debug_port_id;
402
403         tegra_get_board_info(&board_info);
404
405         debug_port_id = get_tegra_uart_debug_port_id();
406         if (debug_port_id < 0) {
407                 debug_port_id = 0;
408                         /* UARTB is debug port
409                          *       for SLT - E1186/E1187/PM269
410                          *       for E1256/E1257
411                          */
412                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
413                         ((board_info.board_id == BOARD_E1186) ||
414                         (board_info.board_id == BOARD_E1187) ||
415                         (board_info.board_id == BOARD_PM269))) ||
416                         (board_info.board_id == BOARD_E1256) ||
417                         (board_info.board_id == BOARD_E1257))
418                                 debug_port_id = 1;
419         }
420
421         switch (debug_port_id) {
422         case 0:
423                 /* UARTA is the debug port. */
424                 pr_info("Selecting UARTA as the debug console\n");
425                 cardhu_uart_devices[0] = &debug_uarta_device;
426                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
427                 debug_uart_port_base = ((struct plat_serial8250_port *)(
428                         debug_uarta_device.dev.platform_data))->mapbase;
429                 break;
430
431         case 1:
432                 /* UARTB is the debug port. */
433                 pr_info("Selecting UARTB as the debug console\n");
434                 cardhu_uart_devices[1] = &debug_uartb_device;
435                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
436                 debug_uart_port_base = ((struct plat_serial8250_port *)(
437                         debug_uartb_device.dev.platform_data))->mapbase;
438                 break;
439
440         case 2:
441                 /* UARTC is the debug port. */
442                 pr_info("Selecting UARTC as the debug console\n");
443                 cardhu_uart_devices[2] = &debug_uartc_device;
444                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
445                 debug_uart_port_base = ((struct plat_serial8250_port *)(
446                         debug_uartc_device.dev.platform_data))->mapbase;
447                 break;
448
449         case 3:
450                 /* UARTD is the debug port. */
451                 pr_info("Selecting UARTD as the debug console\n");
452                 cardhu_uart_devices[3] = &debug_uartd_device;
453                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
454                 debug_uart_port_base = ((struct plat_serial8250_port *)(
455                         debug_uartd_device.dev.platform_data))->mapbase;
456                 break;
457
458         case 4:
459                 /* UARTE is the debug port. */
460                 pr_info("Selecting UARTE as the debug console\n");
461                 cardhu_uart_devices[4] = &debug_uarte_device;
462                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
463                 debug_uart_port_base = ((struct plat_serial8250_port *)(
464                         debug_uarte_device.dev.platform_data))->mapbase;
465                 break;
466
467         default:
468                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
469                 cardhu_uart_devices[0] = &debug_uarta_device;
470                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
471                 debug_uart_port_base = ((struct plat_serial8250_port *)(
472                         debug_uarta_device.dev.platform_data))->mapbase;
473                 break;
474         }
475         return;
476 }
477
478 static void __init cardhu_uart_init(void)
479 {
480         struct clk *c;
481         int i;
482
483         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
484                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
485                 if (IS_ERR_OR_NULL(c)) {
486                         pr_err("Not able to get the clock for %s\n",
487                                                 uart_parent_clk[i].name);
488                         continue;
489                 }
490                 uart_parent_clk[i].parent_clk = c;
491                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
492         }
493         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
494         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
495         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
496         cardhu_loopback_uart_pdata.parent_clk_count =
497                                                 ARRAY_SIZE(uart_parent_clk);
498         cardhu_loopback_uart_pdata.is_loopback = true;
499         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
500         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
501         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
502         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
503         /* UARTE is used for loopback test purpose */
504         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
505
506         /* Register low speed only if it is selected */
507         if (!is_tegra_debug_uartport_hs()) {
508                 uart_debug_init();
509                 /* Clock enable for the debug channel */
510                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
511                         pr_info("The debug console clock name is %s\n",
512                                                 debug_uart_clk->name);
513                         c = tegra_get_clock_by_name("pll_p");
514                         if (IS_ERR_OR_NULL(c))
515                                 pr_err("Not getting the parent clock pll_p\n");
516                         else
517                                 clk_set_parent(debug_uart_clk, c);
518
519                         clk_enable(debug_uart_clk);
520                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
521                 } else {
522                         pr_err("Not getting the clock %s for debug console\n",
523                                         debug_uart_clk->name);
524                 }
525         }
526
527         platform_add_devices(cardhu_uart_devices,
528                                 ARRAY_SIZE(cardhu_uart_devices));
529 }
530
531 static struct platform_device tegra_camera = {
532         .name = "tegra_camera",
533         .id = -1,
534 };
535
536 static struct platform_device *cardhu_spi_devices[] __initdata = {
537         &tegra_spi_device4,
538 };
539
540 static struct platform_device *touch_spi_device[] __initdata = {
541         &tegra_spi_device1,
542 };
543
544 struct spi_clk_parent spi_parent_clk[] = {
545         [0] = {.name = "pll_p"},
546 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
547         [1] = {.name = "pll_m"},
548         [2] = {.name = "clk_m"},
549 #else
550         [1] = {.name = "clk_m"},
551 #endif
552 };
553
554 static struct tegra_spi_platform_data cardhu_spi_pdata = {
555         .is_dma_based           = true,
556         .max_dma_buffer         = (16 * 1024),
557         .is_clkon_always        = false,
558         .max_rate               = 100000000,
559 };
560
561 static void __init cardhu_spi_init(void)
562 {
563         int i;
564         struct clk *c;
565         struct board_info board_info, display_board_info;
566
567         tegra_get_board_info(&board_info);
568         tegra_get_display_board_info(&display_board_info);
569
570         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
571                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
572                 if (IS_ERR_OR_NULL(c)) {
573                         pr_err("Not able to get the clock for %s\n",
574                                                 spi_parent_clk[i].name);
575                         continue;
576                 }
577                 spi_parent_clk[i].parent_clk = c;
578                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
579         }
580         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
581         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
582         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
583         platform_add_devices(cardhu_spi_devices,
584                                 ARRAY_SIZE(cardhu_spi_devices));
585
586         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
587                 platform_add_devices(touch_spi_device,
588                                 ARRAY_SIZE(touch_spi_device));
589         }
590         if (board_info.board_id == BOARD_E1198) {
591                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
592                 platform_device_register(&tegra_spi_device2);
593                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
594                 platform_device_register(&tegra_spi_slave_device1);
595         }
596 }
597
598 static void __init cardhu_dtv_init(void)
599 {
600         struct board_info board_info;
601
602         tegra_get_board_info(&board_info);
603
604         if (board_info.board_id == BOARD_E1186)
605                 platform_device_register(&tegra_dtv_device);
606 }
607
608 static struct resource tegra_rtc_resources[] = {
609         [0] = {
610                 .start = TEGRA_RTC_BASE,
611                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
612                 .flags = IORESOURCE_MEM,
613         },
614         [1] = {
615                 .start = INT_RTC,
616                 .end = INT_RTC,
617                 .flags = IORESOURCE_IRQ,
618         },
619 };
620
621 static struct platform_device tegra_rtc_device = {
622         .name = "tegra_rtc",
623         .id   = -1,
624         .resource = tegra_rtc_resources,
625         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
626 };
627
628 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
629         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
630         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
631         .gpio_hp_mute           = -1,
632         .gpio_int_mic_en        = -1,
633         .gpio_ext_mic_en        = -1,
634 };
635
636 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
637         .gpio_spkr_en           = -1,
638         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
639         .gpio_hp_mute           = -1,
640         .gpio_int_mic_en        = -1,
641         .gpio_ext_mic_en        = -1,
642 };
643
644 static struct platform_device cardhu_audio_wm8903_device = {
645         .name   = "tegra-snd-wm8903",
646         .id     = 0,
647         .dev    = {
648                 .platform_data = &cardhu_audio_wm8903_pdata,
649         },
650 };
651
652 static struct platform_device cardhu_audio_max98095_device = {
653         .name   = "tegra-snd-max98095",
654         .id     = 0,
655         .dev    = {
656                 .platform_data = &cardhu_audio_max98095_pdata,
657         },
658 };
659
660 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
661         .gpio_spkr_en           = -1,
662         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
663         .gpio_hp_mute           = -1,
664         .gpio_int_mic_en        = -1,
665         .gpio_ext_mic_en        = -1,
666         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
667         .audio_port_id          = {
668                 [HIFI_CODEC] = 0,
669                 [BASEBAND] = -1,
670                 [BT_SCO] = 3,
671         },
672         .baseband_param         = {
673                 .rate = -1,
674                 .channels = -1,
675         },
676 };
677
678 static struct platform_device cardhu_audio_aic326x_device = {
679         .name   = "tegra-snd-aic326x",
680         .id     = 0,
681         .dev    = {
682                 .platform_data  = &cardhu_audio_aic326x_pdata,
683         },
684 };
685
686 static struct platform_device *cardhu_devices[] __initdata = {
687         &tegra_pmu_device,
688         &tegra_rtc_device,
689         &tegra_udc_device,
690 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
691         &tegra_smmu_device,
692 #endif
693         &tegra_wdt_device,
694 #if defined(CONFIG_TEGRA_AVP)
695         &tegra_avp_device,
696 #endif
697         &tegra_camera,
698 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
699         &tegra_se_device,
700 #endif
701         &tegra_ahub_device,
702         &tegra_dam_device0,
703         &tegra_dam_device1,
704         &tegra_dam_device2,
705         &tegra_i2s_device0,
706         &tegra_i2s_device1,
707         &tegra_i2s_device3,
708         &tegra_spdif_device,
709         &spdif_dit_device,
710         &bluetooth_dit_device,
711         &baseband_dit_device,
712         &cardhu_bcm4329_rfkill_device,
713         &tegra_pcm_device,
714         &cardhu_audio_wm8903_device,
715         &cardhu_audio_max98095_device,
716         &cardhu_audio_aic326x_device,
717         &tegra_hda_device,
718 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
719         &tegra_aes_device,
720 #endif
721 };
722
723 #define E1506_MXT_CONFIG_CRC 0x62F903
724 static const u8 e1506_config[] = {
725         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
726         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
727         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
728         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
729         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
730         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
731         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
732         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
733         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
734         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
735         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
736         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
737         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
738         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
739         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
740         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
742         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
743         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
744         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
745         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
746         0x00
747 };
748
749 #define MXT_CONFIG_CRC  0xD62DE8
750 static const u8 config[] = {
751         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
752         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
753         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
754         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
755         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
756         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
757         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
758         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
759         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
760         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
761         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
762         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
763         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
764         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
765         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
766         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
767         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
768         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
769         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
770         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
771 };
772
773 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
774 static const u8 config_sku2000[] = {
775         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
776         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
777         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
778         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
779         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
780         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
781         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
782         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
783         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
784         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
785         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
786         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
787         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
788         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
789         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
790         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
791         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
792         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
793         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
794         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
795 };
796
797 static struct mxt_platform_data atmel_mxt_info = {
798         .x_line         = 27,
799         .y_line         = 42,
800         .x_size         = 768,
801         .y_size         = 1366,
802         .blen           = 0x20,
803         .threshold      = 0x3C,
804         .voltage        = 3300000,              /* 3.3V */
805         .orient         = 5,
806         .config         = config,
807         .config_length  = 157,
808         .config_crc     = MXT_CONFIG_CRC,
809         .irqflags       = IRQF_TRIGGER_FALLING,
810 /*      .read_chg       = &read_chg, */
811         .read_chg       = NULL,
812 };
813
814 static struct mxt_platform_data e1506_atmel_mxt_info = {
815         .x_line         = 19,
816         .y_line         = 11,
817         .x_size         = 960,
818         .y_size         = 540,
819         .blen           = 0x10,
820         .threshold      = 0x32,
821         .voltage        = 3300000,              /* 3.3V */
822         .orient         = 3,
823         .config         = e1506_config,
824         .config_length  = 168,
825         .config_crc     = E1506_MXT_CONFIG_CRC,
826         .irqflags       = IRQF_TRIGGER_FALLING,
827 /*      .read_chg       = &read_chg, */
828         .read_chg       = NULL,
829 };
830
831 static struct i2c_board_info __initdata atmel_i2c_info[] = {
832         {
833                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
834                 .platform_data = &atmel_mxt_info,
835         }
836 };
837
838 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
839         {
840                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
841                 .platform_data = &e1506_atmel_mxt_info,
842         }
843 };
844
845 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
846         /* name         parent          rate            enabled */
847         { "sbc1",       "pll_p",        52000000,       true},
848         { NULL,         NULL,           0,              0},
849 };
850
851 static int __init cardhu_touch_init(void)
852 {
853         struct board_info BoardInfo, DisplayBoardInfo;
854
855         tegra_get_board_info(&BoardInfo);
856         tegra_get_display_board_info(&DisplayBoardInfo);
857         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
858                 tegra_clk_init_from_table(spi_clk_init_table);
859
860                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
861         } else {
862                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
863                 gpio_direction_input(TEGRA_GPIO_PH4);
864
865                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
866                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
867                 msleep(1);
868                 gpio_set_value(TEGRA_GPIO_PH6, 1);
869                 msleep(100);
870
871                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
872                         atmel_mxt_info.config = config_sku2000;
873                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
874                 }
875
876                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
877                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
878                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
879                 } else {
880                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
881                         i2c_register_board_info(1, atmel_i2c_info, 1);
882                 }
883         }
884
885         return 0;
886 }
887
888 static void cardu_usb_hsic_postsupend(void)
889 {
890 #ifdef CONFIG_TEGRA_BB_XMM_POWER
891         baseband_xmm_set_power_status(BBXMM_PS_L2);
892 #endif
893 }
894
895 static void cardu_usb_hsic_preresume(void)
896 {
897 #ifdef CONFIG_TEGRA_BB_XMM_POWER
898         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
899 #endif
900 }
901
902 static void cardu_usb_hsic_phy_ready(void)
903 {
904 #ifdef CONFIG_TEGRA_BB_XMM_POWER
905         baseband_xmm_set_power_status(BBXMM_PS_L0);
906 #endif
907 }
908
909 static void cardu_usb_hsic_phy_off(void)
910 {
911 #ifdef CONFIG_TEGRA_BB_XMM_POWER
912         baseband_xmm_set_power_status(BBXMM_PS_L3);
913 #endif
914 }
915
916 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
917         .post_suspend = cardu_usb_hsic_postsupend,
918         .pre_resume = cardu_usb_hsic_preresume,
919         .port_power = cardu_usb_hsic_phy_ready,
920         .post_phy_off = cardu_usb_hsic_phy_off,
921 };
922
923 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
924         .port_otg = false,
925         .has_hostpc = true,
926         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
927         .op_mode        = TEGRA_USB_OPMODE_HOST,
928         .u_data.host = {
929                 .vbus_gpio = -1,
930                 .hot_plug = false,
931                 .remote_wakeup_supported = false,
932                 .power_off_on_suspend = false,
933         },
934         .u_cfg.hsic = {
935                 .sync_start_delay = 9,
936                 .idle_wait_delay = 17,
937                 .term_range_adj = 0,
938                 .elastic_underrun_limit = 16,
939                 .elastic_overrun_limit = 16,
940         },
941         .ops = &hsic_xmm_plat_ops,
942 };
943
944
945 static int hsic_enable_gpio = -1;
946 static int hsic_reset_gpio = -1;
947
948 void hsic_platform_open(void)
949 {
950         int reset_gpio = 0, enable_gpio = 0;
951
952         if (hsic_enable_gpio != -1)
953                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
954         if (hsic_reset_gpio != -1)
955                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
956         /* hsic enable signal deasserted, hsic reset asserted */
957         if (!enable_gpio)
958                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
959         if (!reset_gpio)
960                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
961         if (!enable_gpio)
962                 tegra_gpio_enable(hsic_enable_gpio);
963         if (!reset_gpio)
964                 tegra_gpio_enable(hsic_reset_gpio);
965         /* keep hsic reset asserted for 1 ms */
966         udelay(1000);
967         /* enable (power on) hsic */
968         if (!enable_gpio)
969                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
970         udelay(1000);
971         /* deassert reset */
972         if (!reset_gpio)
973                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
974
975 }
976
977 void hsic_platform_close(void)
978 {
979         if (hsic_enable_gpio != -1) {
980                 gpio_set_value(hsic_enable_gpio, 0);
981                 gpio_free(hsic_enable_gpio);
982         }
983         if (hsic_reset_gpio != -1) {
984                 gpio_set_value(hsic_reset_gpio, 0);
985                 gpio_free(hsic_reset_gpio);
986         }
987 }
988
989 void hsic_power_on(void)
990 {
991         if (hsic_enable_gpio != -1) {
992                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
993                 udelay(1000);
994         }
995 }
996
997 void hsic_power_off(void)
998 {
999         if (hsic_enable_gpio != -1) {
1000                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1001                 udelay(1000);
1002         }
1003 }
1004
1005 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1006         .open = hsic_platform_open,
1007         .close = hsic_platform_close,
1008         .pre_phy_on = hsic_power_on,
1009         .post_phy_off = hsic_power_off,
1010 };
1011
1012 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1013         .port_otg = false,
1014         .has_hostpc = true,
1015         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1016         .op_mode        = TEGRA_USB_OPMODE_HOST,
1017         .u_data.host = {
1018                 .vbus_gpio = -1,
1019                 .hot_plug = false,
1020                 .remote_wakeup_supported = false,
1021                 .power_off_on_suspend = false,
1022         },
1023         .u_cfg.hsic = {
1024                 .sync_start_delay = 9,
1025                 .idle_wait_delay = 17,
1026                 .term_range_adj = 0,
1027                 .elastic_underrun_limit = 16,
1028                 .elastic_overrun_limit = 16,
1029         },
1030         .ops = &hsic_plat_ops,
1031 };
1032
1033 static struct tegra_usb_platform_data tegra_udc_pdata = {
1034         .port_otg = true,
1035         .has_hostpc = true,
1036         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1037         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1038         .u_data.dev = {
1039                 .vbus_pmu_irq = 0,
1040                 .vbus_gpio = -1,
1041                 .charging_supported = false,
1042                 .remote_wakeup_supported = false,
1043         },
1044         .u_cfg.utmi = {
1045                 .hssync_start_delay = 0,
1046                 .elastic_limit = 16,
1047                 .idle_wait_delay = 17,
1048                 .term_range_adj = 6,
1049                 .xcvr_setup = 8,
1050                 .xcvr_lsfslew = 2,
1051                 .xcvr_lsrslew = 2,
1052                 .xcvr_setup_offset = 0,
1053                 .xcvr_use_fuses = 1,
1054         },
1055 };
1056
1057 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1058         .port_otg = true,
1059         .has_hostpc = true,
1060         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1061         .op_mode = TEGRA_USB_OPMODE_HOST,
1062         .u_data.host = {
1063                 .vbus_gpio = -1,
1064                 .vbus_reg = "vdd_vbus_micro_usb",
1065                 .hot_plug = true,
1066                 .remote_wakeup_supported = true,
1067                 .power_off_on_suspend = true,
1068         },
1069         .u_cfg.utmi = {
1070                 .hssync_start_delay = 0,
1071                 .elastic_limit = 16,
1072                 .idle_wait_delay = 17,
1073                 .term_range_adj = 6,
1074                 .xcvr_setup = 15,
1075                 .xcvr_lsfslew = 2,
1076                 .xcvr_lsrslew = 2,
1077                 .xcvr_setup_offset = 0,
1078                 .xcvr_use_fuses = 1,
1079         },
1080 };
1081
1082 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1083         .port_otg = false,
1084         .has_hostpc = true,
1085         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1086         .op_mode        = TEGRA_USB_OPMODE_HOST,
1087         .u_data.host = {
1088                 .vbus_gpio = -1,
1089                 .hot_plug = false,
1090                 .remote_wakeup_supported = true,
1091                 .power_off_on_suspend = true,
1092         },
1093         .u_cfg.utmi = {
1094                 .hssync_start_delay = 0,
1095                 .elastic_limit = 16,
1096                 .idle_wait_delay = 17,
1097                 .term_range_adj = 6,
1098                 .xcvr_setup = 15,
1099                 .xcvr_lsfslew = 2,
1100                 .xcvr_lsrslew = 2,
1101                 .xcvr_setup_offset = 0,
1102                 .xcvr_use_fuses = 1,
1103         },
1104 };
1105
1106 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1107         .port_otg = false,
1108         .has_hostpc = true,
1109         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1110         .op_mode        = TEGRA_USB_OPMODE_HOST,
1111         .u_data.host = {
1112                 .vbus_gpio = -1,
1113                 .vbus_reg = "vdd_vbus_typea_usb",
1114                 .hot_plug = true,
1115                 .remote_wakeup_supported = true,
1116                 .power_off_on_suspend = true,
1117         },
1118         .u_cfg.utmi = {
1119                 .hssync_start_delay = 0,
1120                 .elastic_limit = 16,
1121                 .idle_wait_delay = 17,
1122                 .term_range_adj = 6,
1123                 .xcvr_setup = 8,
1124                 .xcvr_lsfslew = 2,
1125                 .xcvr_lsrslew = 2,
1126                 .xcvr_setup_offset = 0,
1127                 .xcvr_use_fuses = 1,
1128         },
1129 };
1130
1131 static struct tegra_usb_otg_data tegra_otg_pdata = {
1132         .ehci_device = &tegra_ehci1_device,
1133         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1134 };
1135
1136 #if CONFIG_USB_SUPPORT
1137 static void cardhu_usb_init(void)
1138 {
1139         struct board_info bi;
1140
1141         tegra_get_board_info(&bi);
1142
1143         /* OTG should be the first to be registered */
1144         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1145         platform_device_register(&tegra_otg_device);
1146
1147         /* setup the udc platform data */
1148         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1149
1150         if (bi.board_id == BOARD_PM267) {
1151                 hsic_enable_gpio = EN_HSIC_GPIO;
1152                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1153                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1154                 platform_device_register(&tegra_ehci2_device);
1155         } else if (bi.board_id == BOARD_E1256) {
1156                 hsic_enable_gpio = EN_HSIC_GPIO;
1157                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1158                 platform_device_register(&tegra_ehci2_device);
1159         } else if (bi.board_id == BOARD_E1186) {
1160                 tegra_ehci2_device.dev.platform_data =
1161                                                 &tegra_ehci2_hsic_xmm_pdata;
1162                 /* ehci2 registration happens in baseband-xmm-power  */
1163         } else {
1164                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1165                 platform_device_register(&tegra_ehci2_device);
1166         }
1167
1168         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1169         platform_device_register(&tegra_ehci3_device);
1170
1171 }
1172 #else
1173 static void cardhu_usb_init(void) { }
1174 #endif
1175
1176 static struct baseband_power_platform_data tegra_baseband_power_data = {
1177         .baseband_type = BASEBAND_XMM,
1178         .modem = {
1179         .xmm = {
1180                         .bb_rst = XMM_GPIO_BB_RST,
1181                         .bb_on = XMM_GPIO_BB_ON,
1182                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1183                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1184                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1185                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1186                         .hsic_device = &tegra_ehci2_device,
1187                 },
1188         },
1189 };
1190
1191 static struct platform_device tegra_baseband_power_device = {
1192         .name = "baseband_xmm_power",
1193         .id = -1,
1194         .dev = {
1195                 .platform_data = &tegra_baseband_power_data,
1196         },
1197 };
1198
1199 static struct platform_device tegra_baseband_power2_device = {
1200         .name = "baseband_xmm_power2",
1201         .id = -1,
1202         .dev = {
1203                 .platform_data = &tegra_baseband_power_data,
1204         },
1205 };
1206
1207
1208 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1209         .port_status[0] = 1,
1210         .port_status[1] = 1,
1211         .port_status[2] = 1,
1212         .use_dock_detect        = 0,
1213         .gpio           = 0,
1214 };
1215
1216 static void cardhu_pci_init(void)
1217 {
1218         struct board_info board_info;
1219
1220         tegra_get_board_info(&board_info);
1221         if (board_info.board_id == BOARD_E1291) {
1222                 cardhu_pci_platform_data.port_status[0] = 0;
1223                 cardhu_pci_platform_data.port_status[1] = 0;
1224                 cardhu_pci_platform_data.port_status[2] = 1;
1225                 cardhu_pci_platform_data.use_dock_detect = 1;
1226                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1227         }
1228         if ((board_info.board_id == BOARD_E1186) ||
1229                 (board_info.board_id == BOARD_E1187) ||
1230                 (board_info.board_id == BOARD_E1291)) {
1231                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1232                 platform_device_register(&tegra_pci_device);
1233         }
1234 }
1235
1236 static void cardhu_modem_init(void)
1237 {
1238         struct board_info board_info;
1239         int w_disable_gpio, ret;
1240
1241         tegra_get_board_info(&board_info);
1242         switch (board_info.board_id) {
1243         case BOARD_E1291:
1244         case BOARD_E1198:
1245                 if (((board_info.board_id == BOARD_E1291) &&
1246                                 (board_info.fab < BOARD_FAB_A03)) ||
1247                         ((board_info.board_id == BOARD_E1198) &&
1248                                         (board_info.fab < BOARD_FAB_A02))) {
1249                         w_disable_gpio = TEGRA_GPIO_PH5;
1250                 } else {
1251                         w_disable_gpio = TEGRA_GPIO_PDD5;
1252                 }
1253
1254                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1255                 if (ret < 0)
1256                         pr_err("%s: gpio_request failed for gpio %d\n",
1257                                 __func__, w_disable_gpio);
1258                 else
1259                         gpio_direction_input(w_disable_gpio);
1260
1261                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1262                 if (((board_info.board_id == BOARD_E1291) &&
1263                                 (board_info.fab >= BOARD_FAB_A04)) ||
1264                         ((board_info.board_id == BOARD_E1198) &&
1265                                         (board_info.fab >= BOARD_FAB_A02))) {
1266                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1267                         if (ret < 0) {
1268                                 pr_err("%s(): Error in allocating gpio "
1269                                         "TEGRA_GPIO_PH7\n", __func__);
1270                                 break;
1271                         }
1272                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1273                 }
1274                 break;
1275         case BOARD_E1186:
1276                 platform_device_register(&tegra_baseband_power_device);
1277                 platform_device_register(&tegra_baseband_power2_device);
1278                 break;
1279         default:
1280                 break;
1281         }
1282
1283 }
1284
1285 #ifdef CONFIG_SATA_AHCI_TEGRA
1286 static void cardhu_sata_init(void)
1287 {
1288         platform_device_register(&tegra_sata_device);
1289 }
1290 #else
1291 static void cardhu_sata_init(void) { }
1292 #endif
1293
1294 static void __init tegra_cardhu_init(void)
1295 {
1296         tegra_thermal_init(&thermal_data);
1297         tegra_clk_init_from_table(cardhu_clk_init_table);
1298         tegra_enable_pinmux();
1299         cardhu_pinmux_init();
1300         cardhu_i2c_init();
1301         cardhu_spi_init();
1302         cardhu_usb_init();
1303 #ifdef CONFIG_TEGRA_EDP_LIMITS
1304         cardhu_edp_init();
1305 #endif
1306         cardhu_uart_init();
1307         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1308         tegra_ram_console_debug_init();
1309         cardhu_sdhci_init();
1310         cardhu_regulator_init();
1311         cardhu_dtv_init();
1312         cardhu_suspend_init();
1313         cardhu_touch_init();
1314         cardhu_modem_init();
1315         cardhu_kbc_init();
1316         cardhu_scroll_init();
1317         cardhu_keys_init();
1318         cardhu_panel_init();
1319         cardhu_pmon_init();
1320         cardhu_sensors_init();
1321         cardhu_setup_bluesleep();
1322         cardhu_sata_init();
1323         //audio_wired_jack_init();
1324         cardhu_pins_state_init();
1325         cardhu_emc_init();
1326         tegra_release_bootloader_fb();
1327         cardhu_pci_init();
1328 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1329         tegra_wdt_recovery_init();
1330 #endif
1331 }
1332
1333 static void __init tegra_cardhu_reserve(void)
1334 {
1335 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1336         /* support 1920X1200 with 24bpp */
1337         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1338 #else
1339         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1340 #endif
1341         tegra_ram_console_debug_reserve(SZ_1M);
1342 }
1343
1344 MACHINE_START(CARDHU, "cardhu")
1345         .atag_offset    = 0x100,
1346         .map_io         = tegra_map_common_io,
1347         .reserve        = tegra_cardhu_reserve,
1348         .init_early     = tegra30_init_early,
1349         .init_irq       = tegra_init_irq,
1350         .handle_irq     = gic_handle_irq,
1351         .timer          = &tegra_timer,
1352         .init_machine   = tegra_cardhu_init,
1353         .restart        = tegra_assert_system_reset,
1354 MACHINE_END