arm: tegra: cardhu: Use fixed regulator
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <media/tegra_dtv.h>
45
46 #include <mach/clk.h>
47 #include <mach/iomap.h>
48 #include <mach/irqs.h>
49 #include <mach/pinmux.h>
50 #include <mach/iomap.h>
51 #include <mach/io.h>
52 #include <mach/i2s.h>
53 #include <mach/tegra_wm8903_pdata.h>
54 #include <asm/mach-types.h>
55 #include <asm/mach/arch.h>
56 #include <mach/usb_phy.h>
57 #include <mach/thermal.h>
58 #include <mach/pci.h>
59
60 #include "board.h"
61 #include "clock.h"
62 #include "board-cardhu.h"
63 #include "devices.h"
64 #include "gpio-names.h"
65 #include "fuse.h"
66 #include "pm.h"
67 #include "baseband-xmm-power.h"
68 #include "wdt-recovery.h"
69
70 /* All units are in millicelsius */
71 static struct tegra_thermal_data thermal_data = {
72         .temp_throttle = 85000,
73         .temp_shutdown = 90000,
74         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
75 #ifdef CONFIG_TEGRA_EDP_LIMITS
76         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
77         .hysteresis_edp = 3000,
78 #endif
79 #ifdef CONFIG_TEGRA_THERMAL_SYSFS
80         .tc1 = 0,
81         .tc2 = 1,
82         .passive_delay = 2000,
83 #else
84         .hysteresis_throttle = 1000,
85 #endif
86 };
87
88 /* !!!TODO: Change for cardhu (Taken from Ventana) */
89 static struct tegra_utmip_config utmi_phy_config[] = {
90         [0] = {
91                         .hssync_start_delay = 0,
92                         .idle_wait_delay = 17,
93                         .elastic_limit = 16,
94                         .term_range_adj = 6,
95                         .xcvr_setup = 15,
96                         .xcvr_setup_offset = 0,
97                         .xcvr_use_fuses = 1,
98                         .xcvr_lsfslew = 2,
99                         .xcvr_lsrslew = 2,
100         },
101         [1] = {
102                         .hssync_start_delay = 0,
103                         .idle_wait_delay = 17,
104                         .elastic_limit = 16,
105                         .term_range_adj = 6,
106                         .xcvr_setup = 15,
107                         .xcvr_setup_offset = 0,
108                         .xcvr_use_fuses = 1,
109                         .xcvr_lsfslew = 2,
110                         .xcvr_lsrslew = 2,
111         },
112         [2] = {
113                         .hssync_start_delay = 0,
114                         .idle_wait_delay = 17,
115                         .elastic_limit = 16,
116                         .term_range_adj = 6,
117                         .xcvr_setup = 8,
118                         .xcvr_setup_offset = 0,
119                         .xcvr_use_fuses = 1,
120                         .xcvr_lsfslew = 2,
121                         .xcvr_lsrslew = 2,
122         },
123 };
124
125 static struct resource cardhu_bcm4329_rfkill_resources[] = {
126         {
127                 .name   = "bcm4329_nshutdown_gpio",
128                 .start  = TEGRA_GPIO_PU0,
129                 .end    = TEGRA_GPIO_PU0,
130                 .flags  = IORESOURCE_IO,
131         },
132 };
133
134 static struct platform_device cardhu_bcm4329_rfkill_device = {
135         .name = "bcm4329_rfkill",
136         .id             = -1,
137         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
138         .resource       = cardhu_bcm4329_rfkill_resources,
139 };
140
141 static struct resource cardhu_bluesleep_resources[] = {
142         [0] = {
143                 .name = "gpio_host_wake",
144                         .start  = TEGRA_GPIO_PU6,
145                         .end    = TEGRA_GPIO_PU6,
146                         .flags  = IORESOURCE_IO,
147         },
148         [1] = {
149                 .name = "gpio_ext_wake",
150                         .start  = TEGRA_GPIO_PU1,
151                         .end    = TEGRA_GPIO_PU1,
152                         .flags  = IORESOURCE_IO,
153         },
154         [2] = {
155                 .name = "host_wake",
156                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
157                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
158                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
159         },
160 };
161
162 static struct platform_device cardhu_bluesleep_device = {
163         .name           = "bluesleep",
164         .id             = -1,
165         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
166         .resource       = cardhu_bluesleep_resources,
167 };
168
169 static noinline void __init cardhu_setup_bluesleep(void)
170 {
171         platform_device_register(&cardhu_bluesleep_device);
172         tegra_gpio_enable(TEGRA_GPIO_PU6);
173         tegra_gpio_enable(TEGRA_GPIO_PU1);
174         return;
175 }
176
177 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
178         /* name         parent          rate            enabled */
179         { "pll_m",      NULL,           0,              false},
180         { "hda",        "pll_p",        108000000,      false},
181         { "hda2codec_2x","pll_p",       48000000,       false},
182         { "pwm",        "pll_p",        3187500,        false},
183         { "blink",      "clk_32k",      32768,          true},
184         { "i2s1",       "pll_a_out0",   0,              false},
185         { "i2s3",       "pll_a_out0",   0,              false},
186         { "spdif_out",  "pll_a_out0",   0,              false},
187         { "d_audio",    "pll_a_out0",   0,              false},
188         { "dam0",       "pll_a_out0",   0,              false},
189         { "dam1",       "pll_a_out0",   0,              false},
190         { "dam2",       "pll_a_out0",   0,              false},
191         { "audio1",     "i2s1_sync",    0,              false},
192         { "audio3",     "i2s3_sync",    0,              false},
193         { "vi_sensor",  "pll_p",        150000000,      false},
194         { "i2c1",       "pll_p",        3200000,        false},
195         { "i2c2",       "pll_p",        3200000,        false},
196         { "i2c3",       "pll_p",        3200000,        false},
197         { "i2c4",       "pll_p",        3200000,        false},
198         { "i2c5",       "pll_p",        3200000,        false},
199         { NULL,         NULL,           0,              0},
200 };
201
202 static struct pn544_i2c_platform_data nfc_pdata = {
203         .irq_gpio = TEGRA_GPIO_PX0,
204         .ven_gpio = TEGRA_GPIO_PP3,
205         .firm_gpio = TEGRA_GPIO_PO7,
206         };
207
208 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
209         {
210                 I2C_BOARD_INFO("pn544", 0x28),
211                 .platform_data = &nfc_pdata,
212                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
213         },
214 };
215 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
216         .adapter_nr     = 0,
217         .bus_count      = 1,
218         .bus_clk_rate   = { 100000, 0 },
219         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
220         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
221         .arb_recovery = arb_lost_recovery,
222 };
223
224 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
225         .adapter_nr     = 1,
226         .bus_count      = 1,
227         .bus_clk_rate   = { 100000, 0 },
228         .is_clkon_always = true,
229         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
230         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
231         .arb_recovery = arb_lost_recovery,
232 };
233
234 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
235         .adapter_nr     = 2,
236         .bus_count      = 1,
237         .bus_clk_rate   = { 100000, 0 },
238         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
239         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
240         .arb_recovery = arb_lost_recovery,
241 };
242
243 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
244         .adapter_nr     = 3,
245         .bus_count      = 1,
246         .bus_clk_rate   = { 100000, 0 },
247         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
248         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
249         .arb_recovery = arb_lost_recovery,
250 };
251
252 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
253         .adapter_nr     = 4,
254         .bus_count      = 1,
255         .bus_clk_rate   = { 400000, 0 },
256         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
257         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
258         .arb_recovery = arb_lost_recovery,
259 };
260
261
262 #if 0
263 struct tegra_wired_jack_conf audio_wr_jack_conf = {
264         .hp_det_n = TEGRA_GPIO_PW2,
265         .en_mic_ext = TEGRA_GPIO_PX1,
266         .en_mic_int = TEGRA_GPIO_PX0,
267 };
268 #endif
269
270 static struct wm8903_platform_data cardhu_wm8903_pdata = {
271         .irq_active_low = 0,
272         .micdet_cfg = 0,
273         .micdet_delay = 100,
274         .gpio_base = CARDHU_GPIO_WM8903(0),
275         .gpio_cfg = {
276                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
277                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
278                         WM8903_GP2_DIR,
279                 0,
280                 WM8903_GPIO_NO_CONFIG,
281                 WM8903_GPIO_NO_CONFIG,
282         },
283 };
284
285 static struct i2c_board_info __initdata wm8903_board_info = {
286         I2C_BOARD_INFO("wm8903", 0x1a),
287         .platform_data = &cardhu_wm8903_pdata,
288         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
289 };
290
291 static void cardhu_i2c_init(void)
292 {
293         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
294         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
295         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
296         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
297         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
298
299         platform_device_register(&tegra_i2c_device5);
300         platform_device_register(&tegra_i2c_device4);
301         platform_device_register(&tegra_i2c_device3);
302         platform_device_register(&tegra_i2c_device2);
303         platform_device_register(&tegra_i2c_device1);
304
305         i2c_register_board_info(4, &wm8903_board_info, 1);
306         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
307 }
308
309 static struct platform_device *cardhu_uart_devices[] __initdata = {
310         &tegra_uarta_device,
311         &tegra_uartb_device,
312         &tegra_uartc_device,
313         &tegra_uartd_device,
314         &tegra_uarte_device,
315 };
316 static struct uart_clk_parent uart_parent_clk[] = {
317         [0] = {.name = "clk_m"},
318         [1] = {.name = "pll_p"},
319 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
320         [2] = {.name = "pll_m"},
321 #endif
322 };
323
324 static struct tegra_uart_platform_data cardhu_uart_pdata;
325 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
326
327 static void __init uart_debug_init(void)
328 {
329         struct board_info board_info;
330         int debug_port_id;
331
332         tegra_get_board_info(&board_info);
333
334         debug_port_id = get_tegra_uart_debug_port_id();
335         if (debug_port_id < 0) {
336                 debug_port_id = 0;
337                         /* UARTB is debug port
338                          *       for SLT - E1186/E1187/PM269
339                          *       for E1256/E1257
340                          */
341                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
342                         ((board_info.board_id == BOARD_E1186) ||
343                         (board_info.board_id == BOARD_E1187) ||
344                         (board_info.board_id == BOARD_PM269))) ||
345                         (board_info.board_id == BOARD_E1256) ||
346                         (board_info.board_id == BOARD_E1257))
347                                 debug_port_id = 1;
348         }
349         switch (debug_port_id) {
350         case 0:
351                 /* UARTA is the debug port. */
352                 pr_info("Selecting UARTA as the debug console\n");
353                 cardhu_uart_devices[0] = &debug_uarta_device;
354                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
355                 debug_uart_port_base = ((struct plat_serial8250_port *)(
356                         debug_uarta_device.dev.platform_data))->mapbase;
357                 break;
358
359         case 1:
360                 /* UARTB is the debug port. */
361                 pr_info("Selecting UARTB as the debug console\n");
362                 cardhu_uart_devices[1] = &debug_uartb_device;
363                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
364                 debug_uart_port_base = ((struct plat_serial8250_port *)(
365                         debug_uartb_device.dev.platform_data))->mapbase;
366                 break;
367
368         case 2:
369                 /* UARTC is the debug port. */
370                 pr_info("Selecting UARTC as the debug console\n");
371                 cardhu_uart_devices[2] = &debug_uartc_device;
372                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
373                 debug_uart_port_base = ((struct plat_serial8250_port *)(
374                         debug_uartc_device.dev.platform_data))->mapbase;
375                 break;
376
377         case 3:
378                 /* UARTD is the debug port. */
379                 pr_info("Selecting UARTD as the debug console\n");
380                 cardhu_uart_devices[3] = &debug_uartd_device;
381                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
382                 debug_uart_port_base = ((struct plat_serial8250_port *)(
383                         debug_uartd_device.dev.platform_data))->mapbase;
384                 break;
385
386         case 4:
387                 /* UARTE is the debug port. */
388                 pr_info("Selecting UARTE as the debug console\n");
389                 cardhu_uart_devices[4] = &debug_uarte_device;
390                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
391                 debug_uart_port_base = ((struct plat_serial8250_port *)(
392                         debug_uarte_device.dev.platform_data))->mapbase;
393                 break;
394
395         default:
396                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
397                 cardhu_uart_devices[0] = &debug_uarta_device;
398                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
399                 debug_uart_port_base = ((struct plat_serial8250_port *)(
400                         debug_uarta_device.dev.platform_data))->mapbase;
401                 break;
402         }
403         return;
404 }
405
406 static void __init cardhu_uart_init(void)
407 {
408         struct clk *c;
409         int i;
410
411         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
412                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
413                 if (IS_ERR_OR_NULL(c)) {
414                         pr_err("Not able to get the clock for %s\n",
415                                                 uart_parent_clk[i].name);
416                         continue;
417                 }
418                 uart_parent_clk[i].parent_clk = c;
419                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
420         }
421         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
422         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
423         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
424         cardhu_loopback_uart_pdata.parent_clk_count =
425                                                 ARRAY_SIZE(uart_parent_clk);
426         cardhu_loopback_uart_pdata.is_loopback = true;
427         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
428         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
429         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
430         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
431         /* UARTE is used for loopback test purpose */
432         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
433
434         /* Register low speed only if it is selected */
435         if (!is_tegra_debug_uartport_hs()) {
436                 uart_debug_init();
437                 /* Clock enable for the debug channel */
438                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
439                         pr_info("The debug console clock name is %s\n",
440                                                 debug_uart_clk->name);
441                         c = tegra_get_clock_by_name("pll_p");
442                         if (IS_ERR_OR_NULL(c))
443                                 pr_err("Not getting the parent clock pll_p\n");
444                         else
445                                 clk_set_parent(debug_uart_clk, c);
446
447                         clk_enable(debug_uart_clk);
448                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
449                 } else {
450                         pr_err("Not getting the clock %s for debug console\n",
451                                         debug_uart_clk->name);
452                 }
453         }
454
455         platform_add_devices(cardhu_uart_devices,
456                                 ARRAY_SIZE(cardhu_uart_devices));
457 }
458
459 static struct platform_device tegra_camera = {
460         .name = "tegra_camera",
461         .id = -1,
462 };
463
464 static struct platform_device *cardhu_spi_devices[] __initdata = {
465         &tegra_spi_device4,
466 };
467
468 struct spi_clk_parent spi_parent_clk[] = {
469         [0] = {.name = "pll_p"},
470 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
471         [1] = {.name = "pll_m"},
472         [2] = {.name = "clk_m"},
473 #else
474         [1] = {.name = "clk_m"},
475 #endif
476 };
477
478 static struct tegra_spi_platform_data cardhu_spi_pdata = {
479         .is_dma_based           = true,
480         .max_dma_buffer         = (16 * 1024),
481         .is_clkon_always        = false,
482         .max_rate               = 100000000,
483 };
484
485 static void __init cardhu_spi_init(void)
486 {
487         int i;
488         struct clk *c;
489         struct board_info board_info;
490
491         tegra_get_board_info(&board_info);
492
493         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
494                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
495                 if (IS_ERR_OR_NULL(c)) {
496                         pr_err("Not able to get the clock for %s\n",
497                                                 spi_parent_clk[i].name);
498                         continue;
499                 }
500                 spi_parent_clk[i].parent_clk = c;
501                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
502         }
503         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
504         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
505         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
506         platform_add_devices(cardhu_spi_devices,
507                                 ARRAY_SIZE(cardhu_spi_devices));
508
509         if (board_info.board_id == BOARD_E1198) {
510                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
511                 platform_device_register(&tegra_spi_device2);
512                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
513                 platform_device_register(&tegra_spi_slave_device1);
514         }
515 }
516
517 static void __init cardhu_dtv_init(void)
518 {
519         struct board_info board_info;
520
521         tegra_get_board_info(&board_info);
522
523         if (board_info.board_id == BOARD_E1186)
524                 platform_device_register(&tegra_dtv_device);
525 }
526
527 static struct resource tegra_rtc_resources[] = {
528         [0] = {
529                 .start = TEGRA_RTC_BASE,
530                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
531                 .flags = IORESOURCE_MEM,
532         },
533         [1] = {
534                 .start = INT_RTC,
535                 .end = INT_RTC,
536                 .flags = IORESOURCE_IRQ,
537         },
538 };
539
540 static struct platform_device tegra_rtc_device = {
541         .name = "tegra_rtc",
542         .id   = -1,
543         .resource = tegra_rtc_resources,
544         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
545 };
546
547 static struct tegra_wm8903_platform_data cardhu_audio_pdata = {
548         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
549         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
550         .gpio_hp_mute           = -1,
551         .gpio_int_mic_en        = -1,
552         .gpio_ext_mic_en        = -1,
553 };
554
555 static struct platform_device cardhu_audio_device = {
556         .name   = "tegra-snd-wm8903",
557         .id     = 0,
558         .dev    = {
559                 .platform_data  = &cardhu_audio_pdata,
560         },
561 };
562
563 static struct platform_device *cardhu_devices[] __initdata = {
564         &tegra_pmu_device,
565         &tegra_rtc_device,
566         &tegra_udc_device,
567 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
568         &tegra_smmu_device,
569 #endif
570         &tegra_wdt_device,
571 #if defined(CONFIG_TEGRA_AVP)
572         &tegra_avp_device,
573 #endif
574         &tegra_camera,
575 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
576         &tegra_se_device,
577 #endif
578         &tegra_ahub_device,
579         &tegra_dam_device0,
580         &tegra_dam_device1,
581         &tegra_dam_device2,
582         &tegra_i2s_device1,
583         &tegra_i2s_device3,
584         &tegra_spdif_device,
585         &spdif_dit_device,
586         &bluetooth_dit_device,
587         &cardhu_bcm4329_rfkill_device,
588         &tegra_pcm_device,
589         &cardhu_audio_device,
590         &tegra_hda_device,
591 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
592         &tegra_aes_device,
593 #endif
594 };
595
596 #define MXT_CONFIG_CRC  0xD62DE8
597 static const u8 config[] = {
598         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
599         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
600         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
601         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
602         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
603         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
604         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
605         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
606         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
607         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
608         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
609         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
610         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
611         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
612         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
613         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
614         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
615         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
616         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
617         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
618 };
619
620 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
621 static const u8 config_sku2000[] = {
622         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
623         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
624         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
625         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
626         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
627         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
628         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
629         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
631         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
632         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
633         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
634         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
635         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
636         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
637         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
638         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
639         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
640         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
641         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
642 };
643
644 static struct mxt_platform_data atmel_mxt_info = {
645         .x_line         = 27,
646         .y_line         = 42,
647         .x_size         = 768,
648         .y_size         = 1366,
649         .blen           = 0x20,
650         .threshold      = 0x3C,
651         .voltage        = 3300000,              /* 3.3V */
652         .orient         = 5,
653         .config         = config,
654         .config_length  = 157,
655         .config_crc     = MXT_CONFIG_CRC,
656         .irqflags       = IRQF_TRIGGER_FALLING,
657 /*      .read_chg       = &read_chg, */
658         .read_chg       = NULL,
659 };
660
661 static struct i2c_board_info __initdata atmel_i2c_info[] = {
662         {
663                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
664                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
665                 .platform_data = &atmel_mxt_info,
666         }
667 };
668
669 static int __init cardhu_touch_init(void)
670 {
671         struct board_info BoardInfo;
672
673         tegra_gpio_enable(TEGRA_GPIO_PH4);
674         tegra_gpio_enable(TEGRA_GPIO_PH6);
675
676         gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
677         gpio_direction_input(TEGRA_GPIO_PH4);
678
679         gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
680         gpio_direction_output(TEGRA_GPIO_PH6, 0);
681         msleep(1);
682         gpio_set_value(TEGRA_GPIO_PH6, 1);
683         msleep(100);
684
685         tegra_get_board_info(&BoardInfo);
686         if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
687                 atmel_mxt_info.config = config_sku2000;
688                 atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
689         }
690
691         i2c_register_board_info(1, atmel_i2c_info, 1);
692
693         return 0;
694 }
695
696 static struct tegra_uhsic_config uhsic_phy_config = {
697         .enable_gpio = EN_HSIC_GPIO,
698         .reset_gpio = -1,
699         .sync_start_delay = 9,
700         .idle_wait_delay = 17,
701         .term_range_adj = 0,
702         .elastic_underrun_limit = 16,
703         .elastic_overrun_limit = 16,
704 };
705
706 static struct tegra_ehci_platform_data tegra_ehci_uhsic_pdata = {
707         .phy_type = TEGRA_USB_PHY_TYPE_HSIC,
708         .phy_config = &uhsic_phy_config,
709         .operating_mode = TEGRA_USB_HOST,
710         .power_down_on_bus_suspend = 1,
711         .default_enable = true,
712 };
713
714 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
715         [0] = {
716                         .phy_config = &utmi_phy_config[0],
717                         .operating_mode = TEGRA_USB_HOST,
718                         .power_down_on_bus_suspend = 1,
719                         .default_enable = true,
720         },
721         [1] = {
722                         .phy_config = &utmi_phy_config[1],
723                         .operating_mode = TEGRA_USB_HOST,
724                         .power_down_on_bus_suspend = 1,
725                         .default_enable = true,
726         },
727         [2] = {
728                         .phy_config = &utmi_phy_config[2],
729                         .operating_mode = TEGRA_USB_HOST,
730                         .power_down_on_bus_suspend = 1,
731                         .hotplug = 1,
732                         .default_enable = true,
733         },
734 };
735
736 static struct tegra_otg_platform_data tegra_otg_pdata = {
737         .ehci_device = &tegra_ehci1_device,
738         .ehci_pdata = &tegra_ehci_pdata[0],
739 };
740
741 #ifdef CONFIG_USB_SUPPORT
742 static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
743         [0] = {
744                         .instance = 0,
745                         .vbus_gpio = -1,
746                         .vbus_reg_supply = "vdd_vbus_micro_usb",
747         },
748         [1] = {
749                         .instance = 1,
750                         .vbus_gpio = -1,
751         },
752         [2] = {
753                         .instance = 2,
754                         .vbus_gpio = -1,
755                         .vbus_reg_supply = "vdd_vbus_typea_usb",
756         },
757 };
758
759 static int cardhu_usb_hsic_postsupend(void)
760 {
761 #ifdef CONFIG_TEGRA_BB_XMM_POWER
762         baseband_xmm_set_power_status(BBXMM_PS_L2);
763 #endif
764         return 0;
765 }
766
767 static int cardhu_usb_hsic_preresume(void)
768 {
769 #ifdef CONFIG_TEGRA_BB_XMM_POWER
770         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
771 #endif
772         return 0;
773 }
774
775 static int cardhu_usb_hsic_phy_ready(void)
776 {
777 #ifdef CONFIG_TEGRA_BB_XMM_POWER
778         baseband_xmm_set_power_status(BBXMM_PS_L0);
779 #endif
780         return 0;
781 }
782
783 static int cardhu_usb_hsic_phy_off(void)
784 {
785 #ifdef CONFIG_TEGRA_BB_XMM_POWER
786         baseband_xmm_set_power_status(BBXMM_PS_L3);
787 #endif
788         return 0;
789 }
790
791 static void cardhu_usb_init(void)
792 {
793         struct board_info bi;
794
795         tegra_get_board_info(&bi);
796
797         tegra_usb_phy_init(tegra_usb_phy_pdata,
798                         ARRAY_SIZE(tegra_usb_phy_pdata));
799
800         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
801         platform_device_register(&tegra_otg_device);
802         if (bi.board_id == BOARD_PM267) {
803                 uhsic_phy_config.reset_gpio =
804                         PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
805                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
806                 platform_device_register(&tegra_ehci2_device);
807         } else if (bi.board_id == BOARD_E1256) {
808                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
809                 platform_device_register(&tegra_ehci2_device);
810         } else if (bi.board_id == BOARD_E1186) {
811                 /* for baseband devices do not switch off phy during suspend */
812                 tegra_ehci_uhsic_pdata.power_down_on_bus_suspend = 0;
813                 uhsic_phy_config.postsuspend = cardhu_usb_hsic_postsupend;
814                 uhsic_phy_config.preresume = cardhu_usb_hsic_preresume;
815                 uhsic_phy_config.usb_phy_ready = cardhu_usb_hsic_phy_ready;
816                 uhsic_phy_config.post_phy_off = cardhu_usb_hsic_phy_off;
817                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_uhsic_pdata;
818                 /* baseband registration happens in baseband-xmm-power  */
819         } else {
820                 tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
821                 platform_device_register(&tegra_ehci2_device);
822         }
823
824         tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
825         platform_device_register(&tegra_ehci3_device);
826
827 }
828 #else
829 static void cardhu_usb_init(void) { }
830 #endif
831
832 static void cardhu_gps_init(void)
833 {
834         tegra_gpio_enable(TEGRA_GPIO_PU2);
835         tegra_gpio_enable(TEGRA_GPIO_PU3);
836 }
837
838 static void cardhu_nfc_init(void)
839 {
840         tegra_gpio_enable(TEGRA_GPIO_PX0);
841         tegra_gpio_enable(TEGRA_GPIO_PP3);
842         tegra_gpio_enable(TEGRA_GPIO_PO7);
843 }
844
845 static struct baseband_power_platform_data tegra_baseband_power_data = {
846         .baseband_type = BASEBAND_XMM,
847         .modem = {
848         .xmm = {
849                         .bb_rst = XMM_GPIO_BB_RST,
850                         .bb_on = XMM_GPIO_BB_ON,
851                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
852                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
853                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
854                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
855                         .hsic_device = &tegra_ehci2_device,
856                 },
857         },
858 };
859
860 static struct platform_device tegra_baseband_power_device = {
861         .name = "baseband_xmm_power",
862         .id = -1,
863         .dev = {
864                 .platform_data = &tegra_baseband_power_data,
865         },
866 };
867
868 static struct platform_device tegra_baseband_power2_device = {
869         .name = "baseband_xmm_power2",
870         .id = -1,
871         .dev = {
872                 .platform_data = &tegra_baseband_power_data,
873         },
874 };
875
876
877 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
878         .port_status[0] = 1,
879         .port_status[1] = 1,
880         .port_status[2] = 1,
881         .use_dock_detect        = 0,
882         .gpio           = 0,
883 };
884
885 static void cardhu_pci_init(void)
886 {
887         struct board_info board_info;
888
889         tegra_get_board_info(&board_info);
890         if (board_info.board_id == BOARD_E1291) {
891                 cardhu_pci_platform_data.port_status[0] = 0;
892                 cardhu_pci_platform_data.port_status[1] = 0;
893                 cardhu_pci_platform_data.port_status[2] = 1;
894                 cardhu_pci_platform_data.use_dock_detect = 1;
895                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
896         }
897         tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
898         platform_device_register(&tegra_pci_device);
899 }
900
901 static void cardhu_modem_init(void)
902 {
903         struct board_info board_info;
904         int w_disable_gpio, ret;
905
906         tegra_get_board_info(&board_info);
907         switch (board_info.board_id) {
908         case BOARD_E1291:
909         case BOARD_E1198:
910                 if (((board_info.board_id == BOARD_E1291) &&
911                                 (board_info.fab < BOARD_FAB_A03)) ||
912                         ((board_info.board_id == BOARD_E1198) &&
913                                         (board_info.fab < BOARD_FAB_A02))) {
914                         w_disable_gpio = TEGRA_GPIO_PH5;
915                 } else {
916                         w_disable_gpio = TEGRA_GPIO_PDD5;
917                 }
918                 tegra_gpio_enable(w_disable_gpio);
919                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
920                 if (ret < 0)
921                         pr_err("%s: gpio_request failed for gpio %d\n",
922                                 __func__, w_disable_gpio);
923                 else
924                         gpio_direction_input(w_disable_gpio);
925
926                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
927                 if (((board_info.board_id == BOARD_E1291) &&
928                                 (board_info.fab >= BOARD_FAB_A04)) ||
929                         ((board_info.board_id == BOARD_E1198) &&
930                                         (board_info.fab >= BOARD_FAB_A02))) {
931                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
932                         if (ret < 0) {
933                                 pr_err("%s(): Error in allocating gpio "
934                                         "TEGRA_GPIO_PH7\n", __func__);
935                                 break;
936                         }
937                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
938                         tegra_gpio_enable(TEGRA_GPIO_PH7);
939                 }
940                 break;
941         case BOARD_E1186:
942                 tegra_gpio_enable(
943                         tegra_baseband_power_data.modem.xmm.bb_rst);
944                 tegra_gpio_enable(
945                         tegra_baseband_power_data.modem.xmm.bb_on);
946                 tegra_gpio_enable(
947                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
948                 tegra_gpio_enable(
949                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
950                 tegra_gpio_enable(
951                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
952                 tegra_gpio_enable(
953                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
954                 platform_device_register(&tegra_baseband_power_device);
955                 platform_device_register(&tegra_baseband_power2_device);
956                 break;
957         default:
958                 break;
959         }
960
961 }
962
963 #ifdef CONFIG_SATA_AHCI_TEGRA
964 static void cardhu_sata_init(void)
965 {
966         platform_device_register(&tegra_sata_device);
967 }
968 #else
969 static void cardhu_sata_init(void) { }
970 #endif
971
972 static void __init tegra_cardhu_init(void)
973 {
974         tegra_thermal_init(&thermal_data);
975         tegra_clk_init_from_table(cardhu_clk_init_table);
976         cardhu_pinmux_init();
977         cardhu_i2c_init();
978         cardhu_spi_init();
979         cardhu_usb_init();
980 #ifdef CONFIG_TEGRA_EDP_LIMITS
981         cardhu_edp_init();
982 #endif
983         cardhu_uart_init();
984         cardhu_tsensor_init();
985         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
986         tegra_ram_console_debug_init();
987         cardhu_sdhci_init();
988         cardhu_regulator_init();
989         cardhu_dtv_init();
990         cardhu_suspend_init();
991         cardhu_power_off_init();
992         cardhu_touch_init();
993         cardhu_gps_init();
994         cardhu_modem_init();
995         cardhu_kbc_init();
996         cardhu_scroll_init();
997         cardhu_keys_init();
998         cardhu_panel_init();
999         cardhu_pmon_init();
1000         cardhu_sensors_init();
1001         cardhu_setup_bluesleep();
1002         cardhu_sata_init();
1003         //audio_wired_jack_init();
1004         cardhu_pins_state_init();
1005         cardhu_emc_init();
1006         tegra_release_bootloader_fb();
1007         cardhu_nfc_init();
1008         cardhu_pci_init();
1009 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1010         tegra_wdt_recovery_init();
1011 #endif
1012 }
1013
1014 static void __init cardhu_ramconsole_reserve(unsigned long size)
1015 {
1016         struct resource *res;
1017         long ret;
1018
1019         tegra_ram_console_debug_reserve(SZ_1M);
1020 }
1021
1022 static void __init tegra_cardhu_reserve(void)
1023 {
1024 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1025         /* support 1920X1200 with 24bpp */
1026         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1027 #else
1028         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1029 #endif
1030         cardhu_ramconsole_reserve(SZ_1M);
1031 }
1032
1033 MACHINE_START(CARDHU, "cardhu")
1034         .boot_params    = 0x80000100,
1035         .map_io         = tegra_map_common_io,
1036         .reserve        = tegra_cardhu_reserve,
1037         .init_early     = tegra_init_early,
1038         .init_irq       = tegra_init_irq,
1039         .timer          = &tegra_timer,
1040         .init_machine   = tegra_cardhu_init,
1041 MACHINE_END