arm: tegra: cardhu: additions to cardhu board file
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA Corporation.  All rights reserved.
5  * Copyright (c) 2011-2013, NVIDIA Corporation.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/serial_8250.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/panjit_ts.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/gpio.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/spi/spi.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44
45 #include <sound/wm8903.h>
46 #include <sound/max98095.h>
47 #include <media/tegra_dtv.h>
48 #include <media/tegra_camera.h>
49
50 #include <mach/clk.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/iomap.h>
55 #include <mach/io_dpd.h>
56 #include <mach/io.h>
57 #include <mach/i2s.h>
58 #include <mach/tegra_asoc_pdata.h>
59 #include <mach/tegra_rt5640_pdata.h>
60 #include <mach/tegra_wm8903_pdata.h>
61 #include <asm/mach-types.h>
62 #include <asm/mach/arch.h>
63 #include <mach/usb_phy.h>
64 #include <mach/thermal.h>
65 #include <mach/pci.h>
66 #include <mach/tegra_fiq_debugger.h>
67
68 #include "board.h"
69 #include "clock.h"
70 #include "board-cardhu.h"
71 #include "board-touch.h"
72 #include "devices.h"
73 #include "gpio-names.h"
74 #include "fuse.h"
75 #include "pm.h"
76 #include "baseband-xmm-power.h"
77 #include "wdt-recovery.h"
78
79 static struct balanced_throttle throttle_list[] = {
80 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
81         {
82                 .id = BALANCED_THROTTLE_ID_TJ,
83                 .throt_tab_size = 10,
84                 .throt_tab = {
85                         {      0, 1000 },
86                         { 640000, 1000 },
87                         { 640000, 1000 },
88                         { 640000, 1000 },
89                         { 640000, 1000 },
90                         { 640000, 1000 },
91                         { 760000, 1000 },
92                         { 760000, 1050 },
93                         {1000000, 1050 },
94                         {1000000, 1100 },
95                 },
96         },
97 #endif
98 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
99         {
100                 .id = BALANCED_THROTTLE_ID_SKIN,
101                 .throt_tab_size = 6,
102                 .throt_tab = {
103                         { 640000, 1200 },
104                         { 640000, 1200 },
105                         { 760000, 1200 },
106                         { 760000, 1200 },
107                         {1000000, 1200 },
108                         {1000000, 1200 },
109                 },
110         },
111 #endif
112 };
113
114 /* All units are in millicelsius */
115 static struct tegra_thermal_data thermal_data = {
116         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
117         .temp_shutdown = 90000,
118
119 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
120         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
121 #endif
122 #ifdef CONFIG_TEGRA_EDP_LIMITS
123         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
124         .hysteresis_edp = 3000,
125 #endif
126 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
127         .temp_throttle = 85000,
128         .tc1 = 0,
129         .tc2 = 1,
130         .passive_delay = 2000,
131 #endif
132 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
133         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
134         .temp_throttle_skin = 43000,
135         .tc1_skin = 0,
136         .tc2_skin = 1,
137         .passive_delay_skin = 5000,
138
139         .skin_temp_offset = 9793,
140         .skin_period = 1100,
141         .skin_devs_size = 2,
142         .skin_devs = {
143                 {
144                         THERMAL_DEVICE_ID_NCT_EXT,
145                         {
146                                 2, 1, 1, 1,
147                                 1, 1, 1, 1,
148                                 1, 1, 1, 0,
149                                 1, 1, 0, 0,
150                                 0, 0, -1, -7
151                         }
152                 },
153                 {
154                         THERMAL_DEVICE_ID_NCT_INT,
155                         {
156                                 -11, -7, -5, -3,
157                                 -3, -2, -1, 0,
158                                 0, 0, 1, 1,
159                                 1, 2, 2, 3,
160                                 4, 6, 11, 18
161                         }
162                 },
163         },
164 #endif
165 };
166
167 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
168         {
169                 .name           = "bt_rfkill",
170                 .shutdown_gpio  = TEGRA_GPIO_PU0,
171                 .reset_gpio     = TEGRA_GPIO_INVALID,
172                 .type           = RFKILL_TYPE_BLUETOOTH,
173         },
174 };
175
176 static struct platform_device cardhu_bt_rfkill_device = {
177         .name = "rfkill_gpio",
178         .id             = -1,
179         .dev = {
180                 .platform_data = &cardhu_bt_rfkill_pdata,
181         },
182 };
183
184 static struct resource cardhu_bluesleep_resources[] = {
185         [0] = {
186                 .name = "gpio_host_wake",
187                         .start  = TEGRA_GPIO_PU6,
188                         .end    = TEGRA_GPIO_PU6,
189                         .flags  = IORESOURCE_IO,
190         },
191         [1] = {
192                 .name = "gpio_ext_wake",
193                         .start  = TEGRA_GPIO_PU1,
194                         .end    = TEGRA_GPIO_PU1,
195                         .flags  = IORESOURCE_IO,
196         },
197         [2] = {
198                 .name = "host_wake",
199                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
200                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
201                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
202         },
203 };
204
205 static struct platform_device cardhu_bluesleep_device = {
206         .name           = "bluesleep",
207         .id             = -1,
208         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
209         .resource       = cardhu_bluesleep_resources,
210 };
211
212 static noinline void __init cardhu_setup_bluesleep(void)
213 {
214         platform_device_register(&cardhu_bluesleep_device);
215         return;
216 }
217
218 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
219         /* name         parent          rate            enabled */
220         { "pll_m",      NULL,           0,              false},
221         { "hda",        "pll_p",        108000000,      false},
222         { "hda2codec_2x","pll_p",       48000000,       false},
223         { "pwm",        "pll_p",        3187500,        false},
224         { "blink",      "clk_32k",      32768,          true},
225         { "i2s0",       "pll_a_out0",   0,              false},
226         { "i2s1",       "pll_a_out0",   0,              false},
227         { "i2s3",       "pll_a_out0",   0,              false},
228         { "spdif_out",  "pll_a_out0",   0,              false},
229         { "d_audio",    "clk_m",        12000000,       false},
230         { "dam0",       "clk_m",        12000000,       false},
231         { "dam1",       "clk_m",        12000000,       false},
232         { "dam2",       "clk_m",        12000000,       false},
233         { "audio1",     "i2s1_sync",    0,              false},
234         { "audio3",     "i2s3_sync",    0,              false},
235         { "vi_sensor",  "pll_p",        150000000,      false},
236         { "i2c1",       "pll_p",        3200000,        false},
237         { "i2c2",       "pll_p",        3200000,        false},
238         { "i2c3",       "pll_p",        3200000,        false},
239         { "i2c4",       "pll_p",        3200000,        false},
240         { "i2c5",       "pll_p",        3200000,        false},
241         { "vi",         "pll_p",        0,              false},
242         { NULL,         NULL,           0,              0},
243 };
244
245 static struct pn544_i2c_platform_data nfc_pdata = {
246         .irq_gpio = TEGRA_GPIO_PX0,
247         .ven_gpio = TEGRA_GPIO_PP3,
248         .firm_gpio = TEGRA_GPIO_PO7,
249         };
250
251 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
252         {
253                 I2C_BOARD_INFO("pn544", 0x28),
254                 .platform_data = &nfc_pdata,
255                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
256         },
257 };
258 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
259         .adapter_nr     = 0,
260         .bus_count      = 1,
261         .bus_clk_rate   = { 100000, 0 },
262         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
263         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
264         .arb_recovery = arb_lost_recovery,
265 };
266
267 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
268         .adapter_nr     = 1,
269         .bus_count      = 1,
270         .bus_clk_rate   = { 400000, 0 },
271         .is_clkon_always = true,
272         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
273         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
274         .arb_recovery = arb_lost_recovery,
275 };
276
277 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
278         .adapter_nr     = 2,
279         .bus_count      = 1,
280         .bus_clk_rate   = { 100000, 0 },
281         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
282         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
283         .arb_recovery = arb_lost_recovery,
284 };
285
286 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
287         .adapter_nr     = 3,
288         .bus_count      = 1,
289         .bus_clk_rate   = { 10000, 0 },
290         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
291         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
292         .arb_recovery = arb_lost_recovery,
293 };
294
295 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
296         .adapter_nr     = 4,
297         .bus_count      = 1,
298         .bus_clk_rate   = { 400000, 0 },
299         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
300         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
301         .arb_recovery = arb_lost_recovery,
302 };
303
304
305 #if 0
306 struct tegra_wired_jack_conf audio_wr_jack_conf = {
307         .hp_det_n = TEGRA_GPIO_PW2,
308         .en_mic_ext = TEGRA_GPIO_PX1,
309         .en_mic_int = TEGRA_GPIO_PX0,
310 };
311 #endif
312
313 static struct wm8903_platform_data cardhu_wm8903_pdata = {
314         .irq_active_low = 0,
315         .micdet_cfg = 0,
316         .micdet_delay = 100,
317         .gpio_base = CARDHU_GPIO_WM8903(0),
318         .gpio_cfg = {
319                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
320                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
321                         WM8903_GP2_DIR,
322                 0,
323                 WM8903_GPIO_NO_CONFIG,
324                 WM8903_GPIO_NO_CONFIG,
325         },
326 };
327
328 /* Equalizer filter coefs generated from the MAXIM MAX98095
329  * evkit software tool */
330 static struct max98095_eq_cfg max98095_eq_cfg[] = {
331         {
332                 .name = "FLAT",
333                 .rate = 44100,
334                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
335                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
336                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
337                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
338                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
339         },
340         {
341                 .name = "LOWPASS1K",
342                 .rate = 44100,
343                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
344                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
345                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
346                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
347                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
348         },
349         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
350                 .name = "HIBOOST",
351                 .rate = 44100,
352                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
353                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
354                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
355                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
356                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
357         },
358         { /* BASS=12dB, TREBLE=+12dB */
359                 .name = "LOUD12DB",
360                 .rate = 44100,
361                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
362                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
363                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
364                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
365                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
366         },
367         {
368                 .name = "FLAT",
369                 .rate = 16000,
370                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
371                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
372                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
373                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
374                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
375         },
376         {
377                 .name = "LOWPASS1K",
378                 .rate = 16000,
379                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
380                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
381                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
382                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
383                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
384         },
385         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
386                 .name = "HIBOOST",
387                 .rate = 16000,
388                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
389                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
390                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
391                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
392                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
393         },
394         { /* BASS=12dB, TREBLE=+12dB */
395                 .name = "LOUD12DB",
396                 .rate = 16000,
397                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
398                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
399                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
400                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
401                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
402         },
403 };
404
405 static struct max98095_pdata cardhu_max98095_pdata = {
406         /* equalizer configuration */
407         .eq_cfg = max98095_eq_cfg,
408         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
409
410         /* Biquad filter response configuration */
411         .bq_cfg = NULL,
412         .bq_cfgcnt = 0,
413
414         /* microphone configuration */
415         .digmic_left_mode = 1,
416         .digmic_right_mode = 1,
417 };
418
419 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
420         I2C_BOARD_INFO("wm8903", 0x1a),
421         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
422         .platform_data = &cardhu_wm8903_pdata,
423 };
424
425 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
426         I2C_BOARD_INFO("aic3262-codec", 0x18),
427         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
428 };
429
430 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
431         I2C_BOARD_INFO("max98095", 0x10),
432         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
433         .platform_data = &cardhu_max98095_pdata,
434 };
435
436 static struct i2c_board_info __initdata rt5640_board_info = {
437         I2C_BOARD_INFO("rt5640", 0x1c),
438 };
439
440
441 static void cardhu_i2c_init(void)
442 {
443         struct board_info board_info;
444
445         tegra_get_board_info(&board_info);
446         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
447         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
448         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
449         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
450         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
451
452         platform_device_register(&tegra_i2c_device5);
453         platform_device_register(&tegra_i2c_device4);
454         platform_device_register(&tegra_i2c_device3);
455         platform_device_register(&tegra_i2c_device2);
456         platform_device_register(&tegra_i2c_device1);
457
458         if (board_info.board_id == BOARD_PM315)
459                 i2c_register_board_info(4, &rt5640_board_info, 1);
460         else
461                 i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
462         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
463         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
464
465         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
466 }
467
468 static struct platform_device *cardhu_uart_devices[] __initdata = {
469         &tegra_uarta_device,
470         &tegra_uartb_device,
471         &tegra_uartc_device,
472         &tegra_uartd_device,
473         &tegra_uarte_device,
474 };
475 static struct uart_clk_parent uart_parent_clk[] = {
476         [0] = {.name = "clk_m"},
477         [1] = {.name = "pll_p"},
478 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
479         [2] = {.name = "pll_m"},
480 #endif
481 };
482
483 static struct tegra_uart_platform_data cardhu_uart_pdata;
484 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
485
486 static void __init uart_debug_init(void)
487 {
488         struct board_info board_info;
489         int debug_port_id;
490
491         tegra_get_board_info(&board_info);
492
493         debug_port_id = get_tegra_uart_debug_port_id();
494         if (debug_port_id < 0) {
495                 debug_port_id = 0;
496                         /* UARTB is debug port
497                          *       for SLT - E1186/E1187/PM269
498                          *       for E1256/E1257
499                          */
500                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
501                         ((board_info.board_id == BOARD_E1186) ||
502                         (board_info.board_id == BOARD_E1187) ||
503                         (board_info.board_id == BOARD_PM269))) ||
504                         (board_info.board_id == BOARD_E1256) ||
505                         (board_info.board_id == BOARD_E1257))
506                                 debug_port_id = 1;
507         }
508
509 #ifdef CONFIG_TEGRA_IRDA
510         if ((board_info.board_id == BOARD_E1186) ||
511                 (board_info.board_id == BOARD_E1198)) {
512                 if (debug_port_id == 1) {
513                         cardhu_irda_pdata.is_irda = false;
514                         pr_err("UARTB is not available for IrDA\n");
515                 }
516         }
517 #endif
518
519         switch (debug_port_id) {
520         case 0:
521                 /* UARTA is the debug port. */
522                 pr_info("Selecting UARTA as the debug console\n");
523                 cardhu_uart_devices[0] = &debug_uarta_device;
524                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
525                 debug_uart_port_base = ((struct plat_serial8250_port *)(
526                         debug_uarta_device.dev.platform_data))->mapbase;
527                 break;
528
529         case 1:
530                 /* UARTB is the debug port. */
531                 pr_info("Selecting UARTB as the debug console\n");
532                 cardhu_uart_devices[1] = &debug_uartb_device;
533                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
534                 debug_uart_port_base = ((struct plat_serial8250_port *)(
535                         debug_uartb_device.dev.platform_data))->mapbase;
536                 break;
537
538         case 2:
539                 /* UARTC is the debug port. */
540                 pr_info("Selecting UARTC as the debug console\n");
541                 cardhu_uart_devices[2] = &debug_uartc_device;
542                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
543                 debug_uart_port_base = ((struct plat_serial8250_port *)(
544                         debug_uartc_device.dev.platform_data))->mapbase;
545                 break;
546
547         case 3:
548                 /* UARTD is the debug port. */
549                 pr_info("Selecting UARTD as the debug console\n");
550                 cardhu_uart_devices[3] = &debug_uartd_device;
551                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
552                 debug_uart_port_base = ((struct plat_serial8250_port *)(
553                         debug_uartd_device.dev.platform_data))->mapbase;
554                 break;
555
556         case 4:
557                 /* UARTE is the debug port. */
558                 pr_info("Selecting UARTE as the debug console\n");
559                 cardhu_uart_devices[4] = &debug_uarte_device;
560                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
561                 debug_uart_port_base = ((struct plat_serial8250_port *)(
562                         debug_uarte_device.dev.platform_data))->mapbase;
563                 break;
564
565         default:
566                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
567                 cardhu_uart_devices[0] = &debug_uarta_device;
568                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
569                 debug_uart_port_base = ((struct plat_serial8250_port *)(
570                         debug_uarta_device.dev.platform_data))->mapbase;
571                 break;
572         }
573         return;
574 }
575
576 static void __init cardhu_uart_init(void)
577 {
578         struct clk *c;
579         int i;
580         struct board_info board_info;
581
582         tegra_get_board_info(&board_info);
583
584         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
585                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
586                 if (IS_ERR_OR_NULL(c)) {
587                         pr_err("Not able to get the clock for %s\n",
588                                                 uart_parent_clk[i].name);
589                         continue;
590                 }
591                 uart_parent_clk[i].parent_clk = c;
592                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
593         }
594         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
595         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
596         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
597         cardhu_loopback_uart_pdata.parent_clk_count =
598                                                 ARRAY_SIZE(uart_parent_clk);
599         cardhu_loopback_uart_pdata.is_loopback = true;
600         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
601         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
602         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
603         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
604         /* UARTE is used for loopback test purpose */
605         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
606
607         /* Register low speed only if it is selected */
608         if (!is_tegra_debug_uartport_hs()) {
609                 uart_debug_init();
610                 /* Clock enable for the debug channel */
611                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
612                         pr_info("The debug console clock name is %s\n",
613                                                 debug_uart_clk->name);
614                         c = tegra_get_clock_by_name("pll_p");
615                         if (IS_ERR_OR_NULL(c))
616                                 pr_err("Not getting the parent clock pll_p\n");
617                         else
618                                 clk_set_parent(debug_uart_clk, c);
619
620                         clk_enable(debug_uart_clk);
621                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
622                 } else {
623                         pr_err("Not getting the clock %s for debug console\n",
624                                         debug_uart_clk->name);
625                 }
626         }
627
628 #ifdef CONFIG_TEGRA_IRDA
629         if (((board_info.board_id == BOARD_E1186) ||
630                 (board_info.board_id == BOARD_E1198)) &&
631                         cardhu_irda_pdata.is_irda) {
632                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
633                 cardhu_irda_pdata.parent_clk_count =
634                                         ARRAY_SIZE(uart_parent_clk);
635
636                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
637         }
638 #endif
639
640         platform_add_devices(cardhu_uart_devices,
641                                 ARRAY_SIZE(cardhu_uart_devices));
642 }
643
644 static struct tegra_camera_platform_data tegra_camera_pdata = {
645         .limit_3d_emc_clk = false,
646 };
647
648 static struct platform_device tegra_camera = {
649         .name = "tegra_camera",
650         .dev = {
651                 .platform_data = &tegra_camera_pdata,
652         },
653         .id = -1,
654 };
655
656 static void tegra_camera_init(void)
657 {
658         /* For AP37 platform, limit 3d and emc freq when camera is ON */
659         if (TEGRA_REVISION_A03 == tegra_get_revision() &&
660                 0xA0 == tegra_sku_id())
661                 tegra_camera_pdata.limit_3d_emc_clk = true;
662         else
663                 tegra_camera_pdata.limit_3d_emc_clk = false;
664 }
665
666 static struct platform_device *cardhu_spi_devices[] __initdata = {
667         &tegra_spi_device4,
668 };
669
670 static struct platform_device *touch_spi_device[] __initdata = {
671         &tegra_spi_device1,
672 };
673
674 struct spi_clk_parent spi_parent_clk[] = {
675         [0] = {.name = "pll_p"},
676 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
677         [1] = {.name = "pll_m"},
678         [2] = {.name = "clk_m"},
679 #else
680         [1] = {.name = "clk_m"},
681 #endif
682 };
683
684 static struct tegra_spi_platform_data cardhu_spi_pdata = {
685         .is_dma_based           = true,
686         .max_dma_buffer         = (16 * 1024),
687         .is_clkon_always        = false,
688         .max_rate               = 100000000,
689 };
690
691 static void __init cardhu_spi_init(void)
692 {
693         int i;
694         struct clk *c;
695         struct board_info board_info, display_board_info;
696
697         tegra_get_board_info(&board_info);
698         tegra_get_display_board_info(&display_board_info);
699
700         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
701                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
702                 if (IS_ERR_OR_NULL(c)) {
703                         pr_err("Not able to get the clock for %s\n",
704                                                 spi_parent_clk[i].name);
705                         continue;
706                 }
707                 spi_parent_clk[i].parent_clk = c;
708                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
709         }
710         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
711         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
712         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
713         platform_add_devices(cardhu_spi_devices,
714                                 ARRAY_SIZE(cardhu_spi_devices));
715
716         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
717                 platform_add_devices(touch_spi_device,
718                                 ARRAY_SIZE(touch_spi_device));
719         }
720         if (board_info.board_id == BOARD_E1198) {
721                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
722                 platform_device_register(&tegra_spi_device2);
723                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
724                 platform_device_register(&tegra_spi_slave_device1);
725         }
726 }
727
728 static void __init cardhu_dtv_init(void)
729 {
730         struct board_info board_info;
731
732         tegra_get_board_info(&board_info);
733
734         if (board_info.board_id == BOARD_E1186)
735                 platform_device_register(&tegra_dtv_device);
736 }
737
738 static struct resource tegra_rtc_resources[] = {
739         [0] = {
740                 .start = TEGRA_RTC_BASE,
741                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
742                 .flags = IORESOURCE_MEM,
743         },
744         [1] = {
745                 .start = INT_RTC,
746                 .end = INT_RTC,
747                 .flags = IORESOURCE_IRQ,
748         },
749 };
750
751 static struct platform_device tegra_rtc_device = {
752         .name = "tegra_rtc",
753         .id   = -1,
754         .resource = tegra_rtc_resources,
755         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
756 };
757
758 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
759         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
760         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
761         .gpio_hp_mute           = -1,
762         .gpio_int_mic_en        = -1,
763         .gpio_ext_mic_en        = -1,
764         .i2s_param[HIFI_CODEC]  = {
765                 .audio_port_id  = 0,
766                 .is_i2s_master  = 1,
767                 .i2s_mode       = TEGRA_DAIFMT_I2S,
768         },
769         .i2s_param[BASEBAND]    = {
770                 .audio_port_id  = -1,
771         },
772         .i2s_param[BT_SCO]      = {
773                 .audio_port_id  = 3,
774                 .is_i2s_master  = 1,
775                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
776         },
777 };
778
779 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
780         .gpio_spkr_en           = -1,
781         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
782         .gpio_hp_mute           = -1,
783         .gpio_int_mic_en        = -1,
784         .gpio_ext_mic_en        = -1,
785         .i2s_param[HIFI_CODEC]  = {
786                 .audio_port_id  = 0,
787                 .is_i2s_master  = 1,
788                 .i2s_mode       = TEGRA_DAIFMT_I2S,
789         },
790         .i2s_param[BASEBAND]    = {
791                 .audio_port_id  = -1,
792         },
793         .i2s_param[BT_SCO]      = {
794                 .audio_port_id  = 3,
795                 .is_i2s_master  = 1,
796                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
797         },
798 };
799
800 static struct platform_device cardhu_audio_wm8903_device = {
801         .name   = "tegra-snd-wm8903",
802         .id     = 0,
803         .dev    = {
804                 .platform_data = &cardhu_audio_wm8903_pdata,
805         },
806 };
807
808 static struct platform_device cardhu_audio_max98095_device = {
809         .name   = "tegra-snd-max98095",
810         .id     = 0,
811         .dev    = {
812                 .platform_data = &cardhu_audio_max98095_pdata,
813         },
814 };
815
816 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
817         .gpio_spkr_en           = -1,
818         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
819         .gpio_hp_mute           = -1,
820         .gpio_int_mic_en        = -1,
821         .gpio_ext_mic_en        = -1,
822         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
823         .i2s_param[HIFI_CODEC]  = {
824                 .audio_port_id  = 0,
825                 .is_i2s_master  = 1,
826                 .i2s_mode       = TEGRA_DAIFMT_I2S,
827                 .sample_size    = 16,
828         },
829         .i2s_param[BT_SCO]      = {
830                 .sample_size    = 16,
831                 .audio_port_id  = 3,
832                 .is_i2s_master  = 1,
833                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
834         },
835 };
836
837 static struct platform_device cardhu_audio_aic326x_device = {
838         .name   = "tegra-snd-aic326x",
839         .id     = 0,
840         .dev    = {
841                 .platform_data  = &cardhu_audio_aic326x_pdata,
842         },
843 };
844
845 static struct tegra_asoc_platform_data beaver_audio_rt5640_pdata = {
846         .codec_name = "rt5640.4-001c",
847         .codec_dai_name = "rt5640-aif1",
848         .gpio_spkr_en           = TEGRA_GPIO_RTL_SPKR_EN,
849         .gpio_hp_det            = TEGRA_GPIO_RTL_HP_DET,
850         .gpio_hp_mute           = -1,
851         .gpio_int_mic_en        = TEGRA_GPIO_RTL_INT_MIC_EN,
852         .gpio_ext_mic_en        = -1,   /* TEGRA_GPIO_EXT_MIC_EN,*/
853                 .i2s_param[HIFI_CODEC]  = {
854                 .audio_port_id  = 0,
855                 .is_i2s_master  = 1,
856                 .i2s_mode       = TEGRA_DAIFMT_I2S,
857         },
858         .i2s_param[BASEBAND]    = {
859                 .audio_port_id  = -1,
860         },
861         .i2s_param[BT_SCO]      = {
862                 .audio_port_id  = 3,
863                 .is_i2s_master  = 1,
864                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
865         },
866 };
867
868 static struct platform_device beaver_audio_rt5640_device = {
869         .name   = "tegra-snd-rt5640",
870         .id     = 0,
871         .dev    = {
872                 .platform_data = &beaver_audio_rt5640_pdata,
873         },
874 };
875
876
877 static struct platform_device *cardhu_devices[] __initdata = {
878         &tegra_pmu_device,
879         &tegra_rtc_device,
880         &tegra_udc_device,
881 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
882         &tegra_smmu_device,
883 #endif
884         &tegra_wdt0_device,
885         &tegra_wdt1_device,
886         &tegra_wdt2_device,
887 #if defined(CONFIG_TEGRA_AVP)
888         &tegra_avp_device,
889 #endif
890         &tegra_camera,
891 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
892         &tegra_se_device,
893 #endif
894         &tegra_ahub_device,
895         &tegra_dam_device0,
896         &tegra_dam_device1,
897         &tegra_dam_device2,
898         &tegra_i2s_device0,
899         &tegra_i2s_device1,
900         &tegra_i2s_device3,
901         &tegra_spdif_device,
902         &spdif_dit_device,
903         &bluetooth_dit_device,
904         &baseband_dit_device,
905         &cardhu_bt_rfkill_device,
906         &tegra_pcm_device,
907         &cardhu_audio_max98095_device,
908         &cardhu_audio_aic326x_device,
909         &tegra_hda_device,
910         &tegra_cec_device,
911 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
912         &tegra_aes_device,
913 #endif
914 };
915
916 #define E1506_MXT_CONFIG_CRC 0x62F903
917 static const u8 e1506_config[] = {
918         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
919         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
920         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
921         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
922         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
923         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
924         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
925         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
926         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
927         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
928         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
929         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
930         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
931         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
932         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
933         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
934         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
935         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
936         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
937         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
938         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
939         0x00
940 };
941
942 #define MXT_CONFIG_CRC  0xD62DE8
943 static const u8 config[] = {
944         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
945         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
946         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
947         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
948         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
949         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
950         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
951         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
952         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
953         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
954         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
955         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
956         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
957         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
958         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
959         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
960         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
961         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
962         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
963         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
964 };
965
966 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
967 static const u8 config_sku2000[] = {
968         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
969         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
970         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
971         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
972         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
973         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
974         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
975         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
976         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
977         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
978         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
979         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
980         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
981         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
982         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
983         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
984         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
985         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
986         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
987         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
988 };
989 static struct platform_device *cardhu_audio_devices[] __initdata = {
990                 &cardhu_audio_wm8903_device,
991
992 };
993
994 static struct platform_device *beaver_audio_devices[] __initdata = {
995                 &beaver_audio_rt5640_device,
996
997 };
998
999 static struct mxt_platform_data atmel_mxt_info = {
1000         .x_line         = 27,
1001         .y_line         = 42,
1002         .x_size         = 768,
1003         .y_size         = 1366,
1004         .blen           = 0x20,
1005         .threshold      = 0x3C,
1006         .voltage        = 3300000,              /* 3.3V */
1007         .orient         = 5,
1008         .config         = config,
1009         .config_length  = 157,
1010         .config_crc     = MXT_CONFIG_CRC,
1011         .irqflags       = IRQF_TRIGGER_FALLING,
1012 /*      .read_chg       = &read_chg, */
1013         .read_chg       = NULL,
1014 };
1015
1016 static struct mxt_platform_data e1506_atmel_mxt_info = {
1017         .x_line         = 19,
1018         .y_line         = 11,
1019         .x_size         = 960,
1020         .y_size         = 540,
1021         .blen           = 0x10,
1022         .threshold      = 0x32,
1023         .voltage        = 3300000,              /* 3.3V */
1024         .orient         = 3,
1025         .config         = e1506_config,
1026         .config_length  = 168,
1027         .config_crc     = E1506_MXT_CONFIG_CRC,
1028         .irqflags       = IRQF_TRIGGER_FALLING,
1029 /*      .read_chg       = &read_chg, */
1030         .read_chg       = NULL,
1031 };
1032
1033 static struct i2c_board_info __initdata atmel_i2c_info[] = {
1034         {
1035                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
1036                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
1037                 .platform_data = &atmel_mxt_info,
1038         }
1039 };
1040
1041 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
1042         {
1043                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
1044                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
1045                 .platform_data = &e1506_atmel_mxt_info,
1046         }
1047 };
1048
1049 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
1050         /* name         parent          rate            enabled */
1051         { "sbc1",       "pll_p",        52000000,       true},
1052         { NULL,         NULL,           0,              0},
1053 };
1054
1055 static int __init cardhu_touch_init(void)
1056 {
1057         struct board_info BoardInfo, DisplayBoardInfo;
1058
1059         tegra_get_board_info(&BoardInfo);
1060
1061         /* Beaver board does not have any touch hardware*/
1062         if (BoardInfo.board_id == BOARD_PM315)
1063                 return 0;
1064
1065         tegra_get_display_board_info(&DisplayBoardInfo);
1066         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
1067                 tegra_clk_init_from_table(spi_clk_init_table);
1068
1069                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
1070         } else {
1071                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
1072                 gpio_direction_input(TEGRA_GPIO_PH4);
1073
1074                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
1075                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
1076                 msleep(1);
1077                 gpio_set_value(TEGRA_GPIO_PH6, 1);
1078                 msleep(100);
1079
1080                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1081                         atmel_mxt_info.config = config_sku2000;
1082                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1083                 }
1084
1085                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506)
1086                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1087                 else
1088                         i2c_register_board_info(1, atmel_i2c_info, 1);
1089         }
1090
1091         return 0;
1092 }
1093
1094 #if defined(CONFIG_USB_SUPPORT)
1095
1096 static void cardu_usb_hsic_postsupend(void)
1097 {
1098 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1099         baseband_xmm_set_power_status(BBXMM_PS_L2);
1100 #endif
1101 }
1102
1103 static void cardu_usb_hsic_preresume(void)
1104 {
1105 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1106         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1107 #endif
1108 }
1109
1110 static void cardu_usb_hsic_phy_ready(void)
1111 {
1112 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1113         baseband_xmm_set_power_status(BBXMM_PS_L0);
1114 #endif
1115 }
1116
1117 static void cardu_usb_hsic_phy_off(void)
1118 {
1119 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1120         baseband_xmm_set_power_status(BBXMM_PS_L3);
1121 #endif
1122 }
1123
1124 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1125         .post_suspend = cardu_usb_hsic_postsupend,
1126         .pre_resume = cardu_usb_hsic_preresume,
1127         .port_power = cardu_usb_hsic_phy_ready,
1128         .post_phy_off = cardu_usb_hsic_phy_off,
1129 };
1130
1131 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1132         .port_otg = false,
1133         .has_hostpc = true,
1134         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1135         .op_mode        = TEGRA_USB_OPMODE_HOST,
1136         .u_data.host = {
1137                 .vbus_gpio = -1,
1138                 .hot_plug = false,
1139                 .remote_wakeup_supported = false,
1140                 .power_off_on_suspend = false,
1141         },
1142         .ops = &hsic_xmm_plat_ops,
1143 };
1144 #endif
1145
1146 static int hsic_enable_gpio = -1;
1147 static int hsic_reset_gpio = -1;
1148
1149 void hsic_platform_open(void)
1150 {
1151         int reset_gpio = 0, enable_gpio = 0;
1152
1153         if (hsic_enable_gpio != -1)
1154                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1155         if (hsic_reset_gpio != -1)
1156                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1157         /* hsic enable signal deasserted, hsic reset asserted */
1158         if (!enable_gpio)
1159                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1160         if (!reset_gpio)
1161                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1162         /* keep hsic reset asserted for 1 ms */
1163         udelay(1000);
1164         /* enable (power on) hsic */
1165         if (!enable_gpio)
1166                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1167         udelay(1000);
1168         /* deassert reset */
1169         if (!reset_gpio)
1170                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1171
1172 }
1173
1174 void hsic_platform_close(void)
1175 {
1176         if (hsic_enable_gpio != -1) {
1177                 gpio_set_value(hsic_enable_gpio, 0);
1178                 gpio_free(hsic_enable_gpio);
1179         }
1180         if (hsic_reset_gpio != -1) {
1181                 gpio_set_value(hsic_reset_gpio, 0);
1182                 gpio_free(hsic_reset_gpio);
1183         }
1184 }
1185
1186 void hsic_power_on(void)
1187 {
1188         if (hsic_enable_gpio != -1) {
1189                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1190                 udelay(1000);
1191         }
1192 }
1193
1194 void hsic_power_off(void)
1195 {
1196         if (hsic_enable_gpio != -1) {
1197                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1198                 udelay(1000);
1199         }
1200 }
1201
1202 #if defined(CONFIG_USB_SUPPORT)
1203 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1204         .open = hsic_platform_open,
1205         .close = hsic_platform_close,
1206         .pre_phy_on = hsic_power_on,
1207         .post_phy_off = hsic_power_off,
1208 };
1209
1210 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1211         .port_otg = false,
1212         .has_hostpc = true,
1213         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1214         .op_mode        = TEGRA_USB_OPMODE_HOST,
1215         .u_data.host = {
1216                 .vbus_gpio = -1,
1217                 .hot_plug = false,
1218                 .remote_wakeup_supported = false,
1219                 .power_off_on_suspend = false,
1220         },
1221         .ops = &hsic_plat_ops,
1222 };
1223
1224 static struct tegra_usb_platform_data tegra_udc_pdata = {
1225         .port_otg = true,
1226         .has_hostpc = true,
1227         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1228         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1229         .u_data.dev = {
1230                 .vbus_pmu_irq = 0,
1231                 .vbus_gpio = -1,
1232                 .charging_supported = false,
1233                 .remote_wakeup_supported = false,
1234         },
1235         .u_cfg.utmi = {
1236                 .hssync_start_delay = 0,
1237                 .elastic_limit = 16,
1238                 .idle_wait_delay = 17,
1239                 .term_range_adj = 6,
1240                 .xcvr_setup = 8,
1241                 .xcvr_lsfslew = 2,
1242                 .xcvr_lsrslew = 2,
1243                 .xcvr_setup_offset = 0,
1244                 .xcvr_use_fuses = 1,
1245         },
1246 };
1247
1248 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1249         .port_otg = false,
1250         .has_hostpc = true,
1251         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1252         .op_mode        = TEGRA_USB_OPMODE_HOST,
1253         .u_data.host = {
1254                 .vbus_gpio = -1,
1255                 .hot_plug = false,
1256                 .remote_wakeup_supported = true,
1257                 .power_off_on_suspend = true,
1258         },
1259         .u_cfg.utmi = {
1260                 .hssync_start_delay = 0,
1261                 .elastic_limit = 16,
1262                 .idle_wait_delay = 17,
1263                 .term_range_adj = 6,
1264                 .xcvr_setup = 15,
1265                 .xcvr_lsfslew = 2,
1266                 .xcvr_lsrslew = 2,
1267                 .xcvr_setup_offset = 0,
1268                 .xcvr_use_fuses = 1,
1269         },
1270 };
1271
1272 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1273         .port_otg = false,
1274         .has_hostpc = true,
1275         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1276         .op_mode = TEGRA_USB_OPMODE_HOST,
1277         .u_data.host = {
1278                 .vbus_gpio = -1,
1279                 .vbus_reg = "vdd_vbus_typea_usb",
1280                 .hot_plug = true,
1281                 .remote_wakeup_supported = true,
1282                 .power_off_on_suspend = true,
1283         },
1284         .u_cfg.utmi = {
1285                 .hssync_start_delay = 0,
1286                 .elastic_limit = 16,
1287                 .idle_wait_delay = 17,
1288                 .term_range_adj = 6,
1289                 .xcvr_setup = 8,
1290                 .xcvr_lsfslew = 2,
1291                 .xcvr_lsrslew = 2,
1292                 .xcvr_setup_offset = 0,
1293                 .xcvr_use_fuses = 1,
1294         },
1295 };
1296
1297 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1298         .port_otg = true,
1299         .has_hostpc = true,
1300         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1301         .op_mode = TEGRA_USB_OPMODE_HOST,
1302         .u_data.host = {
1303                 .vbus_gpio = -1,
1304                 .vbus_reg = "vdd_vbus_micro_usb",
1305                 .hot_plug = true,
1306                 .remote_wakeup_supported = true,
1307                 .power_off_on_suspend = true,
1308         },
1309         .u_cfg.utmi = {
1310                 .hssync_start_delay = 0,
1311                 .elastic_limit = 16,
1312                 .idle_wait_delay = 17,
1313                 .term_range_adj = 6,
1314                 .xcvr_setup = 15,
1315                 .xcvr_lsfslew = 2,
1316                 .xcvr_lsrslew = 2,
1317                 .xcvr_setup_offset = 0,
1318                 .xcvr_use_fuses = 1,
1319         },
1320 };
1321
1322 static struct tegra_usb_otg_data tegra_otg_pdata = {
1323         .ehci_device = &tegra_ehci1_device,
1324         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1325 };
1326 #endif
1327
1328 #if defined(CONFIG_USB_SUPPORT)
1329 static void cardhu_usb_init(void)
1330 {
1331         struct board_info bi;
1332
1333         tegra_get_board_info(&bi);
1334
1335         /* OTG should be the first to be registered */
1336         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1337         platform_device_register(&tegra_otg_device);
1338
1339         /* setup the udc platform data */
1340         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1341
1342         if (bi.board_id == BOARD_PM267) {
1343                 hsic_enable_gpio = EN_HSIC_GPIO;
1344                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1345                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1346                 platform_device_register(&tegra_ehci2_device);
1347         } else if (bi.board_id == BOARD_E1256) {
1348                 hsic_enable_gpio = EN_HSIC_GPIO;
1349                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1350                 platform_device_register(&tegra_ehci2_device);
1351         } else if (bi.board_id == BOARD_E1186) {
1352                 tegra_ehci2_device.dev.platform_data =
1353                                                 &tegra_ehci2_hsic_xmm_pdata;
1354                 /* ehci2 registration happens in baseband-xmm-power  */
1355         } else {
1356                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1357                 platform_device_register(&tegra_ehci2_device);
1358         }
1359
1360         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1361         platform_device_register(&tegra_ehci3_device);
1362
1363 }
1364 #else
1365 static void cardhu_usb_init(void) { }
1366 #endif
1367
1368 static struct baseband_power_platform_data tegra_baseband_power_data = {
1369         .baseband_type = BASEBAND_XMM,
1370         .modem = {
1371         .xmm = {
1372                         .bb_rst = XMM_GPIO_BB_RST,
1373                         .bb_on = XMM_GPIO_BB_ON,
1374                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1375                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1376                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1377                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1378                         .hsic_device = &tegra_ehci2_device,
1379                 },
1380         },
1381 };
1382
1383 static struct platform_device tegra_baseband_power_device = {
1384         .name = "baseband_xmm_power",
1385         .id = -1,
1386         .dev = {
1387                 .platform_data = &tegra_baseband_power_data,
1388         },
1389 };
1390
1391 static struct platform_device tegra_baseband_power2_device = {
1392         .name = "baseband_xmm_power2",
1393         .id = -1,
1394         .dev = {
1395                 .platform_data = &tegra_baseband_power_data,
1396         },
1397 };
1398
1399
1400 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1401         .port_status[0] = 1,
1402         .port_status[1] = 1,
1403         .port_status[2] = 1,
1404         .use_dock_detect        = 0,
1405         .gpio           = 0,
1406 };
1407
1408 static void cardhu_pci_init(void)
1409 {
1410         struct board_info board_info;
1411
1412         tegra_get_board_info(&board_info);
1413         if (board_info.board_id == BOARD_E1291) {
1414                 cardhu_pci_platform_data.port_status[0] = 0;
1415                 cardhu_pci_platform_data.port_status[1] = 0;
1416                 cardhu_pci_platform_data.port_status[2] = 1;
1417                 cardhu_pci_platform_data.use_dock_detect = 1;
1418                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1419         } else if (board_info.board_id == BOARD_PM315) {
1420                 cardhu_pci_platform_data.port_status[0] = 1;
1421                 cardhu_pci_platform_data.port_status[1] = 0;
1422                 cardhu_pci_platform_data.port_status[2] = 1;
1423                 cardhu_pci_platform_data.use_dock_detect = 0;
1424                 cardhu_pci_platform_data.gpio = 0;
1425         }
1426         if ((board_info.board_id == BOARD_E1186) ||
1427                         (board_info.board_id == BOARD_E1187) ||
1428                         (board_info.board_id == BOARD_E1291) ||
1429                         (board_info.board_id == BOARD_PM315)) {
1430                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1431                 platform_device_register(&tegra_pci_device);
1432         }
1433 }
1434
1435 static void cardhu_modem_init(void)
1436 {
1437         struct board_info board_info;
1438         int w_disable_gpio, ret;
1439
1440         tegra_get_board_info(&board_info);
1441         switch (board_info.board_id) {
1442         case BOARD_E1291:
1443         case BOARD_E1198:
1444                 if (((board_info.board_id == BOARD_E1291) &&
1445                                 (board_info.fab < BOARD_FAB_A03)) ||
1446                         ((board_info.board_id == BOARD_E1198) &&
1447                                         (board_info.fab < BOARD_FAB_A02))) {
1448                         w_disable_gpio = TEGRA_GPIO_PH5;
1449                 } else {
1450                         w_disable_gpio = TEGRA_GPIO_PDD5;
1451                 }
1452
1453                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1454                 if (ret < 0)
1455                         pr_err("%s: gpio_request failed for gpio %d\n",
1456                                 __func__, w_disable_gpio);
1457                 else
1458                         gpio_direction_input(w_disable_gpio);
1459
1460                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1461                 if (((board_info.board_id == BOARD_E1291) &&
1462                                 (board_info.fab >= BOARD_FAB_A04)) ||
1463                         ((board_info.board_id == BOARD_E1198) &&
1464                                         (board_info.fab >= BOARD_FAB_A02))) {
1465                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1466                         if (ret < 0) {
1467                                 pr_err("%s(): Error in allocating gpio "
1468                                         "TEGRA_GPIO_PH7\n", __func__);
1469                                 break;
1470                         }
1471                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1472                 }
1473                 break;
1474         case BOARD_E1186:
1475                 platform_device_register(&tegra_baseband_power_device);
1476                 platform_device_register(&tegra_baseband_power2_device);
1477                 break;
1478         default:
1479                 break;
1480         }
1481
1482 }
1483
1484 #ifdef CONFIG_SATA_AHCI_TEGRA
1485 static void cardhu_sata_init(void)
1486 {
1487         platform_device_register(&tegra_sata_device);
1488 }
1489 #else
1490 static void cardhu_sata_init(void) { }
1491 #endif
1492
1493 static void __init tegra_cardhu_init(void)
1494 {
1495         struct board_info board_info;
1496
1497         tegra_get_board_info(&board_info);
1498         tegra_thermal_init(&thermal_data,
1499                                 throttle_list,
1500                                 ARRAY_SIZE(throttle_list));
1501         tegra_clk_init_from_table(cardhu_clk_init_table);
1502         cardhu_pinmux_init();
1503         cardhu_i2c_init();
1504         cardhu_spi_init();
1505         cardhu_usb_init();
1506 #ifdef CONFIG_TEGRA_EDP_LIMITS
1507         cardhu_edp_init();
1508 #endif
1509         cardhu_uart_init();
1510         tegra_camera_init();
1511         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1512         switch (board_info.board_id) {
1513         case BOARD_PM315:
1514                 platform_add_devices(beaver_audio_devices,
1515                                 ARRAY_SIZE(beaver_audio_devices));
1516                 break;
1517         default:
1518                 platform_add_devices(cardhu_audio_devices,
1519                                 ARRAY_SIZE(cardhu_audio_devices));
1520
1521                 break;
1522         }
1523         tegra_ram_console_debug_init();
1524         tegra_io_dpd_init();
1525         cardhu_sdhci_init();
1526         cardhu_regulator_init();
1527         cardhu_dtv_init();
1528         cardhu_suspend_init();
1529         cardhu_touch_init();
1530         cardhu_modem_init();
1531         cardhu_kbc_init();
1532         cardhu_scroll_init();
1533         cardhu_keys_init();
1534         cardhu_panel_init();
1535         cardhu_pmon_init();
1536         cardhu_sensors_init();
1537         cardhu_setup_bluesleep();
1538         /*
1539          * if you want to add support for SATA in your board
1540          * then add your board check here like
1541          * board_info.board_id == BOARD_E1186
1542          */
1543         if (board_info.board_id == BOARD_PM315)
1544                 cardhu_sata_init();
1545         //audio_wired_jack_init();
1546         cardhu_pins_state_init();
1547         cardhu_emc_init();
1548         tegra_release_bootloader_fb();
1549         cardhu_pci_init();
1550 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1551         tegra_wdt_recovery_init();
1552 #endif
1553         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1554 }
1555
1556 static void __init tegra_cardhu_reserve(void)
1557 {
1558 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1559         /* Support 1920X1080 32bpp,double buffered on HDMI*/
1560         tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M);
1561 #else
1562         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1563 #endif
1564         tegra_ram_console_debug_reserve(SZ_1M);
1565 }
1566
1567 static const char *cardhu_dt_board_compat[] = {
1568         "nvidia,cardhu",
1569         NULL
1570 };
1571
1572 MACHINE_START(CARDHU, "cardhu")
1573         .boot_params    = 0x80000100,
1574         .map_io         = tegra_map_common_io,
1575         .reserve        = tegra_cardhu_reserve,
1576         .init_early     = tegra_init_early,
1577         .init_irq       = tegra_init_irq,
1578         .timer          = &tegra_timer,
1579         .init_machine   = tegra_cardhu_init,
1580         .dt_compat      = cardhu_dt_board_compat,
1581 MACHINE_END