b57bec4dbf7d2b87190d4ea0127c9890ab6f364e
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42
43 #include <sound/wm8903.h>
44 #include <sound/max98095.h>
45 #include <media/tegra_dtv.h>
46
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/irqs.h>
50 #include <mach/pinmux.h>
51 #include <mach/iomap.h>
52 #include <mach/io.h>
53 #include <mach/i2s.h>
54 #include <mach/tegra_asoc_pdata.h>
55 #include <mach/tegra_wm8903_pdata.h>
56 #include <asm/mach-types.h>
57 #include <asm/mach/arch.h>
58 #include <mach/usb_phy.h>
59 #include <mach/thermal.h>
60 #include <mach/pci.h>
61
62 #include "board.h"
63 #include "clock.h"
64 #include "board-cardhu.h"
65 #include "board-touch.h"
66 #include "devices.h"
67 #include "gpio-names.h"
68 #include "fuse.h"
69 #include "pm.h"
70 #include "baseband-xmm-power.h"
71 #include "wdt-recovery.h"
72
73 /* All units are in millicelsius */
74 static struct tegra_thermal_data thermal_data = {
75         .temp_shutdown = 90000,
76         .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
77 #ifdef CONFIG_TEGRA_EDP_LIMITS
78         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
79         .hysteresis_edp = 3000,
80 #endif
81 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
82         .temp_throttle = 85000,
83         .tc1 = 0,
84         .tc2 = 1,
85         .passive_delay = 2000,
86 #endif
87 };
88
89 static struct resource cardhu_bcm4329_rfkill_resources[] = {
90         {
91                 .name   = "bcm4329_nshutdown_gpio",
92                 .start  = TEGRA_GPIO_PU0,
93                 .end    = TEGRA_GPIO_PU0,
94                 .flags  = IORESOURCE_IO,
95         },
96 };
97
98 static struct platform_device cardhu_bcm4329_rfkill_device = {
99         .name = "bcm4329_rfkill",
100         .id             = -1,
101         .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
102         .resource       = cardhu_bcm4329_rfkill_resources,
103 };
104
105 static struct resource cardhu_bluesleep_resources[] = {
106         [0] = {
107                 .name = "gpio_host_wake",
108                         .start  = TEGRA_GPIO_PU6,
109                         .end    = TEGRA_GPIO_PU6,
110                         .flags  = IORESOURCE_IO,
111         },
112         [1] = {
113                 .name = "gpio_ext_wake",
114                         .start  = TEGRA_GPIO_PU1,
115                         .end    = TEGRA_GPIO_PU1,
116                         .flags  = IORESOURCE_IO,
117         },
118         [2] = {
119                 .name = "host_wake",
120                         .start  = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
121                         .end    = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PU6),
122                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
123         },
124 };
125
126 static struct platform_device cardhu_bluesleep_device = {
127         .name           = "bluesleep",
128         .id             = -1,
129         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
130         .resource       = cardhu_bluesleep_resources,
131 };
132
133 static noinline void __init cardhu_setup_bluesleep(void)
134 {
135         platform_device_register(&cardhu_bluesleep_device);
136         tegra_gpio_enable(TEGRA_GPIO_PU6);
137         tegra_gpio_enable(TEGRA_GPIO_PU1);
138         return;
139 }
140
141 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
142         /* name         parent          rate            enabled */
143         { "pll_m",      NULL,           0,              false},
144         { "hda",        "pll_p",        108000000,      false},
145         { "hda2codec_2x","pll_p",       48000000,       false},
146         { "pwm",        "pll_p",        3187500,        false},
147         { "blink",      "clk_32k",      32768,          true},
148         { "i2s0",       "pll_a_out0",   0,              false},
149         { "i2s1",       "pll_a_out0",   0,              false},
150         { "i2s3",       "pll_a_out0",   0,              false},
151         { "spdif_out",  "pll_a_out0",   0,              false},
152         { "d_audio",    "clk_m",        12000000,       false},
153         { "dam0",       "clk_m",        12000000,       false},
154         { "dam1",       "clk_m",        12000000,       false},
155         { "dam2",       "clk_m",        12000000,       false},
156         { "audio1",     "i2s1_sync",    0,              false},
157         { "audio3",     "i2s3_sync",    0,              false},
158         { "vi_sensor",  "pll_p",        150000000,      false},
159         { "i2c1",       "pll_p",        3200000,        false},
160         { "i2c2",       "pll_p",        3200000,        false},
161         { "i2c3",       "pll_p",        3200000,        false},
162         { "i2c4",       "pll_p",        3200000,        false},
163         { "i2c5",       "pll_p",        3200000,        false},
164         { NULL,         NULL,           0,              0},
165 };
166
167 static struct pn544_i2c_platform_data nfc_pdata = {
168         .irq_gpio = TEGRA_GPIO_PX0,
169         .ven_gpio = TEGRA_GPIO_PP3,
170         .firm_gpio = TEGRA_GPIO_PO7,
171         };
172
173 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
174         {
175                 I2C_BOARD_INFO("pn544", 0x28),
176                 .platform_data = &nfc_pdata,
177                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PX0),
178         },
179 };
180 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
181         .adapter_nr     = 0,
182         .bus_count      = 1,
183         .bus_clk_rate   = { 100000, 0 },
184         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
185         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
186         .arb_recovery = arb_lost_recovery,
187 };
188
189 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
190         .adapter_nr     = 1,
191         .bus_count      = 1,
192         .bus_clk_rate   = { 400000, 0 },
193         .is_clkon_always = true,
194         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
195         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
196         .arb_recovery = arb_lost_recovery,
197 };
198
199 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
200         .adapter_nr     = 2,
201         .bus_count      = 1,
202         .bus_clk_rate   = { 100000, 0 },
203         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
204         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
205         .arb_recovery = arb_lost_recovery,
206 };
207
208 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
209         .adapter_nr     = 3,
210         .bus_count      = 1,
211         .bus_clk_rate   = { 10000, 0 },
212         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
213         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
214         .arb_recovery = arb_lost_recovery,
215 };
216
217 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
218         .adapter_nr     = 4,
219         .bus_count      = 1,
220         .bus_clk_rate   = { 400000, 0 },
221         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
222         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
223         .arb_recovery = arb_lost_recovery,
224 };
225
226
227 #if 0
228 struct tegra_wired_jack_conf audio_wr_jack_conf = {
229         .hp_det_n = TEGRA_GPIO_PW2,
230         .en_mic_ext = TEGRA_GPIO_PX1,
231         .en_mic_int = TEGRA_GPIO_PX0,
232 };
233 #endif
234
235 static struct wm8903_platform_data cardhu_wm8903_pdata = {
236         .irq_active_low = 0,
237         .micdet_cfg = 0,
238         .micdet_delay = 100,
239         .gpio_base = CARDHU_GPIO_WM8903(0),
240         .gpio_cfg = {
241                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
242                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
243                         WM8903_GP2_DIR,
244                 0,
245                 WM8903_GPIO_NO_CONFIG,
246                 WM8903_GPIO_NO_CONFIG,
247         },
248 };
249
250 /* Equalizer filter coefs generated from the MAXIM MAX98095
251  * evkit software tool */
252 static struct max98095_eq_cfg max98095_eq_cfg[] = {
253         {
254                 .name = "FLAT",
255                 .rate = 44100,
256                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
257                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
258                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
259                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
260                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
261         },
262         {
263                 .name = "LOWPASS1K",
264                 .rate = 44100,
265                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
266                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
267                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
268                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
269                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
270         },
271         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
272                 .name = "HIBOOST",
273                 .rate = 44100,
274                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
275                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
276                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
277                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
278                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
279         },
280         { /* BASS=12dB, TREBLE=+12dB */
281                 .name = "LOUD12DB",
282                 .rate = 44100,
283                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
284                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
285                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
286                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
287                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
288         },
289         {
290                 .name = "FLAT",
291                 .rate = 16000,
292                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
293                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
294                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
295                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
296                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
297         },
298         {
299                 .name = "LOWPASS1K",
300                 .rate = 16000,
301                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
302                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
303                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
304                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
305                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
306         },
307         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
308                 .name = "HIBOOST",
309                 .rate = 16000,
310                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
311                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
312                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
313                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
314                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
315         },
316         { /* BASS=12dB, TREBLE=+12dB */
317                 .name = "LOUD12DB",
318                 .rate = 16000,
319                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
320                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
321                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
322                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
323                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
324         },
325 };
326
327 static struct max98095_pdata cardhu_max98095_pdata = {
328         /* equalizer configuration */
329         .eq_cfg = max98095_eq_cfg,
330         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
331
332         /* Biquad filter response configuration */
333         .bq_cfg = NULL,
334         .bq_cfgcnt = 0,
335
336         /* microphone configuration */
337         .digmic_left_mode = 1,
338         .digmic_right_mode = 1,
339 };
340
341 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
342         I2C_BOARD_INFO("wm8903", 0x1a),
343         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
344         .platform_data = &cardhu_wm8903_pdata,
345 };
346
347 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
348         I2C_BOARD_INFO("aic3262-codec", 0x18),
349         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
350 };
351
352 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
353         I2C_BOARD_INFO("max98095", 0x10),
354         .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_CDC_IRQ),
355         .platform_data = &cardhu_max98095_pdata,
356 };
357
358 static void cardhu_i2c_init(void)
359 {
360         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
361         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
362         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
363         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
364         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
365
366         platform_device_register(&tegra_i2c_device5);
367         platform_device_register(&tegra_i2c_device4);
368         platform_device_register(&tegra_i2c_device3);
369         platform_device_register(&tegra_i2c_device2);
370         platform_device_register(&tegra_i2c_device1);
371
372         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
373         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
374         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
375
376         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
377 }
378
379 static struct platform_device *cardhu_uart_devices[] __initdata = {
380         &tegra_uarta_device,
381         &tegra_uartb_device,
382         &tegra_uartc_device,
383         &tegra_uartd_device,
384         &tegra_uarte_device,
385 };
386 static struct uart_clk_parent uart_parent_clk[] = {
387         [0] = {.name = "clk_m"},
388         [1] = {.name = "pll_p"},
389 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
390         [2] = {.name = "pll_m"},
391 #endif
392 };
393
394 static struct tegra_uart_platform_data cardhu_uart_pdata;
395 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
396
397 static void __init uart_debug_init(void)
398 {
399         struct board_info board_info;
400         int debug_port_id;
401
402         tegra_get_board_info(&board_info);
403
404         debug_port_id = get_tegra_uart_debug_port_id();
405         if (debug_port_id < 0) {
406                 debug_port_id = 0;
407                         /* UARTB is debug port
408                          *       for SLT - E1186/E1187/PM269
409                          *       for E1256/E1257
410                          */
411                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
412                         ((board_info.board_id == BOARD_E1186) ||
413                         (board_info.board_id == BOARD_E1187) ||
414                         (board_info.board_id == BOARD_PM269))) ||
415                         (board_info.board_id == BOARD_E1256) ||
416                         (board_info.board_id == BOARD_E1257))
417                                 debug_port_id = 1;
418         }
419
420         switch (debug_port_id) {
421         case 0:
422                 /* UARTA is the debug port. */
423                 pr_info("Selecting UARTA as the debug console\n");
424                 cardhu_uart_devices[0] = &debug_uarta_device;
425                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
426                 debug_uart_port_base = ((struct plat_serial8250_port *)(
427                         debug_uarta_device.dev.platform_data))->mapbase;
428                 break;
429
430         case 1:
431                 /* UARTB is the debug port. */
432                 pr_info("Selecting UARTB as the debug console\n");
433                 cardhu_uart_devices[1] = &debug_uartb_device;
434                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
435                 debug_uart_port_base = ((struct plat_serial8250_port *)(
436                         debug_uartb_device.dev.platform_data))->mapbase;
437                 break;
438
439         case 2:
440                 /* UARTC is the debug port. */
441                 pr_info("Selecting UARTC as the debug console\n");
442                 cardhu_uart_devices[2] = &debug_uartc_device;
443                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
444                 debug_uart_port_base = ((struct plat_serial8250_port *)(
445                         debug_uartc_device.dev.platform_data))->mapbase;
446                 break;
447
448         case 3:
449                 /* UARTD is the debug port. */
450                 pr_info("Selecting UARTD as the debug console\n");
451                 cardhu_uart_devices[3] = &debug_uartd_device;
452                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
453                 debug_uart_port_base = ((struct plat_serial8250_port *)(
454                         debug_uartd_device.dev.platform_data))->mapbase;
455                 break;
456
457         case 4:
458                 /* UARTE is the debug port. */
459                 pr_info("Selecting UARTE as the debug console\n");
460                 cardhu_uart_devices[4] = &debug_uarte_device;
461                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
462                 debug_uart_port_base = ((struct plat_serial8250_port *)(
463                         debug_uarte_device.dev.platform_data))->mapbase;
464                 break;
465
466         default:
467                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
468                 cardhu_uart_devices[0] = &debug_uarta_device;
469                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
470                 debug_uart_port_base = ((struct plat_serial8250_port *)(
471                         debug_uarta_device.dev.platform_data))->mapbase;
472                 break;
473         }
474         return;
475 }
476
477 static void __init cardhu_uart_init(void)
478 {
479         struct clk *c;
480         int i;
481
482         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
483                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
484                 if (IS_ERR_OR_NULL(c)) {
485                         pr_err("Not able to get the clock for %s\n",
486                                                 uart_parent_clk[i].name);
487                         continue;
488                 }
489                 uart_parent_clk[i].parent_clk = c;
490                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
491         }
492         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
493         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
494         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
495         cardhu_loopback_uart_pdata.parent_clk_count =
496                                                 ARRAY_SIZE(uart_parent_clk);
497         cardhu_loopback_uart_pdata.is_loopback = true;
498         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
499         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
500         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
501         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
502         /* UARTE is used for loopback test purpose */
503         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
504
505         /* Register low speed only if it is selected */
506         if (!is_tegra_debug_uartport_hs()) {
507                 uart_debug_init();
508                 /* Clock enable for the debug channel */
509                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
510                         pr_info("The debug console clock name is %s\n",
511                                                 debug_uart_clk->name);
512                         c = tegra_get_clock_by_name("pll_p");
513                         if (IS_ERR_OR_NULL(c))
514                                 pr_err("Not getting the parent clock pll_p\n");
515                         else
516                                 clk_set_parent(debug_uart_clk, c);
517
518                         clk_enable(debug_uart_clk);
519                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
520                 } else {
521                         pr_err("Not getting the clock %s for debug console\n",
522                                         debug_uart_clk->name);
523                 }
524         }
525
526         platform_add_devices(cardhu_uart_devices,
527                                 ARRAY_SIZE(cardhu_uart_devices));
528 }
529
530 static struct platform_device tegra_camera = {
531         .name = "tegra_camera",
532         .id = -1,
533 };
534
535 static struct platform_device *cardhu_spi_devices[] __initdata = {
536         &tegra_spi_device4,
537 };
538
539 static struct platform_device *touch_spi_device[] __initdata = {
540         &tegra_spi_device1,
541 };
542
543 struct spi_clk_parent spi_parent_clk[] = {
544         [0] = {.name = "pll_p"},
545 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
546         [1] = {.name = "pll_m"},
547         [2] = {.name = "clk_m"},
548 #else
549         [1] = {.name = "clk_m"},
550 #endif
551 };
552
553 static struct tegra_spi_platform_data cardhu_spi_pdata = {
554         .is_dma_based           = true,
555         .max_dma_buffer         = (16 * 1024),
556         .is_clkon_always        = false,
557         .max_rate               = 100000000,
558 };
559
560 static void __init cardhu_spi_init(void)
561 {
562         int i;
563         struct clk *c;
564         struct board_info board_info, display_board_info;
565
566         tegra_get_board_info(&board_info);
567         tegra_get_display_board_info(&display_board_info);
568
569         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
570                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
571                 if (IS_ERR_OR_NULL(c)) {
572                         pr_err("Not able to get the clock for %s\n",
573                                                 spi_parent_clk[i].name);
574                         continue;
575                 }
576                 spi_parent_clk[i].parent_clk = c;
577                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
578         }
579         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
580         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
581         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
582         platform_add_devices(cardhu_spi_devices,
583                                 ARRAY_SIZE(cardhu_spi_devices));
584
585         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
586                 platform_add_devices(touch_spi_device,
587                                 ARRAY_SIZE(touch_spi_device));
588         }
589         if (board_info.board_id == BOARD_E1198) {
590                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
591                 platform_device_register(&tegra_spi_device2);
592                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
593                 platform_device_register(&tegra_spi_slave_device1);
594         }
595 }
596
597 static void __init cardhu_dtv_init(void)
598 {
599         struct board_info board_info;
600
601         tegra_get_board_info(&board_info);
602
603         if (board_info.board_id == BOARD_E1186)
604                 platform_device_register(&tegra_dtv_device);
605 }
606
607 static struct resource tegra_rtc_resources[] = {
608         [0] = {
609                 .start = TEGRA_RTC_BASE,
610                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
611                 .flags = IORESOURCE_MEM,
612         },
613         [1] = {
614                 .start = INT_RTC,
615                 .end = INT_RTC,
616                 .flags = IORESOURCE_IRQ,
617         },
618 };
619
620 static struct platform_device tegra_rtc_device = {
621         .name = "tegra_rtc",
622         .id   = -1,
623         .resource = tegra_rtc_resources,
624         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
625 };
626
627 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
628         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
629         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
630         .gpio_hp_mute           = -1,
631         .gpio_int_mic_en        = -1,
632         .gpio_ext_mic_en        = -1,
633 };
634
635 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
636         .gpio_spkr_en           = -1,
637         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
638         .gpio_hp_mute           = -1,
639         .gpio_int_mic_en        = -1,
640         .gpio_ext_mic_en        = -1,
641 };
642
643 static struct platform_device cardhu_audio_wm8903_device = {
644         .name   = "tegra-snd-wm8903",
645         .id     = 0,
646         .dev    = {
647                 .platform_data = &cardhu_audio_wm8903_pdata,
648         },
649 };
650
651 static struct platform_device cardhu_audio_max98095_device = {
652         .name   = "tegra-snd-max98095",
653         .id     = 0,
654         .dev    = {
655                 .platform_data = &cardhu_audio_max98095_pdata,
656         },
657 };
658
659 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
660         .gpio_spkr_en           = -1,
661         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
662         .gpio_hp_mute           = -1,
663         .gpio_int_mic_en        = -1,
664         .gpio_ext_mic_en        = -1,
665         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
666         .audio_port_id          = {
667                 [HIFI_CODEC] = 0,
668                 [BASEBAND] = -1,
669                 [BT_SCO] = 3,
670         },
671         .baseband_param         = {
672                 .rate = -1,
673                 .channels = -1,
674         },
675 };
676
677 static struct platform_device cardhu_audio_aic326x_device = {
678         .name   = "tegra-snd-aic326x",
679         .id     = 0,
680         .dev    = {
681                 .platform_data  = &cardhu_audio_aic326x_pdata,
682         },
683 };
684
685 static struct platform_device *cardhu_devices[] __initdata = {
686         &tegra_pmu_device,
687         &tegra_rtc_device,
688         &tegra_udc_device,
689 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
690         &tegra_smmu_device,
691 #endif
692         &tegra_wdt_device,
693 #if defined(CONFIG_TEGRA_AVP)
694         &tegra_avp_device,
695 #endif
696         &tegra_camera,
697 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
698         &tegra_se_device,
699 #endif
700         &tegra_ahub_device,
701         &tegra_dam_device0,
702         &tegra_dam_device1,
703         &tegra_dam_device2,
704         &tegra_i2s_device0,
705         &tegra_i2s_device1,
706         &tegra_i2s_device3,
707         &tegra_spdif_device,
708         &spdif_dit_device,
709         &bluetooth_dit_device,
710         &baseband_dit_device,
711         &cardhu_bcm4329_rfkill_device,
712         &tegra_pcm_device,
713         &cardhu_audio_wm8903_device,
714         &cardhu_audio_max98095_device,
715         &cardhu_audio_aic326x_device,
716         &tegra_hda_device,
717 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
718         &tegra_aes_device,
719 #endif
720 };
721
722 #define MXT_CONFIG_CRC  0xD62DE8
723 static const u8 config[] = {
724         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
725         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
726         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
727         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
728         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
729         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
730         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
731         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
732         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
733         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
734         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
735         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
736         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
737         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
738         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
739         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
740         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
741         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
742         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
743         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
744 };
745
746 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
747 static const u8 config_sku2000[] = {
748         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
749         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
750         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
751         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
752         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
753         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
754         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
755         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
756         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
757         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
758         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
759         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
760         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
761         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
762         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
763         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
764         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
765         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
766         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
767         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
768 };
769
770 static struct mxt_platform_data atmel_mxt_info = {
771         .x_line         = 27,
772         .y_line         = 42,
773         .x_size         = 768,
774         .y_size         = 1366,
775         .blen           = 0x20,
776         .threshold      = 0x3C,
777         .voltage        = 3300000,              /* 3.3V */
778         .orient         = 5,
779         .config         = config,
780         .config_length  = 157,
781         .config_crc     = MXT_CONFIG_CRC,
782         .irqflags       = IRQF_TRIGGER_FALLING,
783 /*      .read_chg       = &read_chg, */
784         .read_chg       = NULL,
785 };
786
787 static struct i2c_board_info __initdata atmel_i2c_info[] = {
788         {
789                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
790                 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PH4),
791                 .platform_data = &atmel_mxt_info,
792         }
793 };
794
795 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
796         /* name         parent          rate            enabled */
797         { "sbc1",       "pll_p",        52000000,       true},
798         { NULL,         NULL,           0,              0},
799 };
800
801 static int __init cardhu_touch_init(void)
802 {
803         struct board_info BoardInfo;
804
805         tegra_get_display_board_info(&BoardInfo);
806         if (BoardInfo.board_id == BOARD_DISPLAY_PM313) {
807                 tegra_clk_init_from_table(spi_clk_init_table);
808
809                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
810         } else {
811                 tegra_gpio_enable(TEGRA_GPIO_PH4);
812                 tegra_gpio_enable(TEGRA_GPIO_PH6);
813
814                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
815                 gpio_direction_input(TEGRA_GPIO_PH4);
816
817                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
818                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
819                 msleep(1);
820                 gpio_set_value(TEGRA_GPIO_PH6, 1);
821                 msleep(100);
822
823                 tegra_get_board_info(&BoardInfo);
824                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
825                         atmel_mxt_info.config = config_sku2000;
826                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
827                 }
828
829                 i2c_register_board_info(1, atmel_i2c_info, 1);
830         }
831
832         return 0;
833 }
834
835 static void cardu_usb_hsic_postsupend(void)
836 {
837 #ifdef CONFIG_TEGRA_BB_XMM_POWER
838         baseband_xmm_set_power_status(BBXMM_PS_L2);
839 #endif
840 }
841
842 static void cardu_usb_hsic_preresume(void)
843 {
844 #ifdef CONFIG_TEGRA_BB_XMM_POWER
845         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
846 #endif
847 }
848
849 static void cardu_usb_hsic_phy_ready(void)
850 {
851 #ifdef CONFIG_TEGRA_BB_XMM_POWER
852         baseband_xmm_set_power_status(BBXMM_PS_L0);
853 #endif
854 }
855
856 static void cardu_usb_hsic_phy_off(void)
857 {
858 #ifdef CONFIG_TEGRA_BB_XMM_POWER
859         baseband_xmm_set_power_status(BBXMM_PS_L3);
860 #endif
861 }
862
863 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
864         .post_suspend = cardu_usb_hsic_postsupend,
865         .pre_resume = cardu_usb_hsic_preresume,
866         .port_power = cardu_usb_hsic_phy_ready,
867         .post_phy_off = cardu_usb_hsic_phy_off,
868 };
869
870 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
871         .port_otg = false,
872         .has_hostpc = true,
873         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
874         .op_mode        = TEGRA_USB_OPMODE_HOST,
875         .u_data.host = {
876                 .vbus_gpio = -1,
877                 .hot_plug = false,
878                 .remote_wakeup_supported = false,
879                 .power_off_on_suspend = false,
880         },
881         .u_cfg.hsic = {
882                 .sync_start_delay = 9,
883                 .idle_wait_delay = 17,
884                 .term_range_adj = 0,
885                 .elastic_underrun_limit = 16,
886                 .elastic_overrun_limit = 16,
887         },
888         .ops = &hsic_xmm_plat_ops,
889 };
890
891
892 static int hsic_enable_gpio = -1;
893 static int hsic_reset_gpio = -1;
894
895 void hsic_platform_open(void)
896 {
897         int reset_gpio = 0, enable_gpio = 0;
898
899         if (hsic_enable_gpio != -1)
900                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
901         if (hsic_reset_gpio != -1)
902                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
903         /* hsic enable signal deasserted, hsic reset asserted */
904         if (!enable_gpio)
905                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
906         if (!reset_gpio)
907                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
908         if (!enable_gpio)
909                 tegra_gpio_enable(hsic_enable_gpio);
910         if (!reset_gpio)
911                 tegra_gpio_enable(hsic_reset_gpio);
912         /* keep hsic reset asserted for 1 ms */
913         udelay(1000);
914         /* enable (power on) hsic */
915         if (!enable_gpio)
916                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
917         udelay(1000);
918         /* deassert reset */
919         if (!reset_gpio)
920                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
921
922 }
923
924 void hsic_platform_close(void)
925 {
926         if (hsic_enable_gpio != -1) {
927                 gpio_set_value(hsic_enable_gpio, 0);
928                 gpio_free(hsic_enable_gpio);
929         }
930         if (hsic_reset_gpio != -1) {
931                 gpio_set_value(hsic_reset_gpio, 0);
932                 gpio_free(hsic_reset_gpio);
933         }
934 }
935
936 void hsic_power_on(void)
937 {
938         if (hsic_enable_gpio != -1) {
939                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
940                 udelay(1000);
941         }
942 }
943
944 void hsic_power_off(void)
945 {
946         if (hsic_enable_gpio != -1) {
947                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
948                 udelay(1000);
949         }
950 }
951
952 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
953         .open = hsic_platform_open,
954         .close = hsic_platform_close,
955         .pre_phy_on = hsic_power_on,
956         .post_phy_off = hsic_power_off,
957 };
958
959 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
960         .port_otg = false,
961         .has_hostpc = true,
962         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
963         .op_mode        = TEGRA_USB_OPMODE_HOST,
964         .u_data.host = {
965                 .vbus_gpio = -1,
966                 .hot_plug = false,
967                 .remote_wakeup_supported = false,
968                 .power_off_on_suspend = false,
969         },
970         .u_cfg.hsic = {
971                 .sync_start_delay = 9,
972                 .idle_wait_delay = 17,
973                 .term_range_adj = 0,
974                 .elastic_underrun_limit = 16,
975                 .elastic_overrun_limit = 16,
976         },
977         .ops = &hsic_plat_ops,
978 };
979
980 static struct tegra_usb_platform_data tegra_udc_pdata = {
981         .port_otg = true,
982         .has_hostpc = true,
983         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
984         .op_mode = TEGRA_USB_OPMODE_DEVICE,
985         .u_data.dev = {
986                 .vbus_pmu_irq = 0,
987                 .vbus_gpio = -1,
988                 .charging_supported = false,
989                 .remote_wakeup_supported = false,
990         },
991         .u_cfg.utmi = {
992                 .hssync_start_delay = 0,
993                 .elastic_limit = 16,
994                 .idle_wait_delay = 17,
995                 .term_range_adj = 6,
996                 .xcvr_setup = 8,
997                 .xcvr_lsfslew = 2,
998                 .xcvr_lsrslew = 2,
999                 .xcvr_setup_offset = 0,
1000                 .xcvr_use_fuses = 1,
1001         },
1002 };
1003
1004 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1005         .port_otg = true,
1006         .has_hostpc = true,
1007         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1008         .op_mode = TEGRA_USB_OPMODE_HOST,
1009         .u_data.host = {
1010                 .vbus_gpio = -1,
1011                 .vbus_reg = "vdd_vbus_micro_usb",
1012                 .hot_plug = true,
1013                 .remote_wakeup_supported = true,
1014                 .power_off_on_suspend = true,
1015         },
1016         .u_cfg.utmi = {
1017                 .hssync_start_delay = 0,
1018                 .elastic_limit = 16,
1019                 .idle_wait_delay = 17,
1020                 .term_range_adj = 6,
1021                 .xcvr_setup = 15,
1022                 .xcvr_lsfslew = 2,
1023                 .xcvr_lsrslew = 2,
1024                 .xcvr_setup_offset = 0,
1025                 .xcvr_use_fuses = 1,
1026         },
1027 };
1028
1029 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1030         .port_otg = false,
1031         .has_hostpc = true,
1032         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1033         .op_mode        = TEGRA_USB_OPMODE_HOST,
1034         .u_data.host = {
1035                 .vbus_gpio = -1,
1036                 .hot_plug = true,
1037                 .remote_wakeup_supported = true,
1038                 .power_off_on_suspend = true,
1039         },
1040         .u_cfg.utmi = {
1041                 .hssync_start_delay = 0,
1042                 .elastic_limit = 16,
1043                 .idle_wait_delay = 17,
1044                 .term_range_adj = 6,
1045                 .xcvr_setup = 15,
1046                 .xcvr_lsfslew = 2,
1047                 .xcvr_lsrslew = 2,
1048                 .xcvr_setup_offset = 0,
1049                 .xcvr_use_fuses = 1,
1050         },
1051 };
1052
1053 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1054         .port_otg = false,
1055         .has_hostpc = true,
1056         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1057         .op_mode        = TEGRA_USB_OPMODE_HOST,
1058         .u_data.host = {
1059                 .vbus_gpio = -1,
1060                 .vbus_reg = "vdd_vbus_typea_usb",
1061                 .hot_plug = true,
1062                 .remote_wakeup_supported = true,
1063                 .power_off_on_suspend = true,
1064         },
1065         .u_cfg.utmi = {
1066                 .hssync_start_delay = 0,
1067                 .elastic_limit = 16,
1068                 .idle_wait_delay = 17,
1069                 .term_range_adj = 6,
1070                 .xcvr_setup = 8,
1071                 .xcvr_lsfslew = 2,
1072                 .xcvr_lsrslew = 2,
1073                 .xcvr_setup_offset = 0,
1074                 .xcvr_use_fuses = 1,
1075         },
1076 };
1077
1078 static struct tegra_usb_otg_data tegra_otg_pdata = {
1079         .ehci_device = &tegra_ehci1_device,
1080         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1081 };
1082
1083 #if CONFIG_USB_SUPPORT
1084 static void cardhu_usb_init(void)
1085 {
1086         struct board_info bi;
1087
1088         tegra_get_board_info(&bi);
1089
1090         /* OTG should be the first to be registered */
1091         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1092         platform_device_register(&tegra_otg_device);
1093
1094         /* setup the udc platform data */
1095         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1096
1097         if (bi.board_id == BOARD_PM267) {
1098                 hsic_enable_gpio = EN_HSIC_GPIO;
1099                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1100                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1101                 platform_device_register(&tegra_ehci2_device);
1102         } else if (bi.board_id == BOARD_E1256) {
1103                 hsic_enable_gpio = EN_HSIC_GPIO;
1104                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1105                 platform_device_register(&tegra_ehci2_device);
1106         } else if (bi.board_id == BOARD_E1186) {
1107                 tegra_ehci2_device.dev.platform_data =
1108                                                 &tegra_ehci2_hsic_xmm_pdata;
1109                 /* ehci2 registration happens in baseband-xmm-power  */
1110         } else {
1111                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1112                 platform_device_register(&tegra_ehci2_device);
1113         }
1114
1115         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1116         platform_device_register(&tegra_ehci3_device);
1117
1118 }
1119 #else
1120 static void cardhu_usb_init(void) { }
1121 #endif
1122
1123 static void cardhu_gps_init(void)
1124 {
1125         tegra_gpio_enable(TEGRA_GPIO_PU2);
1126         tegra_gpio_enable(TEGRA_GPIO_PU3);
1127 }
1128
1129 static void cardhu_nfc_init(void)
1130 {
1131         tegra_gpio_enable(TEGRA_GPIO_PX0);
1132         tegra_gpio_enable(TEGRA_GPIO_PP3);
1133         tegra_gpio_enable(TEGRA_GPIO_PO7);
1134 }
1135
1136 static struct baseband_power_platform_data tegra_baseband_power_data = {
1137         .baseband_type = BASEBAND_XMM,
1138         .modem = {
1139         .xmm = {
1140                         .bb_rst = XMM_GPIO_BB_RST,
1141                         .bb_on = XMM_GPIO_BB_ON,
1142                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1143                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1144                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1145                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1146                         .hsic_device = &tegra_ehci2_device,
1147                 },
1148         },
1149 };
1150
1151 static struct platform_device tegra_baseband_power_device = {
1152         .name = "baseband_xmm_power",
1153         .id = -1,
1154         .dev = {
1155                 .platform_data = &tegra_baseband_power_data,
1156         },
1157 };
1158
1159 static struct platform_device tegra_baseband_power2_device = {
1160         .name = "baseband_xmm_power2",
1161         .id = -1,
1162         .dev = {
1163                 .platform_data = &tegra_baseband_power_data,
1164         },
1165 };
1166
1167
1168 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1169         .port_status[0] = 1,
1170         .port_status[1] = 1,
1171         .port_status[2] = 1,
1172         .use_dock_detect        = 0,
1173         .gpio           = 0,
1174 };
1175
1176 static void cardhu_pci_init(void)
1177 {
1178         struct board_info board_info;
1179
1180         tegra_get_board_info(&board_info);
1181         if (board_info.board_id == BOARD_E1291) {
1182                 cardhu_pci_platform_data.port_status[0] = 0;
1183                 cardhu_pci_platform_data.port_status[1] = 0;
1184                 cardhu_pci_platform_data.port_status[2] = 1;
1185                 cardhu_pci_platform_data.use_dock_detect = 1;
1186                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1187         }
1188         if ((board_info.board_id == BOARD_E1186) ||
1189                 (board_info.board_id == BOARD_E1187) ||
1190                 (board_info.board_id == BOARD_E1291)) {
1191                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1192                 platform_device_register(&tegra_pci_device);
1193         }
1194 }
1195
1196 static void cardhu_modem_init(void)
1197 {
1198         struct board_info board_info;
1199         int w_disable_gpio, ret;
1200
1201         tegra_get_board_info(&board_info);
1202         switch (board_info.board_id) {
1203         case BOARD_E1291:
1204         case BOARD_E1198:
1205                 if (((board_info.board_id == BOARD_E1291) &&
1206                                 (board_info.fab < BOARD_FAB_A03)) ||
1207                         ((board_info.board_id == BOARD_E1198) &&
1208                                         (board_info.fab < BOARD_FAB_A02))) {
1209                         w_disable_gpio = TEGRA_GPIO_PH5;
1210                 } else {
1211                         w_disable_gpio = TEGRA_GPIO_PDD5;
1212                 }
1213                 tegra_gpio_enable(w_disable_gpio);
1214                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1215                 if (ret < 0)
1216                         pr_err("%s: gpio_request failed for gpio %d\n",
1217                                 __func__, w_disable_gpio);
1218                 else
1219                         gpio_direction_input(w_disable_gpio);
1220
1221                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1222                 if (((board_info.board_id == BOARD_E1291) &&
1223                                 (board_info.fab >= BOARD_FAB_A04)) ||
1224                         ((board_info.board_id == BOARD_E1198) &&
1225                                         (board_info.fab >= BOARD_FAB_A02))) {
1226                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1227                         if (ret < 0) {
1228                                 pr_err("%s(): Error in allocating gpio "
1229                                         "TEGRA_GPIO_PH7\n", __func__);
1230                                 break;
1231                         }
1232                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1233                         tegra_gpio_enable(TEGRA_GPIO_PH7);
1234                 }
1235                 break;
1236         case BOARD_E1186:
1237                 tegra_gpio_enable(
1238                         tegra_baseband_power_data.modem.xmm.bb_rst);
1239                 tegra_gpio_enable(
1240                         tegra_baseband_power_data.modem.xmm.bb_on);
1241                 tegra_gpio_enable(
1242                         tegra_baseband_power_data.modem.xmm.ipc_bb_wake);
1243                 tegra_gpio_enable(
1244                         tegra_baseband_power_data.modem.xmm.ipc_ap_wake);
1245                 tegra_gpio_enable(
1246                         tegra_baseband_power_data.modem.xmm.ipc_hsic_active);
1247                 tegra_gpio_enable(
1248                         tegra_baseband_power_data.modem.xmm.ipc_hsic_sus_req);
1249                 platform_device_register(&tegra_baseband_power_device);
1250                 platform_device_register(&tegra_baseband_power2_device);
1251                 break;
1252         default:
1253                 break;
1254         }
1255
1256 }
1257
1258 #ifdef CONFIG_SATA_AHCI_TEGRA
1259 static void cardhu_sata_init(void)
1260 {
1261         platform_device_register(&tegra_sata_device);
1262 }
1263 #else
1264 static void cardhu_sata_init(void) { }
1265 #endif
1266
1267 static void __init tegra_cardhu_init(void)
1268 {
1269         tegra_thermal_init(&thermal_data);
1270         tegra_clk_init_from_table(cardhu_clk_init_table);
1271         cardhu_pinmux_init();
1272         cardhu_i2c_init();
1273         cardhu_spi_init();
1274         cardhu_usb_init();
1275 #ifdef CONFIG_TEGRA_EDP_LIMITS
1276         cardhu_edp_init();
1277 #endif
1278         cardhu_uart_init();
1279         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1280         tegra_ram_console_debug_init();
1281         cardhu_sdhci_init();
1282         cardhu_regulator_init();
1283         cardhu_dtv_init();
1284         cardhu_suspend_init();
1285         cardhu_touch_init();
1286         cardhu_gps_init();
1287         cardhu_modem_init();
1288         cardhu_kbc_init();
1289         cardhu_scroll_init();
1290         cardhu_keys_init();
1291         cardhu_panel_init();
1292         cardhu_pmon_init();
1293         cardhu_sensors_init();
1294         cardhu_setup_bluesleep();
1295         cardhu_sata_init();
1296         //audio_wired_jack_init();
1297         cardhu_pins_state_init();
1298         cardhu_emc_init();
1299         tegra_release_bootloader_fb();
1300         cardhu_nfc_init();
1301         cardhu_pci_init();
1302 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1303         tegra_wdt_recovery_init();
1304 #endif
1305 }
1306
1307 static void __init tegra_cardhu_reserve(void)
1308 {
1309 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1310         /* support 1920X1200 with 24bpp */
1311         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1312 #else
1313         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1314 #endif
1315         tegra_ram_console_debug_reserve(SZ_1M);
1316 }
1317
1318 MACHINE_START(CARDHU, "cardhu")
1319         .boot_params    = 0x80000100,
1320         .map_io         = tegra_map_common_io,
1321         .reserve        = tegra_cardhu_reserve,
1322         .init_early     = tegra_init_early,
1323         .init_irq       = tegra_init_irq,
1324         .timer          = &tegra_timer,
1325         .init_machine   = tegra_cardhu_init,
1326 MACHINE_END