462f8c025c2d49ccfbbe6ec420edcbd5ee01264e
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/clk.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/iomap.h>
55 #include <mach/io.h>
56 #include <mach/i2s.h>
57 #include <mach/tegra_asoc_pdata.h>
58 #include <mach/tegra_wm8903_pdata.h>
59 #include <mach/usb_phy.h>
60 #include <mach/thermal.h>
61 #include <mach/pci.h>
62 #include <mach/gpio-tegra.h>
63 #include <mach/tegra_fiq_debugger.h>
64
65 #include <asm/hardware/gic.h>
66 #include <asm/mach-types.h>
67 #include <asm/mach/arch.h>
68
69 #include "board.h"
70 #include "clock.h"
71 #include "board-cardhu.h"
72 #include "board-touch.h"
73 #include "devices.h"
74 #include "gpio-names.h"
75 #include "fuse.h"
76 #include "pm.h"
77 #include "baseband-xmm-power.h"
78 #include "wdt-recovery.h"
79 #include "common.h"
80
81 static struct balanced_throttle throttle_list[] = {
82 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
83         {
84                 .id = BALANCED_THROTTLE_ID_TJ,
85                 .throt_tab_size = 10,
86                 .throt_tab = {
87                         {      0, 1000 },
88                         { 640000, 1000 },
89                         { 640000, 1000 },
90                         { 640000, 1000 },
91                         { 640000, 1000 },
92                         { 640000, 1000 },
93                         { 760000, 1000 },
94                         { 760000, 1050 },
95                         {1000000, 1050 },
96                         {1000000, 1100 },
97                 },
98         },
99 #endif
100 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
101         {
102                 .id = BALANCED_THROTTLE_ID_SKIN,
103                 .throt_tab_size = 6,
104                 .throt_tab = {
105                         { 640000, 1200 },
106                         { 640000, 1200 },
107                         { 760000, 1200 },
108                         { 760000, 1200 },
109                         {1000000, 1200 },
110                         {1000000, 1200 },
111                 },
112         },
113 #endif
114 };
115
116 /* All units are in millicelsius */
117 static struct tegra_thermal_data thermal_data = {
118         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
119         .temp_shutdown = 90000,
120
121 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
122         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
123 #endif
124 #ifdef CONFIG_TEGRA_EDP_LIMITS
125         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
126         .hysteresis_edp = 3000,
127 #endif
128 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
129         .temp_throttle = 85000,
130         .tc1 = 0,
131         .tc2 = 1,
132         .passive_delay = 2000,
133 #endif
134 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
135         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
136         .temp_throttle_skin = 43000,
137         .tc1_skin = 0,
138         .tc2_skin = 1,
139         .passive_delay_skin = 5000,
140
141         .skin_temp_offset = 9793,
142         .skin_period = 1100,
143         .skin_devs_size = 2,
144         .skin_devs = {
145                 {
146                         THERMAL_DEVICE_ID_NCT_EXT,
147                         {
148                                 2, 1, 1, 1,
149                                 1, 1, 1, 1,
150                                 1, 1, 1, 0,
151                                 1, 1, 0, 0,
152                                 0, 0, -1, -7
153                         }
154                 },
155                 {
156                         THERMAL_DEVICE_ID_NCT_INT,
157                         {
158                                 -11, -7, -5, -3,
159                                 -3, -2, -1, 0,
160                                 0, 0, 1, 1,
161                                 1, 2, 2, 3,
162                                 4, 6, 11, 18
163                         }
164                 },
165         },
166 #endif
167 };
168
169 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
170         {
171                 .name           = "bt_rfkill",
172                 .shutdown_gpio  = TEGRA_GPIO_PU0,
173                 .reset_gpio     = TEGRA_GPIO_INVALID,
174                 .type           = RFKILL_TYPE_BLUETOOTH,
175         },
176 };
177
178 static struct platform_device cardhu_bt_rfkill_device = {
179         .name = "rfkill_gpio",
180         .id             = -1,
181         .dev = {
182                 .platform_data = &cardhu_bt_rfkill_pdata,
183         },
184 };
185
186 static struct resource cardhu_bluesleep_resources[] = {
187         [0] = {
188                 .name = "gpio_host_wake",
189                         .start  = TEGRA_GPIO_PU6,
190                         .end    = TEGRA_GPIO_PU6,
191                         .flags  = IORESOURCE_IO,
192         },
193         [1] = {
194                 .name = "gpio_ext_wake",
195                         .start  = TEGRA_GPIO_PU1,
196                         .end    = TEGRA_GPIO_PU1,
197                         .flags  = IORESOURCE_IO,
198         },
199         [2] = {
200                 .name = "host_wake",
201                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
202         },
203 };
204
205 static struct platform_device cardhu_bluesleep_device = {
206         .name           = "bluesleep",
207         .id             = -1,
208         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
209         .resource       = cardhu_bluesleep_resources,
210 };
211
212 static noinline void __init cardhu_setup_bluesleep(void)
213 {
214         cardhu_bluesleep_resources[2].start =
215                 cardhu_bluesleep_resources[2].end =
216                         gpio_to_irq(TEGRA_GPIO_PU6);
217         platform_device_register(&cardhu_bluesleep_device);
218         return;
219 }
220
221 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
222         /* name         parent          rate            enabled */
223         { "pll_m",      NULL,           0,              false},
224         { "hda",        "pll_p",        108000000,      false},
225         { "hda2codec_2x","pll_p",       48000000,       false},
226         { "pwm",        "pll_p",        3187500,        false},
227         { "blink",      "clk_32k",      32768,          true},
228         { "i2s0",       "pll_a_out0",   0,              false},
229         { "i2s1",       "pll_a_out0",   0,              false},
230         { "i2s3",       "pll_a_out0",   0,              false},
231         { "spdif_out",  "pll_a_out0",   0,              false},
232         { "d_audio",    "clk_m",        12000000,       false},
233         { "dam0",       "clk_m",        12000000,       false},
234         { "dam1",       "clk_m",        12000000,       false},
235         { "dam2",       "clk_m",        12000000,       false},
236         { "audio1",     "i2s1_sync",    0,              false},
237         { "audio3",     "i2s3_sync",    0,              false},
238         { "vi_sensor",  "pll_p",        150000000,      false},
239         { "i2c1",       "pll_p",        3200000,        false},
240         { "i2c2",       "pll_p",        3200000,        false},
241         { "i2c3",       "pll_p",        3200000,        false},
242         { "i2c4",       "pll_p",        3200000,        false},
243         { "i2c5",       "pll_p",        3200000,        false},
244         { NULL,         NULL,           0,              0},
245 };
246
247 static struct pn544_i2c_platform_data nfc_pdata = {
248         .irq_gpio = TEGRA_GPIO_PX0,
249         .ven_gpio = TEGRA_GPIO_PP3,
250         .firm_gpio = TEGRA_GPIO_PO7,
251         };
252
253 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
254         {
255                 I2C_BOARD_INFO("pn544", 0x28),
256                 .platform_data = &nfc_pdata,
257         },
258 };
259 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
260         .adapter_nr     = 0,
261         .bus_count      = 1,
262         .bus_clk_rate   = { 100000, 0 },
263         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
264         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
265         .arb_recovery = arb_lost_recovery,
266 };
267
268 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
269         .adapter_nr     = 1,
270         .bus_count      = 1,
271         .bus_clk_rate   = { 400000, 0 },
272         .is_clkon_always = true,
273         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
274         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
275         .arb_recovery = arb_lost_recovery,
276 };
277
278 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
279         .adapter_nr     = 2,
280         .bus_count      = 1,
281         .bus_clk_rate   = { 100000, 0 },
282         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
283         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
284         .arb_recovery = arb_lost_recovery,
285 };
286
287 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
288         .adapter_nr     = 3,
289         .bus_count      = 1,
290         .bus_clk_rate   = { 10000, 0 },
291         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
292         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
293         .arb_recovery = arb_lost_recovery,
294 };
295
296 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
297         .adapter_nr     = 4,
298         .bus_count      = 1,
299         .bus_clk_rate   = { 400000, 0 },
300         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
301         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
302         .arb_recovery = arb_lost_recovery,
303 };
304
305
306 #if 0
307 struct tegra_wired_jack_conf audio_wr_jack_conf = {
308         .hp_det_n = TEGRA_GPIO_PW2,
309         .en_mic_ext = TEGRA_GPIO_PX1,
310         .en_mic_int = TEGRA_GPIO_PX0,
311 };
312 #endif
313
314 static struct wm8903_platform_data cardhu_wm8903_pdata = {
315         .irq_active_low = 0,
316         .micdet_cfg = 0,
317         .micdet_delay = 100,
318         .gpio_base = CARDHU_GPIO_WM8903(0),
319         .gpio_cfg = {
320                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
321                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
322                         WM8903_GP2_DIR,
323                 WM8903_GPIO_CONFIG_ZERO,
324                 0,
325                 0,
326         },
327 };
328
329 /* Equalizer filter coefs generated from the MAXIM MAX98095
330  * evkit software tool */
331 static struct max98095_eq_cfg max98095_eq_cfg[] = {
332         {
333                 .name = "FLAT",
334                 .rate = 44100,
335                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
336                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
337                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
338                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
339                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
340         },
341         {
342                 .name = "LOWPASS1K",
343                 .rate = 44100,
344                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
345                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
346                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
347                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
348                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
349         },
350         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
351                 .name = "HIBOOST",
352                 .rate = 44100,
353                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
354                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
355                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
356                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
357                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
358         },
359         { /* BASS=12dB, TREBLE=+12dB */
360                 .name = "LOUD12DB",
361                 .rate = 44100,
362                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
363                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
364                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
365                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
366                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
367         },
368         {
369                 .name = "FLAT",
370                 .rate = 16000,
371                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
372                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
373                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
374                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
375                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
376         },
377         {
378                 .name = "LOWPASS1K",
379                 .rate = 16000,
380                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
381                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
382                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
383                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
384                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
385         },
386         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
387                 .name = "HIBOOST",
388                 .rate = 16000,
389                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
390                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
391                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
392                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
393                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
394         },
395         { /* BASS=12dB, TREBLE=+12dB */
396                 .name = "LOUD12DB",
397                 .rate = 16000,
398                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
399                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
400                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
401                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
402                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
403         },
404 };
405
406 static struct max98095_pdata cardhu_max98095_pdata = {
407         /* equalizer configuration */
408         .eq_cfg = max98095_eq_cfg,
409         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
410
411         /* Biquad filter response configuration */
412         .bq_cfg = NULL,
413         .bq_cfgcnt = 0,
414
415         /* microphone configuration */
416         .digmic_left_mode = 1,
417         .digmic_right_mode = 1,
418 };
419
420 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
421         I2C_BOARD_INFO("wm8903", 0x1a),
422         .platform_data = &cardhu_wm8903_pdata,
423 };
424
425 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
426         I2C_BOARD_INFO("aic3262-codec", 0x18),
427 };
428
429 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
430         I2C_BOARD_INFO("max98095", 0x10),
431         .platform_data = &cardhu_max98095_pdata,
432 };
433
434 static void cardhu_i2c_init(void)
435 {
436         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
437         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
438         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
439         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
440         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
441
442         platform_device_register(&tegra_i2c_device5);
443         platform_device_register(&tegra_i2c_device4);
444         platform_device_register(&tegra_i2c_device3);
445         platform_device_register(&tegra_i2c_device2);
446         platform_device_register(&tegra_i2c_device1);
447
448         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
449                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
450         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
451         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
452         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
453
454         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
455         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
456 }
457
458 static struct platform_device *cardhu_uart_devices[] __initdata = {
459         &tegra_uarta_device,
460         &tegra_uartb_device,
461         &tegra_uartc_device,
462         &tegra_uartd_device,
463         &tegra_uarte_device,
464 };
465 static struct uart_clk_parent uart_parent_clk[] = {
466         [0] = {.name = "clk_m"},
467         [1] = {.name = "pll_p"},
468 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
469         [2] = {.name = "pll_m"},
470 #endif
471 };
472
473 static struct tegra_uart_platform_data cardhu_uart_pdata;
474 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
475
476 static void __init uart_debug_init(void)
477 {
478         struct board_info board_info;
479         int debug_port_id;
480
481         tegra_get_board_info(&board_info);
482
483         debug_port_id = get_tegra_uart_debug_port_id();
484         if (debug_port_id < 0) {
485                 debug_port_id = 0;
486                         /* UARTB is debug port
487                          *       for SLT - E1186/E1187/PM269
488                          *       for E1256/E1257
489                          */
490                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
491                         ((board_info.board_id == BOARD_E1186) ||
492                         (board_info.board_id == BOARD_E1187) ||
493                         (board_info.board_id == BOARD_PM269))) ||
494                         (board_info.board_id == BOARD_E1256) ||
495                         (board_info.board_id == BOARD_E1257))
496                                 debug_port_id = 1;
497         }
498
499         switch (debug_port_id) {
500         case 0:
501                 /* UARTA is the debug port. */
502                 pr_info("Selecting UARTA as the debug console\n");
503                 cardhu_uart_devices[0] = &debug_uarta_device;
504                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
505                 debug_uart_port_base = ((struct plat_serial8250_port *)(
506                         debug_uarta_device.dev.platform_data))->mapbase;
507                 break;
508
509         case 1:
510                 /* UARTB is the debug port. */
511                 pr_info("Selecting UARTB as the debug console\n");
512                 cardhu_uart_devices[1] = &debug_uartb_device;
513                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
514                 debug_uart_port_base = ((struct plat_serial8250_port *)(
515                         debug_uartb_device.dev.platform_data))->mapbase;
516                 break;
517
518         case 2:
519                 /* UARTC is the debug port. */
520                 pr_info("Selecting UARTC as the debug console\n");
521                 cardhu_uart_devices[2] = &debug_uartc_device;
522                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
523                 debug_uart_port_base = ((struct plat_serial8250_port *)(
524                         debug_uartc_device.dev.platform_data))->mapbase;
525                 break;
526
527         case 3:
528                 /* UARTD is the debug port. */
529                 pr_info("Selecting UARTD as the debug console\n");
530                 cardhu_uart_devices[3] = &debug_uartd_device;
531                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
532                 debug_uart_port_base = ((struct plat_serial8250_port *)(
533                         debug_uartd_device.dev.platform_data))->mapbase;
534                 break;
535
536         case 4:
537                 /* UARTE is the debug port. */
538                 pr_info("Selecting UARTE as the debug console\n");
539                 cardhu_uart_devices[4] = &debug_uarte_device;
540                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
541                 debug_uart_port_base = ((struct plat_serial8250_port *)(
542                         debug_uarte_device.dev.platform_data))->mapbase;
543                 break;
544
545         default:
546                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
547                 cardhu_uart_devices[0] = &debug_uarta_device;
548                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
549                 debug_uart_port_base = ((struct plat_serial8250_port *)(
550                         debug_uarta_device.dev.platform_data))->mapbase;
551                 break;
552         }
553         return;
554 }
555
556 static void __init cardhu_uart_init(void)
557 {
558         struct clk *c;
559         int i;
560
561         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
562                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
563                 if (IS_ERR_OR_NULL(c)) {
564                         pr_err("Not able to get the clock for %s\n",
565                                                 uart_parent_clk[i].name);
566                         continue;
567                 }
568                 uart_parent_clk[i].parent_clk = c;
569                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
570         }
571         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
572         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
573         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
574         cardhu_loopback_uart_pdata.parent_clk_count =
575                                                 ARRAY_SIZE(uart_parent_clk);
576         cardhu_loopback_uart_pdata.is_loopback = true;
577         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
578         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
579         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
580         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
581         /* UARTE is used for loopback test purpose */
582         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
583
584         /* Register low speed only if it is selected */
585         if (!is_tegra_debug_uartport_hs()) {
586                 uart_debug_init();
587                 /* Clock enable for the debug channel */
588                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
589                         pr_info("The debug console clock name is %s\n",
590                                                 debug_uart_clk->name);
591                         c = tegra_get_clock_by_name("pll_p");
592                         if (IS_ERR_OR_NULL(c))
593                                 pr_err("Not getting the parent clock pll_p\n");
594                         else
595                                 clk_set_parent(debug_uart_clk, c);
596
597                         clk_enable(debug_uart_clk);
598                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
599                 } else {
600                         pr_err("Not getting the clock %s for debug console\n",
601                                         debug_uart_clk->name);
602                 }
603         }
604
605         platform_add_devices(cardhu_uart_devices,
606                                 ARRAY_SIZE(cardhu_uart_devices));
607 }
608
609 static struct platform_device tegra_camera = {
610         .name = "tegra_camera",
611         .id = -1,
612 };
613
614 static struct platform_device *cardhu_spi_devices[] __initdata = {
615         &tegra_spi_device4,
616 };
617
618 static struct platform_device *touch_spi_device[] __initdata = {
619         &tegra_spi_device1,
620 };
621
622 struct spi_clk_parent spi_parent_clk[] = {
623         [0] = {.name = "pll_p"},
624 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
625         [1] = {.name = "pll_m"},
626         [2] = {.name = "clk_m"},
627 #else
628         [1] = {.name = "clk_m"},
629 #endif
630 };
631
632 static struct tegra_spi_platform_data cardhu_spi_pdata = {
633         .is_dma_based           = true,
634         .max_dma_buffer         = (16 * 1024),
635         .is_clkon_always        = false,
636         .max_rate               = 100000000,
637 };
638
639 static void __init cardhu_spi_init(void)
640 {
641         int i;
642         struct clk *c;
643         struct board_info board_info, display_board_info;
644
645         tegra_get_board_info(&board_info);
646         tegra_get_display_board_info(&display_board_info);
647
648         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
649                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
650                 if (IS_ERR_OR_NULL(c)) {
651                         pr_err("Not able to get the clock for %s\n",
652                                                 spi_parent_clk[i].name);
653                         continue;
654                 }
655                 spi_parent_clk[i].parent_clk = c;
656                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
657         }
658         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
659         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
660         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
661         platform_add_devices(cardhu_spi_devices,
662                                 ARRAY_SIZE(cardhu_spi_devices));
663
664         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
665                 platform_add_devices(touch_spi_device,
666                                 ARRAY_SIZE(touch_spi_device));
667         }
668         if (board_info.board_id == BOARD_E1198) {
669                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
670                 platform_device_register(&tegra_spi_device2);
671                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
672                 platform_device_register(&tegra_spi_slave_device1);
673         }
674 }
675
676 static void __init cardhu_dtv_init(void)
677 {
678         struct board_info board_info;
679
680         tegra_get_board_info(&board_info);
681
682         if (board_info.board_id == BOARD_E1186)
683                 platform_device_register(&tegra_dtv_device);
684 }
685
686 static struct resource tegra_rtc_resources[] = {
687         [0] = {
688                 .start = TEGRA_RTC_BASE,
689                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
690                 .flags = IORESOURCE_MEM,
691         },
692         [1] = {
693                 .start = INT_RTC,
694                 .end = INT_RTC,
695                 .flags = IORESOURCE_IRQ,
696         },
697 };
698
699 static struct platform_device tegra_rtc_device = {
700         .name = "tegra_rtc",
701         .id   = -1,
702         .resource = tegra_rtc_resources,
703         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
704 };
705
706 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
707         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
708         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
709         .gpio_hp_mute           = -1,
710         .gpio_int_mic_en        = -1,
711         .gpio_ext_mic_en        = -1,
712 };
713
714 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
715         .gpio_spkr_en           = -1,
716         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
717         .gpio_hp_mute           = -1,
718         .gpio_int_mic_en        = -1,
719         .gpio_ext_mic_en        = -1,
720 };
721
722 static struct platform_device cardhu_audio_wm8903_device = {
723         .name   = "tegra-snd-wm8903",
724         .id     = 0,
725         .dev    = {
726                 .platform_data = &cardhu_audio_wm8903_pdata,
727         },
728 };
729
730 static struct platform_device cardhu_audio_max98095_device = {
731         .name   = "tegra-snd-max98095",
732         .id     = 0,
733         .dev    = {
734                 .platform_data = &cardhu_audio_max98095_pdata,
735         },
736 };
737
738 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
739         .gpio_spkr_en           = -1,
740         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
741         .gpio_hp_mute           = -1,
742         .gpio_int_mic_en        = -1,
743         .gpio_ext_mic_en        = -1,
744         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
745         .audio_port_id          = {
746                 [HIFI_CODEC] = 0,
747                 [BASEBAND] = -1,
748                 [BT_SCO] = 3,
749         },
750         .baseband_param         = {
751                 .rate = -1,
752                 .channels = -1,
753         },
754 };
755
756 static struct platform_device cardhu_audio_aic326x_device = {
757         .name   = "tegra-snd-aic326x",
758         .id     = 0,
759         .dev    = {
760                 .platform_data  = &cardhu_audio_aic326x_pdata,
761         },
762 };
763
764 static struct platform_device *cardhu_devices[] __initdata = {
765         &tegra_pmu_device,
766         &tegra_rtc_device,
767         &tegra_udc_device,
768 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
769         &tegra_smmu_device,
770 #endif
771         &tegra_wdt0_device,
772         &tegra_wdt1_device,
773         &tegra_wdt2_device,
774 #if defined(CONFIG_TEGRA_AVP)
775         &tegra_avp_device,
776 #endif
777         &tegra_camera,
778 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
779         &tegra_se_device,
780 #endif
781         &tegra_ahub_device,
782         &tegra_dam_device0,
783         &tegra_dam_device1,
784         &tegra_dam_device2,
785         &tegra_i2s_device0,
786         &tegra_i2s_device1,
787         &tegra_i2s_device3,
788         &tegra_spdif_device,
789         &spdif_dit_device,
790         &bluetooth_dit_device,
791         &baseband_dit_device,
792         &cardhu_bt_rfkill_device,
793         &tegra_pcm_device,
794         &cardhu_audio_wm8903_device,
795         &cardhu_audio_max98095_device,
796         &cardhu_audio_aic326x_device,
797         &tegra_hda_device,
798         &tegra_cec_device,
799 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
800         &tegra_aes_device,
801 #endif
802 };
803
804 #define E1506_MXT_CONFIG_CRC 0x62F903
805 static const u8 e1506_config[] = {
806         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
807         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
808         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
809         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
810         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
811         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
812         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
813         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
814         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
815         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
816         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
817         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
818         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
819         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
820         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
821         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
822         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
823         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
824         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
825         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
826         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
827         0x00
828 };
829
830 #define MXT_CONFIG_CRC  0xD62DE8
831 static const u8 config[] = {
832         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
833         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
834         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
835         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
836         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
837         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
838         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
839         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
842         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
843         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
844         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
845         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
846         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
847         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
850         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
852 };
853
854 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
855 static const u8 config_sku2000[] = {
856         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
857         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
858         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
859         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
860         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
861         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
862         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
863         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
867         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
868         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
869         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
870         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
871         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
876 };
877
878 static struct mxt_platform_data atmel_mxt_info = {
879         .x_line         = 27,
880         .y_line         = 42,
881         .x_size         = 768,
882         .y_size         = 1366,
883         .blen           = 0x20,
884         .threshold      = 0x3C,
885         .voltage        = 3300000,              /* 3.3V */
886         .orient         = 5,
887         .config         = config,
888         .config_length  = 157,
889         .config_crc     = MXT_CONFIG_CRC,
890         .irqflags       = IRQF_TRIGGER_FALLING,
891 /*      .read_chg       = &read_chg, */
892         .read_chg       = NULL,
893 };
894
895 static struct mxt_platform_data e1506_atmel_mxt_info = {
896         .x_line         = 19,
897         .y_line         = 11,
898         .x_size         = 960,
899         .y_size         = 540,
900         .blen           = 0x10,
901         .threshold      = 0x32,
902         .voltage        = 3300000,              /* 3.3V */
903         .orient         = 3,
904         .config         = e1506_config,
905         .config_length  = 168,
906         .config_crc     = E1506_MXT_CONFIG_CRC,
907         .irqflags       = IRQF_TRIGGER_FALLING,
908 /*      .read_chg       = &read_chg, */
909         .read_chg       = NULL,
910 };
911
912 static struct i2c_board_info __initdata atmel_i2c_info[] = {
913         {
914                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
915                 .platform_data = &atmel_mxt_info,
916         }
917 };
918
919 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
920         {
921                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
922                 .platform_data = &e1506_atmel_mxt_info,
923         }
924 };
925
926 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
927         /* name         parent          rate            enabled */
928         { "sbc1",       "pll_p",        52000000,       true},
929         { NULL,         NULL,           0,              0},
930 };
931
932 static int __init cardhu_touch_init(void)
933 {
934         struct board_info BoardInfo, DisplayBoardInfo;
935
936         tegra_get_board_info(&BoardInfo);
937         tegra_get_display_board_info(&DisplayBoardInfo);
938         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
939                 tegra_clk_init_from_table(spi_clk_init_table);
940
941                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
942         } else {
943                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
944                 gpio_direction_input(TEGRA_GPIO_PH4);
945
946                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
947                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
948                 msleep(1);
949                 gpio_set_value(TEGRA_GPIO_PH6, 1);
950                 msleep(100);
951
952                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
953                         atmel_mxt_info.config = config_sku2000;
954                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
955                 }
956
957                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
958                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
959                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
960                 } else {
961                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
962                         i2c_register_board_info(1, atmel_i2c_info, 1);
963                 }
964         }
965
966         return 0;
967 }
968
969 #if defined(CONFIG_USB_SUPPORT)
970
971 static void cardu_usb_hsic_postsupend(void)
972 {
973 #ifdef CONFIG_TEGRA_BB_XMM_POWER
974         baseband_xmm_set_power_status(BBXMM_PS_L2);
975 #endif
976 }
977
978 static void cardu_usb_hsic_preresume(void)
979 {
980 #ifdef CONFIG_TEGRA_BB_XMM_POWER
981         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
982 #endif
983 }
984
985 static void cardu_usb_hsic_phy_ready(void)
986 {
987 #ifdef CONFIG_TEGRA_BB_XMM_POWER
988         baseband_xmm_set_power_status(BBXMM_PS_L0);
989 #endif
990 }
991
992 static void cardu_usb_hsic_phy_off(void)
993 {
994 #ifdef CONFIG_TEGRA_BB_XMM_POWER
995         baseband_xmm_set_power_status(BBXMM_PS_L3);
996 #endif
997 }
998
999 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1000         .post_suspend = cardu_usb_hsic_postsupend,
1001         .pre_resume = cardu_usb_hsic_preresume,
1002         .port_power = cardu_usb_hsic_phy_ready,
1003         .post_phy_off = cardu_usb_hsic_phy_off,
1004 };
1005
1006 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1007         .port_otg = false,
1008         .has_hostpc = true,
1009         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1010         .op_mode        = TEGRA_USB_OPMODE_HOST,
1011         .u_data.host = {
1012                 .vbus_gpio = -1,
1013                 .hot_plug = false,
1014                 .remote_wakeup_supported = false,
1015                 .power_off_on_suspend = false,
1016         },
1017         .u_cfg.hsic = {
1018                 .sync_start_delay = 9,
1019                 .idle_wait_delay = 17,
1020                 .term_range_adj = 0,
1021                 .elastic_underrun_limit = 16,
1022                 .elastic_overrun_limit = 16,
1023         },
1024         .ops = &hsic_xmm_plat_ops,
1025 };
1026 #endif
1027
1028 static int hsic_enable_gpio = -1;
1029 static int hsic_reset_gpio = -1;
1030
1031 void hsic_platform_open(void)
1032 {
1033         int reset_gpio = 0, enable_gpio = 0;
1034
1035         if (hsic_enable_gpio != -1)
1036                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1037         if (hsic_reset_gpio != -1)
1038                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1039         /* hsic enable signal deasserted, hsic reset asserted */
1040         if (!enable_gpio)
1041                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1042         if (!reset_gpio)
1043                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1044         if (!enable_gpio)
1045                 tegra_gpio_enable(hsic_enable_gpio);
1046         if (!reset_gpio)
1047                 tegra_gpio_enable(hsic_reset_gpio);
1048         /* keep hsic reset asserted for 1 ms */
1049         udelay(1000);
1050         /* enable (power on) hsic */
1051         if (!enable_gpio)
1052                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1053         udelay(1000);
1054         /* deassert reset */
1055         if (!reset_gpio)
1056                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1057
1058 }
1059
1060 void hsic_platform_close(void)
1061 {
1062         if (hsic_enable_gpio != -1) {
1063                 gpio_set_value(hsic_enable_gpio, 0);
1064                 gpio_free(hsic_enable_gpio);
1065         }
1066         if (hsic_reset_gpio != -1) {
1067                 gpio_set_value(hsic_reset_gpio, 0);
1068                 gpio_free(hsic_reset_gpio);
1069         }
1070 }
1071
1072 void hsic_power_on(void)
1073 {
1074         if (hsic_enable_gpio != -1) {
1075                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1076                 udelay(1000);
1077         }
1078 }
1079
1080 void hsic_power_off(void)
1081 {
1082         if (hsic_enable_gpio != -1) {
1083                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1084                 udelay(1000);
1085         }
1086 }
1087
1088 #if defined(CONFIG_USB_SUPPORT)
1089 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1090         .open = hsic_platform_open,
1091         .close = hsic_platform_close,
1092         .pre_phy_on = hsic_power_on,
1093         .post_phy_off = hsic_power_off,
1094 };
1095
1096 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1097         .port_otg = false,
1098         .has_hostpc = true,
1099         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1100         .op_mode        = TEGRA_USB_OPMODE_HOST,
1101         .u_data.host = {
1102                 .vbus_gpio = -1,
1103                 .hot_plug = false,
1104                 .remote_wakeup_supported = false,
1105                 .power_off_on_suspend = false,
1106         },
1107         .u_cfg.hsic = {
1108                 .sync_start_delay = 9,
1109                 .idle_wait_delay = 17,
1110                 .term_range_adj = 0,
1111                 .elastic_underrun_limit = 16,
1112                 .elastic_overrun_limit = 16,
1113         },
1114         .ops = &hsic_plat_ops,
1115 };
1116
1117 static struct tegra_usb_platform_data tegra_udc_pdata = {
1118         .port_otg = true,
1119         .has_hostpc = true,
1120         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1121         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1122         .u_data.dev = {
1123                 .vbus_pmu_irq = 0,
1124                 .vbus_gpio = -1,
1125                 .charging_supported = false,
1126                 .remote_wakeup_supported = false,
1127         },
1128         .u_cfg.utmi = {
1129                 .hssync_start_delay = 0,
1130                 .elastic_limit = 16,
1131                 .idle_wait_delay = 17,
1132                 .term_range_adj = 6,
1133                 .xcvr_setup = 8,
1134                 .xcvr_lsfslew = 2,
1135                 .xcvr_lsrslew = 2,
1136                 .xcvr_setup_offset = 0,
1137                 .xcvr_use_fuses = 1,
1138         },
1139 };
1140
1141 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1142         .port_otg = false,
1143         .has_hostpc = true,
1144         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1145         .op_mode        = TEGRA_USB_OPMODE_HOST,
1146         .u_data.host = {
1147                 .vbus_gpio = -1,
1148                 .hot_plug = false,
1149                 .remote_wakeup_supported = true,
1150                 .power_off_on_suspend = true,
1151         },
1152         .u_cfg.utmi = {
1153                 .hssync_start_delay = 0,
1154                 .elastic_limit = 16,
1155                 .idle_wait_delay = 17,
1156                 .term_range_adj = 6,
1157                 .xcvr_setup = 15,
1158                 .xcvr_lsfslew = 2,
1159                 .xcvr_lsrslew = 2,
1160                 .xcvr_setup_offset = 0,
1161                 .xcvr_use_fuses = 1,
1162         },
1163 };
1164
1165 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1166         .port_otg = false,
1167         .has_hostpc = true,
1168         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1169         .op_mode = TEGRA_USB_OPMODE_HOST,
1170         .u_data.host = {
1171                 .vbus_gpio = -1,
1172                 .vbus_reg = "vdd_vbus_typea_usb",
1173                 .hot_plug = true,
1174                 .remote_wakeup_supported = true,
1175                 .power_off_on_suspend = true,
1176         },
1177         .u_cfg.utmi = {
1178                 .hssync_start_delay = 0,
1179                 .elastic_limit = 16,
1180                 .idle_wait_delay = 17,
1181                 .term_range_adj = 6,
1182                 .xcvr_setup = 8,
1183                 .xcvr_lsfslew = 2,
1184                 .xcvr_lsrslew = 2,
1185                 .xcvr_setup_offset = 0,
1186                 .xcvr_use_fuses = 1,
1187         },
1188 };
1189
1190 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1191         .port_otg = true,
1192         .has_hostpc = true,
1193         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1194         .op_mode = TEGRA_USB_OPMODE_HOST,
1195         .u_data.host = {
1196                 .vbus_gpio = -1,
1197                 .vbus_reg = "vdd_vbus_micro_usb",
1198                 .hot_plug = true,
1199                 .remote_wakeup_supported = true,
1200                 .power_off_on_suspend = true,
1201         },
1202         .u_cfg.utmi = {
1203                 .hssync_start_delay = 0,
1204                 .elastic_limit = 16,
1205                 .idle_wait_delay = 17,
1206                 .term_range_adj = 6,
1207                 .xcvr_setup = 15,
1208                 .xcvr_lsfslew = 2,
1209                 .xcvr_lsrslew = 2,
1210                 .xcvr_setup_offset = 0,
1211                 .xcvr_use_fuses = 1,
1212         },
1213 };
1214
1215 static struct tegra_usb_otg_data tegra_otg_pdata = {
1216         .ehci_device = &tegra_ehci1_device,
1217         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1218 };
1219 #endif
1220
1221 #if defined(CONFIG_USB_SUPPORT)
1222 static void cardhu_usb_init(void)
1223 {
1224         struct board_info bi;
1225
1226         tegra_get_board_info(&bi);
1227
1228         /* OTG should be the first to be registered */
1229         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1230         platform_device_register(&tegra_otg_device);
1231
1232         /* setup the udc platform data */
1233         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1234
1235         if (bi.board_id == BOARD_PM267) {
1236                 hsic_enable_gpio = EN_HSIC_GPIO;
1237                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1238                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1239                 platform_device_register(&tegra_ehci2_device);
1240         } else if (bi.board_id == BOARD_E1256) {
1241                 hsic_enable_gpio = EN_HSIC_GPIO;
1242                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1243                 platform_device_register(&tegra_ehci2_device);
1244         } else if (bi.board_id == BOARD_E1186) {
1245                 tegra_ehci2_device.dev.platform_data =
1246                                                 &tegra_ehci2_hsic_xmm_pdata;
1247                 /* ehci2 registration happens in baseband-xmm-power  */
1248         } else {
1249                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1250                 platform_device_register(&tegra_ehci2_device);
1251         }
1252
1253         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1254         platform_device_register(&tegra_ehci3_device);
1255
1256 }
1257 #else
1258 static void cardhu_usb_init(void) { }
1259 #endif
1260
1261 static struct baseband_power_platform_data tegra_baseband_power_data = {
1262         .baseband_type = BASEBAND_XMM,
1263         .modem = {
1264         .xmm = {
1265                         .bb_rst = XMM_GPIO_BB_RST,
1266                         .bb_on = XMM_GPIO_BB_ON,
1267                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1268                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1269                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1270                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1271                         .hsic_device = &tegra_ehci2_device,
1272                 },
1273         },
1274 };
1275
1276 static struct platform_device tegra_baseband_power_device = {
1277         .name = "baseband_xmm_power",
1278         .id = -1,
1279         .dev = {
1280                 .platform_data = &tegra_baseband_power_data,
1281         },
1282 };
1283
1284 static struct platform_device tegra_baseband_power2_device = {
1285         .name = "baseband_xmm_power2",
1286         .id = -1,
1287         .dev = {
1288                 .platform_data = &tegra_baseband_power_data,
1289         },
1290 };
1291
1292
1293 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1294         .port_status[0] = 1,
1295         .port_status[1] = 1,
1296         .port_status[2] = 1,
1297         .use_dock_detect        = 0,
1298         .gpio           = 0,
1299 };
1300
1301 static void cardhu_pci_init(void)
1302 {
1303         struct board_info board_info;
1304
1305         tegra_get_board_info(&board_info);
1306         if (board_info.board_id == BOARD_E1291) {
1307                 cardhu_pci_platform_data.port_status[0] = 0;
1308                 cardhu_pci_platform_data.port_status[1] = 0;
1309                 cardhu_pci_platform_data.port_status[2] = 1;
1310                 cardhu_pci_platform_data.use_dock_detect = 1;
1311                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1312         }
1313         if ((board_info.board_id == BOARD_E1186) ||
1314                 (board_info.board_id == BOARD_E1187) ||
1315                 (board_info.board_id == BOARD_E1291)) {
1316                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1317                 platform_device_register(&tegra_pci_device);
1318         }
1319 }
1320
1321 static void cardhu_modem_init(void)
1322 {
1323         struct board_info board_info;
1324         int w_disable_gpio, ret;
1325
1326         tegra_get_board_info(&board_info);
1327         switch (board_info.board_id) {
1328         case BOARD_E1291:
1329         case BOARD_E1198:
1330                 if (((board_info.board_id == BOARD_E1291) &&
1331                                 (board_info.fab < BOARD_FAB_A03)) ||
1332                         ((board_info.board_id == BOARD_E1198) &&
1333                                         (board_info.fab < BOARD_FAB_A02))) {
1334                         w_disable_gpio = TEGRA_GPIO_PH5;
1335                 } else {
1336                         w_disable_gpio = TEGRA_GPIO_PDD5;
1337                 }
1338
1339                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1340                 if (ret < 0)
1341                         pr_err("%s: gpio_request failed for gpio %d\n",
1342                                 __func__, w_disable_gpio);
1343                 else
1344                         gpio_direction_input(w_disable_gpio);
1345
1346                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1347                 if (((board_info.board_id == BOARD_E1291) &&
1348                                 (board_info.fab >= BOARD_FAB_A04)) ||
1349                         ((board_info.board_id == BOARD_E1198) &&
1350                                         (board_info.fab >= BOARD_FAB_A02))) {
1351                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1352                         if (ret < 0) {
1353                                 pr_err("%s(): Error in allocating gpio "
1354                                         "TEGRA_GPIO_PH7\n", __func__);
1355                                 break;
1356                         }
1357                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1358                 }
1359                 break;
1360         case BOARD_E1186:
1361                 platform_device_register(&tegra_baseband_power_device);
1362                 platform_device_register(&tegra_baseband_power2_device);
1363                 break;
1364         default:
1365                 break;
1366         }
1367
1368 }
1369
1370 #ifdef CONFIG_SATA_AHCI_TEGRA
1371 static void cardhu_sata_init(void)
1372 {
1373         platform_device_register(&tegra_sata_device);
1374 }
1375 #else
1376 static void cardhu_sata_init(void) { }
1377 #endif
1378
1379 static void __init tegra_cardhu_init(void)
1380 {
1381         tegra_thermal_init(&thermal_data,
1382                                 throttle_list,
1383                                 ARRAY_SIZE(throttle_list));
1384         tegra_clk_init_from_table(cardhu_clk_init_table);
1385         tegra_enable_pinmux();
1386         cardhu_pinmux_init();
1387         cardhu_i2c_init();
1388         cardhu_spi_init();
1389         cardhu_usb_init();
1390 #ifdef CONFIG_TEGRA_EDP_LIMITS
1391         cardhu_edp_init();
1392 #endif
1393         cardhu_uart_init();
1394         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1395         tegra_ram_console_debug_init();
1396         cardhu_sdhci_init();
1397         cardhu_regulator_init();
1398         cardhu_dtv_init();
1399         cardhu_suspend_init();
1400         cardhu_touch_init();
1401         cardhu_modem_init();
1402         cardhu_kbc_init();
1403         cardhu_scroll_init();
1404         cardhu_keys_init();
1405         cardhu_panel_init();
1406         cardhu_pmon_init();
1407         cardhu_sensors_init();
1408         cardhu_setup_bluesleep();
1409         cardhu_sata_init();
1410         //audio_wired_jack_init();
1411         cardhu_pins_state_init();
1412         cardhu_emc_init();
1413         tegra_release_bootloader_fb();
1414         cardhu_pci_init();
1415 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1416         tegra_wdt_recovery_init();
1417 #endif
1418         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1419 }
1420
1421 static void __init tegra_cardhu_reserve(void)
1422 {
1423 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1424         /* support 1920X1200 with 24bpp */
1425         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1426 #else
1427         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1428 #endif
1429         tegra_ram_console_debug_reserve(SZ_1M);
1430 }
1431
1432 MACHINE_START(CARDHU, "cardhu")
1433         .atag_offset    = 0x100,
1434         .soc            = &tegra_soc_desc,
1435         .map_io         = tegra_map_common_io,
1436         .reserve        = tegra_cardhu_reserve,
1437         .init_early     = tegra30_init_early,
1438         .init_irq       = tegra_init_irq,
1439         .handle_irq     = gic_handle_irq,
1440         .timer          = &tegra_timer,
1441         .init_machine   = tegra_cardhu_init,
1442         .restart        = tegra_assert_system_reset,
1443 MACHINE_END