19cb2a3f1915d3d46c3b61c6af8644eafd89bd6b
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/input.h>
35 #include <linux/platform_data/tegra_usb.h>
36 #include <linux/spi/spi.h>
37 #include <linux/i2c/atmel_mxt_ts.h>
38 #include <linux/tegra_uart.h>
39 #include <linux/memblock.h>
40 #include <linux/spi-tegra.h>
41 #include <linux/nfc/pn544.h>
42 #include <linux/rfkill-gpio.h>
43
44 #include <sound/wm8903.h>
45 #include <sound/max98095.h>
46 #include <media/tegra_dtv.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/clk.h>
51 #include <mach/iomap.h>
52 #include <mach/irqs.h>
53 #include <mach/pinmux.h>
54 #include <mach/iomap.h>
55 #include <mach/io_dpd.h>
56 #include <mach/io.h>
57 #include <mach/i2s.h>
58 #include <mach/tegra_asoc_pdata.h>
59 #include <mach/tegra_wm8903_pdata.h>
60 #include <mach/usb_phy.h>
61 #include <mach/thermal.h>
62 #include <mach/pci.h>
63 #include <mach/gpio-tegra.h>
64 #include <mach/tegra_fiq_debugger.h>
65
66 #include <asm/hardware/gic.h>
67 #include <asm/mach-types.h>
68 #include <asm/mach/arch.h>
69
70 #include "board.h"
71 #include "clock.h"
72 #include "board-cardhu.h"
73 #include "board-touch.h"
74 #include "devices.h"
75 #include "gpio-names.h"
76 #include "fuse.h"
77 #include "pm.h"
78 #include "baseband-xmm-power.h"
79 #include "wdt-recovery.h"
80 #include "common.h"
81
82 static struct balanced_throttle throttle_list[] = {
83 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
84         {
85                 .id = BALANCED_THROTTLE_ID_TJ,
86                 .throt_tab_size = 10,
87                 .throt_tab = {
88                         {      0, 1000 },
89                         { 640000, 1000 },
90                         { 640000, 1000 },
91                         { 640000, 1000 },
92                         { 640000, 1000 },
93                         { 640000, 1000 },
94                         { 760000, 1000 },
95                         { 760000, 1050 },
96                         {1000000, 1050 },
97                         {1000000, 1100 },
98                 },
99         },
100 #endif
101 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
102         {
103                 .id = BALANCED_THROTTLE_ID_SKIN,
104                 .throt_tab_size = 6,
105                 .throt_tab = {
106                         { 640000, 1200 },
107                         { 640000, 1200 },
108                         { 760000, 1200 },
109                         { 760000, 1200 },
110                         {1000000, 1200 },
111                         {1000000, 1200 },
112                 },
113         },
114 #endif
115 };
116
117 /* All units are in millicelsius */
118 static struct tegra_thermal_data thermal_data = {
119         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
120         .temp_shutdown = 90000,
121
122 #if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE)
123         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
124 #endif
125 #ifdef CONFIG_TEGRA_EDP_LIMITS
126         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
127         .hysteresis_edp = 3000,
128 #endif
129 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
130         .temp_throttle = 85000,
131         .tc1 = 0,
132         .tc2 = 1,
133         .passive_delay = 2000,
134 #endif
135 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
136         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
137         .temp_throttle_skin = 43000,
138         .tc1_skin = 0,
139         .tc2_skin = 1,
140         .passive_delay_skin = 5000,
141
142         .skin_temp_offset = 9793,
143         .skin_period = 1100,
144         .skin_devs_size = 2,
145         .skin_devs = {
146                 {
147                         THERMAL_DEVICE_ID_NCT_EXT,
148                         {
149                                 2, 1, 1, 1,
150                                 1, 1, 1, 1,
151                                 1, 1, 1, 0,
152                                 1, 1, 0, 0,
153                                 0, 0, -1, -7
154                         }
155                 },
156                 {
157                         THERMAL_DEVICE_ID_NCT_INT,
158                         {
159                                 -11, -7, -5, -3,
160                                 -3, -2, -1, 0,
161                                 0, 0, 1, 1,
162                                 1, 2, 2, 3,
163                                 4, 6, 11, 18
164                         }
165                 },
166         },
167 #endif
168 };
169
170 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
171         {
172                 .name           = "bt_rfkill",
173                 .shutdown_gpio  = TEGRA_GPIO_PU0,
174                 .reset_gpio     = TEGRA_GPIO_INVALID,
175                 .type           = RFKILL_TYPE_BLUETOOTH,
176         },
177 };
178
179 static struct platform_device cardhu_bt_rfkill_device = {
180         .name = "rfkill_gpio",
181         .id             = -1,
182         .dev = {
183                 .platform_data = &cardhu_bt_rfkill_pdata,
184         },
185 };
186
187 static struct resource cardhu_bluesleep_resources[] = {
188         [0] = {
189                 .name = "gpio_host_wake",
190                         .start  = TEGRA_GPIO_PU6,
191                         .end    = TEGRA_GPIO_PU6,
192                         .flags  = IORESOURCE_IO,
193         },
194         [1] = {
195                 .name = "gpio_ext_wake",
196                         .start  = TEGRA_GPIO_PU1,
197                         .end    = TEGRA_GPIO_PU1,
198                         .flags  = IORESOURCE_IO,
199         },
200         [2] = {
201                 .name = "host_wake",
202                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
203         },
204 };
205
206 static struct platform_device cardhu_bluesleep_device = {
207         .name           = "bluesleep",
208         .id             = -1,
209         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
210         .resource       = cardhu_bluesleep_resources,
211 };
212
213 static noinline void __init cardhu_setup_bluesleep(void)
214 {
215         cardhu_bluesleep_resources[2].start =
216                 cardhu_bluesleep_resources[2].end =
217                         gpio_to_irq(TEGRA_GPIO_PU6);
218         platform_device_register(&cardhu_bluesleep_device);
219         return;
220 }
221
222 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
223         /* name         parent          rate            enabled */
224         { "pll_m",      NULL,           0,              false},
225         { "hda",        "pll_p",        108000000,      false},
226         { "hda2codec_2x","pll_p",       48000000,       false},
227         { "pwm",        "pll_p",        3187500,        false},
228         { "blink",      "clk_32k",      32768,          true},
229         { "i2s0",       "pll_a_out0",   0,              false},
230         { "i2s1",       "pll_a_out0",   0,              false},
231         { "i2s3",       "pll_a_out0",   0,              false},
232         { "spdif_out",  "pll_a_out0",   0,              false},
233         { "d_audio",    "clk_m",        12000000,       false},
234         { "dam0",       "clk_m",        12000000,       false},
235         { "dam1",       "clk_m",        12000000,       false},
236         { "dam2",       "clk_m",        12000000,       false},
237         { "audio1",     "i2s1_sync",    0,              false},
238         { "audio3",     "i2s3_sync",    0,              false},
239         { "vi_sensor",  "pll_p",        150000000,      false},
240         { "i2c1",       "pll_p",        3200000,        false},
241         { "i2c2",       "pll_p",        3200000,        false},
242         { "i2c3",       "pll_p",        3200000,        false},
243         { "i2c4",       "pll_p",        3200000,        false},
244         { "i2c5",       "pll_p",        3200000,        false},
245         { "vi",         "pll_p",        0,              false},
246         { NULL,         NULL,           0,              0},
247 };
248
249 static struct pn544_i2c_platform_data nfc_pdata = {
250         .irq_gpio = TEGRA_GPIO_PX0,
251         .ven_gpio = TEGRA_GPIO_PP3,
252         .firm_gpio = TEGRA_GPIO_PO7,
253         };
254
255 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
256         {
257                 I2C_BOARD_INFO("pn544", 0x28),
258                 .platform_data = &nfc_pdata,
259         },
260 };
261 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
262         .adapter_nr     = 0,
263         .bus_count      = 1,
264         .bus_clk_rate   = { 100000, 0 },
265         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
266         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
267         .arb_recovery = arb_lost_recovery,
268 };
269
270 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
271         .adapter_nr     = 1,
272         .bus_count      = 1,
273         .bus_clk_rate   = { 400000, 0 },
274         .is_clkon_always = true,
275         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
276         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
277         .arb_recovery = arb_lost_recovery,
278 };
279
280 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
281         .adapter_nr     = 2,
282         .bus_count      = 1,
283         .bus_clk_rate   = { 100000, 0 },
284         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
285         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
286         .arb_recovery = arb_lost_recovery,
287 };
288
289 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
290         .adapter_nr     = 3,
291         .bus_count      = 1,
292         .bus_clk_rate   = { 10000, 0 },
293         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
294         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
295         .arb_recovery = arb_lost_recovery,
296 };
297
298 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
299         .adapter_nr     = 4,
300         .bus_count      = 1,
301         .bus_clk_rate   = { 400000, 0 },
302         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
303         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
304         .arb_recovery = arb_lost_recovery,
305 };
306
307
308 #if 0
309 struct tegra_wired_jack_conf audio_wr_jack_conf = {
310         .hp_det_n = TEGRA_GPIO_PW2,
311         .en_mic_ext = TEGRA_GPIO_PX1,
312         .en_mic_int = TEGRA_GPIO_PX0,
313 };
314 #endif
315
316 static struct wm8903_platform_data cardhu_wm8903_pdata = {
317         .irq_active_low = 0,
318         .micdet_cfg = 0,
319         .micdet_delay = 100,
320         .gpio_base = CARDHU_GPIO_WM8903(0),
321         .gpio_cfg = {
322                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
323                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
324                         WM8903_GP2_DIR,
325                 WM8903_GPIO_CONFIG_ZERO,
326                 0,
327                 0,
328         },
329 };
330
331 /* Equalizer filter coefs generated from the MAXIM MAX98095
332  * evkit software tool */
333 static struct max98095_eq_cfg max98095_eq_cfg[] = {
334         {
335                 .name = "FLAT",
336                 .rate = 44100,
337                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
338                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
339                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
340                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
341                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
342         },
343         {
344                 .name = "LOWPASS1K",
345                 .rate = 44100,
346                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
347                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
348                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
349                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
350                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
351         },
352         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
353                 .name = "HIBOOST",
354                 .rate = 44100,
355                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
356                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
357                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
358                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
359                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
360         },
361         { /* BASS=12dB, TREBLE=+12dB */
362                 .name = "LOUD12DB",
363                 .rate = 44100,
364                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
365                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
366                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
367                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
368                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
369         },
370         {
371                 .name = "FLAT",
372                 .rate = 16000,
373                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
374                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
375                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
376                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
377                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
378         },
379         {
380                 .name = "LOWPASS1K",
381                 .rate = 16000,
382                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
383                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
384                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
385                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
386                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
387         },
388         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
389                 .name = "HIBOOST",
390                 .rate = 16000,
391                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
392                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
393                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
394                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
395                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
396         },
397         { /* BASS=12dB, TREBLE=+12dB */
398                 .name = "LOUD12DB",
399                 .rate = 16000,
400                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
401                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
402                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
403                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
404                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
405         },
406 };
407
408 static struct max98095_pdata cardhu_max98095_pdata = {
409         /* equalizer configuration */
410         .eq_cfg = max98095_eq_cfg,
411         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
412
413         /* Biquad filter response configuration */
414         .bq_cfg = NULL,
415         .bq_cfgcnt = 0,
416
417         /* microphone configuration */
418         .digmic_left_mode = 1,
419         .digmic_right_mode = 1,
420 };
421
422 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
423         I2C_BOARD_INFO("wm8903", 0x1a),
424         .platform_data = &cardhu_wm8903_pdata,
425 };
426
427 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
428         I2C_BOARD_INFO("aic3262-codec", 0x18),
429 };
430
431 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
432         I2C_BOARD_INFO("max98095", 0x10),
433         .platform_data = &cardhu_max98095_pdata,
434 };
435
436 static void cardhu_i2c_init(void)
437 {
438         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
439         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
440         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
441         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
442         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
443
444         platform_device_register(&tegra_i2c_device5);
445         platform_device_register(&tegra_i2c_device4);
446         platform_device_register(&tegra_i2c_device3);
447         platform_device_register(&tegra_i2c_device2);
448         platform_device_register(&tegra_i2c_device1);
449
450         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
451                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
452         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
453         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
454         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
455
456         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
457         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
458 }
459
460 static struct platform_device *cardhu_uart_devices[] __initdata = {
461         &tegra_uarta_device,
462         &tegra_uartb_device,
463         &tegra_uartc_device,
464         &tegra_uartd_device,
465         &tegra_uarte_device,
466 };
467 static struct uart_clk_parent uart_parent_clk[] = {
468         [0] = {.name = "clk_m"},
469         [1] = {.name = "pll_p"},
470 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
471         [2] = {.name = "pll_m"},
472 #endif
473 };
474
475 static struct tegra_uart_platform_data cardhu_uart_pdata;
476 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
477
478 static void __init uart_debug_init(void)
479 {
480         struct board_info board_info;
481         int debug_port_id;
482
483         tegra_get_board_info(&board_info);
484
485         debug_port_id = get_tegra_uart_debug_port_id();
486         if (debug_port_id < 0) {
487                 debug_port_id = 0;
488                         /* UARTB is debug port
489                          *       for SLT - E1186/E1187/PM269
490                          *       for E1256/E1257
491                          */
492                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
493                         ((board_info.board_id == BOARD_E1186) ||
494                         (board_info.board_id == BOARD_E1187) ||
495                         (board_info.board_id == BOARD_PM269))) ||
496                         (board_info.board_id == BOARD_E1256) ||
497                         (board_info.board_id == BOARD_E1257))
498                                 debug_port_id = 1;
499         }
500
501 #ifdef CONFIG_TEGRA_IRDA
502         if ((board_info.board_id == BOARD_E1186) ||
503                 (board_info.board_id == BOARD_E1198)) {
504                 if (debug_port_id == 1) {
505                         cardhu_irda_pdata.is_irda = false;
506                         pr_err("UARTB is not available for IrDA\n");
507                 }
508         }
509 #endif
510
511         switch (debug_port_id) {
512         case 0:
513                 /* UARTA is the debug port. */
514                 pr_info("Selecting UARTA as the debug console\n");
515                 cardhu_uart_devices[0] = &debug_uarta_device;
516                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
517                 debug_uart_port_base = ((struct plat_serial8250_port *)(
518                         debug_uarta_device.dev.platform_data))->mapbase;
519                 break;
520
521         case 1:
522                 /* UARTB is the debug port. */
523                 pr_info("Selecting UARTB as the debug console\n");
524                 cardhu_uart_devices[1] = &debug_uartb_device;
525                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
526                 debug_uart_port_base = ((struct plat_serial8250_port *)(
527                         debug_uartb_device.dev.platform_data))->mapbase;
528                 break;
529
530         case 2:
531                 /* UARTC is the debug port. */
532                 pr_info("Selecting UARTC as the debug console\n");
533                 cardhu_uart_devices[2] = &debug_uartc_device;
534                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
535                 debug_uart_port_base = ((struct plat_serial8250_port *)(
536                         debug_uartc_device.dev.platform_data))->mapbase;
537                 break;
538
539         case 3:
540                 /* UARTD is the debug port. */
541                 pr_info("Selecting UARTD as the debug console\n");
542                 cardhu_uart_devices[3] = &debug_uartd_device;
543                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
544                 debug_uart_port_base = ((struct plat_serial8250_port *)(
545                         debug_uartd_device.dev.platform_data))->mapbase;
546                 break;
547
548         case 4:
549                 /* UARTE is the debug port. */
550                 pr_info("Selecting UARTE as the debug console\n");
551                 cardhu_uart_devices[4] = &debug_uarte_device;
552                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
553                 debug_uart_port_base = ((struct plat_serial8250_port *)(
554                         debug_uarte_device.dev.platform_data))->mapbase;
555                 break;
556
557         default:
558                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
559                 cardhu_uart_devices[0] = &debug_uarta_device;
560                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
561                 debug_uart_port_base = ((struct plat_serial8250_port *)(
562                         debug_uarta_device.dev.platform_data))->mapbase;
563                 break;
564         }
565         return;
566 }
567
568 static void __init cardhu_uart_init(void)
569 {
570         struct clk *c;
571         int i;
572         struct board_info board_info;
573
574         tegra_get_board_info(&board_info);
575
576         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
577                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
578                 if (IS_ERR_OR_NULL(c)) {
579                         pr_err("Not able to get the clock for %s\n",
580                                                 uart_parent_clk[i].name);
581                         continue;
582                 }
583                 uart_parent_clk[i].parent_clk = c;
584                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
585         }
586         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
587         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
588         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
589         cardhu_loopback_uart_pdata.parent_clk_count =
590                                                 ARRAY_SIZE(uart_parent_clk);
591         cardhu_loopback_uart_pdata.is_loopback = true;
592         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
593         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
594         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
595         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
596         /* UARTE is used for loopback test purpose */
597         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
598
599         /* Register low speed only if it is selected */
600         if (!is_tegra_debug_uartport_hs()) {
601                 uart_debug_init();
602                 /* Clock enable for the debug channel */
603                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
604                         pr_info("The debug console clock name is %s\n",
605                                                 debug_uart_clk->name);
606                         c = tegra_get_clock_by_name("pll_p");
607                         if (IS_ERR_OR_NULL(c))
608                                 pr_err("Not getting the parent clock pll_p\n");
609                         else
610                                 clk_set_parent(debug_uart_clk, c);
611
612                         clk_enable(debug_uart_clk);
613                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
614                 } else {
615                         pr_err("Not getting the clock %s for debug console\n",
616                                         debug_uart_clk->name);
617                 }
618         }
619
620 #ifdef CONFIG_TEGRA_IRDA
621         if (((board_info.board_id == BOARD_E1186) ||
622                 (board_info.board_id == BOARD_E1198)) &&
623                         cardhu_irda_pdata.is_irda) {
624                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
625                 cardhu_irda_pdata.parent_clk_count =
626                                         ARRAY_SIZE(uart_parent_clk);
627
628                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
629         }
630 #endif
631
632         platform_add_devices(cardhu_uart_devices,
633                                 ARRAY_SIZE(cardhu_uart_devices));
634 }
635
636 static struct platform_device tegra_camera = {
637         .name = "tegra_camera",
638         .id = -1,
639 };
640
641 static struct platform_device *cardhu_spi_devices[] __initdata = {
642         &tegra_spi_device4,
643 };
644
645 static struct platform_device *touch_spi_device[] __initdata = {
646         &tegra_spi_device1,
647 };
648
649 struct spi_clk_parent spi_parent_clk[] = {
650         [0] = {.name = "pll_p"},
651 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
652         [1] = {.name = "pll_m"},
653         [2] = {.name = "clk_m"},
654 #else
655         [1] = {.name = "clk_m"},
656 #endif
657 };
658
659 static struct tegra_spi_platform_data cardhu_spi_pdata = {
660         .is_dma_based           = true,
661         .max_dma_buffer         = (16 * 1024),
662         .is_clkon_always        = false,
663         .max_rate               = 100000000,
664 };
665
666 static void __init cardhu_spi_init(void)
667 {
668         int i;
669         struct clk *c;
670         struct board_info board_info, display_board_info;
671
672         tegra_get_board_info(&board_info);
673         tegra_get_display_board_info(&display_board_info);
674
675         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
676                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
677                 if (IS_ERR_OR_NULL(c)) {
678                         pr_err("Not able to get the clock for %s\n",
679                                                 spi_parent_clk[i].name);
680                         continue;
681                 }
682                 spi_parent_clk[i].parent_clk = c;
683                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
684         }
685         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
686         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
687         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
688         platform_add_devices(cardhu_spi_devices,
689                                 ARRAY_SIZE(cardhu_spi_devices));
690
691         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
692                 platform_add_devices(touch_spi_device,
693                                 ARRAY_SIZE(touch_spi_device));
694         }
695         if (board_info.board_id == BOARD_E1198) {
696                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
697                 platform_device_register(&tegra_spi_device2);
698                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
699                 platform_device_register(&tegra_spi_slave_device1);
700         }
701 }
702
703 static void __init cardhu_dtv_init(void)
704 {
705         struct board_info board_info;
706
707         tegra_get_board_info(&board_info);
708
709         if (board_info.board_id == BOARD_E1186)
710                 platform_device_register(&tegra_dtv_device);
711 }
712
713 static struct resource tegra_rtc_resources[] = {
714         [0] = {
715                 .start = TEGRA_RTC_BASE,
716                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
717                 .flags = IORESOURCE_MEM,
718         },
719         [1] = {
720                 .start = INT_RTC,
721                 .end = INT_RTC,
722                 .flags = IORESOURCE_IRQ,
723         },
724 };
725
726 static struct platform_device tegra_rtc_device = {
727         .name = "tegra_rtc",
728         .id   = -1,
729         .resource = tegra_rtc_resources,
730         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
731 };
732
733 static struct tegra_wm8903_platform_data cardhu_audio_wm8903_pdata = {
734         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
735         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
736         .gpio_hp_mute           = -1,
737         .gpio_int_mic_en        = -1,
738         .gpio_ext_mic_en        = -1,
739 };
740
741 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
742         .gpio_spkr_en           = -1,
743         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
744         .gpio_hp_mute           = -1,
745         .gpio_int_mic_en        = -1,
746         .gpio_ext_mic_en        = -1,
747 };
748
749 static struct platform_device cardhu_audio_wm8903_device = {
750         .name   = "tegra-snd-wm8903",
751         .id     = 0,
752         .dev    = {
753                 .platform_data = &cardhu_audio_wm8903_pdata,
754         },
755 };
756
757 static struct platform_device cardhu_audio_max98095_device = {
758         .name   = "tegra-snd-max98095",
759         .id     = 0,
760         .dev    = {
761                 .platform_data = &cardhu_audio_max98095_pdata,
762         },
763 };
764
765 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
766         .gpio_spkr_en           = -1,
767         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
768         .gpio_hp_mute           = -1,
769         .gpio_int_mic_en        = -1,
770         .gpio_ext_mic_en        = -1,
771         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
772         .audio_port_id          = {
773                 [HIFI_CODEC] = 0,
774                 [BASEBAND] = -1,
775                 [BT_SCO] = 3,
776         },
777         .baseband_param         = {
778                 .rate = -1,
779                 .channels = -1,
780         },
781 };
782
783 static struct platform_device cardhu_audio_aic326x_device = {
784         .name   = "tegra-snd-aic326x",
785         .id     = 0,
786         .dev    = {
787                 .platform_data  = &cardhu_audio_aic326x_pdata,
788         },
789 };
790
791 static struct platform_device *cardhu_devices[] __initdata = {
792         &tegra_pmu_device,
793         &tegra_rtc_device,
794         &tegra_udc_device,
795 #if defined(CONFIG_TEGRA_IOVMM_SMMU) ||  defined(CONFIG_TEGRA_IOMMU_SMMU)
796         &tegra_smmu_device,
797 #endif
798         &tegra_wdt0_device,
799         &tegra_wdt1_device,
800         &tegra_wdt2_device,
801 #if defined(CONFIG_TEGRA_AVP)
802         &tegra_avp_device,
803 #endif
804         &tegra_camera,
805 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
806         &tegra_se_device,
807 #endif
808         &tegra_ahub_device,
809         &tegra_dam_device0,
810         &tegra_dam_device1,
811         &tegra_dam_device2,
812         &tegra_i2s_device0,
813         &tegra_i2s_device1,
814         &tegra_i2s_device3,
815         &tegra_spdif_device,
816         &spdif_dit_device,
817         &bluetooth_dit_device,
818         &baseband_dit_device,
819         &cardhu_bt_rfkill_device,
820         &tegra_pcm_device,
821         &cardhu_audio_wm8903_device,
822         &cardhu_audio_max98095_device,
823         &cardhu_audio_aic326x_device,
824         &tegra_hda_device,
825         &tegra_cec_device,
826 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
827         &tegra_aes_device,
828 #endif
829 };
830
831 #define E1506_MXT_CONFIG_CRC 0x62F903
832 static const u8 e1506_config[] = {
833         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
834         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
835         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
836         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
837         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
838         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
839         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
840         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
841         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
842         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
843         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
844         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
845         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
846         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
847         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
848         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
849         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
850         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
851         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
852         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
853         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
854         0x00
855 };
856
857 #define MXT_CONFIG_CRC  0xD62DE8
858 static const u8 config[] = {
859         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
860         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
861         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
862         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
863         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
864         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
866         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
867         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
869         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
870         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
871         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
872         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
873         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
874         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
875         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
876         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
877         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
878         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
879 };
880
881 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
882 static const u8 config_sku2000[] = {
883         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
884         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
885         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
886         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
887         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
888         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
889         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
890         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
891         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
892         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
893         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
894         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
895         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
896         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
897         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
899         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
900         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
901         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
902         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
903 };
904
905 static struct mxt_platform_data atmel_mxt_info = {
906         .x_line         = 27,
907         .y_line         = 42,
908         .x_size         = 768,
909         .y_size         = 1366,
910         .blen           = 0x20,
911         .threshold      = 0x3C,
912         .voltage        = 3300000,              /* 3.3V */
913         .orient         = 5,
914         .config         = config,
915         .config_length  = 157,
916         .config_crc     = MXT_CONFIG_CRC,
917         .irqflags       = IRQF_TRIGGER_FALLING,
918 /*      .read_chg       = &read_chg, */
919         .read_chg       = NULL,
920 };
921
922 static struct mxt_platform_data e1506_atmel_mxt_info = {
923         .x_line         = 19,
924         .y_line         = 11,
925         .x_size         = 960,
926         .y_size         = 540,
927         .blen           = 0x10,
928         .threshold      = 0x32,
929         .voltage        = 3300000,              /* 3.3V */
930         .orient         = 3,
931         .config         = e1506_config,
932         .config_length  = 168,
933         .config_crc     = E1506_MXT_CONFIG_CRC,
934         .irqflags       = IRQF_TRIGGER_FALLING,
935 /*      .read_chg       = &read_chg, */
936         .read_chg       = NULL,
937 };
938
939 static struct i2c_board_info __initdata atmel_i2c_info[] = {
940         {
941                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
942                 .platform_data = &atmel_mxt_info,
943         }
944 };
945
946 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
947         {
948                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
949                 .platform_data = &e1506_atmel_mxt_info,
950         }
951 };
952
953 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
954         /* name         parent          rate            enabled */
955         { "sbc1",       "pll_p",        52000000,       true},
956         { NULL,         NULL,           0,              0},
957 };
958
959 static int __init cardhu_touch_init(void)
960 {
961         struct board_info BoardInfo, DisplayBoardInfo;
962
963         tegra_get_board_info(&BoardInfo);
964         tegra_get_display_board_info(&DisplayBoardInfo);
965         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
966                 tegra_clk_init_from_table(spi_clk_init_table);
967
968                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
969         } else {
970                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
971                 gpio_direction_input(TEGRA_GPIO_PH4);
972
973                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
974                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
975                 msleep(1);
976                 gpio_set_value(TEGRA_GPIO_PH6, 1);
977                 msleep(100);
978
979                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
980                         atmel_mxt_info.config = config_sku2000;
981                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
982                 }
983
984                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
985                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
986                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
987                 } else {
988                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
989                         i2c_register_board_info(1, atmel_i2c_info, 1);
990                 }
991         }
992
993         return 0;
994 }
995
996 #if defined(CONFIG_USB_SUPPORT)
997
998 static void cardu_usb_hsic_postsupend(void)
999 {
1000 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1001         baseband_xmm_set_power_status(BBXMM_PS_L2);
1002 #endif
1003 }
1004
1005 static void cardu_usb_hsic_preresume(void)
1006 {
1007 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1008         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1009 #endif
1010 }
1011
1012 static void cardu_usb_hsic_phy_ready(void)
1013 {
1014 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1015         baseband_xmm_set_power_status(BBXMM_PS_L0);
1016 #endif
1017 }
1018
1019 static void cardu_usb_hsic_phy_off(void)
1020 {
1021 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1022         baseband_xmm_set_power_status(BBXMM_PS_L3);
1023 #endif
1024 }
1025
1026 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1027         .post_suspend = cardu_usb_hsic_postsupend,
1028         .pre_resume = cardu_usb_hsic_preresume,
1029         .port_power = cardu_usb_hsic_phy_ready,
1030         .post_phy_off = cardu_usb_hsic_phy_off,
1031 };
1032
1033 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1034         .port_otg = false,
1035         .has_hostpc = true,
1036         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1037         .op_mode        = TEGRA_USB_OPMODE_HOST,
1038         .u_data.host = {
1039                 .vbus_gpio = -1,
1040                 .hot_plug = false,
1041                 .remote_wakeup_supported = false,
1042                 .power_off_on_suspend = false,
1043         },
1044         .ops = &hsic_xmm_plat_ops,
1045 };
1046 #endif
1047
1048 static int hsic_enable_gpio = -1;
1049 static int hsic_reset_gpio = -1;
1050
1051 void hsic_platform_open(void)
1052 {
1053         int reset_gpio = 0, enable_gpio = 0;
1054
1055         if (hsic_enable_gpio != -1)
1056                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1057         if (hsic_reset_gpio != -1)
1058                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1059         /* hsic enable signal deasserted, hsic reset asserted */
1060         if (!enable_gpio)
1061                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1062         if (!reset_gpio)
1063                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1064         /* keep hsic reset asserted for 1 ms */
1065         udelay(1000);
1066         /* enable (power on) hsic */
1067         if (!enable_gpio)
1068                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1069         udelay(1000);
1070         /* deassert reset */
1071         if (!reset_gpio)
1072                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1073
1074 }
1075
1076 void hsic_platform_close(void)
1077 {
1078         if (hsic_enable_gpio != -1) {
1079                 gpio_set_value(hsic_enable_gpio, 0);
1080                 gpio_free(hsic_enable_gpio);
1081         }
1082         if (hsic_reset_gpio != -1) {
1083                 gpio_set_value(hsic_reset_gpio, 0);
1084                 gpio_free(hsic_reset_gpio);
1085         }
1086 }
1087
1088 void hsic_power_on(void)
1089 {
1090         if (hsic_enable_gpio != -1) {
1091                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1092                 udelay(1000);
1093         }
1094 }
1095
1096 void hsic_power_off(void)
1097 {
1098         if (hsic_enable_gpio != -1) {
1099                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1100                 udelay(1000);
1101         }
1102 }
1103
1104 #if defined(CONFIG_USB_SUPPORT)
1105 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1106         .open = hsic_platform_open,
1107         .close = hsic_platform_close,
1108         .pre_phy_on = hsic_power_on,
1109         .post_phy_off = hsic_power_off,
1110 };
1111
1112 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1113         .port_otg = false,
1114         .has_hostpc = true,
1115         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1116         .op_mode        = TEGRA_USB_OPMODE_HOST,
1117         .u_data.host = {
1118                 .vbus_gpio = -1,
1119                 .hot_plug = false,
1120                 .remote_wakeup_supported = false,
1121                 .power_off_on_suspend = false,
1122         },
1123         .ops = &hsic_plat_ops,
1124 };
1125
1126 static struct tegra_usb_platform_data tegra_udc_pdata = {
1127         .port_otg = true,
1128         .has_hostpc = true,
1129         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1130         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1131         .u_data.dev = {
1132                 .vbus_pmu_irq = 0,
1133                 .vbus_gpio = -1,
1134                 .charging_supported = false,
1135                 .remote_wakeup_supported = false,
1136         },
1137         .u_cfg.utmi = {
1138                 .hssync_start_delay = 0,
1139                 .elastic_limit = 16,
1140                 .idle_wait_delay = 17,
1141                 .term_range_adj = 6,
1142                 .xcvr_setup = 8,
1143                 .xcvr_lsfslew = 2,
1144                 .xcvr_lsrslew = 2,
1145                 .xcvr_setup_offset = 0,
1146                 .xcvr_use_fuses = 1,
1147         },
1148 };
1149
1150 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1151         .port_otg = false,
1152         .has_hostpc = true,
1153         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1154         .op_mode        = TEGRA_USB_OPMODE_HOST,
1155         .u_data.host = {
1156                 .vbus_gpio = -1,
1157                 .hot_plug = false,
1158                 .remote_wakeup_supported = true,
1159                 .power_off_on_suspend = true,
1160         },
1161         .u_cfg.utmi = {
1162                 .hssync_start_delay = 0,
1163                 .elastic_limit = 16,
1164                 .idle_wait_delay = 17,
1165                 .term_range_adj = 6,
1166                 .xcvr_setup = 15,
1167                 .xcvr_lsfslew = 2,
1168                 .xcvr_lsrslew = 2,
1169                 .xcvr_setup_offset = 0,
1170                 .xcvr_use_fuses = 1,
1171         },
1172 };
1173
1174 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1175         .port_otg = false,
1176         .has_hostpc = true,
1177         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1178         .op_mode = TEGRA_USB_OPMODE_HOST,
1179         .u_data.host = {
1180                 .vbus_gpio = -1,
1181                 .vbus_reg = "vdd_vbus_typea_usb",
1182                 .hot_plug = true,
1183                 .remote_wakeup_supported = true,
1184                 .power_off_on_suspend = true,
1185         },
1186         .u_cfg.utmi = {
1187                 .hssync_start_delay = 0,
1188                 .elastic_limit = 16,
1189                 .idle_wait_delay = 17,
1190                 .term_range_adj = 6,
1191                 .xcvr_setup = 8,
1192                 .xcvr_lsfslew = 2,
1193                 .xcvr_lsrslew = 2,
1194                 .xcvr_setup_offset = 0,
1195                 .xcvr_use_fuses = 1,
1196         },
1197 };
1198
1199 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1200         .port_otg = true,
1201         .has_hostpc = true,
1202         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1203         .op_mode = TEGRA_USB_OPMODE_HOST,
1204         .u_data.host = {
1205                 .vbus_gpio = -1,
1206                 .vbus_reg = "vdd_vbus_micro_usb",
1207                 .hot_plug = true,
1208                 .remote_wakeup_supported = true,
1209                 .power_off_on_suspend = true,
1210         },
1211         .u_cfg.utmi = {
1212                 .hssync_start_delay = 0,
1213                 .elastic_limit = 16,
1214                 .idle_wait_delay = 17,
1215                 .term_range_adj = 6,
1216                 .xcvr_setup = 15,
1217                 .xcvr_lsfslew = 2,
1218                 .xcvr_lsrslew = 2,
1219                 .xcvr_setup_offset = 0,
1220                 .xcvr_use_fuses = 1,
1221         },
1222 };
1223
1224 static struct tegra_usb_otg_data tegra_otg_pdata = {
1225         .ehci_device = &tegra_ehci1_device,
1226         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1227 };
1228 #endif
1229
1230 #if defined(CONFIG_USB_SUPPORT)
1231 static void cardhu_usb_init(void)
1232 {
1233         struct board_info bi;
1234
1235         tegra_get_board_info(&bi);
1236
1237         /* OTG should be the first to be registered */
1238         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1239         platform_device_register(&tegra_otg_device);
1240
1241         /* setup the udc platform data */
1242         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1243
1244         if (bi.board_id == BOARD_PM267) {
1245                 hsic_enable_gpio = EN_HSIC_GPIO;
1246                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1247                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1248                 platform_device_register(&tegra_ehci2_device);
1249         } else if (bi.board_id == BOARD_E1256) {
1250                 hsic_enable_gpio = EN_HSIC_GPIO;
1251                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1252                 platform_device_register(&tegra_ehci2_device);
1253         } else if (bi.board_id == BOARD_E1186) {
1254                 tegra_ehci2_device.dev.platform_data =
1255                                                 &tegra_ehci2_hsic_xmm_pdata;
1256                 /* ehci2 registration happens in baseband-xmm-power  */
1257         } else {
1258                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1259                 platform_device_register(&tegra_ehci2_device);
1260         }
1261
1262         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1263         platform_device_register(&tegra_ehci3_device);
1264
1265 }
1266 #else
1267 static void cardhu_usb_init(void) { }
1268 #endif
1269
1270 static struct baseband_power_platform_data tegra_baseband_power_data = {
1271         .baseband_type = BASEBAND_XMM,
1272         .modem = {
1273         .xmm = {
1274                         .bb_rst = XMM_GPIO_BB_RST,
1275                         .bb_on = XMM_GPIO_BB_ON,
1276                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1277                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1278                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1279                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1280                         .hsic_device = &tegra_ehci2_device,
1281                 },
1282         },
1283 };
1284
1285 static struct platform_device tegra_baseband_power_device = {
1286         .name = "baseband_xmm_power",
1287         .id = -1,
1288         .dev = {
1289                 .platform_data = &tegra_baseband_power_data,
1290         },
1291 };
1292
1293 static struct platform_device tegra_baseband_power2_device = {
1294         .name = "baseband_xmm_power2",
1295         .id = -1,
1296         .dev = {
1297                 .platform_data = &tegra_baseband_power_data,
1298         },
1299 };
1300
1301
1302 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1303         .port_status[0] = 1,
1304         .port_status[1] = 1,
1305         .port_status[2] = 1,
1306         .use_dock_detect        = 0,
1307         .gpio           = 0,
1308 };
1309
1310 static void cardhu_pci_init(void)
1311 {
1312         struct board_info board_info;
1313
1314         tegra_get_board_info(&board_info);
1315         if (board_info.board_id == BOARD_E1291) {
1316                 cardhu_pci_platform_data.port_status[0] = 0;
1317                 cardhu_pci_platform_data.port_status[1] = 0;
1318                 cardhu_pci_platform_data.port_status[2] = 1;
1319                 cardhu_pci_platform_data.use_dock_detect = 1;
1320                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1321         }
1322         if ((board_info.board_id == BOARD_E1186) ||
1323                 (board_info.board_id == BOARD_E1187) ||
1324                 (board_info.board_id == BOARD_E1291)) {
1325                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1326                 platform_device_register(&tegra_pci_device);
1327         }
1328 }
1329
1330 static void cardhu_modem_init(void)
1331 {
1332         struct board_info board_info;
1333         int w_disable_gpio, ret;
1334
1335         tegra_get_board_info(&board_info);
1336         switch (board_info.board_id) {
1337         case BOARD_E1291:
1338         case BOARD_E1198:
1339                 if (((board_info.board_id == BOARD_E1291) &&
1340                                 (board_info.fab < BOARD_FAB_A03)) ||
1341                         ((board_info.board_id == BOARD_E1198) &&
1342                                         (board_info.fab < BOARD_FAB_A02))) {
1343                         w_disable_gpio = TEGRA_GPIO_PH5;
1344                 } else {
1345                         w_disable_gpio = TEGRA_GPIO_PDD5;
1346                 }
1347
1348                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1349                 if (ret < 0)
1350                         pr_err("%s: gpio_request failed for gpio %d\n",
1351                                 __func__, w_disable_gpio);
1352                 else
1353                         gpio_direction_input(w_disable_gpio);
1354
1355                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1356                 if (((board_info.board_id == BOARD_E1291) &&
1357                                 (board_info.fab >= BOARD_FAB_A04)) ||
1358                         ((board_info.board_id == BOARD_E1198) &&
1359                                         (board_info.fab >= BOARD_FAB_A02))) {
1360                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1361                         if (ret < 0) {
1362                                 pr_err("%s(): Error in allocating gpio "
1363                                         "TEGRA_GPIO_PH7\n", __func__);
1364                                 break;
1365                         }
1366                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1367                 }
1368                 break;
1369         case BOARD_E1186:
1370                 platform_device_register(&tegra_baseband_power_device);
1371                 platform_device_register(&tegra_baseband_power2_device);
1372                 break;
1373         default:
1374                 break;
1375         }
1376
1377 }
1378
1379 #ifdef CONFIG_SATA_AHCI_TEGRA
1380 static void cardhu_sata_init(void)
1381 {
1382         platform_device_register(&tegra_sata_device);
1383 }
1384 #else
1385 static void cardhu_sata_init(void) { }
1386 #endif
1387
1388 static void __init tegra_cardhu_init(void)
1389 {
1390         tegra_thermal_init(&thermal_data,
1391                                 throttle_list,
1392                                 ARRAY_SIZE(throttle_list));
1393         tegra_clk_init_from_table(cardhu_clk_init_table);
1394         tegra_enable_pinmux();
1395         cardhu_pinmux_init();
1396         cardhu_i2c_init();
1397         cardhu_spi_init();
1398         cardhu_usb_init();
1399 #ifdef CONFIG_TEGRA_EDP_LIMITS
1400         cardhu_edp_init();
1401 #endif
1402         cardhu_uart_init();
1403         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1404         tegra_ram_console_debug_init();
1405         tegra_io_dpd_init();
1406         cardhu_sdhci_init();
1407         cardhu_regulator_init();
1408         cardhu_dtv_init();
1409         cardhu_suspend_init();
1410         cardhu_touch_init();
1411         cardhu_modem_init();
1412         cardhu_kbc_init();
1413         cardhu_scroll_init();
1414         cardhu_keys_init();
1415         cardhu_panel_init();
1416         cardhu_pmon_init();
1417         cardhu_sensors_init();
1418         cardhu_setup_bluesleep();
1419         cardhu_sata_init();
1420         //audio_wired_jack_init();
1421         cardhu_pins_state_init();
1422         cardhu_emc_init();
1423         tegra_release_bootloader_fb();
1424         cardhu_pci_init();
1425 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1426         tegra_wdt_recovery_init();
1427 #endif
1428         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1429 }
1430
1431 static void __init tegra_cardhu_reserve(void)
1432 {
1433 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1434         /* support 1920X1200 with 24bpp */
1435         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1436 #else
1437         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1438 #endif
1439         tegra_ram_console_debug_reserve(SZ_1M);
1440 }
1441
1442 MACHINE_START(CARDHU, "cardhu")
1443         .atag_offset    = 0x100,
1444         .soc            = &tegra_soc_desc,
1445         .map_io         = tegra_map_common_io,
1446         .reserve        = tegra_cardhu_reserve,
1447         .init_early     = tegra30_init_early,
1448         .init_irq       = tegra_init_irq,
1449         .handle_irq     = gic_handle_irq,
1450         .timer          = &tegra_timer,
1451         .init_machine   = tegra_cardhu_init,
1452         .restart        = tegra_assert_system_reset,
1453 MACHINE_END