05d538796e0cb9d47d356fb978ac5faf690e78e0
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  * Copyright (c) 2011-2012, NVIDIA Corporation.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along
18  * with this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/slab.h>
25 #include <linux/ctype.h>
26 #include <linux/platform_device.h>
27 #include <linux/clk.h>
28 #include <linux/serial_8250.h>
29 #include <linux/i2c.h>
30 #include <linux/i2c/panjit_ts.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/i2c-tegra.h>
34 #include <linux/gpio.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37 #include <linux/spi/spi.h>
38 #include <linux/i2c/atmel_mxt_ts.h>
39 #include <linux/tegra_uart.h>
40 #include <linux/memblock.h>
41 #include <linux/spi-tegra.h>
42 #include <linux/nfc/pn544.h>
43 #include <linux/rfkill-gpio.h>
44
45 #include <sound/wm8903.h>
46 #include <sound/max98095.h>
47 #include <media/tegra_dtv.h>
48
49 #include <asm/hardware/gic.h>
50
51 #include <mach/clk.h>
52 #include <mach/iomap.h>
53 #include <mach/irqs.h>
54 #include <mach/pinmux.h>
55 #include <mach/iomap.h>
56 #include <mach/io_dpd.h>
57 #include <mach/io.h>
58 #include <mach/i2s.h>
59 #include <mach/tegra_asoc_pdata.h>
60 #include <mach/tegra_wm8903_pdata.h>
61 #include <mach/usb_phy.h>
62 #include <mach/thermal.h>
63 #include <mach/pci.h>
64 #include <mach/gpio-tegra.h>
65 #include <mach/tegra_fiq_debugger.h>
66
67 #include <asm/hardware/gic.h>
68 #include <asm/mach-types.h>
69 #include <asm/mach/arch.h>
70
71 #include "board.h"
72 #include "clock.h"
73 #include "board-cardhu.h"
74 #include "board-touch.h"
75 #include "devices.h"
76 #include "gpio-names.h"
77 #include "fuse.h"
78 #include "pm.h"
79 #include "baseband-xmm-power.h"
80 #include "wdt-recovery.h"
81 #include "common.h"
82
83 static struct balanced_throttle throttle_list[] = {
84         {
85                 .id = BALANCED_THROTTLE_ID_TJ,
86                 .throt_tab_size = 10,
87                 .throt_tab = {
88                         {      0, 1000 },
89                         { 640000, 1000 },
90                         { 640000, 1000 },
91                         { 640000, 1000 },
92                         { 640000, 1000 },
93                         { 640000, 1000 },
94                         { 760000, 1000 },
95                         { 760000, 1050 },
96                         {1000000, 1050 },
97                         {1000000, 1100 },
98                 },
99         },
100 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
101         {
102                 .id = BALANCED_THROTTLE_ID_SKIN,
103                 .throt_tab_size = 6,
104                 .throt_tab = {
105                         { 640000, 1200 },
106                         { 640000, 1200 },
107                         { 760000, 1200 },
108                         { 760000, 1200 },
109                         {1000000, 1200 },
110                         {1000000, 1200 },
111                 },
112         },
113 #endif
114 };
115
116 /* All units are in millicelsius */
117 static struct tegra_thermal_data thermal_data = {
118         .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT,
119         .temp_shutdown = 90000,
120         .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT,
121 #ifdef CONFIG_TEGRA_EDP_LIMITS
122         .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
123         .hysteresis_edp = 3000,
124 #endif
125         .temp_throttle = 85000,
126         .tc1 = 0,
127         .tc2 = 1,
128         .passive_delay = 2000,
129 #ifdef CONFIG_TEGRA_SKIN_THROTTLE
130         .skin_device_id = THERMAL_DEVICE_ID_SKIN,
131         .temp_throttle_skin = 43000,
132         .tc1_skin = 0,
133         .tc2_skin = 1,
134         .passive_delay_skin = 5000,
135
136         .skin_temp_offset = 9793,
137         .skin_period = 1100,
138         .skin_devs_size = 2,
139         .skin_devs = {
140                 {
141                         THERMAL_DEVICE_ID_NCT_EXT,
142                         {
143                                 2, 1, 1, 1,
144                                 1, 1, 1, 1,
145                                 1, 1, 1, 0,
146                                 1, 1, 0, 0,
147                                 0, 0, -1, -7
148                         }
149                 },
150                 {
151                         THERMAL_DEVICE_ID_NCT_INT,
152                         {
153                                 -11, -7, -5, -3,
154                                 -3, -2, -1, 0,
155                                 0, 0, 1, 1,
156                                 1, 2, 2, 3,
157                                 4, 6, 11, 18
158                         }
159                 },
160         },
161 #endif
162 };
163
164 static struct rfkill_gpio_platform_data cardhu_bt_rfkill_pdata[] = {
165         {
166                 .name           = "bt_rfkill",
167                 .shutdown_gpio  = TEGRA_GPIO_PU0,
168                 .reset_gpio     = TEGRA_GPIO_INVALID,
169                 .type           = RFKILL_TYPE_BLUETOOTH,
170         },
171 };
172
173 static struct platform_device cardhu_bt_rfkill_device = {
174         .name = "rfkill_gpio",
175         .id             = -1,
176         .dev = {
177                 .platform_data = &cardhu_bt_rfkill_pdata,
178         },
179 };
180
181 static struct resource cardhu_bluesleep_resources[] = {
182         [0] = {
183                 .name = "gpio_host_wake",
184                         .start  = TEGRA_GPIO_PU6,
185                         .end    = TEGRA_GPIO_PU6,
186                         .flags  = IORESOURCE_IO,
187         },
188         [1] = {
189                 .name = "gpio_ext_wake",
190                         .start  = TEGRA_GPIO_PU1,
191                         .end    = TEGRA_GPIO_PU1,
192                         .flags  = IORESOURCE_IO,
193         },
194         [2] = {
195                 .name = "host_wake",
196                         .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
197         },
198 };
199
200 static struct platform_device cardhu_bluesleep_device = {
201         .name           = "bluesleep",
202         .id             = -1,
203         .num_resources  = ARRAY_SIZE(cardhu_bluesleep_resources),
204         .resource       = cardhu_bluesleep_resources,
205 };
206
207 static noinline void __init cardhu_setup_bluesleep(void)
208 {
209         cardhu_bluesleep_resources[2].start =
210                 cardhu_bluesleep_resources[2].end =
211                         gpio_to_irq(TEGRA_GPIO_PU6);
212         platform_device_register(&cardhu_bluesleep_device);
213         return;
214 }
215
216 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
217         /* name         parent          rate            enabled */
218         { "pll_m",      NULL,           0,              false},
219         { "hda",        "pll_p",        108000000,      false},
220         { "hda2codec_2x","pll_p",       48000000,       false},
221         { "pwm",        "pll_p",        3187500,        false},
222         { "blink",      "clk_32k",      32768,          true},
223         { "i2s0",       "pll_a_out0",   0,              false},
224         { "i2s1",       "pll_a_out0",   0,              false},
225         { "i2s3",       "pll_a_out0",   0,              false},
226         { "spdif_out",  "pll_a_out0",   0,              false},
227         { "d_audio",    "clk_m",        12000000,       false},
228         { "dam0",       "clk_m",        12000000,       false},
229         { "dam1",       "clk_m",        12000000,       false},
230         { "dam2",       "clk_m",        12000000,       false},
231         { "audio1",     "i2s1_sync",    0,              false},
232         { "audio3",     "i2s3_sync",    0,              false},
233         { "vi_sensor",  "pll_p",        150000000,      false},
234         { "i2c1",       "pll_p",        3200000,        false},
235         { "i2c2",       "pll_p",        3200000,        false},
236         { "i2c3",       "pll_p",        3200000,        false},
237         { "i2c4",       "pll_p",        3200000,        false},
238         { "i2c5",       "pll_p",        3200000,        false},
239         { "vi",         "pll_p",        0,              false},
240         { NULL,         NULL,           0,              0},
241 };
242
243 static struct pn544_i2c_platform_data nfc_pdata = {
244         .irq_gpio = TEGRA_GPIO_PX0,
245         .ven_gpio = TEGRA_GPIO_PP3,
246         .firm_gpio = TEGRA_GPIO_PO7,
247         };
248
249 static struct i2c_board_info __initdata cardhu_i2c_bus3_board_info[] = {
250         {
251                 I2C_BOARD_INFO("pn544", 0x28),
252                 .platform_data = &nfc_pdata,
253         },
254 };
255 static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
256         .adapter_nr     = 0,
257         .bus_count      = 1,
258         .bus_clk_rate   = { 100000, 0 },
259         .scl_gpio               = {TEGRA_GPIO_PC4, 0},
260         .sda_gpio               = {TEGRA_GPIO_PC5, 0},
261         .arb_recovery = arb_lost_recovery,
262 };
263
264 static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
265         .adapter_nr     = 1,
266         .bus_count      = 1,
267         .bus_clk_rate   = { 400000, 0 },
268         .is_clkon_always = true,
269         .scl_gpio               = {TEGRA_GPIO_PT5, 0},
270         .sda_gpio               = {TEGRA_GPIO_PT6, 0},
271         .arb_recovery = arb_lost_recovery,
272 };
273
274 static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
275         .adapter_nr     = 2,
276         .bus_count      = 1,
277         .bus_clk_rate   = { 100000, 0 },
278         .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
279         .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
280         .arb_recovery = arb_lost_recovery,
281 };
282
283 static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
284         .adapter_nr     = 3,
285         .bus_count      = 1,
286         .bus_clk_rate   = { 10000, 0 },
287         .scl_gpio               = {TEGRA_GPIO_PV4, 0},
288         .sda_gpio               = {TEGRA_GPIO_PV5, 0},
289         .arb_recovery = arb_lost_recovery,
290 };
291
292 static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
293         .adapter_nr     = 4,
294         .bus_count      = 1,
295         .bus_clk_rate   = { 400000, 0 },
296         .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
297         .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
298         .arb_recovery = arb_lost_recovery,
299 };
300
301
302 #if 0
303 struct tegra_wired_jack_conf audio_wr_jack_conf = {
304         .hp_det_n = TEGRA_GPIO_PW2,
305         .en_mic_ext = TEGRA_GPIO_PX1,
306         .en_mic_int = TEGRA_GPIO_PX0,
307 };
308 #endif
309
310 static struct wm8903_platform_data cardhu_wm8903_pdata = {
311         .irq_active_low = 0,
312         .micdet_cfg = 0,
313         .micdet_delay = 100,
314         .gpio_base = CARDHU_GPIO_WM8903(0),
315         .gpio_cfg = {
316                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP1_FN_SHIFT),
317                 (WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT << WM8903_GP2_FN_SHIFT) |
318                         WM8903_GP2_DIR,
319                 WM8903_GPIO_CONFIG_ZERO,
320                 0,
321                 0,
322         },
323 };
324
325 /* Equalizer filter coefs generated from the MAXIM MAX98095
326  * evkit software tool */
327 static struct max98095_eq_cfg max98095_eq_cfg[] = {
328         {
329                 .name = "FLAT",
330                 .rate = 44100,
331                 .band1 = {0x2000, 0xC002, 0x4000, 0x00E9, 0x0000},
332                 .band2 = {0x2000, 0xC00F, 0x4000, 0x02BC, 0x0000},
333                 .band3 = {0x2000, 0xC0A7, 0x4000, 0x0916, 0x0000},
334                 .band4 = {0x2000, 0xC5C2, 0x4000, 0x1A87, 0x0000},
335                 .band5 = {0x2000, 0xF6B0, 0x4000, 0x3F51, 0x0000},
336         },
337         {
338                 .name = "LOWPASS1K",
339                 .rate = 44100,
340                 .band1 = {0x205D, 0xC001, 0x3FEF, 0x002E, 0x02E0},
341                 .band2 = {0x5B9A, 0xC093, 0x3AB2, 0x088B, 0x1981},
342                 .band3 = {0x0D22, 0xC170, 0x26EA, 0x0D79, 0x32CF},
343                 .band4 = {0x0894, 0xC612, 0x01B3, 0x1B34, 0x3FFA},
344                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
345         },
346         { /* BASS=-12dB, TREBLE=+9dB, Fc=5KHz */
347                 .name = "HIBOOST",
348                 .rate = 44100,
349                 .band1 = {0x0815, 0xC001, 0x3AA4, 0x0003, 0x19A2},
350                 .band2 = {0x0815, 0xC103, 0x092F, 0x0B55, 0x3F56},
351                 .band3 = {0x0E0A, 0xC306, 0x1E5C, 0x136E, 0x3856},
352                 .band4 = {0x2459, 0xF665, 0x0CAA, 0x3F46, 0x3EBB},
353                 .band5 = {0x5BBB, 0x3FFF, 0xCEB0, 0x0000, 0x28CA},
354         },
355         { /* BASS=12dB, TREBLE=+12dB */
356                 .name = "LOUD12DB",
357                 .rate = 44100,
358                 .band1 = {0x7FC1, 0xC001, 0x3EE8, 0x0020, 0x0BC7},
359                 .band2 = {0x51E9, 0xC016, 0x3C7C, 0x033F, 0x14E9},
360                 .band3 = {0x1745, 0xC12C, 0x1680, 0x0C2F, 0x3BE9},
361                 .band4 = {0x4536, 0xD7E2, 0x0ED4, 0x31DD, 0x3E42},
362                 .band5 = {0x7FEF, 0x3FFF, 0x0BAB, 0x0000, 0x3EED},
363         },
364         {
365                 .name = "FLAT",
366                 .rate = 16000,
367                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
368                 .band2 = {0x2000, 0xC033, 0x4000, 0x0505, 0x0000},
369                 .band3 = {0x2000, 0xC268, 0x4000, 0x115F, 0x0000},
370                 .band4 = {0x2000, 0xDA62, 0x4000, 0x33C6, 0x0000},
371                 .band5 = {0x2000, 0x4000, 0x4000, 0x0000, 0x0000},
372         },
373         {
374                 .name = "LOWPASS1K",
375                 .rate = 16000,
376                 .band1 = {0x2000, 0xC004, 0x4000, 0x0141, 0x0000},
377                 .band2 = {0x5BE8, 0xC3E0, 0x3307, 0x15ED, 0x26A0},
378                 .band3 = {0x0F71, 0xD15A, 0x08B3, 0x2BD0, 0x3F67},
379                 .band4 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
380                 .band5 = {0x0815, 0x3FFF, 0xCF78, 0x0000, 0x29B7},
381         },
382         { /* BASS=-12dB, TREBLE=+9dB, Fc=2KHz */
383                 .name = "HIBOOST",
384                 .rate = 16000,
385                 .band1 = {0x0815, 0xC001, 0x3BD2, 0x0009, 0x16BF},
386                 .band2 = {0x080E, 0xC17E, 0xF653, 0x0DBD, 0x3F43},
387                 .band3 = {0x0F80, 0xDF45, 0xEE33, 0x36FE, 0x3D79},
388                 .band4 = {0x590B, 0x3FF0, 0xE882, 0x02BD, 0x3B87},
389                 .band5 = {0x4C87, 0xF3D0, 0x063F, 0x3ED4, 0x3FB1},
390         },
391         { /* BASS=12dB, TREBLE=+12dB */
392                 .name = "LOUD12DB",
393                 .rate = 16000,
394                 .band1 = {0x7FC1, 0xC001, 0x3D07, 0x0058, 0x1344},
395                 .band2 = {0x2DA6, 0xC013, 0x3CF1, 0x02FF, 0x138B},
396                 .band3 = {0x18F1, 0xC08E, 0x244D, 0x0863, 0x34B5},
397                 .band4 = {0x2BE0, 0xF385, 0x04FD, 0x3EC5, 0x3FCE},
398                 .band5 = {0x7FEF, 0x4000, 0x0BAB, 0x0000, 0x3EED},
399         },
400 };
401
402 static struct max98095_pdata cardhu_max98095_pdata = {
403         /* equalizer configuration */
404         .eq_cfg = max98095_eq_cfg,
405         .eq_cfgcnt = ARRAY_SIZE(max98095_eq_cfg),
406
407         /* Biquad filter response configuration */
408         .bq_cfg = NULL,
409         .bq_cfgcnt = 0,
410
411         /* microphone configuration */
412         .digmic_left_mode = 1,
413         .digmic_right_mode = 1,
414 };
415
416 static struct i2c_board_info __initdata cardhu_codec_wm8903_info = {
417         I2C_BOARD_INFO("wm8903", 0x1a),
418         .platform_data = &cardhu_wm8903_pdata,
419 };
420
421 static struct i2c_board_info __initdata cardhu_codec_aic326x_info = {
422         I2C_BOARD_INFO("aic3262-codec", 0x18),
423 };
424
425 static struct i2c_board_info __initdata cardhu_codec_max98095_info = {
426         I2C_BOARD_INFO("max98095", 0x10),
427         .platform_data = &cardhu_max98095_pdata,
428 };
429
430 static void cardhu_i2c_init(void)
431 {
432         tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
433         tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
434         tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
435         tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
436         tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
437
438         platform_device_register(&tegra_i2c_device5);
439         platform_device_register(&tegra_i2c_device4);
440         platform_device_register(&tegra_i2c_device3);
441         platform_device_register(&tegra_i2c_device2);
442         platform_device_register(&tegra_i2c_device1);
443
444         cardhu_codec_wm8903_info.irq = cardhu_codec_max98095_info.irq =
445                 cardhu_codec_aic326x_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
446         i2c_register_board_info(4, &cardhu_codec_wm8903_info, 1);
447         i2c_register_board_info(4, &cardhu_codec_max98095_info, 1);
448         i2c_register_board_info(4, &cardhu_codec_aic326x_info, 1);
449
450         cardhu_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PX0);
451         i2c_register_board_info(2, cardhu_i2c_bus3_board_info, 1);
452 }
453
454 static struct platform_device *cardhu_uart_devices[] __initdata = {
455         &tegra_uarta_device,
456         &tegra_uartb_device,
457         &tegra_uartc_device,
458         &tegra_uartd_device,
459         &tegra_uarte_device,
460 };
461 static struct uart_clk_parent uart_parent_clk[] = {
462         [0] = {.name = "clk_m"},
463         [1] = {.name = "pll_p"},
464 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
465         [2] = {.name = "pll_m"},
466 #endif
467 };
468
469 static struct tegra_uart_platform_data cardhu_uart_pdata;
470 static struct tegra_uart_platform_data cardhu_loopback_uart_pdata;
471
472 static void __init uart_debug_init(void)
473 {
474         struct board_info board_info;
475         int debug_port_id;
476
477         tegra_get_board_info(&board_info);
478
479         debug_port_id = get_tegra_uart_debug_port_id();
480         if (debug_port_id < 0) {
481                 debug_port_id = 0;
482                         /* UARTB is debug port
483                          *       for SLT - E1186/E1187/PM269
484                          *       for E1256/E1257
485                          */
486                 if (((board_info.sku & SKU_SLT_ULPI_SUPPORT) &&
487                         ((board_info.board_id == BOARD_E1186) ||
488                         (board_info.board_id == BOARD_E1187) ||
489                         (board_info.board_id == BOARD_PM269))) ||
490                         (board_info.board_id == BOARD_E1256) ||
491                         (board_info.board_id == BOARD_E1257))
492                                 debug_port_id = 1;
493         }
494
495 #ifdef CONFIG_TEGRA_IRDA
496         if ((board_info.board_id == BOARD_E1186) ||
497                 (board_info.board_id == BOARD_E1198)) {
498                 if (debug_port_id == 1) {
499                         cardhu_irda_pdata.is_irda = false;
500                         pr_err("UARTB is not available for IrDA\n");
501                 }
502         }
503 #endif
504
505         switch (debug_port_id) {
506         case 0:
507                 /* UARTA is the debug port. */
508                 pr_info("Selecting UARTA as the debug console\n");
509                 cardhu_uart_devices[0] = &debug_uarta_device;
510                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
511                 debug_uart_port_base = ((struct plat_serial8250_port *)(
512                         debug_uarta_device.dev.platform_data))->mapbase;
513                 break;
514
515         case 1:
516                 /* UARTB is the debug port. */
517                 pr_info("Selecting UARTB as the debug console\n");
518                 cardhu_uart_devices[1] = &debug_uartb_device;
519                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartb");
520                 debug_uart_port_base = ((struct plat_serial8250_port *)(
521                         debug_uartb_device.dev.platform_data))->mapbase;
522                 break;
523
524         case 2:
525                 /* UARTC is the debug port. */
526                 pr_info("Selecting UARTC as the debug console\n");
527                 cardhu_uart_devices[2] = &debug_uartc_device;
528                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartc");
529                 debug_uart_port_base = ((struct plat_serial8250_port *)(
530                         debug_uartc_device.dev.platform_data))->mapbase;
531                 break;
532
533         case 3:
534                 /* UARTD is the debug port. */
535                 pr_info("Selecting UARTD as the debug console\n");
536                 cardhu_uart_devices[3] = &debug_uartd_device;
537                 debug_uart_clk =  clk_get_sys("serial8250.0", "uartd");
538                 debug_uart_port_base = ((struct plat_serial8250_port *)(
539                         debug_uartd_device.dev.platform_data))->mapbase;
540                 break;
541
542         case 4:
543                 /* UARTE is the debug port. */
544                 pr_info("Selecting UARTE as the debug console\n");
545                 cardhu_uart_devices[4] = &debug_uarte_device;
546                 debug_uart_clk =  clk_get_sys("serial8250.0", "uarte");
547                 debug_uart_port_base = ((struct plat_serial8250_port *)(
548                         debug_uarte_device.dev.platform_data))->mapbase;
549                 break;
550
551         default:
552                 pr_info("The debug console id %d is invalid, Assuming UARTA", debug_port_id);
553                 cardhu_uart_devices[0] = &debug_uarta_device;
554                 debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
555                 debug_uart_port_base = ((struct plat_serial8250_port *)(
556                         debug_uarta_device.dev.platform_data))->mapbase;
557                 break;
558         }
559         return;
560 }
561
562 static void __init cardhu_uart_init(void)
563 {
564         struct clk *c;
565         int i;
566         struct board_info board_info;
567
568         tegra_get_board_info(&board_info);
569
570         for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
571                 c = tegra_get_clock_by_name(uart_parent_clk[i].name);
572                 if (IS_ERR_OR_NULL(c)) {
573                         pr_err("Not able to get the clock for %s\n",
574                                                 uart_parent_clk[i].name);
575                         continue;
576                 }
577                 uart_parent_clk[i].parent_clk = c;
578                 uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
579         }
580         cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
581         cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
582         cardhu_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
583         cardhu_loopback_uart_pdata.parent_clk_count =
584                                                 ARRAY_SIZE(uart_parent_clk);
585         cardhu_loopback_uart_pdata.is_loopback = true;
586         tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
587         tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
588         tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
589         tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
590         /* UARTE is used for loopback test purpose */
591         tegra_uarte_device.dev.platform_data = &cardhu_loopback_uart_pdata;
592
593         /* Register low speed only if it is selected */
594         if (!is_tegra_debug_uartport_hs()) {
595                 uart_debug_init();
596                 /* Clock enable for the debug channel */
597                 if (!IS_ERR_OR_NULL(debug_uart_clk)) {
598                         pr_info("The debug console clock name is %s\n",
599                                                 debug_uart_clk->name);
600                         c = tegra_get_clock_by_name("pll_p");
601                         if (IS_ERR_OR_NULL(c))
602                                 pr_err("Not getting the parent clock pll_p\n");
603                         else
604                                 clk_set_parent(debug_uart_clk, c);
605
606                         clk_enable(debug_uart_clk);
607                         clk_set_rate(debug_uart_clk, clk_get_rate(c));
608                 } else {
609                         pr_err("Not getting the clock %s for debug console\n",
610                                         debug_uart_clk->name);
611                 }
612         }
613
614 #ifdef CONFIG_TEGRA_IRDA
615         if (((board_info.board_id == BOARD_E1186) ||
616                 (board_info.board_id == BOARD_E1198)) &&
617                         cardhu_irda_pdata.is_irda) {
618                 cardhu_irda_pdata.parent_clk_list = uart_parent_clk;
619                 cardhu_irda_pdata.parent_clk_count =
620                                         ARRAY_SIZE(uart_parent_clk);
621
622                 tegra_uartb_device.dev.platform_data = &cardhu_irda_pdata;
623         }
624 #endif
625
626         platform_add_devices(cardhu_uart_devices,
627                                 ARRAY_SIZE(cardhu_uart_devices));
628 }
629
630 static struct platform_device tegra_camera = {
631         .name = "tegra_camera",
632         .id = -1,
633 };
634
635 static struct platform_device *cardhu_spi_devices[] __initdata = {
636         &tegra_spi_device4,
637 };
638
639 static struct platform_device *touch_spi_device[] __initdata = {
640         &tegra_spi_device1,
641 };
642
643 struct spi_clk_parent spi_parent_clk[] = {
644         [0] = {.name = "pll_p"},
645 #ifndef CONFIG_TEGRA_PLLM_RESTRICTED
646         [1] = {.name = "pll_m"},
647         [2] = {.name = "clk_m"},
648 #else
649         [1] = {.name = "clk_m"},
650 #endif
651 };
652
653 static struct tegra_spi_platform_data cardhu_spi_pdata = {
654         .is_dma_based           = true,
655         .max_dma_buffer         = (16 * 1024),
656         .is_clkon_always        = false,
657         .max_rate               = 100000000,
658 };
659
660 static void __init cardhu_spi_init(void)
661 {
662         int i;
663         struct clk *c;
664         struct board_info board_info, display_board_info;
665
666         tegra_get_board_info(&board_info);
667         tegra_get_display_board_info(&display_board_info);
668
669         for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
670                 c = tegra_get_clock_by_name(spi_parent_clk[i].name);
671                 if (IS_ERR_OR_NULL(c)) {
672                         pr_err("Not able to get the clock for %s\n",
673                                                 spi_parent_clk[i].name);
674                         continue;
675                 }
676                 spi_parent_clk[i].parent_clk = c;
677                 spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
678         }
679         cardhu_spi_pdata.parent_clk_list = spi_parent_clk;
680         cardhu_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
681         tegra_spi_device4.dev.platform_data = &cardhu_spi_pdata;
682         platform_add_devices(cardhu_spi_devices,
683                                 ARRAY_SIZE(cardhu_spi_devices));
684
685         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
686                 platform_add_devices(touch_spi_device,
687                                 ARRAY_SIZE(touch_spi_device));
688         }
689         if (board_info.board_id == BOARD_E1198) {
690                 tegra_spi_device2.dev.platform_data = &cardhu_spi_pdata;
691                 platform_device_register(&tegra_spi_device2);
692                 tegra_spi_slave_device1.dev.platform_data = &cardhu_spi_pdata;
693                 platform_device_register(&tegra_spi_slave_device1);
694         }
695 }
696
697 static void __init cardhu_dtv_init(void)
698 {
699         struct board_info board_info;
700
701         tegra_get_board_info(&board_info);
702
703         if (board_info.board_id == BOARD_E1186)
704                 platform_device_register(&tegra_dtv_device);
705 }
706
707 static struct resource tegra_rtc_resources[] = {
708         [0] = {
709                 .start = TEGRA_RTC_BASE,
710                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
711                 .flags = IORESOURCE_MEM,
712         },
713         [1] = {
714                 .start = INT_RTC,
715                 .end = INT_RTC,
716                 .flags = IORESOURCE_IRQ,
717         },
718 };
719
720 static struct platform_device tegra_rtc_device = {
721         .name = "tegra_rtc",
722         .id   = -1,
723         .resource = tegra_rtc_resources,
724         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
725 };
726
727 static struct tegra_asoc_platform_data cardhu_audio_wm8903_pdata = {
728         .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
729         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
730         .gpio_hp_mute           = -1,
731         .gpio_int_mic_en        = -1,
732         .gpio_ext_mic_en        = -1,
733         .i2s_param[HIFI_CODEC]  = {
734                 .audio_port_id  = 0,
735                 .is_i2s_master  = 1,
736                 .i2s_mode       = TEGRA_DAIFMT_I2S,
737         },
738         .i2s_param[BASEBAND]    = {
739                 .audio_port_id  = -1,
740         },
741         .i2s_param[BT_SCO]      = {
742                 .audio_port_id  = 3,
743                 .is_i2s_master  = 1,
744                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
745         },
746 };
747
748 static struct tegra_asoc_platform_data cardhu_audio_max98095_pdata = {
749         .gpio_spkr_en           = -1,
750         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
751         .gpio_hp_mute           = -1,
752         .gpio_int_mic_en        = -1,
753         .gpio_ext_mic_en        = -1,
754         .i2s_param[HIFI_CODEC]  = {
755                 .audio_port_id  = 0,
756                 .is_i2s_master  = 1,
757                 .i2s_mode       = TEGRA_DAIFMT_I2S,
758         },
759         .i2s_param[BASEBAND]    = {
760                 .audio_port_id  = -1,
761         },
762         .i2s_param[BT_SCO]      = {
763                 .audio_port_id  = 3,
764                 .is_i2s_master  = 1,
765                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
766         },
767 };
768
769 static struct platform_device cardhu_audio_wm8903_device = {
770         .name   = "tegra-snd-wm8903",
771         .id     = 0,
772         .dev    = {
773                 .platform_data = &cardhu_audio_wm8903_pdata,
774         },
775 };
776
777 static struct platform_device cardhu_audio_max98095_device = {
778         .name   = "tegra-snd-max98095",
779         .id     = 0,
780         .dev    = {
781                 .platform_data = &cardhu_audio_max98095_pdata,
782         },
783 };
784
785 static struct tegra_asoc_platform_data cardhu_audio_aic326x_pdata = {
786         .gpio_spkr_en           = -1,
787         .gpio_hp_det            = TEGRA_GPIO_HP_DET,
788         .gpio_hp_mute           = -1,
789         .gpio_int_mic_en        = -1,
790         .gpio_ext_mic_en        = -1,
791         /*defaults for Verbier-Cardhu board with TI AIC326X codec*/
792         .i2s_param[HIFI_CODEC]  = {
793                 .audio_port_id  = 0,
794                 .is_i2s_master  = 1,
795                 .i2s_mode       = TEGRA_DAIFMT_I2S,
796                 .sample_size    = 16,
797         },
798         .i2s_param[BT_SCO]      = {
799                 .sample_size    = 16,
800                 .audio_port_id  = 3,
801                 .is_i2s_master  = 1,
802                 .i2s_mode       = TEGRA_DAIFMT_DSP_A,
803         },
804 };
805
806 static struct platform_device cardhu_audio_aic326x_device = {
807         .name   = "tegra-snd-aic326x",
808         .id     = 0,
809         .dev    = {
810                 .platform_data  = &cardhu_audio_aic326x_pdata,
811         },
812 };
813
814 static struct platform_device *cardhu_devices[] __initdata = {
815         &tegra_pmu_device,
816         &tegra_rtc_device,
817         &tegra_udc_device,
818         &tegra_wdt0_device,
819         &tegra_wdt1_device,
820         &tegra_wdt2_device,
821 #if defined(CONFIG_TEGRA_AVP)
822         &tegra_avp_device,
823 #endif
824         &tegra_camera,
825 #if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
826         &tegra_se_device,
827 #endif
828         &tegra_ahub_device,
829         &tegra_dam_device0,
830         &tegra_dam_device1,
831         &tegra_dam_device2,
832         &tegra_i2s_device0,
833         &tegra_i2s_device1,
834         &tegra_i2s_device3,
835         &tegra_spdif_device,
836         &spdif_dit_device,
837         &bluetooth_dit_device,
838         &baseband_dit_device,
839         &cardhu_bt_rfkill_device,
840         &tegra_pcm_device,
841         &cardhu_audio_wm8903_device,
842         &cardhu_audio_max98095_device,
843         &cardhu_audio_aic326x_device,
844         &tegra_hda_device,
845         &tegra_cec_device,
846 #if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
847         &tegra_aes_device,
848 #endif
849 };
850
851 #define E1506_MXT_CONFIG_CRC 0x62F903
852 static const u8 e1506_config[] = {
853         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
854         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x05, 0x01, 0x00,
855         0x00, 0x1E, 0x0A, 0x8B, 0x00, 0x00, 0x13, 0x0B,
856         0x00, 0x10, 0x32, 0x03, 0x03, 0x00, 0x03, 0x01,
857         0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xBF, 0x03, 0x1B,
858         0x02, 0x00, 0x00, 0x37, 0x37, 0x00, 0x00, 0x00,
859         0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
860         0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
861         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
862         0x00, 0x00, 0x00, 0xA9, 0x7F, 0x9A, 0x0E, 0x00,
863         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
864         0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00,
865         0x00, 0x00, 0x03, 0x23, 0x00, 0x00, 0x00, 0x0A,
866         0x0F, 0x14, 0x19, 0x03, 0x00, 0x00, 0x00, 0x00,
867         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
868         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
869         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
870         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
871         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
872         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
873         0x00, 0x00, 0x00, 0x01, 0x00, 0x03, 0x08, 0x10,
874         0x00
875 };
876
877 #define MXT_CONFIG_CRC  0xD62DE8
878 static const u8 config[] = {
879         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
880         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x00,
881         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
882         0x1B, 0x2A, 0x00, 0x20, 0x3C, 0x04, 0x05, 0x00,
883         0x02, 0x01, 0x00, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
884         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
885         0x00, 0x00, 0x00, 0x64, 0x02, 0x00, 0x00, 0x00,
886         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
887         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
888         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
889         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
890         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
891         0x00, 0x04, 0xFF, 0x03, 0x3F, 0x64, 0x64, 0x01,
892         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
893         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
894         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
895         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
896         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
897         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
898         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
899 };
900
901 #define MXT_CONFIG_CRC_SKU2000  0xA24D9A
902 static const u8 config_sku2000[] = {
903         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
904         0xFF, 0xFF, 0x32, 0x0A, 0x00, 0x14, 0x14, 0x19,
905         0x00, 0x00, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00,
906         0x1B, 0x2A, 0x00, 0x20, 0x3A, 0x04, 0x05, 0x00,  //23=thr  2 di
907         0x04, 0x04, 0x41, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF,
908         0x02, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
909         0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00,  //0A=limit
910         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
911         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
912         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
913         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
914         0x00, 0x00, 0x00, 0x05, 0x0A, 0x15, 0x1E, 0x00,
915         0x00, 0x04, 0x00, 0x03, 0x3F, 0x64, 0x64, 0x01,
916         0x0A, 0x14, 0x28, 0x4B, 0x00, 0x02, 0x00, 0x64,
917         0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
918         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
919         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
920         0x00, 0x00, 0x00, 0x08, 0x10, 0x3C, 0x00, 0x00,
921         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
922         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
923 };
924
925 static struct mxt_platform_data atmel_mxt_info = {
926         .x_line         = 27,
927         .y_line         = 42,
928         .x_size         = 768,
929         .y_size         = 1366,
930         .blen           = 0x20,
931         .threshold      = 0x3C,
932         .voltage        = 3300000,              /* 3.3V */
933         .orient         = 5,
934         .config         = config,
935         .config_length  = 157,
936         .config_crc     = MXT_CONFIG_CRC,
937         .irqflags       = IRQF_TRIGGER_FALLING,
938 /*      .read_chg       = &read_chg, */
939         .read_chg       = NULL,
940 };
941
942 static struct mxt_platform_data e1506_atmel_mxt_info = {
943         .x_line         = 19,
944         .y_line         = 11,
945         .x_size         = 960,
946         .y_size         = 540,
947         .blen           = 0x10,
948         .threshold      = 0x32,
949         .voltage        = 3300000,              /* 3.3V */
950         .orient         = 3,
951         .config         = e1506_config,
952         .config_length  = 168,
953         .config_crc     = E1506_MXT_CONFIG_CRC,
954         .irqflags       = IRQF_TRIGGER_FALLING,
955 /*      .read_chg       = &read_chg, */
956         .read_chg       = NULL,
957 };
958
959 static struct i2c_board_info __initdata atmel_i2c_info[] = {
960         {
961                 I2C_BOARD_INFO("atmel_mxt_ts", 0x5A),
962                 .platform_data = &atmel_mxt_info,
963         }
964 };
965
966 static struct i2c_board_info __initdata e1506_atmel_i2c_info[] = {
967         {
968                 I2C_BOARD_INFO("atmel_mxt_ts", 0x4A),
969                 .platform_data = &e1506_atmel_mxt_info,
970         }
971 };
972
973 static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
974         /* name         parent          rate            enabled */
975         { "sbc1",       "pll_p",        52000000,       true},
976         { NULL,         NULL,           0,              0},
977 };
978
979 static int __init cardhu_touch_init(void)
980 {
981         struct board_info BoardInfo, DisplayBoardInfo;
982
983         tegra_get_board_info(&BoardInfo);
984         tegra_get_display_board_info(&DisplayBoardInfo);
985         if (DisplayBoardInfo.board_id == BOARD_DISPLAY_PM313) {
986                 tegra_clk_init_from_table(spi_clk_init_table);
987
988                 touch_init_raydium(TEGRA_GPIO_PH4, TEGRA_GPIO_PH6, 2);
989         } else {
990                 gpio_request(TEGRA_GPIO_PH4, "atmel-irq");
991                 gpio_direction_input(TEGRA_GPIO_PH4);
992
993                 gpio_request(TEGRA_GPIO_PH6, "atmel-reset");
994                 gpio_direction_output(TEGRA_GPIO_PH6, 0);
995                 msleep(1);
996                 gpio_set_value(TEGRA_GPIO_PH6, 1);
997                 msleep(100);
998
999                 if ((BoardInfo.sku & SKU_TOUCH_MASK) == SKU_TOUCH_2000) {
1000                         atmel_mxt_info.config = config_sku2000;
1001                         atmel_mxt_info.config_crc = MXT_CONFIG_CRC_SKU2000;
1002                 }
1003
1004                 if (DisplayBoardInfo.board_id == BOARD_DISPLAY_E1506) {
1005                         e1506_atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1006                         i2c_register_board_info(1, e1506_atmel_i2c_info, 1);
1007                 } else {
1008                         atmel_i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PH4);
1009                         i2c_register_board_info(1, atmel_i2c_info, 1);
1010                 }
1011         }
1012
1013         return 0;
1014 }
1015
1016 #if defined(CONFIG_USB_SUPPORT)
1017
1018 static void cardu_usb_hsic_postsupend(void)
1019 {
1020 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1021         baseband_xmm_set_power_status(BBXMM_PS_L2);
1022 #endif
1023 }
1024
1025 static void cardu_usb_hsic_preresume(void)
1026 {
1027 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1028         baseband_xmm_set_power_status(BBXMM_PS_L2TOL0);
1029 #endif
1030 }
1031
1032 static void cardu_usb_hsic_phy_ready(void)
1033 {
1034 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1035         baseband_xmm_set_power_status(BBXMM_PS_L0);
1036 #endif
1037 }
1038
1039 static void cardu_usb_hsic_phy_off(void)
1040 {
1041 #ifdef CONFIG_TEGRA_BB_XMM_POWER
1042         baseband_xmm_set_power_status(BBXMM_PS_L3);
1043 #endif
1044 }
1045
1046 static struct tegra_usb_phy_platform_ops hsic_xmm_plat_ops = {
1047         .post_suspend = cardu_usb_hsic_postsupend,
1048         .pre_resume = cardu_usb_hsic_preresume,
1049         .port_power = cardu_usb_hsic_phy_ready,
1050         .post_phy_off = cardu_usb_hsic_phy_off,
1051 };
1052
1053 static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = {
1054         .port_otg = false,
1055         .has_hostpc = true,
1056         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1057         .op_mode        = TEGRA_USB_OPMODE_HOST,
1058         .u_data.host = {
1059                 .vbus_gpio = -1,
1060                 .hot_plug = false,
1061                 .remote_wakeup_supported = false,
1062                 .power_off_on_suspend = false,
1063         },
1064         .ops = &hsic_xmm_plat_ops,
1065 };
1066 #endif
1067
1068 static int hsic_enable_gpio = -1;
1069 static int hsic_reset_gpio = -1;
1070
1071 void hsic_platform_open(void)
1072 {
1073         int reset_gpio = 0, enable_gpio = 0;
1074
1075         if (hsic_enable_gpio != -1)
1076                 enable_gpio = gpio_request(hsic_enable_gpio, "uhsic_enable");
1077         if (hsic_reset_gpio != -1)
1078                 reset_gpio = gpio_request(hsic_reset_gpio, "uhsic_reset");
1079         /* hsic enable signal deasserted, hsic reset asserted */
1080         if (!enable_gpio)
1081                 gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */);
1082         if (!reset_gpio)
1083                 gpio_direction_output(hsic_reset_gpio, 0 /* asserted */);
1084         /* keep hsic reset asserted for 1 ms */
1085         udelay(1000);
1086         /* enable (power on) hsic */
1087         if (!enable_gpio)
1088                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1089         udelay(1000);
1090         /* deassert reset */
1091         if (!reset_gpio)
1092                 gpio_set_value_cansleep(hsic_reset_gpio, 1);
1093
1094 }
1095
1096 void hsic_platform_close(void)
1097 {
1098         if (hsic_enable_gpio != -1) {
1099                 gpio_set_value(hsic_enable_gpio, 0);
1100                 gpio_free(hsic_enable_gpio);
1101         }
1102         if (hsic_reset_gpio != -1) {
1103                 gpio_set_value(hsic_reset_gpio, 0);
1104                 gpio_free(hsic_reset_gpio);
1105         }
1106 }
1107
1108 void hsic_power_on(void)
1109 {
1110         if (hsic_enable_gpio != -1) {
1111                 gpio_set_value_cansleep(hsic_enable_gpio, 1);
1112                 udelay(1000);
1113         }
1114 }
1115
1116 void hsic_power_off(void)
1117 {
1118         if (hsic_enable_gpio != -1) {
1119                 gpio_set_value_cansleep(hsic_enable_gpio, 0);
1120                 udelay(1000);
1121         }
1122 }
1123
1124 #if defined(CONFIG_USB_SUPPORT)
1125 static struct tegra_usb_phy_platform_ops hsic_plat_ops = {
1126         .open = hsic_platform_open,
1127         .close = hsic_platform_close,
1128         .pre_phy_on = hsic_power_on,
1129         .post_phy_off = hsic_power_off,
1130 };
1131
1132 static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = {
1133         .port_otg = false,
1134         .has_hostpc = true,
1135         .phy_intf = TEGRA_USB_PHY_INTF_HSIC,
1136         .op_mode        = TEGRA_USB_OPMODE_HOST,
1137         .u_data.host = {
1138                 .vbus_gpio = -1,
1139                 .hot_plug = false,
1140                 .remote_wakeup_supported = false,
1141                 .power_off_on_suspend = false,
1142         },
1143         .ops = &hsic_plat_ops,
1144 };
1145
1146 static struct tegra_usb_platform_data tegra_udc_pdata = {
1147         .port_otg = true,
1148         .has_hostpc = true,
1149         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1150         .op_mode = TEGRA_USB_OPMODE_DEVICE,
1151         .u_data.dev = {
1152                 .vbus_pmu_irq = 0,
1153                 .vbus_gpio = -1,
1154                 .charging_supported = false,
1155                 .remote_wakeup_supported = false,
1156         },
1157         .u_cfg.utmi = {
1158                 .hssync_start_delay = 0,
1159                 .elastic_limit = 16,
1160                 .idle_wait_delay = 17,
1161                 .term_range_adj = 6,
1162                 .xcvr_setup = 8,
1163                 .xcvr_lsfslew = 2,
1164                 .xcvr_lsrslew = 2,
1165                 .xcvr_setup_offset = 0,
1166                 .xcvr_use_fuses = 1,
1167         },
1168 };
1169
1170 static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
1171         .port_otg = false,
1172         .has_hostpc = true,
1173         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1174         .op_mode        = TEGRA_USB_OPMODE_HOST,
1175         .u_data.host = {
1176                 .vbus_gpio = -1,
1177                 .hot_plug = false,
1178                 .remote_wakeup_supported = true,
1179                 .power_off_on_suspend = true,
1180         },
1181         .u_cfg.utmi = {
1182                 .hssync_start_delay = 0,
1183                 .elastic_limit = 16,
1184                 .idle_wait_delay = 17,
1185                 .term_range_adj = 6,
1186                 .xcvr_setup = 15,
1187                 .xcvr_lsfslew = 2,
1188                 .xcvr_lsrslew = 2,
1189                 .xcvr_setup_offset = 0,
1190                 .xcvr_use_fuses = 1,
1191         },
1192 };
1193
1194 static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
1195         .port_otg = false,
1196         .has_hostpc = true,
1197         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1198         .op_mode = TEGRA_USB_OPMODE_HOST,
1199         .u_data.host = {
1200                 .vbus_gpio = -1,
1201                 .vbus_reg = "vdd_vbus_typea_usb",
1202                 .hot_plug = true,
1203                 .remote_wakeup_supported = true,
1204                 .power_off_on_suspend = true,
1205         },
1206         .u_cfg.utmi = {
1207                 .hssync_start_delay = 0,
1208                 .elastic_limit = 16,
1209                 .idle_wait_delay = 17,
1210                 .term_range_adj = 6,
1211                 .xcvr_setup = 8,
1212                 .xcvr_lsfslew = 2,
1213                 .xcvr_lsrslew = 2,
1214                 .xcvr_setup_offset = 0,
1215                 .xcvr_use_fuses = 1,
1216         },
1217 };
1218
1219 static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
1220         .port_otg = true,
1221         .has_hostpc = true,
1222         .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
1223         .op_mode = TEGRA_USB_OPMODE_HOST,
1224         .u_data.host = {
1225                 .vbus_gpio = -1,
1226                 .vbus_reg = "vdd_vbus_micro_usb",
1227                 .hot_plug = true,
1228                 .remote_wakeup_supported = true,
1229                 .power_off_on_suspend = true,
1230         },
1231         .u_cfg.utmi = {
1232                 .hssync_start_delay = 0,
1233                 .elastic_limit = 16,
1234                 .idle_wait_delay = 17,
1235                 .term_range_adj = 6,
1236                 .xcvr_setup = 15,
1237                 .xcvr_lsfslew = 2,
1238                 .xcvr_lsrslew = 2,
1239                 .xcvr_setup_offset = 0,
1240                 .xcvr_use_fuses = 1,
1241         },
1242 };
1243
1244 static struct tegra_usb_otg_data tegra_otg_pdata = {
1245         .ehci_device = &tegra_ehci1_device,
1246         .ehci_pdata = &tegra_ehci1_utmi_pdata,
1247 };
1248 #endif
1249
1250 #if defined(CONFIG_USB_SUPPORT)
1251 static void cardhu_usb_init(void)
1252 {
1253         struct board_info bi;
1254
1255         tegra_get_board_info(&bi);
1256
1257         /* OTG should be the first to be registered */
1258         tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
1259         platform_device_register(&tegra_otg_device);
1260
1261         /* setup the udc platform data */
1262         tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
1263
1264         if (bi.board_id == BOARD_PM267) {
1265                 hsic_enable_gpio = EN_HSIC_GPIO;
1266                 hsic_reset_gpio = PM267_SMSC4640_HSIC_HUB_RESET_GPIO;
1267                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1268                 platform_device_register(&tegra_ehci2_device);
1269         } else if (bi.board_id == BOARD_E1256) {
1270                 hsic_enable_gpio = EN_HSIC_GPIO;
1271                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_hsic_pdata;
1272                 platform_device_register(&tegra_ehci2_device);
1273         } else if (bi.board_id == BOARD_E1186) {
1274                 tegra_ehci2_device.dev.platform_data =
1275                                                 &tegra_ehci2_hsic_xmm_pdata;
1276                 /* ehci2 registration happens in baseband-xmm-power  */
1277         } else {
1278                 tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
1279                 platform_device_register(&tegra_ehci2_device);
1280         }
1281
1282         tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
1283         platform_device_register(&tegra_ehci3_device);
1284
1285 }
1286 #else
1287 static void cardhu_usb_init(void) { }
1288 #endif
1289
1290 static struct baseband_power_platform_data tegra_baseband_power_data = {
1291         .baseband_type = BASEBAND_XMM,
1292         .modem = {
1293         .xmm = {
1294                         .bb_rst = XMM_GPIO_BB_RST,
1295                         .bb_on = XMM_GPIO_BB_ON,
1296                         .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE,
1297                         .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE,
1298                         .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE,
1299                         .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ,
1300                         .hsic_device = &tegra_ehci2_device,
1301                 },
1302         },
1303 };
1304
1305 static struct platform_device tegra_baseband_power_device = {
1306         .name = "baseband_xmm_power",
1307         .id = -1,
1308         .dev = {
1309                 .platform_data = &tegra_baseband_power_data,
1310         },
1311 };
1312
1313 static struct platform_device tegra_baseband_power2_device = {
1314         .name = "baseband_xmm_power2",
1315         .id = -1,
1316         .dev = {
1317                 .platform_data = &tegra_baseband_power_data,
1318         },
1319 };
1320
1321
1322 static struct tegra_pci_platform_data cardhu_pci_platform_data = {
1323         .port_status[0] = 1,
1324         .port_status[1] = 1,
1325         .port_status[2] = 1,
1326         .use_dock_detect        = 0,
1327         .gpio           = 0,
1328 };
1329
1330 static void cardhu_pci_init(void)
1331 {
1332         struct board_info board_info;
1333
1334         tegra_get_board_info(&board_info);
1335         if (board_info.board_id == BOARD_E1291) {
1336                 cardhu_pci_platform_data.port_status[0] = 0;
1337                 cardhu_pci_platform_data.port_status[1] = 0;
1338                 cardhu_pci_platform_data.port_status[2] = 1;
1339                 cardhu_pci_platform_data.use_dock_detect = 1;
1340                 cardhu_pci_platform_data.gpio = DOCK_DETECT_GPIO;
1341         }
1342         if ((board_info.board_id == BOARD_E1186) ||
1343                 (board_info.board_id == BOARD_E1187) ||
1344                 (board_info.board_id == BOARD_E1291)) {
1345                 tegra_pci_device.dev.platform_data = &cardhu_pci_platform_data;
1346                 platform_device_register(&tegra_pci_device);
1347         }
1348 }
1349
1350 static void cardhu_modem_init(void)
1351 {
1352         struct board_info board_info;
1353         int w_disable_gpio, ret;
1354
1355         tegra_get_board_info(&board_info);
1356         switch (board_info.board_id) {
1357         case BOARD_E1291:
1358         case BOARD_E1198:
1359                 if (((board_info.board_id == BOARD_E1291) &&
1360                                 (board_info.fab < BOARD_FAB_A03)) ||
1361                         ((board_info.board_id == BOARD_E1198) &&
1362                                         (board_info.fab < BOARD_FAB_A02))) {
1363                         w_disable_gpio = TEGRA_GPIO_PH5;
1364                 } else {
1365                         w_disable_gpio = TEGRA_GPIO_PDD5;
1366                 }
1367
1368                 ret = gpio_request(w_disable_gpio, "w_disable_gpio");
1369                 if (ret < 0)
1370                         pr_err("%s: gpio_request failed for gpio %d\n",
1371                                 __func__, w_disable_gpio);
1372                 else
1373                         gpio_direction_input(w_disable_gpio);
1374
1375                 /* E1291-A04 & E1198:A02: Set PERST signal to high */
1376                 if (((board_info.board_id == BOARD_E1291) &&
1377                                 (board_info.fab >= BOARD_FAB_A04)) ||
1378                         ((board_info.board_id == BOARD_E1198) &&
1379                                         (board_info.fab >= BOARD_FAB_A02))) {
1380                         ret = gpio_request(TEGRA_GPIO_PH7, "modem_perst");
1381                         if (ret < 0) {
1382                                 pr_err("%s(): Error in allocating gpio "
1383                                         "TEGRA_GPIO_PH7\n", __func__);
1384                                 break;
1385                         }
1386                         gpio_direction_output(TEGRA_GPIO_PH7, 1);
1387                 }
1388                 break;
1389         case BOARD_E1186:
1390                 platform_device_register(&tegra_baseband_power_device);
1391                 platform_device_register(&tegra_baseband_power2_device);
1392                 break;
1393         default:
1394                 break;
1395         }
1396
1397 }
1398
1399 #ifdef CONFIG_SATA_AHCI_TEGRA
1400 static void cardhu_sata_init(void)
1401 {
1402         platform_device_register(&tegra_sata_device);
1403 }
1404 #else
1405 static void cardhu_sata_init(void) { }
1406 #endif
1407
1408 static void __init tegra_cardhu_init(void)
1409 {
1410         tegra_thermal_init(&thermal_data,
1411                                 throttle_list,
1412                                 ARRAY_SIZE(throttle_list));
1413         tegra_clk_init_from_table(cardhu_clk_init_table);
1414         tegra_enable_pinmux();
1415         tegra_smmu_init();
1416         cardhu_pinmux_init();
1417         cardhu_i2c_init();
1418         cardhu_spi_init();
1419         cardhu_usb_init();
1420 #ifdef CONFIG_TEGRA_EDP_LIMITS
1421         cardhu_edp_init();
1422 #endif
1423         cardhu_uart_init();
1424         platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
1425         tegra_ram_console_debug_init();
1426         tegra_io_dpd_init();
1427         cardhu_sdhci_init();
1428         cardhu_regulator_init();
1429         cardhu_dtv_init();
1430         cardhu_suspend_init();
1431         cardhu_touch_init();
1432         cardhu_modem_init();
1433         cardhu_kbc_init();
1434         cardhu_scroll_init();
1435         cardhu_keys_init();
1436         cardhu_panel_init();
1437         cardhu_pmon_init();
1438         cardhu_sensors_init();
1439         cardhu_setup_bluesleep();
1440         cardhu_sata_init();
1441         //audio_wired_jack_init();
1442         cardhu_pins_state_init();
1443         cardhu_emc_init();
1444         tegra_release_bootloader_fb();
1445         cardhu_pci_init();
1446 #ifdef CONFIG_TEGRA_WDT_RECOVERY
1447         tegra_wdt_recovery_init();
1448 #endif
1449         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
1450 }
1451
1452 static void __init tegra_cardhu_reserve(void)
1453 {
1454 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
1455         /* support 1920X1200 with 24bpp */
1456         tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
1457 #else
1458         tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
1459 #endif
1460         tegra_ram_console_debug_reserve(SZ_1M);
1461 }
1462
1463 static const char *cardhu_dt_board_compat[] = {
1464         "nvidia,cardhu",
1465         NULL
1466 };
1467
1468 MACHINE_START(CARDHU, "cardhu")
1469         .atag_offset    = 0x100,
1470         .soc            = &tegra_soc_desc,
1471         .map_io         = tegra_map_common_io,
1472         .reserve        = tegra_cardhu_reserve,
1473         .init_early     = tegra30_init_early,
1474         .init_irq       = tegra_init_irq,
1475         .handle_irq     = gic_handle_irq,
1476         .timer          = &tegra_timer,
1477         .init_machine   = tegra_cardhu_init,
1478         .restart        = tegra_assert_system_reset,
1479         .dt_compat      = cardhu_dt_board_compat,
1480 MACHINE_END