ARM: tegra: power: Added global EDP Capping table
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-power.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu-power.c
3  *
4  * Copyright (C) 2011 NVIDIA, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18  * 02111-1307, USA
19  */
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/regulator/machine.h>
25 #include <linux/mfd/tps6591x.h>
26 #include <linux/gpio.h>
27 #include <linux/io.h>
28 #include <linux/regulator/gpio-switch-regulator.h>
29 #include <linux/regulator/tps6591x-regulator.h>
30 #include <linux/regulator/tps6236x-regulator.h>
31
32 #include <mach/iomap.h>
33 #include <mach/irqs.h>
34 #include <mach/pinmux.h>
35 #include <mach/edp.h>
36
37 #include "gpio-names.h"
38 #include "board.h"
39 #include "board-cardhu.h"
40 #include "pm.h"
41 #include "wakeups-t3.h"
42
43 #define PMC_CTRL                0x0
44 #define PMC_CTRL_INTR_LOW       (1 << 17)
45
46 static struct regulator_consumer_supply tps6591x_vdd1_supply_skubit0_0[] = {
47         REGULATOR_SUPPLY("vdd_core", NULL),
48         REGULATOR_SUPPLY("en_vddio_ddr_1v2", NULL),
49 };
50
51 static struct regulator_consumer_supply tps6591x_vdd1_supply_skubit0_1[] = {
52         REGULATOR_SUPPLY("en_vddio_ddr_1v2", NULL),
53 };
54
55 static struct regulator_consumer_supply tps6591x_vdd2_supply_0[] = {
56         REGULATOR_SUPPLY("vdd_gen1v5", NULL),
57         REGULATOR_SUPPLY("vcore_lcd", NULL),
58         REGULATOR_SUPPLY("track_ldo1", NULL),
59         REGULATOR_SUPPLY("external_ldo_1v2", NULL),
60         REGULATOR_SUPPLY("vcore_cam1", NULL),
61         REGULATOR_SUPPLY("vcore_cam2", NULL),
62 };
63
64 static struct regulator_consumer_supply tps6591x_vddctrl_supply_0[] = {
65         REGULATOR_SUPPLY("vdd_cpu_pmu", NULL),
66         REGULATOR_SUPPLY("vdd_cpu", NULL),
67         REGULATOR_SUPPLY("vdd_sys", NULL),
68 };
69
70 static struct regulator_consumer_supply tps6591x_vio_supply_0[] = {
71         REGULATOR_SUPPLY("vdd_gen1v8", NULL),
72         REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
73         REGULATOR_SUPPLY("avdd_usb_pll", NULL),
74         REGULATOR_SUPPLY("avdd_osc", NULL),
75         REGULATOR_SUPPLY("vddio_sys", NULL),
76         REGULATOR_SUPPLY("vddio_sdmmc4", NULL),
77         REGULATOR_SUPPLY("vdd1v8_satelite", NULL),
78         REGULATOR_SUPPLY("vddio_uart", NULL),
79         REGULATOR_SUPPLY("vddio_audio", NULL),
80         REGULATOR_SUPPLY("vddio_bb", NULL),
81         REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
82         REGULATOR_SUPPLY("vddio_cam", NULL),
83         REGULATOR_SUPPLY("vddio_vi", NULL),
84         REGULATOR_SUPPLY("ldo6", NULL),
85         REGULATOR_SUPPLY("ldo7", NULL),
86         REGULATOR_SUPPLY("ldo8", NULL),
87         REGULATOR_SUPPLY("vcore_audio", NULL),
88         REGULATOR_SUPPLY("avcore_audio", NULL),
89         REGULATOR_SUPPLY("vddio_sdmmc3", NULL),
90         REGULATOR_SUPPLY("vcore1_lpddr2", NULL),
91         REGULATOR_SUPPLY("vcom_1v8", NULL),
92         REGULATOR_SUPPLY("pmuio_1v8", NULL),
93         REGULATOR_SUPPLY("avdd_ic_usb", NULL),
94 };
95
96 static struct regulator_consumer_supply tps6591x_ldo1_supply_0[] = {
97         REGULATOR_SUPPLY("avdd_pexb", NULL),
98         REGULATOR_SUPPLY("vdd_pexb", NULL),
99         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
100         REGULATOR_SUPPLY("avdd_pexa", NULL),
101         REGULATOR_SUPPLY("vdd_pexa", NULL),
102 };
103
104 static struct regulator_consumer_supply tps6591x_ldo2_supply_0[] = {
105         REGULATOR_SUPPLY("avdd_sata", NULL),
106         REGULATOR_SUPPLY("vdd_sata", NULL),
107         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
108         REGULATOR_SUPPLY("avdd_plle", NULL),
109 };
110
111 static struct regulator_consumer_supply tps6591x_ldo3_supply_e118x[] = {
112         REGULATOR_SUPPLY("vddio_sdmmc1", NULL),
113 };
114
115 static struct regulator_consumer_supply tps6591x_ldo3_supply_e1198[] = {
116         REGULATOR_SUPPLY("unused_rail_ldo3", NULL),
117 };
118
119 static struct regulator_consumer_supply tps6591x_ldo4_supply_0[] = {
120         REGULATOR_SUPPLY("vdd_rtc", NULL),
121 };
122
123 static struct regulator_consumer_supply tps6591x_ldo5_supply_e118x[] = {
124         REGULATOR_SUPPLY("avdd_vdac", NULL),
125 };
126
127 static struct regulator_consumer_supply tps6591x_ldo5_supply_e1198[] = {
128         REGULATOR_SUPPLY("avdd_vdac", NULL),
129         REGULATOR_SUPPLY("vddio_sdmmc1", NULL),
130 };
131
132 static struct regulator_consumer_supply tps6591x_ldo6_supply_0[] = {
133         REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
134 };
135 static struct regulator_consumer_supply tps6591x_ldo7_supply_0[] = {
136         REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
137         REGULATOR_SUPPLY("avdd_pllm", NULL),
138         REGULATOR_SUPPLY("avdd_pllu_d", NULL),
139         REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
140         REGULATOR_SUPPLY("avdd_pllx", NULL),
141 };
142
143 static struct regulator_consumer_supply tps6591x_ldo8_supply_0[] = {
144         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
145 };
146
147 #define TPS_PDATA_INIT(_name, _sname, _minmv, _maxmv, _supply_reg, _always_on, \
148         _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, _ectrl) \
149         static struct tps6591x_regulator_platform_data pdata_##_name##_##_sname = \
150         {                                                               \
151                 .regulator = {                                          \
152                         .constraints = {                                \
153                                 .min_uV = (_minmv)*1000,                \
154                                 .max_uV = (_maxmv)*1000,                \
155                                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |  \
156                                                      REGULATOR_MODE_STANDBY), \
157                                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |    \
158                                                    REGULATOR_CHANGE_STATUS |  \
159                                                    REGULATOR_CHANGE_VOLTAGE), \
160                                 .always_on = _always_on,                \
161                                 .boot_on = _boot_on,                    \
162                                 .apply_uV = _apply_uv,                  \
163                         },                                              \
164                         .num_consumer_supplies =                        \
165                                 ARRAY_SIZE(tps6591x_##_name##_supply_##_sname), \
166                         .consumer_supplies = tps6591x_##_name##_supply_##_sname,        \
167                         .supply_regulator = _supply_reg,                \
168                 },                                                      \
169                 .init_uV =  _init_uV * 1000,                            \
170                 .init_enable = _init_enable,                            \
171                 .init_apply = _init_apply,                              \
172                 .ectrl = _ectrl                                         \
173         }
174
175 TPS_PDATA_INIT(vdd1, skubit0_0, 600,  1500, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF);
176 TPS_PDATA_INIT(vdd1, skubit0_1, 600,  1500, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF);
177 TPS_PDATA_INIT(vdd2, 0,         600,  1500, 0, 1, 1, 0, -1, 0, 0, 0);
178 TPS_PDATA_INIT(vddctrl, 0,      600,  1400, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_EN1);
179 TPS_PDATA_INIT(vio,  0,         1500, 3300, 0, 1, 1, 0, -1, 0, 0, 0);
180
181 TPS_PDATA_INIT(ldo1, 0,         1000, 3300, tps6591x_rails(VDD_2), 0, 0, 0, -1, 0, 1, 0);
182 TPS_PDATA_INIT(ldo2, 0,         1050, 1050, tps6591x_rails(VDD_2), 0, 0, 1, -1, 0, 1, 0);
183
184 TPS_PDATA_INIT(ldo3, e118x,     1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
185 TPS_PDATA_INIT(ldo3, e1198,     1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
186 TPS_PDATA_INIT(ldo4, 0,         1000, 3300, 0, 1, 0, 0, -1, 0, 0, 0);
187 TPS_PDATA_INIT(ldo5, e118x,     1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
188 TPS_PDATA_INIT(ldo5, e1198,     1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
189
190 TPS_PDATA_INIT(ldo6, 0,         1000, 3300, tps6591x_rails(VIO), 0, 0, 0, -1, 0, 0, 0);
191 TPS_PDATA_INIT(ldo7, 0,         1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 0, 0);
192 TPS_PDATA_INIT(ldo8, 0,         1000, 3300, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, 0);
193
194 #if defined(CONFIG_RTC_DRV_TPS6591x)
195 static struct tps6591x_rtc_platform_data rtc_data = {
196         .irq = TEGRA_NR_IRQS + TPS6591X_INT_RTC_ALARM,
197         .time = {
198                 .tm_year = 2000,
199                 .tm_mon = 0,
200                 .tm_mday = 1,
201                 .tm_hour = 0,
202                 .tm_min = 0,
203                 .tm_sec = 0,
204         },
205 };
206
207 #define TPS_RTC_REG()                                   \
208         {                                               \
209                 .id     = 0,                            \
210                 .name   = "rtc_tps6591x",               \
211                 .platform_data = &rtc_data,             \
212         }
213 #endif
214
215 #define TPS_REG(_id, _name, _sname)                             \
216         {                                                       \
217                 .id     = TPS6591X_ID_##_id,                    \
218                 .name   = "tps6591x-regulator",                 \
219                 .platform_data  = &pdata_##_name##_##_sname,    \
220         }
221
222 #define TPS6591X_DEV_COMMON_E118X               \
223         TPS_REG(VDD_2, vdd2, 0),                \
224         TPS_REG(VDDCTRL, vddctrl, 0),           \
225         TPS_REG(LDO_1, ldo1, 0),                \
226         TPS_REG(LDO_2, ldo2, 0),                \
227         TPS_REG(LDO_3, ldo3, e118x),            \
228         TPS_REG(LDO_4, ldo4, 0),                \
229         TPS_REG(LDO_5, ldo5, e118x),            \
230         TPS_REG(LDO_6, ldo6, 0),                \
231         TPS_REG(LDO_7, ldo7, 0),                \
232         TPS_REG(LDO_8, ldo8, 0)
233
234 static struct tps6591x_subdev_info tps_devs_e118x_skubit0_0[] = {
235         TPS_REG(VIO, vio, 0),
236         TPS_REG(VDD_1, vdd1, skubit0_0),
237         TPS6591X_DEV_COMMON_E118X,
238 #if defined(CONFIG_RTC_DRV_TPS6591x)
239         TPS_RTC_REG(),
240 #endif
241 };
242
243 static struct tps6591x_subdev_info tps_devs_e118x_skubit0_1[] = {
244         TPS_REG(VIO, vio, 0),
245         TPS_REG(VDD_1, vdd1, skubit0_1),
246         TPS6591X_DEV_COMMON_E118X,
247 #if defined(CONFIG_RTC_DRV_TPS6591x)
248         TPS_RTC_REG(),
249 #endif
250 };
251
252 #define TPS6591X_DEV_COMMON_CARDHU              \
253         TPS_REG(VDD_2, vdd2, 0),                \
254         TPS_REG(VDDCTRL, vddctrl, 0),           \
255         TPS_REG(LDO_1, ldo1, 0),                \
256         TPS_REG(LDO_2, ldo2, 0),                \
257         TPS_REG(LDO_3, ldo3, e1198),            \
258         TPS_REG(LDO_4, ldo4, 0),                \
259         TPS_REG(LDO_5, ldo5, e1198),            \
260         TPS_REG(LDO_6, ldo6, 0),                \
261         TPS_REG(LDO_7, ldo7, 0),                \
262         TPS_REG(LDO_8, ldo8, 0)
263
264 static struct tps6591x_subdev_info tps_devs_e1198_skubit0_0[] = {
265         TPS_REG(VIO, vio, 0),
266         TPS_REG(VDD_1, vdd1, skubit0_0),
267         TPS6591X_DEV_COMMON_CARDHU,
268 #if defined(CONFIG_RTC_DRV_TPS6591x)
269         TPS_RTC_REG(),
270 #endif
271 };
272
273 static struct tps6591x_subdev_info tps_devs_e1198_skubit0_1[] = {
274         TPS_REG(VIO, vio, 0),
275         TPS_REG(VDD_1, vdd1, skubit0_1),
276         TPS6591X_DEV_COMMON_CARDHU,
277 #if defined(CONFIG_RTC_DRV_TPS6591x)
278         TPS_RTC_REG(),
279 #endif
280 };
281
282 #define TPS_GPIO_INIT_PDATA(gpio_nr, _init_apply, _sleep_en, _pulldn_en, _output_en, _output_val)       \
283         [gpio_nr] = {                                   \
284                         .sleep_en       = _sleep_en,    \
285                         .pulldn_en      = _pulldn_en,   \
286                         .output_mode_en = _output_en,   \
287                         .output_val     = _output_val,  \
288                         .init_apply     = _init_apply,  \
289                      }
290 static struct tps6591x_gpio_init_data tps_gpio_pdata_e1291_a04[] =  {
291         TPS_GPIO_INIT_PDATA(0, 0, 0, 0, 0, 0),
292         TPS_GPIO_INIT_PDATA(1, 0, 0, 0, 0, 0),
293         TPS_GPIO_INIT_PDATA(2, 1, 1, 0, 1, 1),
294         TPS_GPIO_INIT_PDATA(3, 0, 0, 0, 0, 0),
295         TPS_GPIO_INIT_PDATA(4, 0, 0, 0, 0, 0),
296         TPS_GPIO_INIT_PDATA(5, 0, 0, 0, 0, 0),
297         TPS_GPIO_INIT_PDATA(6, 0, 0, 0, 0, 0),
298         TPS_GPIO_INIT_PDATA(7, 0, 0, 0, 0, 0),
299         TPS_GPIO_INIT_PDATA(8, 0, 0, 0, 0, 0),
300 };
301
302 static struct tps6591x_sleep_keepon_data tps_slp_keepon = {
303         .clkout32k_keepon = 1,
304 };
305
306 static struct tps6591x_platform_data tps_platform = {
307         .irq_base       = TPS6591X_IRQ_BASE,
308         .gpio_base      = TPS6591X_GPIO_BASE,
309         .dev_slp_en     = true,
310         .slp_keepon     = &tps_slp_keepon,
311 };
312
313 static struct i2c_board_info __initdata cardhu_regulators[] = {
314         {
315                 I2C_BOARD_INFO("tps6591x", 0x2D),
316                 .irq            = INT_EXTERNAL_PMU,
317                 .platform_data  = &tps_platform,
318         },
319 };
320
321 /* TPS62361B DC-DC converter */
322 static struct regulator_consumer_supply tps6236x_dcdc_supply[] = {
323         REGULATOR_SUPPLY("vdd_core", NULL),
324 };
325
326 static struct tps6236x_regulator_platform_data tps6236x_pdata = {
327         .reg_init_data = {                                      \
328                 .constraints = {                                \
329                         .min_uV = 500000,                       \
330                         .max_uV = 1770000,                      \
331                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |  \
332                                              REGULATOR_MODE_STANDBY), \
333                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |    \
334                                            REGULATOR_CHANGE_STATUS |  \
335                                            REGULATOR_CHANGE_VOLTAGE), \
336                         .always_on = 1,                         \
337                         .boot_on =  1,                          \
338                         .apply_uV = 0,                          \
339                 },                                              \
340                 .num_consumer_supplies = ARRAY_SIZE(tps6236x_dcdc_supply), \
341                 .consumer_supplies = tps6236x_dcdc_supply,              \
342                 },                                                      \
343         .internal_pd_enable = 0,                                        \
344         .vsel = 3,                                                      \
345         .init_uV = -1,                                                  \
346         .init_apply = 0,                                                \
347 };
348
349 static struct i2c_board_info __initdata tps6236x_boardinfo[] = {
350         {
351                 I2C_BOARD_INFO("tps62361B", 0x60),
352                 .platform_data  = &tps6236x_pdata,
353         },
354 };
355
356 int __init cardhu_regulator_init(void)
357 {
358         struct board_info board_info;
359         struct board_info pmu_board_info;
360         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
361         u32 pmc_ctrl;
362
363         /* configure the power management controller to trigger PMU
364          * interrupts when low */
365
366         pmc_ctrl = readl(pmc + PMC_CTRL);
367         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
368
369         /* The regulator details have complete constraints */
370         regulator_has_full_constraints();
371
372         tegra_get_board_info(&board_info);
373         tegra_get_pmu_board_info(&pmu_board_info);
374
375         if ((board_info.board_id == BOARD_E1198) ||
376                 (board_info.board_id == BOARD_E1291)) {
377                 if (board_info.sku & SKU_DCDC_TPS62361_SUPPORT) {
378                         tps_platform.num_subdevs =
379                                         ARRAY_SIZE(tps_devs_e1198_skubit0_1);
380                         tps_platform.subdevs = tps_devs_e1198_skubit0_1;
381                 } else {
382                         tps_platform.num_subdevs =
383                                         ARRAY_SIZE(tps_devs_e1198_skubit0_0);
384                         tps_platform.subdevs = tps_devs_e1198_skubit0_0;
385                 }
386         } else {
387                 if (pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT) {
388                         tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_e118x_skubit0_1);
389                         tps_platform.subdevs = tps_devs_e118x_skubit0_1;
390                 } else {
391                         tps_platform.num_subdevs = ARRAY_SIZE(tps_devs_e118x_skubit0_0);
392                         tps_platform.subdevs = tps_devs_e118x_skubit0_0;
393                 }
394         }
395
396         /* E1291-A04: Enable DEV_SLP and enable sleep on GPIO2 */
397         if ((board_info.board_id == BOARD_E1291) && (board_info.fab == BOARD_FAB_A04)) {
398                 tps_platform.dev_slp_en = true;
399                 tps_platform.gpio_init_data = tps_gpio_pdata_e1291_a04;
400                 tps_platform.num_gpioinit_data =
401                                         ARRAY_SIZE(tps_gpio_pdata_e1291_a04);
402         }
403
404         i2c_register_board_info(4, cardhu_regulators, 1);
405
406         /* Resgister the TPS6236x for all boards whose sku bit 0 is set. */
407         if ((board_info.sku & SKU_DCDC_TPS62361_SUPPORT) ||
408                         (pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT)) {
409                 pr_info("Registering the device TPS62361B\n");
410                 i2c_register_board_info(4, tps6236x_boardinfo, 1);
411         }
412         return 0;
413 }
414
415 /* EN_5V_CP from PMU GP0 */
416 static struct regulator_consumer_supply gpio_switch_en_5v_cp_supply[] = {
417         REGULATOR_SUPPLY("vdd_5v0_sby", NULL),
418         REGULATOR_SUPPLY("vdd_hall", NULL),
419         REGULATOR_SUPPLY("vterm_ddr", NULL),
420         REGULATOR_SUPPLY("v2ref_ddr", NULL),
421 };
422 static int gpio_switch_en_5v_cp_voltages[] = { 5000};
423
424 /* EN_5V0 From PMU GP2 */
425 static struct regulator_consumer_supply gpio_switch_en_5v0_supply[] = {
426         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
427 };
428 static int gpio_switch_en_5v0_voltages[] = { 5000};
429
430 /* EN_DDR From PMU GP6 */
431 static struct regulator_consumer_supply gpio_switch_en_ddr_supply[] = {
432         REGULATOR_SUPPLY("mem_vddio_ddr", NULL),
433         REGULATOR_SUPPLY("t30_vddio_ddr", NULL),
434 };
435 static int gpio_switch_en_ddr_voltages[] = { 1500};
436
437 /* EN_3V3_SYS From PMU GP7 */
438 static struct regulator_consumer_supply gpio_switch_en_3v3_sys_supply[] = {
439         REGULATOR_SUPPLY("vdd_lvds", NULL),
440         REGULATOR_SUPPLY("vdd_pnl", NULL),
441         REGULATOR_SUPPLY("vcom_3v3", NULL),
442         REGULATOR_SUPPLY("vdd_3v3", NULL),
443         REGULATOR_SUPPLY("vcore_mmc", NULL),
444         REGULATOR_SUPPLY("vddio_pex_ctl", NULL),
445         REGULATOR_SUPPLY("hvdd_pex", NULL),
446         REGULATOR_SUPPLY("avdd_hdmi", NULL),
447         REGULATOR_SUPPLY("vpp_fuse", NULL),
448         REGULATOR_SUPPLY("avdd_usb", NULL),
449         REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
450         REGULATOR_SUPPLY("vcore_nand", NULL),
451         REGULATOR_SUPPLY("hvdd_sata", NULL),
452         REGULATOR_SUPPLY("vddio_gmi_pmu", NULL),
453         REGULATOR_SUPPLY("avdd_cam1", NULL),
454         REGULATOR_SUPPLY("vdd_af", NULL),
455         REGULATOR_SUPPLY("avdd_cam2", NULL),
456         REGULATOR_SUPPLY("vdd_acc", NULL),
457         REGULATOR_SUPPLY("vdd_phtl", NULL),
458         REGULATOR_SUPPLY("vddio_tp", NULL),
459         REGULATOR_SUPPLY("vdd_led", NULL),
460         REGULATOR_SUPPLY("vddio_cec", NULL),
461         REGULATOR_SUPPLY("vdd_cmps", NULL),
462         REGULATOR_SUPPLY("vdd_temp", NULL),
463         REGULATOR_SUPPLY("vpp_kfuse", NULL),
464         REGULATOR_SUPPLY("vddio_ts", NULL),
465         REGULATOR_SUPPLY("vdd_ir_led", NULL),
466         REGULATOR_SUPPLY("vddio_1wire", NULL),
467         REGULATOR_SUPPLY("avddio_audio", NULL),
468         REGULATOR_SUPPLY("vdd_ec", NULL),
469         REGULATOR_SUPPLY("vcom_pa", NULL),
470         REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
471         REGULATOR_SUPPLY("vdd_3v3_dock", NULL),
472         REGULATOR_SUPPLY("vdd_3v3_edid", NULL),
473         REGULATOR_SUPPLY("vdd_3v3_hdmi_cec", NULL),
474         REGULATOR_SUPPLY("vdd_3v3_gmi", NULL),
475         REGULATOR_SUPPLY("vdd_3v3_spk_amp", NULL),
476         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
477         REGULATOR_SUPPLY("vdd_3v3_cam", NULL),
478         REGULATOR_SUPPLY("vdd_3v3_als", NULL),
479         REGULATOR_SUPPLY("debug_cons", NULL),
480 };
481 static int gpio_switch_en_3v3_sys_voltages[] = { 3300};
482
483 /* DIS_5V_SWITCH from AP SPI2_SCK X02 */
484 static struct regulator_consumer_supply gpio_switch_dis_5v_switch_supply[] = {
485         REGULATOR_SUPPLY("master_5v_switch", NULL),
486 };
487 static int gpio_switch_dis_5v_switch_voltages[] = { 5000};
488
489 /* EN_VDD_BL */
490 static struct regulator_consumer_supply gpio_switch_en_vdd_bl_supply[] = {
491         REGULATOR_SUPPLY("vdd_backlight", NULL),
492         REGULATOR_SUPPLY("vdd_backlight1", NULL),
493 };
494 static int gpio_switch_en_vdd_bl_voltages[] = { 5000};
495
496 /* EN_VDD_BL2 (E1291-A03) from AP PEX_L0_PRSNT_N DD.00 */
497 static struct regulator_consumer_supply gpio_switch_en_vdd_bl2_supply[] = {
498         REGULATOR_SUPPLY("vdd_backlight2", NULL),
499 };
500 static int gpio_switch_en_vdd_bl2_voltages[] = { 5000};
501
502 /* EN_3V3_MODEM from AP GPIO VI_VSYNCH D06*/
503 static struct regulator_consumer_supply gpio_switch_en_3v3_modem_supply[] = {
504         REGULATOR_SUPPLY("vdd_3v3_mini_card", NULL),
505         REGULATOR_SUPPLY("vdd_mini_card", NULL),
506 };
507 static int gpio_switch_en_3v3_modem_voltages[] = { 3300};
508
509 /* EN_USB1_VBUS_OC*/
510 static struct regulator_consumer_supply gpio_switch_en_usb1_vbus_oc_supply[] = {
511         REGULATOR_SUPPLY("vdd_vbus_micro_usb", NULL),
512 };
513 static int gpio_switch_en_usb1_vbus_oc_voltages[] = { 5000};
514
515 /*EN_USB3_VBUS_OC*/
516 static struct regulator_consumer_supply gpio_switch_en_usb3_vbus_oc_supply[] = {
517         REGULATOR_SUPPLY("vdd_vbus_typea_usb", NULL),
518 };
519 static int gpio_switch_en_usb3_vbus_oc_voltages[] = { 5000};
520
521 /* EN_VDDIO_VID_OC from AP GPIO VI_PCLK T00*/
522 static struct regulator_consumer_supply gpio_switch_en_vddio_vid_oc_supply[] = {
523         REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
524 };
525 static int gpio_switch_en_vddio_vid_oc_voltages[] = { 5000};
526
527 /* EN_VDD_PNL1 from AP GPIO VI_D6 L04*/
528 static struct regulator_consumer_supply gpio_switch_en_vdd_pnl1_supply[] = {
529         REGULATOR_SUPPLY("vdd_lcd_panel", NULL),
530 };
531 static int gpio_switch_en_vdd_pnl1_voltages[] = { 3300};
532
533 /* CAM1_LDO_EN from AP GPIO KB_ROW6 R06*/
534 static struct regulator_consumer_supply gpio_switch_cam1_ldo_en_supply[] = {
535         REGULATOR_SUPPLY("vdd_2v8_cam1", NULL),
536         REGULATOR_SUPPLY("vdd_2v8_cam1_af", NULL),
537 };
538 static int gpio_switch_cam1_ldo_en_voltages[] = { 2800};
539
540 /* CAM2_LDO_EN from AP GPIO KB_ROW7 R07*/
541 static struct regulator_consumer_supply gpio_switch_cam2_ldo_en_supply[] = {
542         REGULATOR_SUPPLY("vdd_2v8_cam2", NULL),
543         REGULATOR_SUPPLY("vdd_2v8_cam2_af", NULL),
544 };
545 static int gpio_switch_cam2_ldo_en_voltages[] = { 2800};
546
547 /* CAM3_LDO_EN from AP GPIO KB_ROW8 S00*/
548 static struct regulator_consumer_supply gpio_switch_cam3_ldo_en_supply[] = {
549         REGULATOR_SUPPLY("vdd_cam3", NULL),
550 };
551 static int gpio_switch_cam3_ldo_en_voltages[] = { 3300};
552
553 /* EN_VDD_COM from AP GPIO SDMMC3_DAT5 D00*/
554 static struct regulator_consumer_supply gpio_switch_en_vdd_com_supply[] = {
555         REGULATOR_SUPPLY("vdd_com_bd", NULL),
556 };
557 static int gpio_switch_en_vdd_com_voltages[] = { 3300};
558
559 /* EN_VDD_SDMMC1 from AP GPIO VI_HSYNC D07*/
560 static struct regulator_consumer_supply gpio_switch_en_vdd_sdmmc1_supply[] = {
561         REGULATOR_SUPPLY("vddio_sd_slot", NULL),
562 };
563 static int gpio_switch_en_vdd_sdmmc1_voltages[] = { 3300};
564
565 /* EN_3V3_EMMC from AP GPIO SDMMC3_DAT4 D01*/
566 static struct regulator_consumer_supply gpio_switch_en_3v3_emmc_supply[] = {
567         REGULATOR_SUPPLY("vdd_emmc_core", NULL),
568 };
569 static int gpio_switch_en_3v3_emmc_voltages[] = { 3300};
570
571 /* EN_3V3_PEX_HVDD from AP GPIO VI_D09 L07*/
572 static struct regulator_consumer_supply gpio_switch_en_3v3_pex_hvdd_supply[] = {
573         REGULATOR_SUPPLY("hvdd_pex_3v3", NULL),
574 };
575 static int gpio_switch_en_3v3_pex_hvdd_voltages[] = { 3300};
576
577 /* EN_3v3_FUSE from AP GPIO VI_D08 L06*/
578 static struct regulator_consumer_supply gpio_switch_en_3v3_fuse_supply[] = {
579         REGULATOR_SUPPLY("vdd_fuse", NULL),
580 };
581 static int gpio_switch_en_3v3_fuse_voltages[] = { 3300};
582
583 /* EN_1V8_CAM from AP GPIO GPIO_PBB4 PBB04*/
584 static struct regulator_consumer_supply gpio_switch_en_1v8_cam_supply[] = {
585         REGULATOR_SUPPLY("vdd_1v8_cam1", NULL),
586         REGULATOR_SUPPLY("vdd_1v8_cam2", NULL),
587         REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
588 };
589 static int gpio_switch_en_1v8_cam_voltages[] = { 1800};
590
591 static struct regulator_consumer_supply gpio_switch_en_vbrtr_supply[] = {
592         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
593 };
594 static int gpio_switch_en_vbrtr_voltages[] = { 3300};
595
596 static int enable_load_switch_rail(
597                 struct gpio_switch_regulator_subdev_data *psubdev_data)
598 {
599         int ret;
600
601         if (psubdev_data->pin_group <= 0)
602                 return -EINVAL;
603
604         /* Tristate and make pin as input*/
605         ret = tegra_pinmux_set_tristate(psubdev_data->pin_group,
606                                                 TEGRA_TRI_TRISTATE);
607         if (ret < 0)
608                 return ret;
609         return gpio_direction_input(psubdev_data->gpio_nr);
610 }
611
612 static int disable_load_switch_rail(
613                 struct gpio_switch_regulator_subdev_data *psubdev_data)
614 {
615         int ret;
616
617         if (psubdev_data->pin_group <= 0)
618                 return -EINVAL;
619
620         /* Un-tristate and driver low */
621         ret = tegra_pinmux_set_tristate(psubdev_data->pin_group,
622                                                 TEGRA_TRI_NORMAL);
623         if (ret < 0)
624                 return ret;
625         return gpio_direction_output(psubdev_data->gpio_nr, 0);
626 }
627
628
629 /* Macro for defining gpio switch regulator sub device data */
630 #define GREG_INIT(_id, _var, _name, _input_supply, _always_on, _boot_on, \
631         _gpio_nr, _active_low, _init_state, _pg, _enable, _disable)      \
632         static struct gpio_switch_regulator_subdev_data gpio_pdata_##_var =  \
633         {                                                               \
634                 .regulator_name = "gpio-switch-"#_name,                 \
635                 .input_supply   = _input_supply,                        \
636                 .id             = _id,                                  \
637                 .gpio_nr        = _gpio_nr,                             \
638                 .pin_group      = _pg,                                  \
639                 .active_low     = _active_low,                          \
640                 .init_state     = _init_state,                          \
641                 .voltages       = gpio_switch_##_name##_voltages,       \
642                 .n_voltages     = ARRAY_SIZE(gpio_switch_##_name##_voltages), \
643                 .num_consumer_supplies =                                \
644                                 ARRAY_SIZE(gpio_switch_##_name##_supply), \
645                 .consumer_supplies = gpio_switch_##_name##_supply,      \
646                 .constraints = {                                        \
647                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
648                                              REGULATOR_MODE_STANDBY),   \
649                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
650                                            REGULATOR_CHANGE_STATUS |    \
651                                            REGULATOR_CHANGE_VOLTAGE),   \
652                         .always_on = _always_on,                        \
653                         .boot_on = _boot_on,                            \
654                 },                                                      \
655                 .enable_rail = _enable,                                 \
656                 .disable_rail = _disable,                               \
657         }
658
659 /* common to most of boards*/
660 GREG_INIT(0, en_5v_cp,          en_5v_cp,       NULL,                   1,      0,      TPS6591X_GPIO_0,        false,  1,      0,      0,      0);
661 GREG_INIT(1, en_5v0,            en_5v0,         NULL,                   0,      0,      TPS6591X_GPIO_2,        false,  0,      0,      0,      0);
662 GREG_INIT(2, en_ddr,            en_ddr,         NULL,                   0,      0,      TPS6591X_GPIO_6,        false,  0,      0,      0,      0);
663 GREG_INIT(3, en_3v3_sys,        en_3v3_sys,     NULL,                   0,      0,      TPS6591X_GPIO_7,        false,  0,      0,      0,      0);
664 GREG_INIT(4, en_vdd_bl,         en_vdd_bl,      NULL,                   0,      0,      TEGRA_GPIO_PK3,         false,  1,      0,      0,      0);
665 GREG_INIT(5, en_3v3_modem,      en_3v3_modem,   NULL,                   1,      0,      TEGRA_GPIO_PD6,         false,  1,      0,      0,      0);
666 GREG_INIT(6, en_vdd_pnl1,       en_vdd_pnl1,    "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PL4,         false,  1,      0,      0,      0);
667 GREG_INIT(7, cam3_ldo_en,       cam3_ldo_en,    "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PS0,         false,  0,      0,      0,      0);
668 GREG_INIT(8, en_vdd_com,        en_vdd_com,     "vdd_3v3_devices",      1,      0,      TEGRA_GPIO_PD0,         false,  1,      0,      0,      0);
669 GREG_INIT(9, en_3v3_fuse,       en_3v3_fuse,    "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PL6,         false,  0,      0,      0,      0);
670 GREG_INIT(10, en_3v3_emmc,      en_3v3_emmc,    "vdd_3v3_devices",      1,      0,      TEGRA_GPIO_PD1,         false,  1,      0,      0,      0);
671 GREG_INIT(11, en_vdd_sdmmc1,    en_vdd_sdmmc1,  "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PD7,         false,  1,      0,      0,      0);
672 GREG_INIT(12, en_3v3_pex_hvdd,  en_3v3_pex_hvdd, "vdd_3v3_devices",     0,      0,      TEGRA_GPIO_PL7,         false,  0,      0,      0,      0);
673 GREG_INIT(13, en_1v8_cam,       en_1v8_cam,     "vdd_gen1v8",           0,      0,      TEGRA_GPIO_PBB4,        false,  0,      0,      0,      0);
674
675 /* E1291-A04 specific */
676 GREG_INIT(1, en_5v0_a04,        en_5v0,         NULL,                   0,      0,      TPS6591X_GPIO_8,        false,  0,      0,      0,      0);
677 GREG_INIT(2, en_ddr_a04,        en_ddr,         NULL,                   0,      0,      TPS6591X_GPIO_7,        false,  0,      0,      0,      0);
678 GREG_INIT(3, en_3v3_sys_a04,    en_3v3_sys,     NULL,                   0,      0,      TPS6591X_GPIO_6,        false,  0,      0,      0,      0);
679
680
681 /*Specific to pm269*/
682 GREG_INIT(4, en_vdd_bl_pm269,           en_vdd_bl,              NULL,
683         0,      0,      TEGRA_GPIO_PH3, false,  1,      0,      0,      0);
684 GREG_INIT(6, en_vdd_pnl1_pm269,         en_vdd_pnl1,            "vdd_3v3_devices",
685         0,      0,      TEGRA_GPIO_PW1, false,  1,      0,      0,      0);
686 GREG_INIT(9, en_3v3_fuse_pm269,         en_3v3_fuse,            "vdd_3v3_devices",
687         0,      0,      TEGRA_GPIO_PC1, false,  0,      0,      0,      0);
688 GREG_INIT(11, en_vdd_sdmmc1_pm269,      en_vdd_sdmmc1,          "vdd_3v3_devices",
689         0,      0,      TEGRA_GPIO_PP1, false,  1,      0,      0,      0);
690 GREG_INIT(12, en_3v3_pex_hvdd_pm269,    en_3v3_pex_hvdd,        "vdd_3v3_devices",
691         0,      0,      TEGRA_GPIO_PC6, false,  0,      0,      0,      0);
692 GREG_INIT(17, en_vddio_vid_oc_pm269,    en_vddio_vid_oc,        "master_5v_switch",
693         0,      0,      TEGRA_GPIO_PP2, false,  0,      TEGRA_PINGROUP_DAP3_DOUT,
694         enable_load_switch_rail, disable_load_switch_rail);
695
696 /* Specific to E1187/E1186/E1256 */
697 GREG_INIT(14, dis_5v_switch_e118x,      dis_5v_switch,          "vdd_5v0_sys",
698                 0,      0,      TEGRA_GPIO_PX2,         true,   0,      0,      0,      0);
699 GREG_INIT(15, en_usb1_vbus_oc_e118x,    en_usb1_vbus_oc,        "master_5v_switch",
700                 0,      0,      TEGRA_GPIO_PI4,         false,  0,      TEGRA_PINGROUP_GMI_RST_N,
701                 enable_load_switch_rail, disable_load_switch_rail);
702 GREG_INIT(16, en_usb3_vbus_oc_e118x,    en_usb3_vbus_oc,        "master_5v_switch",
703                 0,      0,      TEGRA_GPIO_PH7,         false,  0,      TEGRA_PINGROUP_GMI_AD15,
704                 enable_load_switch_rail, disable_load_switch_rail);
705 GREG_INIT(17, en_vddio_vid_oc_e118x,    en_vddio_vid_oc,        "master_5v_switch",
706                 0,      0,      TEGRA_GPIO_PT0,         false,  0,      TEGRA_PINGROUP_VI_PCLK,
707                 enable_load_switch_rail, disable_load_switch_rail);
708
709 /* E1198/E1291 specific  fab < A03 */
710 GREG_INIT(15, en_usb1_vbus_oc,          en_usb1_vbus_oc,        "vdd_5v0_sys",
711                 0,      0,      TEGRA_GPIO_PI4,         false,  0,      TEGRA_PINGROUP_GMI_RST_N,
712                 enable_load_switch_rail, disable_load_switch_rail);
713 GREG_INIT(16, en_usb3_vbus_oc,          en_usb3_vbus_oc,        "vdd_5v0_sys",
714                 0,      0,      TEGRA_GPIO_PH7,         false,  0,      TEGRA_PINGROUP_GMI_AD15,
715                 enable_load_switch_rail, disable_load_switch_rail);
716
717 /* E1198/E1291 specific  fab >= A03 */
718 GREG_INIT(15, en_usb1_vbus_oc_a03,      en_usb1_vbus_oc,        "vdd_5v0_sys",
719                 0,      0,      TEGRA_GPIO_PDD6,                false,  0,      TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
720                 enable_load_switch_rail, disable_load_switch_rail);
721 GREG_INIT(16, en_usb3_vbus_oc_a03,              en_usb3_vbus_oc,        "vdd_5v0_sys",
722                 0,      0,      TEGRA_GPIO_PDD4,                false,  0,      TEGRA_PINGROUP_PEX_L1_PRSNT_N,
723                 enable_load_switch_rail, disable_load_switch_rail);
724
725 /* E1198/E1291 specific */
726 GREG_INIT(17, en_vddio_vid_oc,          en_vddio_vid_oc,        "vdd_5v0_sys",
727                 0,      0,      TEGRA_GPIO_PT0,         false,  0,      TEGRA_PINGROUP_VI_PCLK,
728                 enable_load_switch_rail, disable_load_switch_rail);
729
730 /* E1198/E1291 specific*/
731 GREG_INIT(18, cam1_ldo_en,      cam1_ldo_en,    "vdd_3v3_cam",  0,      0,      TEGRA_GPIO_PR6,         false,  0,      0,      0,      0);
732 GREG_INIT(19, cam2_ldo_en,      cam2_ldo_en,    "vdd_3v3_cam",  0,      0,      TEGRA_GPIO_PR7,         false,  0,      0,      0,      0);
733
734 /* E1291 A03 specific */
735 GREG_INIT(20, en_vdd_bl1_a03,   en_vdd_bl,      NULL,           0,      0,      TEGRA_GPIO_PDD2,        false,  1,      0,      0,      0);
736 GREG_INIT(21, en_vdd_bl2_a03,   en_vdd_bl2,     NULL,           0,      0,      TEGRA_GPIO_PDD0,        false,  1,      0,      0,      0);
737
738 GREG_INIT(22, en_vbrtr,         en_vbrtr,       "vdd_3v3_devices",      0,      0,      PMU_TCA6416_GPIO_PORT12,        false,  0,      0,      0,      0);
739
740 #define ADD_GPIO_REG(_name) &gpio_pdata_##_name
741
742 #define COMMON_GPIO_REG \
743         ADD_GPIO_REG(en_5v_cp),                 \
744         ADD_GPIO_REG(en_5v0),                   \
745         ADD_GPIO_REG(en_ddr),                   \
746         ADD_GPIO_REG(en_3v3_sys),               \
747         ADD_GPIO_REG(en_3v3_modem),             \
748         ADD_GPIO_REG(en_vdd_pnl1),              \
749         ADD_GPIO_REG(cam3_ldo_en),              \
750         ADD_GPIO_REG(en_vdd_com),               \
751         ADD_GPIO_REG(en_3v3_fuse),              \
752         ADD_GPIO_REG(en_3v3_emmc),              \
753         ADD_GPIO_REG(en_vdd_sdmmc1),            \
754         ADD_GPIO_REG(en_3v3_pex_hvdd),          \
755         ADD_GPIO_REG(en_1v8_cam),
756
757 #define COMMON_GPIO_REG_E1291_A04 \
758         ADD_GPIO_REG(en_5v_cp),                 \
759         ADD_GPIO_REG(en_5v0_a04),               \
760         ADD_GPIO_REG(en_ddr_a04),               \
761         ADD_GPIO_REG(en_3v3_sys_a04),           \
762         ADD_GPIO_REG(en_3v3_modem),             \
763         ADD_GPIO_REG(en_vdd_pnl1),              \
764         ADD_GPIO_REG(cam3_ldo_en),              \
765         ADD_GPIO_REG(en_vdd_com),               \
766         ADD_GPIO_REG(en_3v3_fuse),              \
767         ADD_GPIO_REG(en_3v3_emmc),              \
768         ADD_GPIO_REG(en_vdd_sdmmc1),            \
769         ADD_GPIO_REG(en_3v3_pex_hvdd),          \
770         ADD_GPIO_REG(en_1v8_cam),
771
772 #define PM269_GPIO_REG \
773         ADD_GPIO_REG(en_5v_cp),                 \
774         ADD_GPIO_REG(en_5v0),                   \
775         ADD_GPIO_REG(en_ddr),                   \
776         ADD_GPIO_REG(en_vdd_bl_pm269),          \
777         ADD_GPIO_REG(en_3v3_sys),               \
778         ADD_GPIO_REG(en_3v3_modem),             \
779         ADD_GPIO_REG(en_vdd_pnl1_pm269),                \
780         ADD_GPIO_REG(cam3_ldo_en),              \
781         ADD_GPIO_REG(en_vdd_com),               \
782         ADD_GPIO_REG(en_3v3_fuse_pm269),        \
783         ADD_GPIO_REG(en_3v3_emmc),              \
784         ADD_GPIO_REG(en_vdd_sdmmc1_pm269),      \
785         ADD_GPIO_REG(en_3v3_pex_hvdd_pm269),    \
786         ADD_GPIO_REG(en_1v8_cam),               \
787         ADD_GPIO_REG(dis_5v_switch_e118x),      \
788         ADD_GPIO_REG(en_usb1_vbus_oc_e118x),    \
789         ADD_GPIO_REG(en_usb3_vbus_oc_e118x),    \
790         ADD_GPIO_REG(en_vddio_vid_oc_pm269),
791
792 #define E118x_GPIO_REG  \
793         ADD_GPIO_REG(en_vdd_bl),                \
794         ADD_GPIO_REG(dis_5v_switch_e118x),      \
795         ADD_GPIO_REG(en_usb1_vbus_oc_e118x),    \
796         ADD_GPIO_REG(en_usb3_vbus_oc_e118x),    \
797         ADD_GPIO_REG(en_vddio_vid_oc_e118x), \
798         ADD_GPIO_REG(en_vbrtr),
799
800 #define E1198_GPIO_REG  \
801         ADD_GPIO_REG(en_vddio_vid_oc),          \
802         ADD_GPIO_REG(cam1_ldo_en),              \
803         ADD_GPIO_REG(cam2_ldo_en),
804
805 #define E1291_1198_A00_GPIO_REG \
806         ADD_GPIO_REG(en_usb1_vbus_oc),          \
807         ADD_GPIO_REG(en_usb3_vbus_oc),          \
808         ADD_GPIO_REG(en_vdd_bl),
809
810 #define E1291_A03_GPIO_REG      \
811         ADD_GPIO_REG(en_usb1_vbus_oc_a03),              \
812         ADD_GPIO_REG(en_usb3_vbus_oc_a03),              \
813         ADD_GPIO_REG(en_vdd_bl1_a03), \
814         ADD_GPIO_REG(en_vdd_bl2_a03),
815
816 /* Gpio switch regulator platform data  for E1186/E1187/E1256*/
817 static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e118x[] = {
818         COMMON_GPIO_REG
819         E118x_GPIO_REG
820 };
821
822 /* Gpio switch regulator platform data for E1198 and E1291*/
823 static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e1198[] = {
824         COMMON_GPIO_REG
825         E1291_1198_A00_GPIO_REG
826         E1198_GPIO_REG
827 };
828
829 /* Gpio switch regulator platform data for PM269*/
830 static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_pm269[] = {
831         PM269_GPIO_REG
832 };
833
834 /* Gpio switch regulator platform data for E1291 A03*/
835 static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e1291_a03[] = {
836         COMMON_GPIO_REG
837         E1291_A03_GPIO_REG
838         E1198_GPIO_REG
839 };
840
841 /* Gpio switch regulator platform data for E1291 A04*/
842 static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e1291_a04[] = {
843         COMMON_GPIO_REG_E1291_A04
844         E1291_A03_GPIO_REG
845         E1198_GPIO_REG
846 };
847
848
849 static struct gpio_switch_regulator_platform_data  gswitch_pdata;
850 static struct platform_device gswitch_regulator_pdata = {
851         .name = "gpio-switch-regulator",
852         .id   = -1,
853         .dev  = {
854              .platform_data = &gswitch_pdata,
855         },
856 };
857
858 int __init cardhu_gpio_switch_regulator_init(void)
859 {
860         int i;
861         struct board_info board_info;
862         tegra_get_board_info(&board_info);
863         switch (board_info.board_id) {
864         case BOARD_E1198:
865                 gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e1198);
866                 gswitch_pdata.subdevs = gswitch_subdevs_e1198;
867                 break;
868         case BOARD_E1291:
869                 if (board_info.fab == BOARD_FAB_A03) {
870                         gswitch_pdata.num_subdevs =
871                                         ARRAY_SIZE(gswitch_subdevs_e1291_a03);
872                         gswitch_pdata.subdevs = gswitch_subdevs_e1291_a03;
873                 } else if (board_info.fab == BOARD_FAB_A04) {
874                         gswitch_pdata.num_subdevs =
875                                         ARRAY_SIZE(gswitch_subdevs_e1291_a04);
876                         gswitch_pdata.subdevs = gswitch_subdevs_e1291_a04;
877                 } else {
878                         gswitch_pdata.num_subdevs =
879                                         ARRAY_SIZE(gswitch_subdevs_e1198);
880                         gswitch_pdata.subdevs = gswitch_subdevs_e1198;
881                 }
882                 break;
883         case BOARD_PM269:
884                 gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_pm269);
885                 gswitch_pdata.subdevs = gswitch_subdevs_pm269;
886                 break;
887         default:
888                 gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e118x);
889                 gswitch_pdata.subdevs = gswitch_subdevs_e118x;
890                 break;
891         }
892
893         for (i = 0; i < gswitch_pdata.num_subdevs; ++i) {
894                 struct gpio_switch_regulator_subdev_data *gswitch_data = gswitch_pdata.subdevs[i];
895                 if (gswitch_data->gpio_nr <= TEGRA_NR_GPIOS)
896                         tegra_gpio_enable(gswitch_data->gpio_nr);
897         }
898
899         return platform_device_register(&gswitch_regulator_pdata);
900 }
901
902 static void cardhu_board_suspend(int lp_state, enum suspend_stage stg)
903 {
904         if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
905                 tegra_console_uart_suspend();
906 }
907
908 static void cardhu_board_resume(int lp_state, enum resume_stage stg)
909 {
910         if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
911                 tegra_console_uart_resume();
912 }
913
914 static struct tegra_suspend_platform_data cardhu_suspend_data = {
915         .cpu_timer      = 2000,
916         .cpu_off_timer  = 200,
917         .suspend_mode   = TEGRA_SUSPEND_LP2,
918         .core_timer     = 0x7e7e,
919         .core_off_timer = 0,
920         .corereq_high   = true,
921         .sysclkreq_high = true,
922         .cpu_lp2_min_residency = 2000,
923         .board_suspend = cardhu_board_suspend,
924         .board_resume = cardhu_board_resume,
925 };
926
927 int __init cardhu_suspend_init(void)
928 {
929         struct board_info board_info;
930         struct board_info pmu_board_info;
931
932         tegra_get_board_info(&board_info);
933         tegra_get_pmu_board_info(&pmu_board_info);
934
935         /* For PMU Fab A03 and A04 make core_pwr_req to high */
936         if ((pmu_board_info.fab == BOARD_FAB_A03) || (pmu_board_info.fab == BOARD_FAB_A04))
937                 cardhu_suspend_data.corereq_high = true;
938
939         /* CORE_PWR_REQ to be high for all processor/pmu board whose sku bit 0
940          * is set. This is require to enable the dc-dc converter tps62361x */
941         if ((board_info.sku & SKU_DCDC_TPS62361_SUPPORT) || (pmu_board_info.sku & SKU_DCDC_TPS62361_SUPPORT))
942                 cardhu_suspend_data.corereq_high = true;
943
944         switch (board_info.board_id) {
945         case BOARD_E1291:
946                 /* CORE_PWR_REQ to be high for E1291-A03 */
947                 if (board_info.fab == BOARD_FAB_A03)
948                         cardhu_suspend_data.corereq_high = true;
949                 break;
950         case BOARD_E1198:
951         case BOARD_PM269:
952                 break;
953         case BOARD_E1187:
954         case BOARD_E1186:
955         case BOARD_E1256:
956                 cardhu_suspend_data.cpu_timer = 5000;
957                 cardhu_suspend_data.cpu_off_timer = 5000;
958                 break;
959         default:
960                 break;
961         }
962
963         tegra_init_suspend(&cardhu_suspend_data);
964         return 0;
965 }
966
967 static void cardhu_power_off(void)
968 {
969         int ret;
970         pr_err("cardhu: Powering off the device\n");
971         ret = tps6591x_power_off();
972         if (ret)
973                 pr_err("cardhu: failed to power off\n");
974
975         while (1);
976 }
977
978 int __init cardhu_power_off_init(void)
979 {
980         pm_power_off = cardhu_power_off;
981         return 0;
982 }
983
984 #ifdef CONFIG_TEGRA_EDP_LIMITS
985
986 int __init cardhu_edp_init(void)
987 {
988         /* Temporary initalization, needs to be set to the actual
989            regulator current */
990         tegra_init_cpu_edp_limits(5000);
991         return 0;
992 }
993 #endif