arm: tegra: cardhu: pm298: Correct min_uV for SD1 power rail
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-pm298-power-rails.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu-pm298-power-rails.c
3  *
4  * Copyright (C) 2011 NVIDIA, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
18  * 02111-1307, USA
19  */
20 #include <linux/i2c.h>
21 #include <linux/pda_power.h>
22 #include <linux/platform_device.h>
23 #include <linux/resource.h>
24 #include <linux/regulator/machine.h>
25 #include <linux/gpio.h>
26 #include <linux/io.h>
27 #include <linux/regulator/gpio-switch-regulator.h>
28 #include <linux/mfd/max77663-core.h>
29 #include <linux/regulator/max77663-regulator.h>
30
31 #include <mach/iomap.h>
32 #include <mach/irqs.h>
33 #include <mach/pinmux.h>
34 #include <mach/edp.h>
35
36 #include "gpio-names.h"
37 #include "board.h"
38 #include "board-cardhu.h"
39 #include "pm.h"
40 #include "wakeups-t3.h"
41 #include "mach/tsensor.h"
42
43 #define PMC_CTRL                0x0
44 #define PMC_CTRL_INTR_LOW       BIT(17)
45
46 static struct regulator_consumer_supply max77663_sd0_supply[] = {
47         REGULATOR_SUPPLY("vdd_cpu_pmu", NULL),
48         REGULATOR_SUPPLY("vdd_cpu", NULL),
49         REGULATOR_SUPPLY("vdd_sys", NULL),
50 };
51
52 static struct regulator_consumer_supply max77663_sd1_supply[] = {
53         REGULATOR_SUPPLY("vdd_core", NULL),
54         REGULATOR_SUPPLY("en_vddio_ddr_1v2", NULL),
55 };
56
57 static struct regulator_consumer_supply max77663_sd2_supply[] = {
58         REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
59         REGULATOR_SUPPLY("avdd_usb_pll", NULL),
60         REGULATOR_SUPPLY("avdd_osc", NULL),
61         REGULATOR_SUPPLY("vdd1v8_satelite", NULL),
62         REGULATOR_SUPPLY("vddio_uart", NULL),
63         REGULATOR_SUPPLY("pwrdet_uart", NULL),
64         REGULATOR_SUPPLY("vddio_audio", NULL),
65         REGULATOR_SUPPLY("pwrdet_audio", NULL),
66         REGULATOR_SUPPLY("vddio_bb", NULL),
67         REGULATOR_SUPPLY("pwrdet_bb", NULL),
68         REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
69         REGULATOR_SUPPLY("pwrdet_lcd", NULL),
70         REGULATOR_SUPPLY("vddio_cam", NULL),
71         REGULATOR_SUPPLY("pwrdet_cam", NULL),
72         REGULATOR_SUPPLY("vddio_vi", NULL),
73         REGULATOR_SUPPLY("pwrdet_vi", NULL),
74         REGULATOR_SUPPLY("ldo6", NULL),
75         REGULATOR_SUPPLY("ldo7", NULL),
76         REGULATOR_SUPPLY("ldo8", NULL),
77         REGULATOR_SUPPLY("vcore_audio", NULL),
78         REGULATOR_SUPPLY("avcore_audio", NULL),
79         REGULATOR_SUPPLY("vddio_sdmmc3", NULL),
80         REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
81         REGULATOR_SUPPLY("vcore1_lpddr2", NULL),
82         REGULATOR_SUPPLY("vcom_1v8", NULL),
83         REGULATOR_SUPPLY("pmuio_1v8", NULL),
84         REGULATOR_SUPPLY("avdd_ic_usb", NULL),
85         REGULATOR_SUPPLY("vdd_gen1v8", NULL),
86 };
87
88 static struct regulator_consumer_supply max77663_sd3_supply[] = {
89         REGULATOR_SUPPLY("vdd_gen1v5", NULL),
90         REGULATOR_SUPPLY("vcore_lcd", NULL),
91         REGULATOR_SUPPLY("track_ldo1", NULL),
92         REGULATOR_SUPPLY("external_ldo_1v2", NULL),
93         REGULATOR_SUPPLY("vcore_cam1", NULL),
94         REGULATOR_SUPPLY("vcore_cam2", NULL),
95         REGULATOR_SUPPLY("avdd_pexb", NULL),
96         REGULATOR_SUPPLY("vdd_pexb", NULL),
97         REGULATOR_SUPPLY("avdd_pex_pll", NULL),
98         REGULATOR_SUPPLY("avdd_pexa", NULL),
99         REGULATOR_SUPPLY("vdd_pexa", NULL),
100         REGULATOR_SUPPLY("vcom_1v2", NULL),
101         REGULATOR_SUPPLY("vdio_hsic", NULL),
102 };
103
104 static struct regulator_consumer_supply max77663_ldo0_supply[] = {
105         REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
106 };
107
108 static struct regulator_consumer_supply max77663_ldo1_supply[] = {
109         REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
110         REGULATOR_SUPPLY("avdd_pllm", NULL),
111         REGULATOR_SUPPLY("avdd_pllu_d", NULL),
112         REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
113         REGULATOR_SUPPLY("avdd_pllx", NULL),
114 };
115
116 static struct regulator_consumer_supply max77663_ldo2_supply[] = {
117         REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
118         REGULATOR_SUPPLY("pwrdet_mipi", NULL),
119 };
120
121 static struct regulator_consumer_supply max77663_ldo3_supply[] = {
122         REGULATOR_SUPPLY("vddio_sdmmc4", NULL),
123         REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
124 };
125
126 static struct regulator_consumer_supply max77663_ldo4_supply[] = {
127         REGULATOR_SUPPLY("vdd_rtc", NULL),
128 };
129
130 static struct regulator_consumer_supply max77663_ldo5_supply[] = {
131         REGULATOR_SUPPLY("vddio_sdmmc1", NULL),
132         REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
133 };
134
135 static struct regulator_consumer_supply max77663_ldo6_supply[] = {
136         REGULATOR_SUPPLY("vddio_sys", NULL),
137 };
138
139 static struct regulator_consumer_supply max77663_ldo7_supply[] = {
140         REGULATOR_SUPPLY("unused_ldo7", NULL),
141 };
142
143 static struct regulator_consumer_supply max77663_ldo8_supply[] = {
144         REGULATOR_SUPPLY("vcore_mmc", NULL),
145 };
146
147 static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
148         {
149                 .src = FPS_SRC_0,
150                 .en_src = FPS_EN_SRC_EN0,
151                 .time_period = FPS_TIME_PERIOD_DEF,
152         },
153         {
154                 .src = FPS_SRC_1,
155                 .en_src = FPS_EN_SRC_EN1,
156                 .time_period = FPS_TIME_PERIOD_DEF,
157         },
158         {
159                 .src = FPS_SRC_2,
160                 .en_src = FPS_EN_SRC_EN0,
161                 .time_period = FPS_TIME_PERIOD_DEF,
162         },
163 };
164
165 #define MAX77663_PDATA_INIT(_id, _min_uV, _max_uV, _supply_reg,         \
166                             _always_on, _boot_on, _apply_uV,            \
167                             _init_apply, _init_enable, _init_uV,        \
168                             _fps_src, _fps_pu_period, _fps_pd_period, _flags) \
169         static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id = \
170         {                                                               \
171                 .init_data = {                                          \
172                         .constraints = {                                \
173                                 .min_uV = _min_uV,                      \
174                                 .max_uV = _max_uV,                      \
175                                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |  \
176                                                      REGULATOR_MODE_STANDBY), \
177                                 .valid_ops_mask = (REGULATOR_CHANGE_MODE |    \
178                                                    REGULATOR_CHANGE_STATUS |  \
179                                                    REGULATOR_CHANGE_VOLTAGE), \
180                                 .always_on = _always_on,                \
181                                 .boot_on = _boot_on,                    \
182                                 .apply_uV = _apply_uV,                  \
183                         },                                              \
184                         .num_consumer_supplies =                        \
185                                 ARRAY_SIZE(max77663_##_id##_supply),    \
186                         .consumer_supplies = max77663_##_id##_supply,   \
187                         .supply_regulator = _supply_reg,                \
188                 },                                                      \
189                 .init_apply = _init_apply,                              \
190                 .init_enable = _init_enable,                            \
191                 .init_uV = _init_uV,                                    \
192                 .fps_src = _fps_src,                                    \
193                 .fps_pu_period = _fps_pu_period,                        \
194                 .fps_pd_period = _fps_pd_period,                        \
195                 .fps_cfgs = max77663_fps_cfgs,                          \
196                 .flags = _flags,                                        \
197         }
198
199 MAX77663_PDATA_INIT(sd0,  600000, 3387500, NULL, 1, 0, 0,
200                     0, 0, -1, FPS_SRC_NONE, -1, -1, EN2_CTRL_SD0 | SD_FSRADE_DISABLE);
201
202 MAX77663_PDATA_INIT(sd1,  800000, 1587500, NULL, 1, 0, 0,
203                     1, 1, -1, FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
204
205 MAX77663_PDATA_INIT(sd2,  600000, 3387500, NULL, 1, 0, 0,
206                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
207
208 MAX77663_PDATA_INIT(sd3,  600000, 3387500, NULL, 0, 0, 0,
209                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
210
211 MAX77663_PDATA_INIT(ldo0, 800000, 2350000, max77663_rails(sd2), 0, 0, 0,
212                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
213
214 MAX77663_PDATA_INIT(ldo1, 800000, 2350000, max77663_rails(sd2), 0, 0, 0,
215                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
216
217 MAX77663_PDATA_INIT(ldo2, 800000, 3950000, max77663_rails(sd2), 0, 0, 0,
218                     0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
219
220 MAX77663_PDATA_INIT(ldo3, 800000, 3950000, NULL, 0, 0, 0,
221                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
222
223 MAX77663_PDATA_INIT(ldo4, 800000, 1587500, NULL, 0, 0, 0,
224                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
225
226 MAX77663_PDATA_INIT(ldo5, 800000, 3950000, NULL, 0, 0, 0,
227                     0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
228
229 MAX77663_PDATA_INIT(ldo6, 800000, 3950000, NULL, 1, 0, 0,
230                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
231
232 MAX77663_PDATA_INIT(ldo7, 800000, 3950000, NULL, 0, 0, 0,
233                     0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
234
235 MAX77663_PDATA_INIT(ldo8, 800000, 3950000, NULL, 0, 0, 0,
236                     1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
237
238 #define MAX77663_REG(_id, _data)                                        \
239         {                                                               \
240                 .name = "max77663-regulator",                           \
241                 .id = MAX77663_REGULATOR_ID_##_id,                      \
242                 .platform_data = &max77663_regulator_pdata_##_data,     \
243                 .pdata_size = sizeof(max77663_regulator_pdata_##_data), \
244         }
245
246 #define MAX77663_RTC()                                                  \
247         {                                                               \
248                 .name = "max77663-rtc",                                 \
249                 .id = 0,                                                \
250         }
251
252 static struct mfd_cell max77663_subdevs[] = {
253         MAX77663_REG(SD0, sd0),
254         MAX77663_REG(SD1, sd1),
255         MAX77663_REG(SD2, sd2),
256         MAX77663_REG(SD3, sd3),
257         MAX77663_REG(LDO0, ldo0),
258         MAX77663_REG(LDO1, ldo1),
259         MAX77663_REG(LDO2, ldo2),
260         MAX77663_REG(LDO3, ldo3),
261         MAX77663_REG(LDO4, ldo4),
262         MAX77663_REG(LDO5, ldo5),
263         MAX77663_REG(LDO6, ldo6),
264         MAX77663_REG(LDO7, ldo7),
265         MAX77663_REG(LDO8, ldo8),
266         MAX77663_RTC(),
267 };
268
269 struct max77663_gpio_config max77663_gpio_cfgs[] = {
270         {
271                 .gpio = MAX77663_GPIO0,
272                 .dir = GPIO_DIR_OUT,
273                 .dout = GPIO_DOUT_LOW,
274                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
275                 .alternate = GPIO_ALT_DISABLE,
276         },
277         {
278                 .gpio = MAX77663_GPIO1,
279                 .dir = GPIO_DIR_OUT,
280                 .dout = GPIO_DOUT_HIGH,
281                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
282                 .alternate = GPIO_ALT_DISABLE,
283         },
284         {
285                 .gpio = MAX77663_GPIO2,
286                 .dir = GPIO_DIR_OUT,
287                 .dout = GPIO_DOUT_HIGH,
288                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
289                 .alternate = GPIO_ALT_DISABLE,
290         },
291         {
292                 .gpio = MAX77663_GPIO3,
293                 .dir = GPIO_DIR_OUT,
294                 .dout = GPIO_DOUT_HIGH,
295                 .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
296                 .alternate = GPIO_ALT_DISABLE,
297         },
298         {
299                 .gpio = MAX77663_GPIO4,
300                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
301                 .alternate = GPIO_ALT_ENABLE,
302         },
303         {
304                 .gpio = MAX77663_GPIO5,
305                 .dir = GPIO_DIR_OUT,
306                 .dout = GPIO_DOUT_LOW,
307                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
308                 .alternate = GPIO_ALT_DISABLE,
309         },
310         {
311                 .gpio = MAX77663_GPIO6,
312                 .dir = GPIO_DIR_OUT,
313                 .dout = GPIO_DOUT_LOW,
314                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
315                 .alternate = GPIO_ALT_DISABLE,
316         },
317         {
318                 .gpio = MAX77663_GPIO7,
319                 .dir = GPIO_DIR_OUT,
320                 .dout = GPIO_DOUT_LOW,
321                 .out_drv = GPIO_OUT_DRV_PUSH_PULL,
322                 .alternate = GPIO_ALT_DISABLE,
323         },
324 };
325
326 static struct max77663_platform_data max7763_pdata = {
327         .irq_base       = MAX77663_IRQ_BASE,
328         .gpio_base      = MAX77663_GPIO_BASE,
329
330         .num_gpio_cfgs = ARRAY_SIZE(max77663_gpio_cfgs),
331         .gpio_cfgs = max77663_gpio_cfgs,
332
333         .num_subdevs    = ARRAY_SIZE(max77663_subdevs),
334         .sub_devices    = max77663_subdevs,
335 };
336
337 static struct i2c_board_info __initdata max77663_regulators[] = {
338         {
339                 /* The I2C address was determined by OTP factory setting */
340                 I2C_BOARD_INFO("max77663", 0x1C),
341                 .irq            = INT_EXTERNAL_PMU,
342                 .platform_data  = &max7763_pdata,
343         },
344 };
345
346 int __init cardhu_pm298_regulator_init(void)
347 {
348         struct board_info board_info;
349         struct board_info pmu_board_info;
350         void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
351         u32 pmc_ctrl;
352
353         /* configure the power management controller to trigger PMU
354          * interrupts when low */
355         pmc_ctrl = readl(pmc + PMC_CTRL);
356         writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
357
358         /* The regulator details have complete constraints */
359         tegra_get_board_info(&board_info);
360         tegra_get_pmu_board_info(&pmu_board_info);
361         if (pmu_board_info.board_id != BOARD_PMU_PM298) {
362                 pr_err("%s(): Board ID is not proper\n", __func__);
363                 return -ENODEV;
364         }
365
366         i2c_register_board_info(4, max77663_regulators,
367                                 ARRAY_SIZE(max77663_regulators));
368
369         return 0;
370 }
371
372 static struct regulator_consumer_supply gpio_switch_en_track_ldo2_supply[] = {
373         REGULATOR_SUPPLY("avdd_sata", NULL),
374         REGULATOR_SUPPLY("vdd_sata", NULL),
375         REGULATOR_SUPPLY("avdd_sata_pll", NULL),
376         REGULATOR_SUPPLY("avdd_plle", NULL),
377 };
378 static int gpio_switch_en_track_ldo2_voltages[] = { 3300};
379
380 static struct regulator_consumer_supply gpio_switch_en_5v0_supply[] = {
381         REGULATOR_SUPPLY("vdd_5v0_sys", NULL),
382         REGULATOR_SUPPLY("vdd_5v0_sby", NULL),
383         REGULATOR_SUPPLY("vdd_hall", NULL),
384         REGULATOR_SUPPLY("vterm_ddr", NULL),
385         REGULATOR_SUPPLY("v2ref_ddr", NULL),
386 };
387 static int gpio_switch_en_5v0_voltages[] = { 5000};
388
389 static struct regulator_consumer_supply gpio_switch_en_ddr_supply[] = {
390         REGULATOR_SUPPLY("mem_vddio_ddr", NULL),
391         REGULATOR_SUPPLY("t30_vddio_ddr", NULL),
392 };
393 static int gpio_switch_en_ddr_voltages[] = { 1500};
394
395 static struct regulator_consumer_supply gpio_switch_en_3v3_sys_supply[] = {
396         REGULATOR_SUPPLY("avdd_vdac", NULL),
397         REGULATOR_SUPPLY("vdd_lvds", NULL),
398         REGULATOR_SUPPLY("vdd_pnl", NULL),
399         REGULATOR_SUPPLY("vcom_3v3", NULL),
400         REGULATOR_SUPPLY("vdd_3v3", NULL),
401         REGULATOR_SUPPLY("vddio_pex_ctl", NULL),
402         REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
403         REGULATOR_SUPPLY("hvdd_pex_pmu", NULL),
404         REGULATOR_SUPPLY("avdd_hdmi", NULL),
405         REGULATOR_SUPPLY("vpp_fuse", NULL),
406         REGULATOR_SUPPLY("avdd_usb", NULL),
407         REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
408         REGULATOR_SUPPLY("vcore_nand", NULL),
409         REGULATOR_SUPPLY("hvdd_sata", NULL),
410         REGULATOR_SUPPLY("vddio_gmi_pmu", NULL),
411         REGULATOR_SUPPLY("pwrdet_nand", NULL),
412         REGULATOR_SUPPLY("avdd_cam1", NULL),
413         REGULATOR_SUPPLY("vdd_af", NULL),
414         REGULATOR_SUPPLY("avdd_cam2", NULL),
415         REGULATOR_SUPPLY("vdd_acc", NULL),
416         REGULATOR_SUPPLY("vdd_phtl", NULL),
417         REGULATOR_SUPPLY("vddio_tp", NULL),
418         REGULATOR_SUPPLY("vdd_led", NULL),
419         REGULATOR_SUPPLY("vddio_cec", NULL),
420         REGULATOR_SUPPLY("vdd_cmps", NULL),
421         REGULATOR_SUPPLY("vdd_temp", NULL),
422         REGULATOR_SUPPLY("vpp_kfuse", NULL),
423         REGULATOR_SUPPLY("vddio_ts", NULL),
424         REGULATOR_SUPPLY("vdd_ir_led", NULL),
425         REGULATOR_SUPPLY("vddio_1wire", NULL),
426         REGULATOR_SUPPLY("avddio_audio", NULL),
427         REGULATOR_SUPPLY("vdd_ec", NULL),
428         REGULATOR_SUPPLY("vcom_pa", NULL),
429         REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
430         REGULATOR_SUPPLY("vdd_3v3_dock", NULL),
431         REGULATOR_SUPPLY("vdd_3v3_edid", NULL),
432         REGULATOR_SUPPLY("vdd_3v3_hdmi_cec", NULL),
433         REGULATOR_SUPPLY("vdd_3v3_gmi", NULL),
434         REGULATOR_SUPPLY("vdd_3v3_spk_amp", NULL),
435         REGULATOR_SUPPLY("vdd_3v3_sensor", NULL),
436         REGULATOR_SUPPLY("vdd_3v3_cam", NULL),
437         REGULATOR_SUPPLY("vdd_3v3_als", NULL),
438         REGULATOR_SUPPLY("debug_cons", NULL),
439         REGULATOR_SUPPLY("vdd", "4-004c"),
440 };
441 static int gpio_switch_en_3v3_sys_voltages[] = { 3300};
442
443 /* DIS_5V_SWITCH from AP SPI2_SCK X02 */
444 static struct regulator_consumer_supply gpio_switch_dis_5v_switch_supply[] = {
445         REGULATOR_SUPPLY("master_5v_switch", NULL),
446 };
447 static int gpio_switch_dis_5v_switch_voltages[] = { 5000};
448
449 /* EN_VDD_BL */
450 static struct regulator_consumer_supply gpio_switch_en_vdd_bl_supply[] = {
451         REGULATOR_SUPPLY("vdd_backlight", NULL),
452         REGULATOR_SUPPLY("vdd_backlight1", NULL),
453 };
454 static int gpio_switch_en_vdd_bl_voltages[] = { 5000};
455
456 /* EN_3V3_MODEM from AP GPIO VI_VSYNCH D06*/
457 static struct regulator_consumer_supply gpio_switch_en_3v3_modem_supply[] = {
458         REGULATOR_SUPPLY("vdd_3v3_mini_card", NULL),
459         REGULATOR_SUPPLY("vdd_mini_card", NULL),
460 };
461 static int gpio_switch_en_3v3_modem_voltages[] = { 3300};
462
463 /* EN_USB1_VBUS_OC*/
464 static struct regulator_consumer_supply gpio_switch_en_usb1_vbus_oc_supply[] = {
465         REGULATOR_SUPPLY("vdd_vbus_micro_usb", NULL),
466 };
467 static int gpio_switch_en_usb1_vbus_oc_voltages[] = { 5000};
468
469 /*EN_USB3_VBUS_OC*/
470 static struct regulator_consumer_supply gpio_switch_en_usb3_vbus_oc_supply[] = {
471         REGULATOR_SUPPLY("vdd_vbus_typea_usb", NULL),
472 };
473 static int gpio_switch_en_usb3_vbus_oc_voltages[] = { 5000};
474
475 /* EN_VDDIO_VID_OC from AP GPIO VI_PCLK T00*/
476 static struct regulator_consumer_supply gpio_switch_en_vddio_vid_oc_supply[] = {
477         REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
478 };
479 static int gpio_switch_en_vddio_vid_oc_voltages[] = { 5000};
480
481 /* EN_VDD_PNL1 from AP GPIO VI_D6 L04*/
482 static struct regulator_consumer_supply gpio_switch_en_vdd_pnl1_supply[] = {
483         REGULATOR_SUPPLY("vdd_lcd_panel", NULL),
484 };
485 static int gpio_switch_en_vdd_pnl1_voltages[] = { 3300};
486
487 /* CAM1_LDO_EN from AP GPIO KB_ROW6 R06*/
488 static struct regulator_consumer_supply gpio_switch_cam1_ldo_en_supply[] = {
489         REGULATOR_SUPPLY("vdd_2v8_cam1", NULL),
490         REGULATOR_SUPPLY("vdd_2v8_cam1_af", NULL),
491 };
492 static int gpio_switch_cam1_ldo_en_voltages[] = { 2800};
493
494 /* CAM2_LDO_EN from AP GPIO KB_ROW7 R07*/
495 static struct regulator_consumer_supply gpio_switch_cam2_ldo_en_supply[] = {
496         REGULATOR_SUPPLY("vdd_2v8_cam2", NULL),
497         REGULATOR_SUPPLY("vdd_2v8_cam2_af", NULL),
498 };
499 static int gpio_switch_cam2_ldo_en_voltages[] = { 2800};
500
501 /* CAM3_LDO_EN from AP GPIO KB_ROW8 S00*/
502 static struct regulator_consumer_supply gpio_switch_cam3_ldo_en_supply[] = {
503         REGULATOR_SUPPLY("vdd_cam3", NULL),
504 };
505 static int gpio_switch_cam3_ldo_en_voltages[] = { 3300};
506
507 /* EN_VDD_COM from AP GPIO SDMMC3_DAT5 D00*/
508 static struct regulator_consumer_supply gpio_switch_en_vdd_com_supply[] = {
509         REGULATOR_SUPPLY("vdd_com_bd", NULL),
510 };
511 static int gpio_switch_en_vdd_com_voltages[] = { 3300};
512
513 /* EN_VDD_SDMMC1 from AP GPIO VI_HSYNC D07*/
514 static struct regulator_consumer_supply gpio_switch_en_vdd_sdmmc1_supply[] = {
515         REGULATOR_SUPPLY("vddio_sd_slot", NULL),
516 };
517 static int gpio_switch_en_vdd_sdmmc1_voltages[] = { 3300};
518
519 /* EN_3V3_EMMC from AP GPIO SDMMC3_DAT4 D01*/
520 static struct regulator_consumer_supply gpio_switch_en_3v3_emmc_supply[] = {
521         REGULATOR_SUPPLY("vdd_emmc_core", NULL),
522 };
523 static int gpio_switch_en_3v3_emmc_voltages[] = { 3300};
524
525 /* EN_3V3_PEX_HVDD from AP GPIO VI_D09 L07*/
526 static struct regulator_consumer_supply gpio_switch_en_3v3_pex_hvdd_supply[] = {
527         REGULATOR_SUPPLY("hvdd_pex", NULL),
528 };
529 static int gpio_switch_en_3v3_pex_hvdd_voltages[] = { 3300};
530
531 /* EN_3v3_FUSE from AP GPIO VI_D08 L06*/
532 static struct regulator_consumer_supply gpio_switch_en_3v3_fuse_supply[] = {
533         REGULATOR_SUPPLY("vdd_fuse", NULL),
534 };
535 static int gpio_switch_en_3v3_fuse_voltages[] = { 3300};
536
537 /* EN_1V8_CAM from AP GPIO GPIO_PBB4 PBB04*/
538 static struct regulator_consumer_supply gpio_switch_en_1v8_cam_supply[] = {
539         REGULATOR_SUPPLY("vdd_1v8_cam1", NULL),
540         REGULATOR_SUPPLY("vdd_1v8_cam2", NULL),
541         REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
542 };
543 static int gpio_switch_en_1v8_cam_voltages[] = { 1800};
544
545 static struct regulator_consumer_supply gpio_switch_en_vbrtr_supply[] = {
546         REGULATOR_SUPPLY("vdd_vbrtr", NULL),
547 };
548 static int gpio_switch_en_vbrtr_voltages[] = { 3300};
549
550 static int enable_load_switch_rail(
551                 struct gpio_switch_regulator_subdev_data *psubdev_data)
552 {
553         int ret;
554
555         if (psubdev_data->pin_group <= 0)
556                 return -EINVAL;
557
558         /* Tristate and make pin as input*/
559         ret = tegra_pinmux_set_tristate(psubdev_data->pin_group,
560                                                 TEGRA_TRI_TRISTATE);
561         if (ret < 0)
562                 return ret;
563         return gpio_direction_input(psubdev_data->gpio_nr);
564 }
565
566 static int disable_load_switch_rail(
567                 struct gpio_switch_regulator_subdev_data *psubdev_data)
568 {
569         int ret;
570
571         if (psubdev_data->pin_group <= 0)
572                 return -EINVAL;
573
574         /* Un-tristate and driver low */
575         ret = tegra_pinmux_set_tristate(psubdev_data->pin_group,
576                                                 TEGRA_TRI_NORMAL);
577         if (ret < 0)
578                 return ret;
579         return gpio_direction_output(psubdev_data->gpio_nr, 0);
580 }
581
582
583 /* Macro for defining gpio switch regulator sub device data */
584 #define GREG_INIT(_id, _var, _name, _input_supply, _always_on, _boot_on, \
585         _gpio_nr, _active_low, _init_state, _pg, _enable, _disable)      \
586         static struct gpio_switch_regulator_subdev_data gpio_pdata_##_var =  \
587         {                                                               \
588                 .regulator_name = "gpio-switch-"#_name,                 \
589                 .input_supply   = _input_supply,                        \
590                 .id             = _id,                                  \
591                 .gpio_nr        = _gpio_nr,                             \
592                 .pin_group      = _pg,                                  \
593                 .active_low     = _active_low,                          \
594                 .init_state     = _init_state,                          \
595                 .voltages       = gpio_switch_##_name##_voltages,       \
596                 .n_voltages     = ARRAY_SIZE(gpio_switch_##_name##_voltages), \
597                 .num_consumer_supplies =                                \
598                                 ARRAY_SIZE(gpio_switch_##_name##_supply), \
599                 .consumer_supplies = gpio_switch_##_name##_supply,      \
600                 .constraints = {                                        \
601                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
602                                              REGULATOR_MODE_STANDBY),   \
603                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
604                                            REGULATOR_CHANGE_STATUS |    \
605                                            REGULATOR_CHANGE_VOLTAGE),   \
606                         .always_on = _always_on,                        \
607                         .boot_on = _boot_on,                            \
608                 },                                                      \
609                 .enable_rail = _enable,                                 \
610                 .disable_rail = _disable,                               \
611         }
612
613 /* common to most of boards*/
614 GREG_INIT(0, en_track_ldo2,     en_track_ldo2,  NULL,                   0,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO0,    false,  0,      0,      0,      0);
615 GREG_INIT(1, en_5v0,            en_5v0,         NULL,                   1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO2,    false,  1,      0,      0,      0);
616 GREG_INIT(2, en_ddr,            en_ddr,         NULL,                   1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO3,    false,  1,      0,      0,      0);
617 GREG_INIT(3, en_3v3_sys,        en_3v3_sys,     NULL,                   1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO1,    false,  1,      0,      0,      0);
618 GREG_INIT(4, en_vdd_bl,         en_vdd_bl,      NULL,                   0,      0,      TEGRA_GPIO_PK3,         false,  1,      0,      0,      0);
619 GREG_INIT(5, en_3v3_modem,      en_3v3_modem,   NULL,                   1,      0,      TEGRA_GPIO_PD6,         false,  1,      0,      0,      0);
620 GREG_INIT(6, en_vdd_pnl1,       en_vdd_pnl1,    "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PL4,         false,  1,      0,      0,      0);
621 GREG_INIT(7, cam3_ldo_en,       cam3_ldo_en,    "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PS0,         false,  0,      0,      0,      0);
622 GREG_INIT(8, en_vdd_com,        en_vdd_com,     "vdd_3v3_devices",      1,      0,      TEGRA_GPIO_PD0,         false,  1,      0,      0,      0);
623 GREG_INIT(9, en_3v3_fuse,       en_3v3_fuse,    "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PL6,         false,  0,      0,      0,      0);
624 GREG_INIT(10, en_3v3_emmc,      en_3v3_emmc,    "vdd_3v3_devices",      1,      0,      TEGRA_GPIO_PD1,         false,  1,      0,      0,      0);
625 GREG_INIT(11, en_vdd_sdmmc1,    en_vdd_sdmmc1,  "vdd_3v3_devices",      0,      0,      TEGRA_GPIO_PD7,         false,  1,      0,      0,      0);
626 GREG_INIT(12, en_3v3_pex_hvdd,  en_3v3_pex_hvdd, "hvdd_pex_pmu",        0,      0,      TEGRA_GPIO_PL7,         false,  0,      0,      0,      0);
627 GREG_INIT(13, en_1v8_cam,       en_1v8_cam,     "vdd_gen1v8",           0,      0,      TEGRA_GPIO_PBB4,        false,  0,      0,      0,      0);
628
629 /*Specific to pm269*/
630 GREG_INIT(4, en_vdd_bl_pm269,           en_vdd_bl,              NULL,
631         0,      0,      TEGRA_GPIO_PH3, false,  1,      0,      0,      0);
632 GREG_INIT(6, en_vdd_pnl1_pm269,         en_vdd_pnl1,            "vdd_3v3_devices",
633         0,      0,      TEGRA_GPIO_PW1, false,  1,      0,      0,      0);
634 GREG_INIT(9, en_3v3_fuse_pm269,         en_3v3_fuse,            "vdd_3v3_devices",
635         0,      0,      TEGRA_GPIO_PC1, false,  0,      0,      0,      0);
636 GREG_INIT(11, en_vdd_sdmmc1_pm269,      en_vdd_sdmmc1,          "vdd_3v3_devices",
637         0,      0,      TEGRA_GPIO_PP1, false,  1,      0,      0,      0);
638 GREG_INIT(12, en_3v3_pex_hvdd_pm269,    en_3v3_pex_hvdd,        "hvdd_pex_pmu",
639         0,      0,      TEGRA_GPIO_PC6, false,  0,      0,      0,      0);
640 GREG_INIT(17, en_vddio_vid_oc_pm269,    en_vddio_vid_oc,        "master_5v_switch",
641         0,      0,      TEGRA_GPIO_PP2, false,  0,      TEGRA_PINGROUP_DAP3_DOUT,
642         enable_load_switch_rail, disable_load_switch_rail);
643
644 /* Specific to E1187/E1186/E1256 */
645 GREG_INIT(14, dis_5v_switch_e118x,      dis_5v_switch,          "vdd_5v0_sys",
646                 0,      0,      TEGRA_GPIO_PX2,         true,   0,      0,      0,      0);
647 GREG_INIT(15, en_usb1_vbus_oc_e118x,    en_usb1_vbus_oc,        "master_5v_switch",
648                 0,      0,      TEGRA_GPIO_PI4,         false,  0,      TEGRA_PINGROUP_GMI_RST_N,
649                 enable_load_switch_rail, disable_load_switch_rail);
650 GREG_INIT(16, en_usb3_vbus_oc_e118x,    en_usb3_vbus_oc,        "master_5v_switch",
651                 0,      0,      TEGRA_GPIO_PH7,         false,  0,      TEGRA_PINGROUP_GMI_AD15,
652                 enable_load_switch_rail, disable_load_switch_rail);
653 GREG_INIT(17, en_vddio_vid_oc_e118x,    en_vddio_vid_oc,        "master_5v_switch",
654                 0,      0,      TEGRA_GPIO_PT0,         false,  0,      TEGRA_PINGROUP_VI_PCLK,
655                 enable_load_switch_rail, disable_load_switch_rail);
656
657 /* E1198/E1291 specific*/
658 GREG_INIT(18, cam1_ldo_en,      cam1_ldo_en,    "vdd_3v3_cam",  0,      0,      TEGRA_GPIO_PR6,         false,  0,      0,      0,      0);
659 GREG_INIT(19, cam2_ldo_en,      cam2_ldo_en,    "vdd_3v3_cam",  0,      0,      TEGRA_GPIO_PR7,         false,  0,      0,      0,      0);
660
661 GREG_INIT(22, en_vbrtr,         en_vbrtr,       "vdd_3v3_devices",      0,      0,      PMU_TCA6416_GPIO_PORT12,        false,  0,      0,      0,      0);
662
663 #define ADD_GPIO_REG(_name) &gpio_pdata_##_name
664
665 #define COMMON_GPIO_REG \
666         ADD_GPIO_REG(en_track_ldo2),            \
667         ADD_GPIO_REG(en_5v0),                   \
668         ADD_GPIO_REG(en_ddr),                   \
669         ADD_GPIO_REG(en_3v3_sys),               \
670         ADD_GPIO_REG(en_3v3_modem),             \
671         ADD_GPIO_REG(en_vdd_pnl1),              \
672         ADD_GPIO_REG(cam1_ldo_en),              \
673         ADD_GPIO_REG(cam2_ldo_en),              \
674         ADD_GPIO_REG(cam3_ldo_en),              \
675         ADD_GPIO_REG(en_vdd_com),               \
676         ADD_GPIO_REG(en_3v3_fuse),              \
677         ADD_GPIO_REG(en_3v3_emmc),              \
678         ADD_GPIO_REG(en_vdd_sdmmc1),            \
679         ADD_GPIO_REG(en_3v3_pex_hvdd),          \
680         ADD_GPIO_REG(en_1v8_cam),
681
682 #define PM269_GPIO_REG \
683         ADD_GPIO_REG(en_track_ldo2),            \
684         ADD_GPIO_REG(en_5v0),                   \
685         ADD_GPIO_REG(en_ddr),                   \
686         ADD_GPIO_REG(en_vdd_bl_pm269),          \
687         ADD_GPIO_REG(en_3v3_sys),               \
688         ADD_GPIO_REG(en_3v3_modem),             \
689         ADD_GPIO_REG(en_vdd_pnl1_pm269),        \
690         ADD_GPIO_REG(cam1_ldo_en),              \
691         ADD_GPIO_REG(cam2_ldo_en),              \
692         ADD_GPIO_REG(cam3_ldo_en),              \
693         ADD_GPIO_REG(en_vdd_com),               \
694         ADD_GPIO_REG(en_3v3_fuse_pm269),        \
695         ADD_GPIO_REG(en_3v3_emmc),              \
696         ADD_GPIO_REG(en_vdd_sdmmc1_pm269),      \
697         ADD_GPIO_REG(en_3v3_pex_hvdd_pm269),    \
698         ADD_GPIO_REG(en_1v8_cam),               \
699         ADD_GPIO_REG(dis_5v_switch_e118x),      \
700         ADD_GPIO_REG(en_usb1_vbus_oc_e118x),    \
701         ADD_GPIO_REG(en_usb3_vbus_oc_e118x),    \
702         ADD_GPIO_REG(en_vddio_vid_oc_pm269),
703
704 #define E118x_GPIO_REG  \
705         ADD_GPIO_REG(en_vdd_bl),                \
706         ADD_GPIO_REG(dis_5v_switch_e118x),      \
707         ADD_GPIO_REG(en_usb1_vbus_oc_e118x),    \
708         ADD_GPIO_REG(en_usb3_vbus_oc_e118x),    \
709         ADD_GPIO_REG(en_vddio_vid_oc_e118x),    \
710         ADD_GPIO_REG(en_vbrtr),
711
712 /* Gpio switch regulator platform data  for E1186/E1187/E1256*/
713 static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_e118x[] = {
714         COMMON_GPIO_REG
715         E118x_GPIO_REG
716 };
717
718 /* Gpio switch regulator platform data for PM269*/
719 static struct gpio_switch_regulator_subdev_data *gswitch_subdevs_pm269[] = {
720         PM269_GPIO_REG
721 };
722
723 static struct gpio_switch_regulator_platform_data  gswitch_pdata;
724 static struct platform_device gswitch_regulator_pdata = {
725         .name = "gpio-switch-regulator",
726         .id   = -1,
727         .dev  = {
728              .platform_data = &gswitch_pdata,
729         },
730 };
731
732 int __init cardhu_pm298_gpio_switch_regulator_init(void)
733 {
734         int i;
735         struct board_info board_info;
736         tegra_get_board_info(&board_info);
737
738         switch (board_info.board_id) {
739         case BOARD_PM269:
740                 gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_pm269);
741                 gswitch_pdata.subdevs = gswitch_subdevs_pm269;
742                 break;
743
744         default:
745                 gswitch_pdata.num_subdevs = ARRAY_SIZE(gswitch_subdevs_e118x);
746                 gswitch_pdata.subdevs = gswitch_subdevs_e118x;
747                 break;
748         }
749
750         for (i = 0; i < gswitch_pdata.num_subdevs; ++i) {
751                 struct gpio_switch_regulator_subdev_data *gswitch_data =
752                                                 gswitch_pdata.subdevs[i];
753                 if (gswitch_data->gpio_nr <= TEGRA_NR_GPIOS)
754                         tegra_gpio_enable(gswitch_data->gpio_nr);
755         }
756
757         return platform_device_register(&gswitch_regulator_pdata);
758 }