Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-panel.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu-panel.c
3  *
4  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/delay.h>
22 #include <linux/ion.h>
23 #include <linux/tegra_ion.h>
24 #include <linux/gpio.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/resource.h>
27 #include <asm/mach-types.h>
28 #include <linux/platform_device.h>
29 #include <linux/pwm_backlight.h>
30 #include <asm/atomic.h>
31 #include <linux/nvhost.h>
32 #include <linux/nvmap.h>
33 #include <mach/irqs.h>
34 #include <mach/iomap.h>
35 #include <mach/dc.h>
36 #include <mach/fb.h>
37 #include <mach/smmu.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "board.h"
41 #include "clock.h"
42 #include "dvfs.h"
43 #include "board-cardhu.h"
44 #include "devices.h"
45 #include "gpio-names.h"
46 #include "tegra3_host1x_devices.h"
47
48 #define DC_CTRL_MODE    (TEGRA_DC_OUT_ONE_SHOT_MODE | \
49                          TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
50
51 #define AVDD_LCD PMU_TCA6416_GPIO_PORT17
52 #define DSI_PANEL_RESET 1
53
54 /* Select LVDS panel resolution. 13X7 is default */
55 #define PM313_LVDS_PANEL_19X12                  1
56 #define PM313_LVDS_PANEL_BPP                    0 /* 0:24bpp, 1:18bpp */
57
58 /* PM313 display board specific pins */
59 #define pm313_R_FDE                     TEGRA_GPIO_PW0
60 #define pm313_R_FB                      TEGRA_GPIO_PN4
61 #define pm313_MODE0                     TEGRA_GPIO_PZ4
62 #define pm313_MODE1                     TEGRA_GPIO_PW1
63 #define pm313_BPP                       TEGRA_GPIO_PN6 /* 0:24bpp, 1:18bpp */
64 #define pm313_lvds_shutdown             TEGRA_GPIO_PL2
65
66 /* E1506 display board pins */
67 #define e1506_lcd_te            TEGRA_GPIO_PJ1
68 #define e1506_dsi_vddio         TEGRA_GPIO_PH1
69 #define e1506_dsia_bl_pwm       TEGRA_GPIO_PH0
70 #define e1506_panel_enb         TEGRA_GPIO_PW1
71 #define e1506_bl_enb            TEGRA_GPIO_PH2
72
73 /* E1247 reworked for pm269 pins */
74 #define e1247_pm269_lvds_shutdown       TEGRA_GPIO_PN6
75
76 /* E1247 cardhu default display board pins */
77 #define cardhu_lvds_shutdown            TEGRA_GPIO_PL2
78
79 /* common pins( backlight ) for all display boards */
80 #define cardhu_bl_enb                   TEGRA_GPIO_PH2
81 #define cardhu_bl_pwm                   TEGRA_GPIO_PH0
82 #define cardhu_hdmi_hpd                 TEGRA_GPIO_PN7
83
84 /* common dsi panel pins */
85 #define cardhu_dsia_bl_enb              TEGRA_GPIO_PW1
86 #define cardhu_dsib_bl_enb              TEGRA_GPIO_PW0
87 #define cardhu_dsi_pnl_reset            TEGRA_GPIO_PD2
88 #define cardhu_dsi_219_pnl_reset        TEGRA_GPIO_PW0
89
90 #ifdef CONFIG_TEGRA_DC
91 static struct regulator *cardhu_hdmi_reg = NULL;
92 static struct regulator *cardhu_hdmi_pll = NULL;
93 static struct regulator *cardhu_hdmi_vddio = NULL;
94 #endif
95
96 static atomic_t sd_brightness = ATOMIC_INIT(255);
97
98 static struct regulator *cardhu_dsi_reg = NULL;
99 static struct regulator *cardhu_lvds_reg = NULL;
100 static struct regulator *cardhu_lvds_vdd_bl = NULL;
101 static struct regulator *cardhu_lvds_vdd_panel = NULL;
102
103 static struct board_info board_info;
104 static struct board_info display_board_info;
105
106 static tegra_dc_bl_output cardhu_bl_output_measured = {
107         0, 1, 2, 3, 4, 5, 6, 7,
108         8, 9, 10, 11, 12, 13, 14, 15,
109         16, 17, 18, 19, 20, 21, 22, 23,
110         24, 25, 26, 27, 28, 29, 30, 31,
111         32, 33, 34, 35, 36, 37, 38, 39,
112         40, 41, 42, 43, 44, 45, 46, 47,
113         48, 49, 49, 50, 51, 52, 53, 54,
114         55, 56, 57, 58, 59, 60, 61, 62,
115         63, 64, 65, 66, 67, 68, 69, 70,
116         70, 72, 73, 74, 75, 76, 77, 78,
117         79, 80, 81, 82, 83, 84, 85, 86,
118         87, 88, 89, 90, 91, 92, 93, 94,
119         95, 96, 97, 98, 99, 100, 101, 102,
120         103, 104, 105, 106, 107, 108, 110, 111,
121         112, 113, 114, 115, 116, 117, 118, 119,
122         120, 121, 122, 123, 124, 124, 125, 126,
123         127, 128, 129, 130, 131, 132, 133, 133,
124         134, 135, 136, 137, 138, 139, 140, 141,
125         142, 143, 144, 145, 146, 147, 148, 148,
126         149, 150, 151, 152, 153, 154, 155, 156,
127         157, 158, 159, 160, 161, 162, 163, 164,
128         165, 166, 167, 168, 169, 170, 171, 172,
129         173, 174, 175, 176, 177, 179, 180, 181,
130         182, 184, 185, 186, 187, 188, 189, 190,
131         191, 192, 193, 194, 195, 196, 197, 198,
132         199, 200, 201, 202, 203, 204, 205, 206,
133         207, 208, 209, 211, 212, 213, 214, 215,
134         216, 217, 218, 219, 220, 221, 222, 223,
135         224, 225, 226, 227, 228, 229, 230, 231,
136         232, 233, 234, 235, 236, 237, 238, 239,
137         240, 241, 242, 243, 244, 245, 246, 247,
138         248, 249, 250, 251, 252, 253, 254, 255
139 };
140
141 static p_tegra_dc_bl_output bl_output = cardhu_bl_output_measured;
142
143 static bool is_panel_218;
144 static bool is_panel_219;
145 static bool is_panel_1506;
146
147 static bool is_dsi_panel(void)
148 {
149         return is_panel_218 || is_panel_219 || is_panel_1506;
150 }
151
152 static int cardhu_backlight_init(struct device *dev)
153 {
154         int ret = 0;
155
156         if (WARN_ON(ARRAY_SIZE(cardhu_bl_output_measured) != 256))
157                 pr_err("bl_output array does not have 256 elements\n");
158
159         if (!is_dsi_panel()) {
160                 ret = gpio_request(cardhu_bl_enb, "backlight_enb");
161                 if (ret < 0)
162                         return ret;
163
164                 ret = gpio_direction_output(cardhu_bl_enb, 1);
165                 if (ret < 0)
166                         gpio_free(cardhu_bl_enb);
167         } else if (is_panel_218) {
168                 /* Enable back light for DSIa panel */
169                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
170                 if (ret < 0)
171                         return ret;
172
173                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
174                 if (ret < 0)
175                         gpio_free(cardhu_dsia_bl_enb);
176
177                 /* Enable back light for DSIb panel */
178                 ret = gpio_request(cardhu_dsib_bl_enb, "dsib_bl_enable");
179                 if (ret < 0)
180                         return ret;
181
182                 ret = gpio_direction_output(cardhu_dsib_bl_enb, 1);
183                 if (ret < 0)
184                         gpio_free(cardhu_dsib_bl_enb);
185         } else if (is_panel_219) {
186                 /* Enable back light for DSIa panel */
187                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
188                 if (ret < 0)
189                         return ret;
190
191                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
192                 if (ret < 0)
193                         gpio_free(cardhu_dsia_bl_enb);
194         }
195
196         return ret;
197 };
198
199 static void cardhu_backlight_exit(struct device *dev)
200 {
201         if (!is_dsi_panel()) {
202                 /* int ret; */
203                 /*ret = gpio_request(cardhu_bl_enb, "backlight_enb");*/
204                 gpio_set_value(cardhu_bl_enb, 0);
205                 gpio_free(cardhu_bl_enb);
206         } else if (is_panel_218) {
207                 /* Disable back light for DSIa panel */
208                 gpio_set_value(cardhu_dsia_bl_enb, 0);
209                 gpio_free(cardhu_dsia_bl_enb);
210
211                 /* Disable back light for DSIb panel */
212                 gpio_set_value(cardhu_dsib_bl_enb, 0);
213                 gpio_free(cardhu_dsib_bl_enb);
214
215                 gpio_set_value(cardhu_lvds_shutdown, 1);
216                 mdelay(20);
217         } else if (is_panel_219) {
218                 /* Disable back light for DSIa panel */
219                 gpio_set_value(cardhu_dsia_bl_enb, 0);
220                 gpio_free(cardhu_dsia_bl_enb);
221
222                 gpio_set_value(cardhu_lvds_shutdown, 1);
223                 mdelay(20);
224         }
225 }
226
227 static int cardhu_backlight_notify(struct device *unused, int brightness)
228 {
229         int cur_sd_brightness = atomic_read(&sd_brightness);
230
231         if (!is_dsi_panel()) {
232                 /* Set the backlight GPIO pin mode to 'backlight_enable' */
233                 gpio_set_value(cardhu_bl_enb, !!brightness);
234         } else if (is_panel_218) {
235                 /* DSIa */
236                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
237
238                 /* DSIb */
239                 gpio_set_value(cardhu_dsib_bl_enb, !!brightness);
240         } else if (is_panel_219) {
241                 /* DSIa */
242                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
243         } else if (is_panel_1506) {
244                 /* DSIa */
245                 gpio_set_value(e1506_bl_enb, !!brightness);
246         }
247
248         /* SD brightness is a percentage, 8-bit value. */
249         brightness = (brightness * cur_sd_brightness) / 255;
250
251         /* Apply any backlight response curve */
252         if (brightness > 255) {
253                 pr_info("Error: Brightness > 255!\n");
254         } else {
255                 brightness = bl_output[brightness];
256         }
257
258         return brightness;
259 }
260
261 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info);
262
263 static struct platform_pwm_backlight_data cardhu_backlight_data = {
264         .pwm_id         = 0,
265         .max_brightness = 255,
266         .dft_brightness = 224,
267         .pwm_period_ns  = 1000000,
268         .init           = cardhu_backlight_init,
269         .exit           = cardhu_backlight_exit,
270         .notify         = cardhu_backlight_notify,
271         /* Only toggle backlight on fb blank notifications for disp1 */
272         .check_fb       = cardhu_disp1_check_fb,
273 };
274
275 static struct platform_device cardhu_backlight_device = {
276         .name   = "pwm-backlight",
277         .id     = -1,
278         .dev    = {
279                 .platform_data = &cardhu_backlight_data,
280         },
281 };
282
283 static int cardhu_panel_enable(void)
284 {
285         if (cardhu_lvds_reg == NULL) {
286                 cardhu_lvds_reg = regulator_get(NULL, "vdd_lvds");
287                 if (WARN_ON(IS_ERR(cardhu_lvds_reg)))
288                         pr_err("%s: couldn't get regulator vdd_lvds: %ld\n",
289                                 __func__, PTR_ERR(cardhu_lvds_reg));
290                 else
291                         regulator_enable(cardhu_lvds_reg);
292         }
293
294         if (cardhu_lvds_vdd_bl == NULL) {
295                 cardhu_lvds_vdd_bl = regulator_get(NULL, "vdd_backlight");
296                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_bl)))
297                         pr_err("%s: couldn't get regulator vdd_backlight: %ld\n",
298                                 __func__, PTR_ERR(cardhu_lvds_vdd_bl));
299                 else
300                         regulator_enable(cardhu_lvds_vdd_bl);
301         }
302
303         if (cardhu_lvds_vdd_panel == NULL) {
304                 cardhu_lvds_vdd_panel = regulator_get(NULL, "vdd_lcd_panel");
305                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_panel)))
306                         pr_err("%s: couldn't get regulator vdd_lcd_panel: %ld\n",
307                                 __func__, PTR_ERR(cardhu_lvds_vdd_panel));
308                 else
309                         regulator_enable(cardhu_lvds_vdd_panel);
310         }
311
312         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
313                 /* lvds configuration */
314                 gpio_set_value(pm313_R_FDE, 1);
315                 gpio_set_value(pm313_R_FB, 1);
316                 gpio_set_value(pm313_MODE0, 1);
317                 gpio_set_value(pm313_MODE1, 0);
318                 gpio_set_value(pm313_BPP, PM313_LVDS_PANEL_BPP);
319
320                 /* FIXME : it may require more or less delay for latching
321                   values correctly before enabling RGB2LVDS */
322                 mdelay(100);
323                 gpio_set_value(pm313_lvds_shutdown, 1);
324         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
325                         board_info.board_id == BOARD_PM269) ||
326                         (board_info.board_id == BOARD_E1257) ||
327                         (board_info.board_id == BOARD_PM305) ||
328                         (board_info.board_id == BOARD_PM311))
329                 gpio_set_value(e1247_pm269_lvds_shutdown, 1);
330         else
331                 gpio_set_value(cardhu_lvds_shutdown, 1);
332
333         return 0;
334 }
335
336 static int cardhu_panel_disable(void)
337 {
338         regulator_disable(cardhu_lvds_reg);
339         regulator_put(cardhu_lvds_reg);
340         cardhu_lvds_reg = NULL;
341
342         regulator_disable(cardhu_lvds_vdd_bl);
343         regulator_put(cardhu_lvds_vdd_bl);
344         cardhu_lvds_vdd_bl = NULL;
345
346         regulator_disable(cardhu_lvds_vdd_panel);
347         regulator_put(cardhu_lvds_vdd_panel);
348
349         cardhu_lvds_vdd_panel= NULL;
350
351         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
352                 gpio_set_value(pm313_lvds_shutdown, 0);
353         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
354                         board_info.board_id == BOARD_PM269) ||
355                         (board_info.board_id == BOARD_E1257) ||
356                         (board_info.board_id == BOARD_PM305) ||
357                         (board_info.board_id == BOARD_PM311)) {
358                 gpio_set_value(e1247_pm269_lvds_shutdown, 0);
359         } else {
360                 gpio_set_value(cardhu_lvds_shutdown, 0);
361         }
362         return 0;
363 }
364
365 #ifdef CONFIG_TEGRA_DC
366 static int cardhu_hdmi_vddio_enable(void)
367 {
368         int ret;
369         if (!cardhu_hdmi_vddio) {
370                 cardhu_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
371                 if (IS_ERR_OR_NULL(cardhu_hdmi_vddio)) {
372                         ret = PTR_ERR(cardhu_hdmi_vddio);
373                         pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
374                         cardhu_hdmi_vddio = NULL;
375                         return ret;
376                 }
377         }
378         ret = regulator_enable(cardhu_hdmi_vddio);
379         if (ret < 0) {
380                 pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
381                 regulator_put(cardhu_hdmi_vddio);
382                 cardhu_hdmi_vddio = NULL;
383                 return ret;
384         }
385         return ret;
386 }
387
388 static int cardhu_hdmi_vddio_disable(void)
389 {
390         if (cardhu_hdmi_vddio) {
391                 regulator_disable(cardhu_hdmi_vddio);
392                 regulator_put(cardhu_hdmi_vddio);
393                 cardhu_hdmi_vddio = NULL;
394         }
395         return 0;
396 }
397
398 static int cardhu_hdmi_enable(void)
399 {
400         int ret;
401         if (!cardhu_hdmi_reg) {
402                 cardhu_hdmi_reg = regulator_get(NULL, "avdd_hdmi");
403                 if (IS_ERR_OR_NULL(cardhu_hdmi_reg)) {
404                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
405                         cardhu_hdmi_reg = NULL;
406                         return PTR_ERR(cardhu_hdmi_reg);
407                 }
408         }
409         ret = regulator_enable(cardhu_hdmi_reg);
410         if (ret < 0) {
411                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
412                 return ret;
413         }
414         if (!cardhu_hdmi_pll) {
415                 cardhu_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll");
416                 if (IS_ERR_OR_NULL(cardhu_hdmi_pll)) {
417                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
418                         cardhu_hdmi_pll = NULL;
419                         regulator_put(cardhu_hdmi_reg);
420                         cardhu_hdmi_reg = NULL;
421                         return PTR_ERR(cardhu_hdmi_pll);
422                 }
423         }
424         ret = regulator_enable(cardhu_hdmi_pll);
425         if (ret < 0) {
426                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
427                 return ret;
428         }
429         return 0;
430 }
431
432 static int cardhu_hdmi_disable(void)
433 {
434         regulator_disable(cardhu_hdmi_reg);
435         regulator_put(cardhu_hdmi_reg);
436         cardhu_hdmi_reg = NULL;
437
438         regulator_disable(cardhu_hdmi_pll);
439         regulator_put(cardhu_hdmi_pll);
440         cardhu_hdmi_pll = NULL;
441         return 0;
442 }
443
444 static struct resource cardhu_disp1_resources[] = {
445         {
446                 .name   = "irq",
447                 .start  = INT_DISPLAY_GENERAL,
448                 .end    = INT_DISPLAY_GENERAL,
449                 .flags  = IORESOURCE_IRQ,
450         },
451         {
452                 .name   = "regs",
453                 .start  = TEGRA_DISPLAY_BASE,
454                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
455                 .flags  = IORESOURCE_MEM,
456         },
457         {
458                 .name   = "fbmem",
459                 .start  = 0,    /* Filled in by cardhu_panel_init() */
460                 .end    = 0,    /* Filled in by cardhu_panel_init() */
461                 .flags  = IORESOURCE_MEM,
462         },
463 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
464         {
465                 .name   = "dsi_regs",
466                 .start  = TEGRA_DSIB_BASE,
467                 .end    = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1,
468                 .flags  = IORESOURCE_MEM,
469         },
470 #else
471         {
472                 .name   = "dsi_regs",
473                 .start  = TEGRA_DSI_BASE,
474                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
475                 .flags  = IORESOURCE_MEM,
476         },
477 #endif
478 };
479
480 static struct resource cardhu_disp2_resources[] = {
481         {
482                 .name   = "irq",
483                 .start  = INT_DISPLAY_B_GENERAL,
484                 .end    = INT_DISPLAY_B_GENERAL,
485                 .flags  = IORESOURCE_IRQ,
486         },
487         {
488                 .name   = "regs",
489                 .start  = TEGRA_DISPLAY2_BASE,
490                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
491                 .flags  = IORESOURCE_MEM,
492         },
493         {
494                 .name   = "fbmem",
495                 .flags  = IORESOURCE_MEM,
496                 .start  = 0,
497                 .end    = 0,
498         },
499         {
500                 .name   = "hdmi_regs",
501                 .start  = TEGRA_HDMI_BASE,
502                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
503                 .flags  = IORESOURCE_MEM,
504         },
505 };
506 #endif
507
508 static struct tegra_dc_mode panel_19X12_modes[] = {
509         {
510                 .pclk = 154000000,
511                 .h_ref_to_sync = 11,
512                 .v_ref_to_sync = 1,
513                 .h_sync_width = 32,
514                 .v_sync_width = 6,
515                 .h_back_porch = 80,
516                 .v_back_porch = 26,
517                 .h_active = 1920,
518                 .v_active = 1200,
519                 .h_front_porch = 48,
520                 .v_front_porch = 3,
521         },
522 };
523
524 static struct tegra_dc_mode cardhu_panel_modes[] = {
525         {
526                 /* 1366x768@60Hz */
527                 .pclk = 74180000,
528                 .h_ref_to_sync = 1,
529                 .v_ref_to_sync = 1,
530                 .h_sync_width = 30,
531                 .v_sync_width = 5,
532                 .h_back_porch = 52,
533                 .v_back_porch = 20,
534                 .h_active = 1366,
535                 .v_active = 768,
536                 .h_front_porch = 64,
537                 .v_front_porch = 25,
538         },
539         {
540                 /* 1366x768@50Hz */
541                 .pclk = 74180000,
542                 .h_ref_to_sync = 1,
543                 .v_ref_to_sync = 1,
544                 .h_sync_width = 30,
545                 .v_sync_width = 5,
546                 .h_back_porch = 56,
547                 .v_back_porch = 80,
548                 .h_active = 1366,
549                 .v_active = 768,
550                 .h_front_porch = 64,
551                 .v_front_porch = 125,
552         },
553         {
554                 /* 1366x768@48 */
555                 .pclk = 74180000,
556                 .h_ref_to_sync = 1,
557                 .v_ref_to_sync = 1,
558                 .h_sync_width = 30,
559                 .v_sync_width = 5,
560                 .h_back_porch = 52,
561                 .v_back_porch = 98,
562                 .h_active = 1366,
563                 .v_active = 768,
564                 .h_front_porch = 64,
565                 .v_front_porch = 152,
566         },
567 };
568
569 static struct tegra_dc_mode cardhu_panel_modes_55hz[] = {
570         {
571                 /* 1366x768p 55Hz */
572                 .pclk = 68000000,
573                 .h_ref_to_sync = 0,
574                 .v_ref_to_sync = 12,
575                 .h_sync_width = 30,
576                 .v_sync_width = 5,
577                 .h_back_porch = 52,
578                 .v_back_porch = 20,
579                 .h_active = 1366,
580                 .v_active = 768,
581                 .h_front_porch = 64,
582                 .v_front_porch = 25,
583         },
584 };
585
586 static struct tegra_dc_sd_settings cardhu_sd_settings = {
587         .enable = 1, /* enabled by default. */
588         .use_auto_pwm = false,
589         .hw_update_delay = 0,
590         .bin_width = -1,
591         .aggressiveness = 1,
592         .phase_in_adjustments = true,
593         .use_vid_luma = false,
594         /* Default video coefficients */
595         .coeff = {5, 9, 2},
596         .fc = {0, 0},
597         /* Immediate backlight changes */
598         .blp = {1024, 255},
599         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
600         /* Default BL TF */
601         .bltf = {
602                         {
603                                 {57, 65, 74, 83},
604                                 {93, 103, 114, 126},
605                                 {138, 151, 165, 179},
606                                 {194, 209, 225, 242},
607                         },
608                         {
609                                 {58, 66, 75, 84},
610                                 {94, 105, 116, 127},
611                                 {140, 153, 166, 181},
612                                 {196, 211, 227, 244},
613                         },
614                         {
615                                 {60, 68, 77, 87},
616                                 {97, 107, 119, 130},
617                                 {143, 156, 170, 184},
618                                 {199, 215, 231, 248},
619                         },
620                         {
621                                 {64, 73, 82, 91},
622                                 {102, 113, 124, 137},
623                                 {149, 163, 177, 192},
624                                 {207, 223, 240, 255},
625                         },
626                 },
627         /* Default LUT */
628         .lut = {
629                         {
630                                 {250, 250, 250},
631                                 {194, 194, 194},
632                                 {149, 149, 149},
633                                 {113, 113, 113},
634                                 {82, 82, 82},
635                                 {56, 56, 56},
636                                 {34, 34, 34},
637                                 {15, 15, 15},
638                                 {0, 0, 0},
639                         },
640                         {
641                                 {246, 246, 246},
642                                 {191, 191, 191},
643                                 {147, 147, 147},
644                                 {111, 111, 111},
645                                 {80, 80, 80},
646                                 {55, 55, 55},
647                                 {33, 33, 33},
648                                 {14, 14, 14},
649                                 {0, 0, 0},
650                         },
651                         {
652                                 {239, 239, 239},
653                                 {185, 185, 185},
654                                 {142, 142, 142},
655                                 {107, 107, 107},
656                                 {77, 77, 77},
657                                 {52, 52, 52},
658                                 {30, 30, 30},
659                                 {12, 12, 12},
660                                 {0, 0, 0},
661                         },
662                         {
663                                 {224, 224, 224},
664                                 {173, 173, 173},
665                                 {133, 133, 133},
666                                 {99, 99, 99},
667                                 {70, 70, 70},
668                                 {46, 46, 46},
669                                 {25, 25, 25},
670                                 {7, 7, 7},
671                                 {0, 0, 0},
672                         },
673                 },
674         .sd_brightness = &sd_brightness,
675         .bl_device = &cardhu_backlight_device,
676 };
677
678 #ifdef CONFIG_TEGRA_DC
679 static struct tegra_fb_data cardhu_fb_data = {
680         .win            = 0,
681         .xres           = 1366,
682         .yres           = 768,
683         .bits_per_pixel = 32,
684         .flags          = TEGRA_FB_FLIP_ON_PROBE,
685 };
686
687 static struct tegra_fb_data cardhu_hdmi_fb_data = {
688         .win            = 0,
689         .xres           = 640,
690         .yres           = 480,
691         .bits_per_pixel = 32,
692         .flags          = TEGRA_FB_FLIP_ON_PROBE,
693 };
694
695 static struct tegra_dc_out cardhu_disp2_out = {
696         .type           = TEGRA_DC_OUT_HDMI,
697         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
698         .parent_clk     = "pll_d2_out0",
699
700         .dcc_bus        = 3,
701         .hotplug_gpio   = cardhu_hdmi_hpd,
702
703         .max_pixclock   = KHZ2PICOS(148500),
704
705         .align          = TEGRA_DC_ALIGN_MSB,
706         .order          = TEGRA_DC_ORDER_RED_BLUE,
707
708         .enable         = cardhu_hdmi_enable,
709         .disable        = cardhu_hdmi_disable,
710
711         .postsuspend    = cardhu_hdmi_vddio_disable,
712         .hotplug_init   = cardhu_hdmi_vddio_enable,
713 };
714
715 static struct tegra_dc_platform_data cardhu_disp2_pdata = {
716         .flags          = TEGRA_DC_FLAG_ENABLED,
717         .default_out    = &cardhu_disp2_out,
718         .fb             = &cardhu_hdmi_fb_data,
719         .emc_clk_rate   = 300000000,
720 };
721 #endif
722
723 static int cardhu_dsi_panel_enable(void)
724 {
725         int ret;
726
727         if (cardhu_dsi_reg == NULL) {
728                 cardhu_dsi_reg = regulator_get(NULL, "avdd_dsi_csi");
729                 if (IS_ERR_OR_NULL(cardhu_dsi_reg)) {
730                         pr_err("dsi: Could not get regulator avdd_dsi_csi\n");
731                         cardhu_dsi_reg = NULL;
732                         return PTR_ERR(cardhu_dsi_reg);
733                 }
734         }
735
736         regulator_enable(cardhu_dsi_reg);
737
738         if (!is_panel_1506) {
739                 ret = gpio_request(AVDD_LCD, "avdd_lcd");
740                 if (ret < 0)
741                         gpio_free(AVDD_LCD);
742                 ret = gpio_direction_output(AVDD_LCD, 1);
743                 if (ret < 0)
744                         gpio_free(AVDD_LCD);
745         }
746
747         if (is_panel_219) {
748                 ret = gpio_request(cardhu_bl_pwm, "bl_pwm");
749                 if (ret < 0)
750                         return ret;
751                 ret = gpio_direction_output(cardhu_bl_pwm, 0);
752                 if (ret < 0) {
753                         gpio_free(cardhu_bl_pwm);
754                         return ret;
755                 }
756
757                 ret = gpio_request(cardhu_bl_enb, "bl_enb");
758                 if (ret < 0)
759                         return ret;
760                 ret = gpio_direction_output(cardhu_bl_enb, 0);
761                 if (ret < 0) {
762                         gpio_free(cardhu_bl_enb);
763                         return ret;
764                 }
765
766                 gpio_set_value(cardhu_lvds_shutdown, 1);
767                 mdelay(20);
768                 gpio_set_value(cardhu_bl_pwm, 1);
769                 mdelay(10);
770                 gpio_set_value(cardhu_bl_enb, 1);
771                 mdelay(15);
772         } else if (is_panel_1506) {
773                 ret = gpio_request(e1506_dsi_vddio, "e1506_dsi_vddio");
774                 if (ret < 0)
775                         return ret;
776                 ret = gpio_direction_output(e1506_dsi_vddio, 0);
777                 if (ret < 0) {
778                         gpio_free(e1506_dsi_vddio);
779                         return ret;
780                 }
781
782                 ret = gpio_request(e1506_panel_enb, "e1506_panel_enb");
783                 if (ret < 0)
784                         return ret;
785                 ret = gpio_direction_output(e1506_panel_enb, 0);
786                 if (ret < 0) {
787                         gpio_free(e1506_panel_enb);
788                         return ret;
789                 }
790
791                 ret = gpio_request(e1506_bl_enb, "e1506_bl_enb");
792                 if (ret < 0)
793                         return ret;
794                 ret = gpio_direction_output(e1506_bl_enb, 0);
795                 if (ret < 0) {
796                         gpio_free(e1506_bl_enb);
797                         return ret;
798                 }
799
800                 gpio_set_value(e1506_dsi_vddio, 1);
801                 mdelay(1);
802                 gpio_set_value(e1506_panel_enb, 1);
803                 mdelay(10);
804                 gpio_set_value(e1506_bl_enb, 1);
805                 mdelay(15);
806         }
807
808 #if DSI_PANEL_RESET
809         if (is_panel_218) {
810                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
811                 if (ret < 0)
812                         return ret;
813
814                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
815                 if (ret < 0) {
816                         gpio_free(cardhu_dsi_pnl_reset);
817                         return ret;
818                 }
819
820                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
821                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
822                 mdelay(2);
823                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
824                 mdelay(2);
825         } else if (is_panel_219) {
826                 ret = gpio_request(cardhu_dsi_219_pnl_reset, "dsi_panel_reset");
827                 if (ret < 0)
828                         return ret;
829                 ret = gpio_direction_output(cardhu_dsi_219_pnl_reset, 0);
830                 if (ret < 0) {
831                         gpio_free(cardhu_dsi_219_pnl_reset);
832                         return ret;
833                 }
834
835                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
836                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
837                 mdelay(10);
838                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
839                 mdelay(10);
840                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
841                 mdelay(15);
842         } else if (is_panel_1506) {
843                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
844                 if (ret < 0)
845                         return ret;
846                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
847                 if (ret < 0) {
848                         gpio_free(cardhu_dsi_pnl_reset);
849                         return ret;
850                 }
851
852                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
853                 mdelay(1);
854                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
855                 mdelay(1);
856                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
857                 mdelay(20);
858         }
859 #endif
860
861         return 0;
862 }
863
864 static int cardhu_dsi_panel_disable(void)
865 {
866         int err;
867
868         err = 0;
869
870         if (is_panel_219) {
871                 gpio_free(cardhu_dsi_219_pnl_reset);
872                 gpio_free(cardhu_bl_enb);
873                 gpio_free(cardhu_bl_pwm);
874                 gpio_free(cardhu_lvds_shutdown);
875         } else if (is_panel_218) {
876                 gpio_free(cardhu_dsi_pnl_reset);
877         } else if (is_panel_1506) {
878                 tegra_gpio_disable(e1506_bl_enb);
879                 gpio_free(e1506_bl_enb);
880                 tegra_gpio_disable(cardhu_dsi_pnl_reset);
881                 gpio_free(cardhu_dsi_pnl_reset);
882                 tegra_gpio_disable(e1506_panel_enb);
883                 gpio_free(e1506_panel_enb);
884                 tegra_gpio_disable(e1506_dsi_vddio);
885                 gpio_free(e1506_dsi_vddio);
886         }
887         return err;
888 }
889
890 static int cardhu_dsi_panel_postsuspend(void)
891 {
892         int err;
893
894         err = 0;
895         printk(KERN_INFO "DSI panel postsuspend\n");
896
897         if (cardhu_dsi_reg) {
898                 err = regulator_disable(cardhu_dsi_reg);
899                 if (err < 0)
900                         printk(KERN_ERR
901                         "DSI regulator avdd_dsi_csi disable failed\n");
902                 regulator_put(cardhu_dsi_reg);
903                 cardhu_dsi_reg = NULL;
904         }
905
906         if (is_panel_218)
907                 gpio_free(AVDD_LCD);
908
909         return err;
910 }
911
912 static struct tegra_dsi_cmd dsi_init_cmd[] = {
913         DSI_CMD_SHORT(0x05, 0x11, 0x00),
914         DSI_DLY_MS(150),
915 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
916         DSI_CMD_SHORT(0x15, 0x35, 0x00),
917 #endif
918         DSI_CMD_SHORT(0x05, 0x29, 0x00),
919         DSI_DLY_MS(20),
920 };
921
922 u8 password_array[] = {0xb9, 0xff, 0x83, 0x92};
923
924 static struct tegra_dsi_cmd dsi_init_cmd_1506[] = {
925         DSI_CMD_SHORT(0x05, 0x11, 0x00),
926         DSI_DLY_MS(150),
927         DSI_CMD_LONG(0x39, password_array),
928         DSI_DLY_MS(10),
929         DSI_CMD_SHORT(0x15, 0xd4, 0x0c),
930         DSI_DLY_MS(10),
931         DSI_CMD_SHORT(0x15, 0xba, 0x11),
932         DSI_DLY_MS(10),
933 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
934         DSI_CMD_SHORT(0x15, 0x35, 0x00),
935 #endif
936         DSI_CMD_SHORT(0x05, 0x29, 0x00),
937         DSI_DLY_MS(20),
938 };
939
940 static struct tegra_dsi_cmd dsi_early_suspend_cmd[] = {
941         DSI_CMD_SHORT(0x05, 0x28, 0x00),
942         DSI_DLY_MS(20),
943 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
944         DSI_CMD_SHORT(0x05, 0x34, 0x00),
945 #endif
946 };
947
948 static struct tegra_dsi_cmd dsi_late_resume_cmd[] = {
949 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
950         DSI_CMD_SHORT(0x15, 0x35, 0x00),
951 #endif
952         DSI_CMD_SHORT(0x05, 0x29, 0x00),
953         DSI_DLY_MS(20),
954 };
955
956 static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
957         DSI_CMD_SHORT(0x05, 0x28, 0x00),
958         DSI_DLY_MS(120),
959 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
960         DSI_CMD_SHORT(0x05, 0x34, 0x00),
961 #endif
962         DSI_CMD_SHORT(0x05, 0x10, 0x00),
963         DSI_DLY_MS(5),
964 };
965
966 static struct tegra_dsi_cmd dsi_suspend_cmd_1506[] = {
967         DSI_CMD_SHORT(0x05, 0x28, 0x00),
968         DSI_CMD_SHORT(0x05, 0x10, 0x00),
969         DSI_DLY_MS(120),
970 };
971
972 struct tegra_dsi_out cardhu_dsi = {
973         .n_data_lanes = 2,
974         .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
975
976 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
977         /*
978          * The one-shot frame time must be shorter than the time between TE.
979          * Increasing refresh_rate will result in a decrease in the frame time
980          * for one-shot. rated_refresh_rate is only an approximation of the
981          * TE rate, and is only used to report refresh rate to upper layers.
982          */
983         .refresh_rate = 66,
984         .rated_refresh_rate = 60,
985 #else
986         .refresh_rate = 60,
987 #endif
988         .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
989
990         .panel_has_frame_buffer = true,
991 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
992         .dsi_instance = 1,
993 #else
994         .dsi_instance = 0,
995 #endif
996         .panel_reset = DSI_PANEL_RESET,
997         .power_saving_suspend = true,
998
999         .n_early_suspend_cmd = ARRAY_SIZE(dsi_early_suspend_cmd),
1000         .dsi_early_suspend_cmd = dsi_early_suspend_cmd,
1001
1002         .n_late_resume_cmd = ARRAY_SIZE(dsi_late_resume_cmd),
1003         .dsi_late_resume_cmd = dsi_late_resume_cmd,
1004
1005         .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
1006         .dsi_suspend_cmd = dsi_suspend_cmd,
1007
1008         .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
1009         .lp_cmd_mode_freq_khz = 430000,
1010 };
1011
1012 static struct tegra_dc_mode cardhu_dsi_modes_219[] = {
1013         {
1014                 .pclk = 10000000,
1015                 .h_ref_to_sync = 4,
1016                 .v_ref_to_sync = 1,
1017                 .h_sync_width = 16,
1018                 .v_sync_width = 1,
1019                 .h_back_porch = 32,
1020                 .v_back_porch = 1,
1021                 .h_active = 540,
1022                 .v_active = 960,
1023                 .h_front_porch = 32,
1024                 .v_front_porch = 2,
1025         },
1026 };
1027
1028 static struct tegra_dc_mode cardhu_dsi_modes_218[] = {
1029         {
1030                 .pclk = 323000000,
1031                 .h_ref_to_sync = 11,
1032                 .v_ref_to_sync = 1,
1033                 .h_sync_width = 16,
1034                 .v_sync_width = 4,
1035                 .h_back_porch = 16,
1036                 .v_back_porch = 4,
1037                 .h_active = 864,
1038                 .v_active = 480,
1039                 .h_front_porch = 16,
1040                 .v_front_porch = 4,
1041         },
1042 };
1043
1044 static struct tegra_dc_mode cardhu_dsi_modes_1506[] = {
1045         {
1046                 .pclk = 61417000,
1047                 .h_ref_to_sync = 2,
1048                 .v_ref_to_sync = 2,
1049                 .h_sync_width = 4,
1050                 .v_sync_width = 4,
1051                 .h_back_porch = 100,
1052                 .v_back_porch = 14,
1053                 .h_active = 720,
1054                 .v_active = 1280,
1055                 .h_front_porch = 4,
1056                 .v_front_porch = 4,
1057         },
1058 };
1059
1060
1061 static struct tegra_fb_data cardhu_dsi_fb_data = {
1062         .win            = 0,
1063         .bits_per_pixel = 32,
1064         .flags          = TEGRA_FB_FLIP_ON_PROBE,
1065 };
1066
1067 static struct tegra_dc_out cardhu_disp1_out = {
1068         .align          = TEGRA_DC_ALIGN_MSB,
1069         .order          = TEGRA_DC_ORDER_RED_BLUE,
1070         .sd_settings    = &cardhu_sd_settings,
1071         .parent_clk     = "pll_d_out0",
1072
1073 };
1074
1075 #ifdef CONFIG_TEGRA_DC
1076 static struct tegra_dc_platform_data cardhu_disp1_pdata = {
1077         .flags          = TEGRA_DC_FLAG_ENABLED,
1078         .default_out    = &cardhu_disp1_out,
1079         .emc_clk_rate   = 300000000,
1080 };
1081
1082 static struct nvhost_device cardhu_disp1_device = {
1083         .name           = "tegradc",
1084         .id             = 0,
1085         .resource       = cardhu_disp1_resources,
1086         .num_resources  = ARRAY_SIZE(cardhu_disp1_resources),
1087         .dev = {
1088                 .platform_data = &cardhu_disp1_pdata,
1089         },
1090 };
1091
1092 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1093 {
1094         return info->device == &cardhu_disp1_device.dev;
1095 }
1096
1097 static struct nvhost_device cardhu_disp2_device = {
1098         .name           = "tegradc",
1099         .id             = 1,
1100         .resource       = cardhu_disp2_resources,
1101         .num_resources  = ARRAY_SIZE(cardhu_disp2_resources),
1102         .dev = {
1103                 .platform_data = &cardhu_disp2_pdata,
1104         },
1105 };
1106 #else
1107 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1108 {
1109         return 0;
1110 }
1111 #endif
1112
1113 #if defined(CONFIG_TEGRA_NVMAP)
1114 static struct nvmap_platform_carveout cardhu_carveouts[] = {
1115         [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
1116         [1] = {
1117                 .name           = "generic-0",
1118                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
1119                 .base           = 0,    /* Filled in by cardhu_panel_init() */
1120                 .size           = 0,    /* Filled in by cardhu_panel_init() */
1121                 .buddy_size     = SZ_32K,
1122         },
1123 };
1124
1125 static struct nvmap_platform_data cardhu_nvmap_data = {
1126         .carveouts      = cardhu_carveouts,
1127         .nr_carveouts   = ARRAY_SIZE(cardhu_carveouts),
1128 };
1129
1130 static struct platform_device cardhu_nvmap_device = {
1131         .name   = "tegra-nvmap",
1132         .id     = -1,
1133         .dev    = {
1134                 .platform_data = &cardhu_nvmap_data,
1135         },
1136 };
1137 #endif
1138
1139 #if defined(CONFIG_ION_TEGRA)
1140
1141 static struct platform_device tegra_iommu_device = {
1142         .name = "tegra_iommu_device",
1143         .id = -1,
1144         .dev = {
1145                 .platform_data = (void *)((1 << HWGRP_COUNT) - 1),
1146         },
1147 };
1148
1149 static struct ion_platform_data tegra_ion_data = {
1150         .nr = 4,
1151         .heaps = {
1152                 {
1153                         .type = ION_HEAP_TYPE_CARVEOUT,
1154                         .id = TEGRA_ION_HEAP_CARVEOUT,
1155                         .name = "carveout",
1156                         .base = 0,
1157                         .size = 0,
1158                 },
1159                 {
1160                         .type = ION_HEAP_TYPE_CARVEOUT,
1161                         .id = TEGRA_ION_HEAP_IRAM,
1162                         .name = "iram",
1163                         .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
1164                         .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
1165                 },
1166                 {
1167                         .type = ION_HEAP_TYPE_CARVEOUT,
1168                         .id = TEGRA_ION_HEAP_VPR,
1169                         .name = "vpr",
1170                         .base = 0,
1171                         .size = 0,
1172                 },
1173                 {
1174                         .type = ION_HEAP_TYPE_IOMMU,
1175                         .id = TEGRA_ION_HEAP_IOMMU,
1176                         .name = "iommu",
1177                         .base = TEGRA_SMMU_BASE,
1178                         .size = TEGRA_SMMU_SIZE,
1179                         .priv = &tegra_iommu_device.dev,
1180                 },
1181         },
1182 };
1183
1184 static struct platform_device tegra_ion_device = {
1185         .name = "ion-tegra",
1186         .id = -1,
1187         .dev = {
1188                 .platform_data = &tegra_ion_data,
1189         },
1190 };
1191 #endif
1192
1193 static struct platform_device *cardhu_gfx_devices[] __initdata = {
1194 #if defined(CONFIG_TEGRA_NVMAP)
1195         &cardhu_nvmap_device,
1196 #endif
1197 #if defined(CONFIG_ION_TEGRA)
1198         &tegra_ion_device,
1199 #endif
1200         &tegra_pwfm0_device,
1201         &cardhu_backlight_device,
1202 };
1203
1204 static void cardhu_panel_preinit(void)
1205 {
1206         if (display_board_info.board_id == BOARD_DISPLAY_E1213)
1207                 is_panel_218 = true;
1208         else if (display_board_info.board_id == BOARD_DISPLAY_E1253)
1209                 is_panel_219 = true;
1210         else if (display_board_info.board_id == BOARD_DISPLAY_E1506)
1211                 is_panel_1506 = true;
1212
1213         if (!is_dsi_panel()) {
1214                 cardhu_disp1_out.parent_clk_backup = "pll_d2_out0";
1215                 cardhu_disp1_out.type = TEGRA_DC_OUT_RGB;
1216                 cardhu_disp1_out.depth = 18;
1217                 cardhu_disp1_out.dither = TEGRA_DC_ORDERED_DITHER;
1218                 cardhu_disp1_out.modes = cardhu_panel_modes;
1219                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes);
1220                 cardhu_disp1_out.enable = cardhu_panel_enable;
1221                 cardhu_disp1_out.disable = cardhu_panel_disable;
1222
1223                 cardhu_disp1_pdata.fb = &cardhu_fb_data;
1224         } else {
1225                 cardhu_disp1_out.flags = DC_CTRL_MODE;
1226                 cardhu_disp1_out.type = TEGRA_DC_OUT_DSI;
1227                 cardhu_disp1_out.dsi = &cardhu_dsi;
1228                 cardhu_disp1_out.enable = cardhu_dsi_panel_enable;
1229                 cardhu_disp1_out.disable = cardhu_dsi_panel_disable;
1230                 cardhu_disp1_out.postsuspend = cardhu_dsi_panel_postsuspend;
1231
1232                 cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd);
1233                 cardhu_dsi.dsi_init_cmd = dsi_init_cmd;
1234                 cardhu_dsi.n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd);
1235                 cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd;
1236
1237                 if (is_panel_218) {
1238                         cardhu_disp1_out.modes  = cardhu_dsi_modes_218;
1239                         cardhu_disp1_out.n_modes =
1240                                 ARRAY_SIZE(cardhu_dsi_modes_218);
1241                         cardhu_dsi_fb_data.xres = 864;
1242                         cardhu_dsi_fb_data.yres = 480;
1243                 } else if (is_panel_219) {
1244                         cardhu_disp1_out.modes  = cardhu_dsi_modes_219;
1245                         cardhu_disp1_out.n_modes =
1246                                 ARRAY_SIZE(cardhu_dsi_modes_219);
1247                         cardhu_dsi_fb_data.xres = 540;
1248                         cardhu_dsi_fb_data.yres = 960;
1249                 } else if (is_panel_1506) {
1250                         cardhu_disp1_out.modes  = cardhu_dsi_modes_1506;
1251                         cardhu_disp1_out.n_modes =
1252                                 ARRAY_SIZE(cardhu_dsi_modes_1506);
1253                         cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd_1506);
1254                         cardhu_dsi.dsi_init_cmd = dsi_init_cmd_1506;
1255                         cardhu_dsi.n_suspend_cmd =
1256                                 ARRAY_SIZE(dsi_suspend_cmd_1506);
1257                         cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd_1506;
1258                         cardhu_dsi.panel_send_dc_frames = true,
1259                         cardhu_dsi_fb_data.xres = 720;
1260                         cardhu_dsi_fb_data.yres = 1280;
1261                 }
1262
1263                 cardhu_disp1_pdata.fb = &cardhu_dsi_fb_data;
1264         }
1265 }
1266
1267 int __init cardhu_panel_init(void)
1268 {
1269         int err;
1270         struct resource __maybe_unused *res;
1271
1272         tegra_get_board_info(&board_info);
1273         tegra_get_display_board_info(&display_board_info);
1274
1275 #if defined(CONFIG_TEGRA_NVMAP)
1276         cardhu_carveouts[1].base = tegra_carveout_start;
1277         cardhu_carveouts[1].size = tegra_carveout_size;
1278 #endif
1279
1280 #if defined(CONFIG_ION_TEGRA)
1281         tegra_ion_data.heaps[0].base = tegra_carveout_start;
1282         tegra_ion_data.heaps[0].size = tegra_carveout_size;
1283 #endif
1284
1285         cardhu_panel_preinit();
1286         if (is_dsi_panel()) {
1287                 if (is_panel_1506) {
1288                         /*
1289                          * HACK: To be Removed
1290                          */
1291                         int i;
1292                         struct clk *c = tegra_get_clock_by_name("dsia");
1293
1294                         for (i = 0; i < c->dvfs->num_freqs; i++)
1295                                 c->dvfs->freqs[i] = 500000000;
1296                 }
1297                 goto skip_lvds;
1298         }
1299 #if defined(CONFIG_TEGRA_DC)
1300         if (WARN_ON(board_info.board_id == BOARD_E1291 &&
1301                 ((board_info.sku & SKU_TOUCHSCREEN_MECH_FIX) == 0))) {
1302                 /* use 55Hz panel timings to reduce noise on sensitive touch */
1303                 printk("Using cardhu_panel_modes_55hz\n");
1304                 cardhu_disp1_out.parent_clk = "pll_p";
1305                 cardhu_disp1_out.modes = cardhu_panel_modes_55hz;
1306                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes_55hz);
1307         }
1308
1309         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
1310                 /* initialize the values */
1311 #if defined(PM313_LVDS_PANEL_19X12)
1312                 cardhu_disp1_out.modes = panel_19X12_modes;
1313                 cardhu_disp1_out.n_modes = ARRAY_SIZE(panel_19X12_modes);
1314                 cardhu_disp1_out.parent_clk = "pll_d_out0";
1315 #if (PM313_LVDS_PANEL_BPP == 1)
1316                 cardhu_disp1_out.depth = 18;
1317 #else
1318                 cardhu_disp1_out.depth = 24;
1319 #endif
1320                 cardhu_fb_data.xres = 1920;
1321                 cardhu_fb_data.yres = 1200;
1322
1323                 cardhu_disp2_out.parent_clk = "pll_d2_out0";
1324                 cardhu_hdmi_fb_data.xres = 1920;
1325                 cardhu_hdmi_fb_data.yres = 1200;
1326 #endif
1327
1328                 /* lvds configuration */
1329                 err = gpio_request(pm313_R_FDE, "R_FDE");
1330                 err |= gpio_direction_output(pm313_R_FDE, 1);
1331
1332                 err |= gpio_request(pm313_R_FB, "R_FB");
1333                 err |= gpio_direction_output(pm313_R_FB, 1);
1334
1335                 err |= gpio_request(pm313_MODE0, "MODE0");
1336                 err |= gpio_direction_output(pm313_MODE0, 1);
1337
1338                 err |= gpio_request(pm313_MODE1, "MODE1");
1339                 err |= gpio_direction_output(pm313_MODE1, 0);
1340
1341                 err |= gpio_request(pm313_BPP, "BPP");
1342                 err |= gpio_direction_output(pm313_BPP, PM313_LVDS_PANEL_BPP);
1343
1344                 err = gpio_request(pm313_lvds_shutdown, "lvds_shutdown");
1345                 /* free ride provided by bootloader */
1346                 err |= gpio_direction_output(pm313_lvds_shutdown, 1);
1347
1348                 if (err)
1349                         printk(KERN_ERR "ERROR(s) in LVDS configuration\n");
1350         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
1351                                 board_info.board_id == BOARD_PM269) ||
1352                                 (board_info.board_id == BOARD_E1257) ||
1353                                 (board_info.board_id == BOARD_PM305) ||
1354                                 (board_info.board_id == BOARD_PM311)) {
1355                 gpio_request(e1247_pm269_lvds_shutdown, "lvds_shutdown");
1356                 gpio_direction_output(e1247_pm269_lvds_shutdown, 1);
1357         } else {
1358                 gpio_request(cardhu_lvds_shutdown, "lvds_shutdown");
1359                 gpio_direction_output(cardhu_lvds_shutdown, 1);
1360         }
1361 #endif
1362
1363 skip_lvds:
1364         gpio_request(cardhu_hdmi_hpd, "hdmi_hpd");
1365         gpio_direction_input(cardhu_hdmi_hpd);
1366
1367 #if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
1368         tegra_gpio_enable(e1506_lcd_te);
1369         gpio_request(e1506_lcd_te, "lcd_te");
1370         gpio_direction_input(e1506_lcd_te);
1371 #endif
1372
1373 #ifdef CONFIG_TEGRA_GRHOST
1374         err = tegra3_register_host1x_devices();
1375         if (err)
1376                 return err;
1377 #endif
1378
1379         err = platform_add_devices(cardhu_gfx_devices,
1380                                 ARRAY_SIZE(cardhu_gfx_devices));
1381
1382 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1383         res = nvhost_get_resource_byname(&cardhu_disp1_device,
1384                                          IORESOURCE_MEM, "fbmem");
1385         res->start = tegra_fb_start;
1386         res->end = tegra_fb_start + tegra_fb_size - 1;
1387 #endif
1388
1389         /* Copy the bootloader fb to the fb. */
1390         tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
1391                                 min(tegra_fb_size, tegra_bootloader_fb_size));
1392
1393 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1394         if (!err)
1395                 err = nvhost_device_register(&cardhu_disp1_device);
1396
1397         res = nvhost_get_resource_byname(&cardhu_disp2_device,
1398                                          IORESOURCE_MEM, "fbmem");
1399         res->start = tegra_fb2_start;
1400         res->end = tegra_fb2_start + tegra_fb2_size - 1;
1401
1402         /* Copy the bootloader fb to the fb2. */
1403         tegra_move_framebuffer(tegra_fb2_start, tegra_bootloader_fb_start,
1404                                 min(tegra_fb2_size, tegra_bootloader_fb_size));
1405
1406         if (!err)
1407                 err = nvhost_device_register(&cardhu_disp2_device);
1408 #endif
1409
1410 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
1411         if (!err)
1412                 err = nvhost_device_register(&nvavp_device);
1413 #endif
1414         return err;
1415 }