video: tegra: host: Register devices in SoC files
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-panel.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu-panel.c
3  *
4  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/delay.h>
22 #include <linux/ion.h>
23 #include <linux/tegra_ion.h>
24 #include <linux/gpio.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/resource.h>
27 #include <asm/mach-types.h>
28 #include <linux/platform_device.h>
29 #ifdef CONFIG_HAS_EARLYSUSPEND
30 #include <linux/earlysuspend.h>
31 #endif
32 #include <linux/pwm_backlight.h>
33 #include <asm/atomic.h>
34 #include <linux/nvhost.h>
35 #include <linux/nvmap.h>
36 #include <mach/irqs.h>
37 #include <mach/iomap.h>
38 #include <mach/dc.h>
39 #include <mach/fb.h>
40 #include <mach/smmu.h>
41 #include <mach/gpio-tegra.h>
42
43 #include "board.h"
44 #include "clock.h"
45 #include "dvfs.h"
46 #include "board-cardhu.h"
47 #include "devices.h"
48 #include "gpio-names.h"
49 #include "tegra3_host1x_devices.h"
50
51 #define DC_CTRL_MODE    TEGRA_DC_OUT_ONE_SHOT_MODE
52
53 #define AVDD_LCD PMU_TCA6416_GPIO_PORT17
54 #define DSI_PANEL_RESET 1
55
56 /* Select LVDS panel resolution. 13X7 is default */
57 #define PM313_LVDS_PANEL_19X12                  1
58 #define PM313_LVDS_PANEL_BPP                    0 /* 0:24bpp, 1:18bpp */
59
60 /* PM313 display board specific pins */
61 #define pm313_R_FDE                     TEGRA_GPIO_PW0
62 #define pm313_R_FB                      TEGRA_GPIO_PN4
63 #define pm313_MODE0                     TEGRA_GPIO_PZ4
64 #define pm313_MODE1                     TEGRA_GPIO_PW1
65 #define pm313_BPP                       TEGRA_GPIO_PN6 /* 0:24bpp, 1:18bpp */
66 #define pm313_lvds_shutdown             TEGRA_GPIO_PH1
67
68 /* E1506 display board pins */
69 #define e1506_lcd_te            TEGRA_GPIO_PJ1
70 #define e1506_dsi_vddio         TEGRA_GPIO_PH1
71 #define e1506_dsia_bl_pwm       TEGRA_GPIO_PH0
72 #define e1506_panel_enb         TEGRA_GPIO_PW1
73 #define e1506_bl_enb            TEGRA_GPIO_PH2
74
75 /* E1247 reworked for pm269 pins */
76 #define e1247_pm269_lvds_shutdown       TEGRA_GPIO_PN6
77
78 /* E1247 cardhu default display board pins */
79 #define cardhu_lvds_shutdown            TEGRA_GPIO_PL2
80
81 /* common pins( backlight ) for all display boards */
82 #define cardhu_bl_enb                   TEGRA_GPIO_PH2
83 #define cardhu_bl_pwm                   TEGRA_GPIO_PH0
84 #define cardhu_hdmi_hpd                 TEGRA_GPIO_PN7
85
86 /* common dsi panel pins */
87 #define cardhu_dsia_bl_enb              TEGRA_GPIO_PW1
88 #define cardhu_dsib_bl_enb              TEGRA_GPIO_PW0
89 #define cardhu_dsi_pnl_reset            TEGRA_GPIO_PD2
90 #define cardhu_dsi_219_pnl_reset        TEGRA_GPIO_PW0
91
92 #ifdef CONFIG_TEGRA_DC
93 static struct regulator *cardhu_hdmi_reg = NULL;
94 static struct regulator *cardhu_hdmi_pll = NULL;
95 static struct regulator *cardhu_hdmi_vddio = NULL;
96 #endif
97
98 static atomic_t sd_brightness = ATOMIC_INIT(255);
99
100 static struct regulator *cardhu_dsi_reg = NULL;
101 static struct regulator *cardhu_lvds_reg = NULL;
102 static struct regulator *cardhu_lvds_vdd_bl = NULL;
103 static struct regulator *cardhu_lvds_vdd_panel = NULL;
104
105 static struct board_info board_info;
106 static struct board_info display_board_info;
107
108 static tegra_dc_bl_output cardhu_bl_output_measured = {
109         0, 1, 2, 3, 4, 5, 6, 7,
110         8, 9, 10, 11, 12, 13, 14, 15,
111         16, 17, 18, 19, 20, 21, 22, 23,
112         24, 25, 26, 27, 28, 29, 30, 31,
113         32, 33, 34, 35, 36, 37, 38, 39,
114         40, 41, 42, 43, 44, 45, 46, 47,
115         48, 49, 49, 50, 51, 52, 53, 54,
116         55, 56, 57, 58, 59, 60, 61, 62,
117         63, 64, 65, 66, 67, 68, 69, 70,
118         70, 72, 73, 74, 75, 76, 77, 78,
119         79, 80, 81, 82, 83, 84, 85, 86,
120         87, 88, 89, 90, 91, 92, 93, 94,
121         95, 96, 97, 98, 99, 100, 101, 102,
122         103, 104, 105, 106, 107, 108, 110, 111,
123         112, 113, 114, 115, 116, 117, 118, 119,
124         120, 121, 122, 123, 124, 124, 125, 126,
125         127, 128, 129, 130, 131, 132, 133, 133,
126         134, 135, 136, 137, 138, 139, 140, 141,
127         142, 143, 144, 145, 146, 147, 148, 148,
128         149, 150, 151, 152, 153, 154, 155, 156,
129         157, 158, 159, 160, 161, 162, 163, 164,
130         165, 166, 167, 168, 169, 170, 171, 172,
131         173, 174, 175, 176, 177, 179, 180, 181,
132         182, 184, 185, 186, 187, 188, 189, 190,
133         191, 192, 193, 194, 195, 196, 197, 198,
134         199, 200, 201, 202, 203, 204, 205, 206,
135         207, 208, 209, 211, 212, 213, 214, 215,
136         216, 217, 218, 219, 220, 221, 222, 223,
137         224, 225, 226, 227, 228, 229, 230, 231,
138         232, 233, 234, 235, 236, 237, 238, 239,
139         240, 241, 242, 243, 244, 245, 246, 247,
140         248, 249, 250, 251, 252, 253, 254, 255
141 };
142
143 static p_tegra_dc_bl_output bl_output = cardhu_bl_output_measured;
144
145 static bool kernel_1st_panel_init = true;
146 static bool is_panel_218;
147 static bool is_panel_219;
148 static bool is_panel_1506;
149
150 static bool is_dsi_panel(void)
151 {
152         return is_panel_218 || is_panel_219 || is_panel_1506;
153 }
154
155 static int cardhu_backlight_init(struct device *dev)
156 {
157         int ret = 0;
158
159         if (WARN_ON(ARRAY_SIZE(cardhu_bl_output_measured) != 256))
160                 pr_err("bl_output array does not have 256 elements\n");
161
162         if (!is_dsi_panel()) {
163                 ret = gpio_request(cardhu_bl_enb, "backlight_enb");
164                 if (ret < 0)
165                         return ret;
166
167                 ret = gpio_direction_output(cardhu_bl_enb, 1);
168                 if (ret < 0)
169                         gpio_free(cardhu_bl_enb);
170         } else if (is_panel_218) {
171                 /* Enable back light for DSIa panel */
172                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
173                 if (ret < 0)
174                         return ret;
175
176                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
177                 if (ret < 0)
178                         gpio_free(cardhu_dsia_bl_enb);
179
180                 /* Enable back light for DSIb panel */
181                 ret = gpio_request(cardhu_dsib_bl_enb, "dsib_bl_enable");
182                 if (ret < 0)
183                         return ret;
184
185                 ret = gpio_direction_output(cardhu_dsib_bl_enb, 1);
186                 if (ret < 0)
187                         gpio_free(cardhu_dsib_bl_enb);
188         } else if (is_panel_219) {
189                 /* Enable back light for DSIa panel */
190                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
191                 if (ret < 0)
192                         return ret;
193
194                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
195                 if (ret < 0)
196                         gpio_free(cardhu_dsia_bl_enb);
197         }
198
199         return ret;
200 };
201
202 static void cardhu_backlight_exit(struct device *dev)
203 {
204         if (!is_dsi_panel()) {
205                 /* int ret; */
206                 /*ret = gpio_request(cardhu_bl_enb, "backlight_enb");*/
207                 gpio_set_value(cardhu_bl_enb, 0);
208                 gpio_free(cardhu_bl_enb);
209         } else if (is_panel_218) {
210                 /* Disable back light for DSIa panel */
211                 gpio_set_value(cardhu_dsia_bl_enb, 0);
212                 gpio_free(cardhu_dsia_bl_enb);
213
214                 /* Disable back light for DSIb panel */
215                 gpio_set_value(cardhu_dsib_bl_enb, 0);
216                 gpio_free(cardhu_dsib_bl_enb);
217
218                 gpio_set_value(cardhu_lvds_shutdown, 1);
219                 mdelay(20);
220         } else if (is_panel_219) {
221                 /* Disable back light for DSIa panel */
222                 gpio_set_value(cardhu_dsia_bl_enb, 0);
223                 gpio_free(cardhu_dsia_bl_enb);
224
225                 gpio_set_value(cardhu_lvds_shutdown, 1);
226                 mdelay(20);
227         }
228 }
229
230 static int cardhu_backlight_notify(struct device *unused, int brightness)
231 {
232         int cur_sd_brightness = atomic_read(&sd_brightness);
233
234         if (!is_dsi_panel()) {
235                 /* Set the backlight GPIO pin mode to 'backlight_enable' */
236                 gpio_set_value(cardhu_bl_enb, !!brightness);
237         } else if (is_panel_218) {
238                 /* DSIa */
239                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
240
241                 /* DSIb */
242                 gpio_set_value(cardhu_dsib_bl_enb, !!brightness);
243         } else if (is_panel_219) {
244                 /* DSIa */
245                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
246         } else if (is_panel_1506) {
247                 /* DSIa */
248                 gpio_set_value(e1506_bl_enb, !!brightness);
249         }
250
251         /* SD brightness is a percentage, 8-bit value. */
252         brightness = (brightness * cur_sd_brightness) / 255;
253
254         /* Apply any backlight response curve */
255         if (brightness > 255) {
256                 pr_info("Error: Brightness > 255!\n");
257         } else {
258                 /* This value depends on the panel.
259                   Current 19X12 panel with PM313 gets
260                   full brightness when the output is 0. */
261                 if (display_board_info.board_id == BOARD_DISPLAY_PM313)
262                         brightness = 255 - bl_output[brightness];
263                 else
264                         brightness = bl_output[brightness];
265         }
266
267         return brightness;
268 }
269
270 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info);
271
272 static struct platform_pwm_backlight_data cardhu_backlight_data = {
273         .pwm_id         = 0,
274         .max_brightness = 255,
275         .dft_brightness = 224,
276         .pwm_period_ns  = 1000000,
277         .init           = cardhu_backlight_init,
278         .exit           = cardhu_backlight_exit,
279         .notify         = cardhu_backlight_notify,
280         /* Only toggle backlight on fb blank notifications for disp1 */
281         .check_fb       = cardhu_disp1_check_fb,
282 };
283
284 static struct platform_device cardhu_backlight_device = {
285         .name   = "pwm-backlight",
286         .id     = -1,
287         .dev    = {
288                 .platform_data = &cardhu_backlight_data,
289         },
290 };
291
292 static int cardhu_panel_enable(void)
293 {
294         if (cardhu_lvds_reg == NULL) {
295                 cardhu_lvds_reg = regulator_get(NULL, "vdd_lvds");
296                 if (WARN_ON(IS_ERR(cardhu_lvds_reg)))
297                         pr_err("%s: couldn't get regulator vdd_lvds: %ld\n",
298                                 __func__, PTR_ERR(cardhu_lvds_reg));
299                 else
300                         regulator_enable(cardhu_lvds_reg);
301         }
302
303         if (cardhu_lvds_vdd_bl == NULL) {
304                 cardhu_lvds_vdd_bl = regulator_get(NULL, "vdd_backlight");
305                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_bl)))
306                         pr_err("%s: couldn't get regulator vdd_backlight: %ld\n",
307                                 __func__, PTR_ERR(cardhu_lvds_vdd_bl));
308                 else
309                         regulator_enable(cardhu_lvds_vdd_bl);
310         }
311
312         if (cardhu_lvds_vdd_panel == NULL) {
313                 cardhu_lvds_vdd_panel = regulator_get(NULL, "vdd_lcd_panel");
314                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_panel)))
315                         pr_err("%s: couldn't get regulator vdd_lcd_panel: %ld\n",
316                                 __func__, PTR_ERR(cardhu_lvds_vdd_panel));
317                 else
318                         regulator_enable(cardhu_lvds_vdd_panel);
319         }
320
321         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
322                 /* lvds configuration */
323                 gpio_set_value(pm313_R_FDE, 1);
324                 gpio_set_value(pm313_R_FB, 1);
325                 gpio_set_value(pm313_MODE0, 1);
326                 gpio_set_value(pm313_MODE1, 0);
327                 gpio_set_value(pm313_BPP, PM313_LVDS_PANEL_BPP);
328
329                 /* FIXME : it may require more or less delay for latching
330                   values correctly before enabling RGB2LVDS */
331                 mdelay(100);
332                 gpio_set_value(pm313_lvds_shutdown, 1);
333         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
334                         board_info.board_id == BOARD_PM269) ||
335                         (board_info.board_id == BOARD_E1257) ||
336                         (board_info.board_id == BOARD_PM305) ||
337                         (board_info.board_id == BOARD_PM311))
338                 gpio_set_value(e1247_pm269_lvds_shutdown, 1);
339         else
340                 gpio_set_value(cardhu_lvds_shutdown, 1);
341
342         return 0;
343 }
344
345 static int cardhu_panel_disable(void)
346 {
347         regulator_disable(cardhu_lvds_reg);
348         regulator_put(cardhu_lvds_reg);
349         cardhu_lvds_reg = NULL;
350
351         regulator_disable(cardhu_lvds_vdd_bl);
352         regulator_put(cardhu_lvds_vdd_bl);
353         cardhu_lvds_vdd_bl = NULL;
354
355         regulator_disable(cardhu_lvds_vdd_panel);
356         regulator_put(cardhu_lvds_vdd_panel);
357
358         cardhu_lvds_vdd_panel= NULL;
359
360         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
361                 gpio_set_value(pm313_lvds_shutdown, 0);
362         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
363                         board_info.board_id == BOARD_PM269) ||
364                         (board_info.board_id == BOARD_E1257) ||
365                         (board_info.board_id == BOARD_PM305) ||
366                         (board_info.board_id == BOARD_PM311)) {
367                 gpio_set_value(e1247_pm269_lvds_shutdown, 0);
368         } else {
369                 gpio_set_value(cardhu_lvds_shutdown, 0);
370         }
371         return 0;
372 }
373
374 #ifdef CONFIG_TEGRA_DC
375 static int cardhu_hdmi_vddio_enable(void)
376 {
377         int ret;
378         if (!cardhu_hdmi_vddio) {
379                 cardhu_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
380                 if (IS_ERR_OR_NULL(cardhu_hdmi_vddio)) {
381                         ret = PTR_ERR(cardhu_hdmi_vddio);
382                         pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
383                         cardhu_hdmi_vddio = NULL;
384                         return ret;
385                 }
386         }
387         ret = regulator_enable(cardhu_hdmi_vddio);
388         if (ret < 0) {
389                 pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
390                 regulator_put(cardhu_hdmi_vddio);
391                 cardhu_hdmi_vddio = NULL;
392                 return ret;
393         }
394         return ret;
395 }
396
397 static int cardhu_hdmi_vddio_disable(void)
398 {
399         if (cardhu_hdmi_vddio) {
400                 regulator_disable(cardhu_hdmi_vddio);
401                 regulator_put(cardhu_hdmi_vddio);
402                 cardhu_hdmi_vddio = NULL;
403         }
404         return 0;
405 }
406
407 static int cardhu_hdmi_enable(void)
408 {
409         int ret;
410         if (!cardhu_hdmi_reg) {
411                 cardhu_hdmi_reg = regulator_get(NULL, "avdd_hdmi");
412                 if (IS_ERR_OR_NULL(cardhu_hdmi_reg)) {
413                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
414                         cardhu_hdmi_reg = NULL;
415                         return PTR_ERR(cardhu_hdmi_reg);
416                 }
417         }
418         ret = regulator_enable(cardhu_hdmi_reg);
419         if (ret < 0) {
420                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
421                 return ret;
422         }
423         if (!cardhu_hdmi_pll) {
424                 cardhu_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll");
425                 if (IS_ERR_OR_NULL(cardhu_hdmi_pll)) {
426                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
427                         cardhu_hdmi_pll = NULL;
428                         regulator_put(cardhu_hdmi_reg);
429                         cardhu_hdmi_reg = NULL;
430                         return PTR_ERR(cardhu_hdmi_pll);
431                 }
432         }
433         ret = regulator_enable(cardhu_hdmi_pll);
434         if (ret < 0) {
435                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
436                 return ret;
437         }
438         return 0;
439 }
440
441 static int cardhu_hdmi_disable(void)
442 {
443         regulator_disable(cardhu_hdmi_reg);
444         regulator_put(cardhu_hdmi_reg);
445         cardhu_hdmi_reg = NULL;
446
447         regulator_disable(cardhu_hdmi_pll);
448         regulator_put(cardhu_hdmi_pll);
449         cardhu_hdmi_pll = NULL;
450         return 0;
451 }
452
453 static struct resource cardhu_disp1_resources[] = {
454         {
455                 .name   = "irq",
456                 .start  = INT_DISPLAY_GENERAL,
457                 .end    = INT_DISPLAY_GENERAL,
458                 .flags  = IORESOURCE_IRQ,
459         },
460         {
461                 .name   = "regs",
462                 .start  = TEGRA_DISPLAY_BASE,
463                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
464                 .flags  = IORESOURCE_MEM,
465         },
466         {
467                 .name   = "fbmem",
468                 .start  = 0,    /* Filled in by cardhu_panel_init() */
469                 .end    = 0,    /* Filled in by cardhu_panel_init() */
470                 .flags  = IORESOURCE_MEM,
471         },
472 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
473         {
474                 .name   = "dsi_regs",
475                 .start  = TEGRA_DSIB_BASE,
476                 .end    = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1,
477                 .flags  = IORESOURCE_MEM,
478         },
479 #else
480         {
481                 .name   = "dsi_regs",
482                 .start  = TEGRA_DSI_BASE,
483                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
484                 .flags  = IORESOURCE_MEM,
485         },
486 #endif
487 };
488
489 static struct resource cardhu_disp2_resources[] = {
490         {
491                 .name   = "irq",
492                 .start  = INT_DISPLAY_B_GENERAL,
493                 .end    = INT_DISPLAY_B_GENERAL,
494                 .flags  = IORESOURCE_IRQ,
495         },
496         {
497                 .name   = "regs",
498                 .start  = TEGRA_DISPLAY2_BASE,
499                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
500                 .flags  = IORESOURCE_MEM,
501         },
502         {
503                 .name   = "fbmem",
504                 .flags  = IORESOURCE_MEM,
505                 .start  = 0,
506                 .end    = 0,
507         },
508         {
509                 .name   = "hdmi_regs",
510                 .start  = TEGRA_HDMI_BASE,
511                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
512                 .flags  = IORESOURCE_MEM,
513         },
514 };
515 #endif
516
517 static struct tegra_dc_mode panel_19X12_modes[] = {
518         {
519                 .pclk = 154000000,
520                 .h_ref_to_sync = 11,
521                 .v_ref_to_sync = 1,
522                 .h_sync_width = 32,
523                 .v_sync_width = 6,
524                 .h_back_porch = 80,
525                 .v_back_porch = 26,
526                 .h_active = 1920,
527                 .v_active = 1200,
528                 .h_front_porch = 48,
529                 .v_front_porch = 3,
530         },
531 };
532
533 static struct tegra_dc_mode cardhu_panel_modes[] = {
534         {
535                 /* 1366x768@60Hz */
536                 .pclk = 74180000,
537                 .h_ref_to_sync = 1,
538                 .v_ref_to_sync = 1,
539                 .h_sync_width = 30,
540                 .v_sync_width = 5,
541                 .h_back_porch = 52,
542                 .v_back_porch = 20,
543                 .h_active = 1366,
544                 .v_active = 768,
545                 .h_front_porch = 64,
546                 .v_front_porch = 25,
547         },
548         {
549                 /* 1366x768@50Hz */
550                 .pclk = 74180000,
551                 .h_ref_to_sync = 1,
552                 .v_ref_to_sync = 1,
553                 .h_sync_width = 30,
554                 .v_sync_width = 5,
555                 .h_back_porch = 56,
556                 .v_back_porch = 80,
557                 .h_active = 1366,
558                 .v_active = 768,
559                 .h_front_porch = 64,
560                 .v_front_porch = 125,
561         },
562         {
563                 /* 1366x768@48 */
564                 .pclk = 74180000,
565                 .h_ref_to_sync = 1,
566                 .v_ref_to_sync = 1,
567                 .h_sync_width = 30,
568                 .v_sync_width = 5,
569                 .h_back_porch = 52,
570                 .v_back_porch = 98,
571                 .h_active = 1366,
572                 .v_active = 768,
573                 .h_front_porch = 64,
574                 .v_front_porch = 152,
575         },
576 };
577
578 static struct tegra_dc_mode cardhu_panel_modes_55hz[] = {
579         {
580                 /* 1366x768p 55Hz */
581                 .pclk = 68000000,
582                 .h_ref_to_sync = 0,
583                 .v_ref_to_sync = 12,
584                 .h_sync_width = 30,
585                 .v_sync_width = 5,
586                 .h_back_porch = 52,
587                 .v_back_porch = 20,
588                 .h_active = 1366,
589                 .v_active = 768,
590                 .h_front_porch = 64,
591                 .v_front_porch = 25,
592         },
593 };
594
595 static struct tegra_dc_sd_settings cardhu_sd_settings = {
596         .enable = 1, /* enabled by default. */
597         .use_auto_pwm = false,
598         .hw_update_delay = 0,
599         .bin_width = -1,
600         .aggressiveness = 1,
601         .phase_in_adjustments = true,
602         .use_vid_luma = false,
603         /* Default video coefficients */
604         .coeff = {5, 9, 2},
605         .fc = {0, 0},
606         /* Immediate backlight changes */
607         .blp = {1024, 255},
608         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
609         /* Default BL TF */
610         .bltf = {
611                         {
612                                 {57, 65, 74, 83},
613                                 {93, 103, 114, 126},
614                                 {138, 151, 165, 179},
615                                 {194, 209, 225, 242},
616                         },
617                         {
618                                 {58, 66, 75, 84},
619                                 {94, 105, 116, 127},
620                                 {140, 153, 166, 181},
621                                 {196, 211, 227, 244},
622                         },
623                         {
624                                 {60, 68, 77, 87},
625                                 {97, 107, 119, 130},
626                                 {143, 156, 170, 184},
627                                 {199, 215, 231, 248},
628                         },
629                         {
630                                 {64, 73, 82, 91},
631                                 {102, 113, 124, 137},
632                                 {149, 163, 177, 192},
633                                 {207, 223, 240, 255},
634                         },
635                 },
636         /* Default LUT */
637         .lut = {
638                         {
639                                 {250, 250, 250},
640                                 {194, 194, 194},
641                                 {149, 149, 149},
642                                 {113, 113, 113},
643                                 {82, 82, 82},
644                                 {56, 56, 56},
645                                 {34, 34, 34},
646                                 {15, 15, 15},
647                                 {0, 0, 0},
648                         },
649                         {
650                                 {246, 246, 246},
651                                 {191, 191, 191},
652                                 {147, 147, 147},
653                                 {111, 111, 111},
654                                 {80, 80, 80},
655                                 {55, 55, 55},
656                                 {33, 33, 33},
657                                 {14, 14, 14},
658                                 {0, 0, 0},
659                         },
660                         {
661                                 {239, 239, 239},
662                                 {185, 185, 185},
663                                 {142, 142, 142},
664                                 {107, 107, 107},
665                                 {77, 77, 77},
666                                 {52, 52, 52},
667                                 {30, 30, 30},
668                                 {12, 12, 12},
669                                 {0, 0, 0},
670                         },
671                         {
672                                 {224, 224, 224},
673                                 {173, 173, 173},
674                                 {133, 133, 133},
675                                 {99, 99, 99},
676                                 {70, 70, 70},
677                                 {46, 46, 46},
678                                 {25, 25, 25},
679                                 {7, 7, 7},
680                                 {0, 0, 0},
681                         },
682                 },
683         .sd_brightness = &sd_brightness,
684         .bl_device = &cardhu_backlight_device,
685 };
686
687 #ifdef CONFIG_TEGRA_DC
688 static struct tegra_fb_data cardhu_fb_data = {
689         .win            = 0,
690         .xres           = 1366,
691         .yres           = 768,
692         .bits_per_pixel = 32,
693         .flags          = TEGRA_FB_FLIP_ON_PROBE,
694 };
695
696 static struct tegra_fb_data cardhu_hdmi_fb_data = {
697         .win            = 0,
698         .xres           = 640,
699         .yres           = 480,
700         .bits_per_pixel = 32,
701         .flags          = TEGRA_FB_FLIP_ON_PROBE,
702 };
703
704 static struct tegra_dc_out cardhu_disp2_out = {
705         .type           = TEGRA_DC_OUT_HDMI,
706         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
707         .parent_clk     = "pll_d2_out0",
708
709         .dcc_bus        = 3,
710         .hotplug_gpio   = cardhu_hdmi_hpd,
711
712         .max_pixclock   = KHZ2PICOS(148500),
713
714         .align          = TEGRA_DC_ALIGN_MSB,
715         .order          = TEGRA_DC_ORDER_RED_BLUE,
716
717         .enable         = cardhu_hdmi_enable,
718         .disable        = cardhu_hdmi_disable,
719
720         .postsuspend    = cardhu_hdmi_vddio_disable,
721         .hotplug_init   = cardhu_hdmi_vddio_enable,
722 };
723
724 static struct tegra_dc_platform_data cardhu_disp2_pdata = {
725         .flags          = TEGRA_DC_FLAG_ENABLED,
726         .default_out    = &cardhu_disp2_out,
727         .fb             = &cardhu_hdmi_fb_data,
728         .emc_clk_rate   = 300000000,
729 };
730 #endif
731
732 static int cardhu_dsi_panel_enable(void)
733 {
734         int ret;
735
736         if (cardhu_dsi_reg == NULL) {
737                 cardhu_dsi_reg = regulator_get(NULL, "avdd_dsi_csi");
738                 if (IS_ERR_OR_NULL(cardhu_dsi_reg)) {
739                         pr_err("dsi: Could not get regulator avdd_dsi_csi\n");
740                         cardhu_dsi_reg = NULL;
741                         return PTR_ERR(cardhu_dsi_reg);
742                 }
743         }
744
745         regulator_enable(cardhu_dsi_reg);
746
747         if (!is_panel_1506) {
748                 ret = gpio_request(AVDD_LCD, "avdd_lcd");
749                 if (ret < 0)
750                         gpio_free(AVDD_LCD);
751                 ret = gpio_direction_output(AVDD_LCD, 1);
752                 if (ret < 0)
753                         gpio_free(AVDD_LCD);
754         }
755
756         if (is_panel_219) {
757                 ret = gpio_request(cardhu_bl_pwm, "bl_pwm");
758                 if (ret < 0)
759                         return ret;
760                 ret = gpio_direction_output(cardhu_bl_pwm, 0);
761                 if (ret < 0) {
762                         gpio_free(cardhu_bl_pwm);
763                         return ret;
764                 }
765
766                 ret = gpio_request(cardhu_bl_enb, "bl_enb");
767                 if (ret < 0)
768                         return ret;
769                 ret = gpio_direction_output(cardhu_bl_enb, 0);
770                 if (ret < 0) {
771                         gpio_free(cardhu_bl_enb);
772                         return ret;
773                 }
774
775                 gpio_set_value(cardhu_lvds_shutdown, 1);
776                 mdelay(20);
777                 gpio_set_value(cardhu_bl_pwm, 1);
778                 mdelay(10);
779                 gpio_set_value(cardhu_bl_enb, 1);
780                 mdelay(15);
781         } else if (is_panel_1506) {
782                 ret = gpio_request(e1506_dsi_vddio, "e1506_dsi_vddio");
783                 if (ret < 0)
784                         return ret;
785                 ret = gpio_direction_output(e1506_dsi_vddio, 0);
786                 if (ret < 0) {
787                         gpio_free(e1506_dsi_vddio);
788                         return ret;
789                 }
790
791                 ret = gpio_request(e1506_panel_enb, "e1506_panel_enb");
792                 if (ret < 0)
793                         return ret;
794                 ret = gpio_direction_output(e1506_panel_enb, 0);
795                 if (ret < 0) {
796                         gpio_free(e1506_panel_enb);
797                         return ret;
798                 }
799
800                 ret = gpio_request(e1506_bl_enb, "e1506_bl_enb");
801                 if (ret < 0)
802                         return ret;
803                 ret = gpio_direction_output(e1506_bl_enb, 0);
804                 if (ret < 0) {
805                         gpio_free(e1506_bl_enb);
806                         return ret;
807                 }
808
809                 gpio_set_value(e1506_dsi_vddio, 1);
810                 mdelay(10);
811                 gpio_set_value(e1506_panel_enb, 1);
812                 mdelay(10);
813                 gpio_set_value(e1506_bl_enb, 1);
814                 mdelay(15);
815         }
816
817 #if DSI_PANEL_RESET
818         if (is_panel_218) {
819                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
820                 if (ret < 0)
821                         return ret;
822
823                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
824                 if (ret < 0) {
825                         gpio_free(cardhu_dsi_pnl_reset);
826                         return ret;
827                 }
828
829                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
830                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
831                 mdelay(2);
832                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
833                 mdelay(2);
834         } else if (is_panel_219) {
835                 ret = gpio_request(cardhu_dsi_219_pnl_reset, "dsi_panel_reset");
836                 if (ret < 0)
837                         return ret;
838                 ret = gpio_direction_output(cardhu_dsi_219_pnl_reset, 0);
839                 if (ret < 0) {
840                         gpio_free(cardhu_dsi_219_pnl_reset);
841                         return ret;
842                 }
843
844                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
845                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
846                 mdelay(10);
847                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
848                 mdelay(10);
849                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
850                 mdelay(15);
851         } else if (is_panel_1506) {
852                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
853                 if (ret < 0)
854                         return ret;
855                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
856                 if (ret < 0) {
857                         gpio_free(cardhu_dsi_pnl_reset);
858                         return ret;
859                 }
860
861                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
862                 mdelay(1);
863                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
864                 mdelay(1);
865                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
866                 mdelay(20);
867         }
868 #endif
869
870         return 0;
871 }
872
873 static int cardhu_dsi_panel_disable(void)
874 {
875         int err;
876
877         err = 0;
878
879         if (is_panel_219) {
880                 gpio_free(cardhu_dsi_219_pnl_reset);
881                 gpio_free(cardhu_bl_enb);
882                 gpio_free(cardhu_bl_pwm);
883                 gpio_free(cardhu_lvds_shutdown);
884         } else if (is_panel_218) {
885                 gpio_free(cardhu_dsi_pnl_reset);
886         } else if (is_panel_1506) {
887                 tegra_gpio_disable(e1506_bl_enb);
888                 gpio_free(e1506_bl_enb);
889                 tegra_gpio_disable(e1506_panel_enb);
890                 gpio_free(e1506_panel_enb);
891                 tegra_gpio_disable(e1506_dsi_vddio);
892                 gpio_free(e1506_dsi_vddio);
893                 if (kernel_1st_panel_init != true) {
894                         tegra_gpio_disable(cardhu_dsi_pnl_reset);
895                         gpio_free(cardhu_dsi_pnl_reset);
896                 } else
897                         kernel_1st_panel_init = false;
898         }
899         return err;
900 }
901
902 static int cardhu_dsi_panel_postsuspend(void)
903 {
904         int err;
905
906         err = 0;
907         printk(KERN_INFO "DSI panel postsuspend\n");
908
909         if (cardhu_dsi_reg) {
910                 err = regulator_disable(cardhu_dsi_reg);
911                 if (err < 0)
912                         printk(KERN_ERR
913                         "DSI regulator avdd_dsi_csi disable failed\n");
914                 regulator_put(cardhu_dsi_reg);
915                 cardhu_dsi_reg = NULL;
916         }
917
918         if (is_panel_218)
919                 gpio_free(AVDD_LCD);
920
921         return err;
922 }
923
924 static struct tegra_dsi_cmd dsi_init_cmd[] = {
925         DSI_CMD_SHORT(0x05, 0x11, 0x00),
926         DSI_DLY_MS(150),
927 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
928         DSI_CMD_SHORT(0x15, 0x35, 0x00),
929 #endif
930         DSI_CMD_SHORT(0x05, 0x29, 0x00),
931         DSI_DLY_MS(20),
932 };
933
934 u8 password_array[] = {0xb9, 0xff, 0x83, 0x92};
935
936 static struct tegra_dsi_cmd dsi_init_cmd_1506[] = {
937         DSI_CMD_SHORT(0x05, 0x11, 0x00),
938         DSI_DLY_MS(150),
939         DSI_CMD_LONG(0x39, password_array),
940         DSI_DLY_MS(10),
941         DSI_CMD_SHORT(0x15, 0xd4, 0x0c),
942         DSI_DLY_MS(10),
943         DSI_CMD_SHORT(0x15, 0xba, 0x11),
944         DSI_DLY_MS(10),
945 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
946         DSI_CMD_SHORT(0x15, 0x35, 0x00),
947 #endif
948         DSI_CMD_SHORT(0x05, 0x29, 0x00),
949         DSI_DLY_MS(20),
950 };
951
952 static struct tegra_dsi_cmd dsi_early_suspend_cmd[] = {
953         DSI_CMD_SHORT(0x05, 0x28, 0x00),
954         DSI_DLY_MS(20),
955 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
956         DSI_CMD_SHORT(0x05, 0x34, 0x00),
957 #endif
958 };
959
960 static struct tegra_dsi_cmd dsi_late_resume_cmd[] = {
961 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
962         DSI_CMD_SHORT(0x15, 0x35, 0x00),
963 #endif
964         DSI_CMD_SHORT(0x05, 0x29, 0x00),
965         DSI_DLY_MS(20),
966 };
967
968 static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
969         DSI_CMD_SHORT(0x05, 0x28, 0x00),
970         DSI_DLY_MS(120),
971 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
972         DSI_CMD_SHORT(0x05, 0x34, 0x00),
973 #endif
974         DSI_CMD_SHORT(0x05, 0x10, 0x00),
975         DSI_DLY_MS(5),
976 };
977
978 struct tegra_dsi_out cardhu_dsi = {
979         .n_data_lanes = 2,
980         .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
981
982 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
983         /*
984          * The one-shot frame time must be shorter than the time between TE.
985          * Increasing refresh_rate will result in a decrease in the frame time
986          * for one-shot. rated_refresh_rate is only an approximation of the
987          * TE rate, and is only used to report refresh rate to upper layers.
988          */
989         .refresh_rate = 66,
990         .rated_refresh_rate = 60,
991 #else
992         .refresh_rate = 60,
993 #endif
994         .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
995
996         .panel_has_frame_buffer = true,
997 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
998         .dsi_instance = 1,
999 #else
1000         .dsi_instance = 0,
1001 #endif
1002         .panel_reset = DSI_PANEL_RESET,
1003         .power_saving_suspend = true,
1004
1005         .n_early_suspend_cmd = ARRAY_SIZE(dsi_early_suspend_cmd),
1006         .dsi_early_suspend_cmd = dsi_early_suspend_cmd,
1007
1008         .n_late_resume_cmd = ARRAY_SIZE(dsi_late_resume_cmd),
1009         .dsi_late_resume_cmd = dsi_late_resume_cmd,
1010
1011         .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
1012         .dsi_suspend_cmd = dsi_suspend_cmd,
1013
1014         .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
1015         .lp_cmd_mode_freq_khz = 430000,
1016 };
1017
1018 static struct tegra_dc_mode cardhu_dsi_modes_219[] = {
1019         {
1020                 .pclk = 10000000,
1021                 .h_ref_to_sync = 4,
1022                 .v_ref_to_sync = 1,
1023                 .h_sync_width = 16,
1024                 .v_sync_width = 1,
1025                 .h_back_porch = 32,
1026                 .v_back_porch = 1,
1027                 .h_active = 540,
1028                 .v_active = 960,
1029                 .h_front_porch = 32,
1030                 .v_front_porch = 2,
1031         },
1032 };
1033
1034 static struct tegra_dc_mode cardhu_dsi_modes_218[] = {
1035         {
1036                 .pclk = 323000000,
1037                 .h_ref_to_sync = 11,
1038                 .v_ref_to_sync = 1,
1039                 .h_sync_width = 16,
1040                 .v_sync_width = 4,
1041                 .h_back_porch = 16,
1042                 .v_back_porch = 4,
1043                 .h_active = 864,
1044                 .v_active = 480,
1045                 .h_front_porch = 16,
1046                 .v_front_porch = 4,
1047         },
1048 };
1049
1050 static struct tegra_dc_mode cardhu_dsi_modes_1506[] = {
1051         {
1052                 .pclk = 61417000,
1053                 .h_ref_to_sync = 2,
1054                 .v_ref_to_sync = 2,
1055                 .h_sync_width = 4,
1056                 .v_sync_width = 4,
1057                 .h_back_porch = 100,
1058                 .v_back_porch = 14,
1059                 .h_active = 720,
1060                 .v_active = 1280,
1061                 .h_front_porch = 4,
1062                 .v_front_porch = 4,
1063         },
1064 };
1065
1066
1067 static struct tegra_fb_data cardhu_dsi_fb_data = {
1068         .win            = 0,
1069         .bits_per_pixel = 32,
1070         .flags          = TEGRA_FB_FLIP_ON_PROBE,
1071 };
1072
1073 static struct tegra_dc_out cardhu_disp1_out = {
1074         .align          = TEGRA_DC_ALIGN_MSB,
1075         .order          = TEGRA_DC_ORDER_RED_BLUE,
1076         .sd_settings    = &cardhu_sd_settings,
1077         .parent_clk     = "pll_d_out0",
1078
1079 };
1080
1081 #ifdef CONFIG_TEGRA_DC
1082 static struct tegra_dc_platform_data cardhu_disp1_pdata = {
1083         .flags          = TEGRA_DC_FLAG_ENABLED,
1084         .default_out    = &cardhu_disp1_out,
1085         .emc_clk_rate   = 300000000,
1086 };
1087
1088 static struct nvhost_device cardhu_disp1_device = {
1089         .name           = "tegradc",
1090         .id             = 0,
1091         .resource       = cardhu_disp1_resources,
1092         .num_resources  = ARRAY_SIZE(cardhu_disp1_resources),
1093         .dev = {
1094                 .platform_data = &cardhu_disp1_pdata,
1095         },
1096 };
1097
1098 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1099 {
1100         return info->device == &cardhu_disp1_device.dev;
1101 }
1102
1103 static struct nvhost_device cardhu_disp2_device = {
1104         .name           = "tegradc",
1105         .id             = 1,
1106         .resource       = cardhu_disp2_resources,
1107         .num_resources  = ARRAY_SIZE(cardhu_disp2_resources),
1108         .dev = {
1109                 .platform_data = &cardhu_disp2_pdata,
1110         },
1111 };
1112 #else
1113 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1114 {
1115         return 0;
1116 }
1117 #endif
1118
1119 #if defined(CONFIG_TEGRA_NVMAP)
1120 static struct nvmap_platform_carveout cardhu_carveouts[] = {
1121         [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
1122         [1] = {
1123                 .name           = "generic-0",
1124                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
1125                 .base           = 0,    /* Filled in by cardhu_panel_init() */
1126                 .size           = 0,    /* Filled in by cardhu_panel_init() */
1127                 .buddy_size     = SZ_32K,
1128         },
1129 };
1130
1131 static struct nvmap_platform_data cardhu_nvmap_data = {
1132         .carveouts      = cardhu_carveouts,
1133         .nr_carveouts   = ARRAY_SIZE(cardhu_carveouts),
1134 };
1135
1136 static struct platform_device cardhu_nvmap_device = {
1137         .name   = "tegra-nvmap",
1138         .id     = -1,
1139         .dev    = {
1140                 .platform_data = &cardhu_nvmap_data,
1141         },
1142 };
1143 #endif
1144
1145 #if defined(CONFIG_ION_TEGRA)
1146
1147 static struct platform_device tegra_iommu_device = {
1148         .name = "tegra_iommu_device",
1149         .id = -1,
1150         .dev = {
1151                 .platform_data = (void *)((1 << HWGRP_COUNT) - 1),
1152         },
1153 };
1154
1155 static struct ion_platform_data tegra_ion_data = {
1156         .nr = 4,
1157         .heaps = {
1158                 {
1159                         .type = ION_HEAP_TYPE_CARVEOUT,
1160                         .id = TEGRA_ION_HEAP_CARVEOUT,
1161                         .name = "carveout",
1162                         .base = 0,
1163                         .size = 0,
1164                 },
1165                 {
1166                         .type = ION_HEAP_TYPE_CARVEOUT,
1167                         .id = TEGRA_ION_HEAP_IRAM,
1168                         .name = "iram",
1169                         .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
1170                         .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
1171                 },
1172                 {
1173                         .type = ION_HEAP_TYPE_CARVEOUT,
1174                         .id = TEGRA_ION_HEAP_VPR,
1175                         .name = "vpr",
1176                         .base = 0,
1177                         .size = 0,
1178                 },
1179                 {
1180                         .type = ION_HEAP_TYPE_IOMMU,
1181                         .id = TEGRA_ION_HEAP_IOMMU,
1182                         .name = "iommu",
1183                         .base = TEGRA_SMMU_BASE,
1184                         .size = TEGRA_SMMU_SIZE,
1185                         .priv = &tegra_iommu_device.dev,
1186                 },
1187         },
1188 };
1189
1190 static struct platform_device tegra_ion_device = {
1191         .name = "ion-tegra",
1192         .id = -1,
1193         .dev = {
1194                 .platform_data = &tegra_ion_data,
1195         },
1196 };
1197 #endif
1198
1199 static struct platform_device *cardhu_gfx_devices[] __initdata = {
1200 #if defined(CONFIG_TEGRA_NVMAP)
1201         &cardhu_nvmap_device,
1202 #endif
1203 #if defined(CONFIG_ION_TEGRA)
1204         &tegra_ion_device,
1205 #endif
1206         &tegra_pwfm0_device,
1207         &cardhu_backlight_device,
1208 };
1209
1210
1211 #ifdef CONFIG_HAS_EARLYSUSPEND
1212 /* put early_suspend/late_resume handlers here for the display in order
1213  * to keep the code out of the display driver, keeping it closer to upstream
1214  */
1215 struct early_suspend cardhu_panel_early_suspender;
1216
1217 static void cardhu_panel_early_suspend(struct early_suspend *h)
1218 {
1219         /* power down LCD, add use a black screen for HDMI */
1220         if (num_registered_fb > 0)
1221                 fb_blank(registered_fb[0], FB_BLANK_POWERDOWN);
1222         if (num_registered_fb > 1)
1223                 fb_blank(registered_fb[1], FB_BLANK_NORMAL);
1224 }
1225
1226 static void cardhu_panel_late_resume(struct early_suspend *h)
1227 {
1228         unsigned i;
1229         for (i = 0; i < num_registered_fb; i++)
1230                 fb_blank(registered_fb[i], FB_BLANK_UNBLANK);
1231 }
1232 #endif
1233
1234 static void cardhu_panel_preinit(void)
1235 {
1236         if (display_board_info.board_id == BOARD_DISPLAY_E1213)
1237                 is_panel_218 = true;
1238         else if (display_board_info.board_id == BOARD_DISPLAY_E1253)
1239                 is_panel_219 = true;
1240         else if (display_board_info.board_id == BOARD_DISPLAY_E1506)
1241                 is_panel_1506 = true;
1242
1243         if (!is_dsi_panel()) {
1244                 cardhu_disp1_out.parent_clk_backup = "pll_d2_out0";
1245                 cardhu_disp1_out.type = TEGRA_DC_OUT_RGB;
1246                 cardhu_disp1_out.depth = 18;
1247                 cardhu_disp1_out.dither = TEGRA_DC_ORDERED_DITHER;
1248                 cardhu_disp1_out.modes = cardhu_panel_modes;
1249                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes);
1250                 cardhu_disp1_out.enable = cardhu_panel_enable;
1251                 cardhu_disp1_out.disable = cardhu_panel_disable;
1252
1253                 cardhu_disp1_pdata.fb = &cardhu_fb_data;
1254         } else {
1255                 cardhu_disp1_out.flags = DC_CTRL_MODE;
1256                 cardhu_disp1_out.type = TEGRA_DC_OUT_DSI;
1257                 cardhu_disp1_out.dsi = &cardhu_dsi;
1258                 cardhu_disp1_out.enable = cardhu_dsi_panel_enable;
1259                 cardhu_disp1_out.disable = cardhu_dsi_panel_disable;
1260                 cardhu_disp1_out.postsuspend = cardhu_dsi_panel_postsuspend;
1261
1262                 cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd);
1263                 cardhu_dsi.dsi_init_cmd = dsi_init_cmd;
1264
1265                 if (is_panel_218) {
1266                         cardhu_disp1_out.modes  = cardhu_dsi_modes_218;
1267                         cardhu_disp1_out.n_modes =
1268                                 ARRAY_SIZE(cardhu_dsi_modes_218);
1269                         cardhu_dsi_fb_data.xres = 864;
1270                         cardhu_dsi_fb_data.yres = 480;
1271                 } else if (is_panel_219) {
1272                         cardhu_disp1_out.modes  = cardhu_dsi_modes_219;
1273                         cardhu_disp1_out.n_modes =
1274                                 ARRAY_SIZE(cardhu_dsi_modes_219);
1275                         cardhu_dsi_fb_data.xres = 540;
1276                         cardhu_dsi_fb_data.yres = 960;
1277                 } else if (is_panel_1506) {
1278                         cardhu_disp1_out.modes  = cardhu_dsi_modes_1506;
1279                         cardhu_disp1_out.n_modes =
1280                                 ARRAY_SIZE(cardhu_dsi_modes_1506);
1281                         cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd_1506);
1282                         cardhu_dsi.dsi_init_cmd = dsi_init_cmd_1506;
1283                         cardhu_dsi_fb_data.xres = 720;
1284                         cardhu_dsi_fb_data.yres = 1280;
1285                 }
1286
1287                 cardhu_disp1_pdata.fb = &cardhu_dsi_fb_data;
1288         }
1289 }
1290
1291 int __init cardhu_panel_init(void)
1292 {
1293         int err;
1294         struct resource __maybe_unused *res;
1295
1296         tegra_get_board_info(&board_info);
1297         tegra_get_display_board_info(&display_board_info);
1298
1299 #if defined(CONFIG_TEGRA_NVMAP)
1300         cardhu_carveouts[1].base = tegra_carveout_start;
1301         cardhu_carveouts[1].size = tegra_carveout_size;
1302 #endif
1303
1304 #if defined(CONFIG_ION_TEGRA)
1305         tegra_ion_data.heaps[0].base = tegra_carveout_start;
1306         tegra_ion_data.heaps[0].size = tegra_carveout_size;
1307 #endif
1308
1309         cardhu_panel_preinit();
1310         if (is_dsi_panel()) {
1311                 if (is_panel_1506) {
1312                         /*
1313                          * HACK: To be Removed
1314                          */
1315                         int i;
1316                         struct clk *c = tegra_get_clock_by_name("dsia");
1317
1318                         for (i = 0; i < c->dvfs->num_freqs; i++)
1319                                 c->dvfs->freqs[i] = 500000000;
1320                 }
1321                 goto skip_lvds;
1322         }
1323 #if defined(CONFIG_TEGRA_DC)
1324         if (WARN_ON(board_info.board_id == BOARD_E1291 &&
1325                 ((board_info.sku & SKU_TOUCHSCREEN_MECH_FIX) == 0))) {
1326                 /* use 55Hz panel timings to reduce noise on sensitive touch */
1327                 printk("Using cardhu_panel_modes_55hz\n");
1328                 cardhu_disp1_out.parent_clk = "pll_p";
1329                 cardhu_disp1_out.modes = cardhu_panel_modes_55hz;
1330                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes_55hz);
1331         }
1332
1333         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
1334                 /* initialize the values */
1335 #if defined(PM313_LVDS_PANEL_19X12)
1336                 cardhu_disp1_out.modes = panel_19X12_modes;
1337                 cardhu_disp1_out.n_modes = ARRAY_SIZE(panel_19X12_modes);
1338                 cardhu_disp1_out.parent_clk = "pll_d_out0";
1339 #if (PM313_LVDS_PANEL_BPP == 1)
1340                 cardhu_disp1_out.depth = 18;
1341 #else
1342                 cardhu_disp1_out.depth = 24;
1343 #endif
1344                 cardhu_fb_data.xres = 1920;
1345                 cardhu_fb_data.yres = 1200;
1346
1347                 cardhu_disp2_out.parent_clk = "pll_d2_out0";
1348                 cardhu_hdmi_fb_data.xres = 1920;
1349                 cardhu_hdmi_fb_data.yres = 1200;
1350 #endif
1351
1352                 /* lvds configuration */
1353                 err = gpio_request(pm313_R_FDE, "R_FDE");
1354                 err |= gpio_direction_output(pm313_R_FDE, 1);
1355
1356                 err |= gpio_request(pm313_R_FB, "R_FB");
1357                 err |= gpio_direction_output(pm313_R_FB, 1);
1358
1359                 err |= gpio_request(pm313_MODE0, "MODE0");
1360                 err |= gpio_direction_output(pm313_MODE0, 1);
1361
1362                 err |= gpio_request(pm313_MODE1, "MODE1");
1363                 err |= gpio_direction_output(pm313_MODE1, 0);
1364
1365                 err |= gpio_request(pm313_BPP, "BPP");
1366                 err |= gpio_direction_output(pm313_BPP, PM313_LVDS_PANEL_BPP);
1367
1368                 err = gpio_request(pm313_lvds_shutdown, "lvds_shutdown");
1369                 /* free ride provided by bootloader */
1370                 err |= gpio_direction_output(pm313_lvds_shutdown, 1);
1371
1372                 if (err)
1373                         printk(KERN_ERR "ERROR(s) in LVDS configuration\n");
1374         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
1375                                 board_info.board_id == BOARD_PM269) ||
1376                                 (board_info.board_id == BOARD_E1257) ||
1377                                 (board_info.board_id == BOARD_PM305) ||
1378                                 (board_info.board_id == BOARD_PM311)) {
1379                 gpio_request(e1247_pm269_lvds_shutdown, "lvds_shutdown");
1380                 gpio_direction_output(e1247_pm269_lvds_shutdown, 1);
1381         } else {
1382                 gpio_request(cardhu_lvds_shutdown, "lvds_shutdown");
1383                 gpio_direction_output(cardhu_lvds_shutdown, 1);
1384         }
1385 #endif
1386
1387 skip_lvds:
1388         gpio_request(cardhu_hdmi_hpd, "hdmi_hpd");
1389         gpio_direction_input(cardhu_hdmi_hpd);
1390
1391 #if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
1392         tegra_gpio_enable(e1506_lcd_te);
1393         gpio_request(e1506_lcd_te, "lcd_te");
1394         gpio_direction_input(e1506_lcd_te);
1395 #endif
1396
1397 #ifdef CONFIG_HAS_EARLYSUSPEND
1398         cardhu_panel_early_suspender.suspend = cardhu_panel_early_suspend;
1399         cardhu_panel_early_suspender.resume = cardhu_panel_late_resume;
1400         cardhu_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
1401         register_early_suspend(&cardhu_panel_early_suspender);
1402 #endif
1403
1404 #ifdef CONFIG_TEGRA_GRHOST
1405         err = tegra3_register_host1x_devices();
1406         if (err)
1407                 return err;
1408 #endif
1409
1410         err = platform_add_devices(cardhu_gfx_devices,
1411                                 ARRAY_SIZE(cardhu_gfx_devices));
1412
1413 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1414         res = nvhost_get_resource_byname(&cardhu_disp1_device,
1415                                          IORESOURCE_MEM, "fbmem");
1416         res->start = tegra_fb_start;
1417         res->end = tegra_fb_start + tegra_fb_size - 1;
1418 #endif
1419
1420         /* Copy the bootloader fb to the fb. */
1421         tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
1422                                 min(tegra_fb_size, tegra_bootloader_fb_size));
1423
1424 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1425         if (!err)
1426                 err = nvhost_device_register(&cardhu_disp1_device);
1427
1428         res = nvhost_get_resource_byname(&cardhu_disp2_device,
1429                                          IORESOURCE_MEM, "fbmem");
1430         res->start = tegra_fb2_start;
1431         res->end = tegra_fb2_start + tegra_fb2_size - 1;
1432
1433         /* Copy the bootloader fb to the fb2. */
1434         tegra_move_framebuffer(tegra_fb2_start, tegra_bootloader_fb_start,
1435                                 min(tegra_fb2_size, tegra_bootloader_fb_size));
1436
1437         if (!err)
1438                 err = nvhost_device_register(&cardhu_disp2_device);
1439 #endif
1440
1441 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
1442         if (!err)
1443                 err = nvhost_device_register(&nvavp_device);
1444 #endif
1445         return err;
1446 }