arm: tegra: sd: enable sd dpd
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-panel.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu-panel.c
3  *
4  * Copyright (c) 2010-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/delay.h>
22 #include <linux/ion.h>
23 #include <linux/tegra_ion.h>
24 #include <linux/gpio.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/resource.h>
27 #include <asm/mach-types.h>
28 #include <linux/platform_device.h>
29 #include <linux/earlysuspend.h>
30 #include <linux/pwm_backlight.h>
31 #include <asm/atomic.h>
32 #include <linux/nvhost.h>
33 #include <linux/nvmap.h>
34 #include <mach/irqs.h>
35 #include <mach/iomap.h>
36 #include <mach/dc.h>
37 #include <mach/fb.h>
38 #include <mach/smmu.h>
39
40 #include "board.h"
41 #include "board-cardhu.h"
42 #include "devices.h"
43 #include "gpio-names.h"
44 #include "tegra3_host1x_devices.h"
45
46 #define DC_CTRL_MODE    (TEGRA_DC_OUT_ONE_SHOT_MODE | \
47                          TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
48
49 #define AVDD_LCD PMU_TCA6416_GPIO_PORT17
50 #define DSI_PANEL_RESET 1
51
52 /* Select LVDS panel resolution. 13X7 is default */
53 #define PM313_LVDS_PANEL_19X12                  1
54 #define PM313_LVDS_PANEL_BPP                    0 /* 0:24bpp, 1:18bpp */
55
56 /* PM313 display board specific pins */
57 #define pm313_R_FDE                     TEGRA_GPIO_PW0
58 #define pm313_R_FB                      TEGRA_GPIO_PN4
59 #define pm313_MODE0                     TEGRA_GPIO_PZ4
60 #define pm313_MODE1                     TEGRA_GPIO_PW1
61 #define pm313_BPP                       TEGRA_GPIO_PN6 /* 0:24bpp, 1:18bpp */
62 #define pm313_lvds_shutdown             TEGRA_GPIO_PL2
63
64 /* E1506 display board pins */
65 #define e1506_lcd_te            TEGRA_GPIO_PJ1
66 #define e1506_dsi_vddio         TEGRA_GPIO_PH1
67 #define e1506_dsia_bl_pwm       TEGRA_GPIO_PH0
68 #define e1506_panel_enb         TEGRA_GPIO_PW1
69 #define e1506_bl_enb            TEGRA_GPIO_PH2
70
71 /* E1247 reworked for pm269 pins */
72 #define e1247_pm269_lvds_shutdown       TEGRA_GPIO_PN6
73
74 /* E1247 cardhu default display board pins */
75 #define cardhu_lvds_shutdown            TEGRA_GPIO_PL2
76
77 /* common pins( backlight ) for all display boards */
78 #define cardhu_bl_enb                   TEGRA_GPIO_PH2
79 #define cardhu_bl_pwm                   TEGRA_GPIO_PH0
80 #define cardhu_hdmi_hpd                 TEGRA_GPIO_PN7
81
82 /* common dsi panel pins */
83 #define cardhu_dsia_bl_enb              TEGRA_GPIO_PW1
84 #define cardhu_dsib_bl_enb              TEGRA_GPIO_PW0
85 #define cardhu_dsi_pnl_reset            TEGRA_GPIO_PD2
86 #define cardhu_dsi_219_pnl_reset        TEGRA_GPIO_PW0
87
88 #ifdef CONFIG_TEGRA_DC
89 static struct regulator *cardhu_hdmi_reg = NULL;
90 static struct regulator *cardhu_hdmi_pll = NULL;
91 static struct regulator *cardhu_hdmi_vddio = NULL;
92 #endif
93
94 static atomic_t sd_brightness = ATOMIC_INIT(255);
95
96 static struct regulator *cardhu_dsi_reg = NULL;
97 static struct regulator *cardhu_lvds_reg = NULL;
98 static struct regulator *cardhu_lvds_vdd_bl = NULL;
99 static struct regulator *cardhu_lvds_vdd_panel = NULL;
100
101 static struct board_info board_info;
102 static struct board_info display_board_info;
103
104 static tegra_dc_bl_output cardhu_bl_output_measured = {
105         0, 1, 2, 3, 4, 5, 6, 7,
106         8, 9, 10, 11, 12, 13, 14, 15,
107         16, 17, 18, 19, 20, 21, 22, 23,
108         24, 25, 26, 27, 28, 29, 30, 31,
109         32, 33, 34, 35, 36, 37, 38, 39,
110         40, 41, 42, 43, 44, 45, 46, 47,
111         48, 49, 49, 50, 51, 52, 53, 54,
112         55, 56, 57, 58, 59, 60, 61, 62,
113         63, 64, 65, 66, 67, 68, 69, 70,
114         70, 72, 73, 74, 75, 76, 77, 78,
115         79, 80, 81, 82, 83, 84, 85, 86,
116         87, 88, 89, 90, 91, 92, 93, 94,
117         95, 96, 97, 98, 99, 100, 101, 102,
118         103, 104, 105, 106, 107, 108, 110, 111,
119         112, 113, 114, 115, 116, 117, 118, 119,
120         120, 121, 122, 123, 124, 124, 125, 126,
121         127, 128, 129, 130, 131, 132, 133, 133,
122         134, 135, 136, 137, 138, 139, 140, 141,
123         142, 143, 144, 145, 146, 147, 148, 148,
124         149, 150, 151, 152, 153, 154, 155, 156,
125         157, 158, 159, 160, 161, 162, 163, 164,
126         165, 166, 167, 168, 169, 170, 171, 172,
127         173, 174, 175, 176, 177, 179, 180, 181,
128         182, 184, 185, 186, 187, 188, 189, 190,
129         191, 192, 193, 194, 195, 196, 197, 198,
130         199, 200, 201, 202, 203, 204, 205, 206,
131         207, 208, 209, 211, 212, 213, 214, 215,
132         216, 217, 218, 219, 220, 221, 222, 223,
133         224, 225, 226, 227, 228, 229, 230, 231,
134         232, 233, 234, 235, 236, 237, 238, 239,
135         240, 241, 242, 243, 244, 245, 246, 247,
136         248, 249, 250, 251, 252, 253, 254, 255
137 };
138
139 static p_tegra_dc_bl_output bl_output = cardhu_bl_output_measured;
140
141 static bool is_panel_218;
142 static bool is_panel_219;
143 static bool is_panel_1506;
144
145 static bool is_dsi_panel(void)
146 {
147         return is_panel_218 || is_panel_219 || is_panel_1506;
148 }
149
150 static int cardhu_backlight_init(struct device *dev)
151 {
152         int ret = 0;
153
154         if (WARN_ON(ARRAY_SIZE(cardhu_bl_output_measured) != 256))
155                 pr_err("bl_output array does not have 256 elements\n");
156
157         if (!is_dsi_panel()) {
158                 ret = gpio_request(cardhu_bl_enb, "backlight_enb");
159                 if (ret < 0)
160                         return ret;
161
162                 ret = gpio_direction_output(cardhu_bl_enb, 1);
163                 if (ret < 0)
164                         gpio_free(cardhu_bl_enb);
165         } else if (is_panel_218) {
166                 /* Enable back light for DSIa panel */
167                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
168                 if (ret < 0)
169                         return ret;
170
171                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
172                 if (ret < 0)
173                         gpio_free(cardhu_dsia_bl_enb);
174
175                 /* Enable back light for DSIb panel */
176                 ret = gpio_request(cardhu_dsib_bl_enb, "dsib_bl_enable");
177                 if (ret < 0)
178                         return ret;
179
180                 ret = gpio_direction_output(cardhu_dsib_bl_enb, 1);
181                 if (ret < 0)
182                         gpio_free(cardhu_dsib_bl_enb);
183         } else if (is_panel_219) {
184                 /* Enable back light for DSIa panel */
185                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
186                 if (ret < 0)
187                         return ret;
188
189                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
190                 if (ret < 0)
191                         gpio_free(cardhu_dsia_bl_enb);
192         }
193
194         return ret;
195 };
196
197 static void cardhu_backlight_exit(struct device *dev)
198 {
199         if (!is_dsi_panel()) {
200                 /* int ret; */
201                 /*ret = gpio_request(cardhu_bl_enb, "backlight_enb");*/
202                 gpio_set_value(cardhu_bl_enb, 0);
203                 gpio_free(cardhu_bl_enb);
204         } else if (is_panel_218) {
205                 /* Disable back light for DSIa panel */
206                 gpio_set_value(cardhu_dsia_bl_enb, 0);
207                 gpio_free(cardhu_dsia_bl_enb);
208
209                 /* Disable back light for DSIb panel */
210                 gpio_set_value(cardhu_dsib_bl_enb, 0);
211                 gpio_free(cardhu_dsib_bl_enb);
212
213                 gpio_set_value(cardhu_lvds_shutdown, 1);
214                 mdelay(20);
215         } else if (is_panel_219) {
216                 /* Disable back light for DSIa panel */
217                 gpio_set_value(cardhu_dsia_bl_enb, 0);
218                 gpio_free(cardhu_dsia_bl_enb);
219
220                 gpio_set_value(cardhu_lvds_shutdown, 1);
221                 mdelay(20);
222         }
223 }
224
225 static int cardhu_backlight_notify(struct device *unused, int brightness)
226 {
227         int cur_sd_brightness = atomic_read(&sd_brightness);
228
229         if (!is_dsi_panel()) {
230                 /* Set the backlight GPIO pin mode to 'backlight_enable' */
231                 gpio_set_value(cardhu_bl_enb, !!brightness);
232         } else if (is_panel_218) {
233                 /* DSIa */
234                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
235
236                 /* DSIb */
237                 gpio_set_value(cardhu_dsib_bl_enb, !!brightness);
238         } else if (is_panel_219) {
239                 /* DSIa */
240                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
241         } else if (is_panel_1506) {
242                 /* DSIa */
243                 gpio_set_value(e1506_bl_enb, !!brightness);
244         }
245
246         /* SD brightness is a percentage, 8-bit value. */
247         brightness = (brightness * cur_sd_brightness) / 255;
248
249         /* Apply any backlight response curve */
250         if (brightness > 255) {
251                 pr_info("Error: Brightness > 255!\n");
252         } else {
253                 brightness = bl_output[brightness];
254         }
255
256         return brightness;
257 }
258
259 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info);
260
261 static struct platform_pwm_backlight_data cardhu_backlight_data = {
262         .pwm_id         = 0,
263         .max_brightness = 255,
264         .dft_brightness = 224,
265         .pwm_period_ns  = 1000000,
266         .init           = cardhu_backlight_init,
267         .exit           = cardhu_backlight_exit,
268         .notify         = cardhu_backlight_notify,
269         /* Only toggle backlight on fb blank notifications for disp1 */
270         .check_fb       = cardhu_disp1_check_fb,
271 };
272
273 static struct platform_device cardhu_backlight_device = {
274         .name   = "pwm-backlight",
275         .id     = -1,
276         .dev    = {
277                 .platform_data = &cardhu_backlight_data,
278         },
279 };
280
281 static int cardhu_panel_enable(void)
282 {
283         if (cardhu_lvds_reg == NULL) {
284                 cardhu_lvds_reg = regulator_get(NULL, "vdd_lvds");
285                 if (WARN_ON(IS_ERR(cardhu_lvds_reg)))
286                         pr_err("%s: couldn't get regulator vdd_lvds: %ld\n",
287                                 __func__, PTR_ERR(cardhu_lvds_reg));
288                 else
289                         regulator_enable(cardhu_lvds_reg);
290         }
291
292         if (cardhu_lvds_vdd_bl == NULL) {
293                 cardhu_lvds_vdd_bl = regulator_get(NULL, "vdd_backlight");
294                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_bl)))
295                         pr_err("%s: couldn't get regulator vdd_backlight: %ld\n",
296                                 __func__, PTR_ERR(cardhu_lvds_vdd_bl));
297                 else
298                         regulator_enable(cardhu_lvds_vdd_bl);
299         }
300
301         if (cardhu_lvds_vdd_panel == NULL) {
302                 cardhu_lvds_vdd_panel = regulator_get(NULL, "vdd_lcd_panel");
303                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_panel)))
304                         pr_err("%s: couldn't get regulator vdd_lcd_panel: %ld\n",
305                                 __func__, PTR_ERR(cardhu_lvds_vdd_panel));
306                 else
307                         regulator_enable(cardhu_lvds_vdd_panel);
308         }
309
310         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
311                 /* lvds configuration */
312                 gpio_set_value(pm313_R_FDE, 1);
313                 gpio_set_value(pm313_R_FB, 1);
314                 gpio_set_value(pm313_MODE0, 1);
315                 gpio_set_value(pm313_MODE1, 0);
316                 gpio_set_value(pm313_BPP, PM313_LVDS_PANEL_BPP);
317
318                 /* FIXME : it may require more or less delay for latching
319                   values correctly before enabling RGB2LVDS */
320                 mdelay(100);
321                 gpio_set_value(pm313_lvds_shutdown, 1);
322         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
323                         board_info.board_id == BOARD_PM269) ||
324                         (board_info.board_id == BOARD_E1257) ||
325                         (board_info.board_id == BOARD_PM305) ||
326                         (board_info.board_id == BOARD_PM311))
327                 gpio_set_value(e1247_pm269_lvds_shutdown, 1);
328         else
329                 gpio_set_value(cardhu_lvds_shutdown, 1);
330
331         return 0;
332 }
333
334 static int cardhu_panel_disable(void)
335 {
336         regulator_disable(cardhu_lvds_reg);
337         regulator_put(cardhu_lvds_reg);
338         cardhu_lvds_reg = NULL;
339
340         regulator_disable(cardhu_lvds_vdd_bl);
341         regulator_put(cardhu_lvds_vdd_bl);
342         cardhu_lvds_vdd_bl = NULL;
343
344         regulator_disable(cardhu_lvds_vdd_panel);
345         regulator_put(cardhu_lvds_vdd_panel);
346
347         cardhu_lvds_vdd_panel= NULL;
348
349         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
350                 gpio_set_value(pm313_lvds_shutdown, 0);
351         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
352                         board_info.board_id == BOARD_PM269) ||
353                         (board_info.board_id == BOARD_E1257) ||
354                         (board_info.board_id == BOARD_PM305) ||
355                         (board_info.board_id == BOARD_PM311)) {
356                 gpio_set_value(e1247_pm269_lvds_shutdown, 0);
357         } else {
358                 gpio_set_value(cardhu_lvds_shutdown, 0);
359         }
360         return 0;
361 }
362
363 #ifdef CONFIG_TEGRA_DC
364 static int cardhu_hdmi_vddio_enable(void)
365 {
366         int ret;
367         if (!cardhu_hdmi_vddio) {
368                 cardhu_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
369                 if (IS_ERR_OR_NULL(cardhu_hdmi_vddio)) {
370                         ret = PTR_ERR(cardhu_hdmi_vddio);
371                         pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
372                         cardhu_hdmi_vddio = NULL;
373                         return ret;
374                 }
375         }
376         ret = regulator_enable(cardhu_hdmi_vddio);
377         if (ret < 0) {
378                 pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
379                 regulator_put(cardhu_hdmi_vddio);
380                 cardhu_hdmi_vddio = NULL;
381                 return ret;
382         }
383         return ret;
384 }
385
386 static int cardhu_hdmi_vddio_disable(void)
387 {
388         if (cardhu_hdmi_vddio) {
389                 regulator_disable(cardhu_hdmi_vddio);
390                 regulator_put(cardhu_hdmi_vddio);
391                 cardhu_hdmi_vddio = NULL;
392         }
393         return 0;
394 }
395
396 static int cardhu_hdmi_enable(void)
397 {
398         int ret;
399         if (!cardhu_hdmi_reg) {
400                 cardhu_hdmi_reg = regulator_get(NULL, "avdd_hdmi");
401                 if (IS_ERR_OR_NULL(cardhu_hdmi_reg)) {
402                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
403                         cardhu_hdmi_reg = NULL;
404                         return PTR_ERR(cardhu_hdmi_reg);
405                 }
406         }
407         ret = regulator_enable(cardhu_hdmi_reg);
408         if (ret < 0) {
409                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
410                 return ret;
411         }
412         if (!cardhu_hdmi_pll) {
413                 cardhu_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll");
414                 if (IS_ERR_OR_NULL(cardhu_hdmi_pll)) {
415                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
416                         cardhu_hdmi_pll = NULL;
417                         regulator_put(cardhu_hdmi_reg);
418                         cardhu_hdmi_reg = NULL;
419                         return PTR_ERR(cardhu_hdmi_pll);
420                 }
421         }
422         ret = regulator_enable(cardhu_hdmi_pll);
423         if (ret < 0) {
424                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
425                 return ret;
426         }
427         return 0;
428 }
429
430 static int cardhu_hdmi_disable(void)
431 {
432         regulator_disable(cardhu_hdmi_reg);
433         regulator_put(cardhu_hdmi_reg);
434         cardhu_hdmi_reg = NULL;
435
436         regulator_disable(cardhu_hdmi_pll);
437         regulator_put(cardhu_hdmi_pll);
438         cardhu_hdmi_pll = NULL;
439         return 0;
440 }
441
442 static struct resource cardhu_disp1_resources[] = {
443         {
444                 .name   = "irq",
445                 .start  = INT_DISPLAY_GENERAL,
446                 .end    = INT_DISPLAY_GENERAL,
447                 .flags  = IORESOURCE_IRQ,
448         },
449         {
450                 .name   = "regs",
451                 .start  = TEGRA_DISPLAY_BASE,
452                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
453                 .flags  = IORESOURCE_MEM,
454         },
455         {
456                 .name   = "fbmem",
457                 .start  = 0,    /* Filled in by cardhu_panel_init() */
458                 .end    = 0,    /* Filled in by cardhu_panel_init() */
459                 .flags  = IORESOURCE_MEM,
460         },
461 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
462         {
463                 .name   = "dsi_regs",
464                 .start  = TEGRA_DSIB_BASE,
465                 .end    = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1,
466                 .flags  = IORESOURCE_MEM,
467         },
468 #else
469         {
470                 .name   = "dsi_regs",
471                 .start  = TEGRA_DSI_BASE,
472                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
473                 .flags  = IORESOURCE_MEM,
474         },
475 #endif
476 };
477
478 static struct resource cardhu_disp2_resources[] = {
479         {
480                 .name   = "irq",
481                 .start  = INT_DISPLAY_B_GENERAL,
482                 .end    = INT_DISPLAY_B_GENERAL,
483                 .flags  = IORESOURCE_IRQ,
484         },
485         {
486                 .name   = "regs",
487                 .start  = TEGRA_DISPLAY2_BASE,
488                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
489                 .flags  = IORESOURCE_MEM,
490         },
491         {
492                 .name   = "fbmem",
493                 .flags  = IORESOURCE_MEM,
494                 .start  = 0,
495                 .end    = 0,
496         },
497         {
498                 .name   = "hdmi_regs",
499                 .start  = TEGRA_HDMI_BASE,
500                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
501                 .flags  = IORESOURCE_MEM,
502         },
503 };
504 #endif
505
506 static struct tegra_dc_mode panel_19X12_modes[] = {
507         {
508                 .pclk = 154000000,
509                 .h_ref_to_sync = 11,
510                 .v_ref_to_sync = 1,
511                 .h_sync_width = 32,
512                 .v_sync_width = 6,
513                 .h_back_porch = 80,
514                 .v_back_porch = 26,
515                 .h_active = 1920,
516                 .v_active = 1200,
517                 .h_front_porch = 48,
518                 .v_front_porch = 3,
519         },
520 };
521
522 static struct tegra_dc_mode cardhu_panel_modes[] = {
523         {
524                 /* 1366x768@60Hz */
525                 .pclk = 74180000,
526                 .h_ref_to_sync = 1,
527                 .v_ref_to_sync = 1,
528                 .h_sync_width = 30,
529                 .v_sync_width = 5,
530                 .h_back_porch = 52,
531                 .v_back_porch = 20,
532                 .h_active = 1366,
533                 .v_active = 768,
534                 .h_front_porch = 64,
535                 .v_front_porch = 25,
536         },
537         {
538                 /* 1366x768@50Hz */
539                 .pclk = 74180000,
540                 .h_ref_to_sync = 1,
541                 .v_ref_to_sync = 1,
542                 .h_sync_width = 30,
543                 .v_sync_width = 5,
544                 .h_back_porch = 56,
545                 .v_back_porch = 80,
546                 .h_active = 1366,
547                 .v_active = 768,
548                 .h_front_porch = 64,
549                 .v_front_porch = 125,
550         },
551         {
552                 /* 1366x768@48 */
553                 .pclk = 74180000,
554                 .h_ref_to_sync = 1,
555                 .v_ref_to_sync = 1,
556                 .h_sync_width = 30,
557                 .v_sync_width = 5,
558                 .h_back_porch = 52,
559                 .v_back_porch = 98,
560                 .h_active = 1366,
561                 .v_active = 768,
562                 .h_front_porch = 64,
563                 .v_front_porch = 152,
564         },
565 };
566
567 static struct tegra_dc_mode cardhu_panel_modes_55hz[] = {
568         {
569                 /* 1366x768p 55Hz */
570                 .pclk = 68000000,
571                 .h_ref_to_sync = 0,
572                 .v_ref_to_sync = 12,
573                 .h_sync_width = 30,
574                 .v_sync_width = 5,
575                 .h_back_porch = 52,
576                 .v_back_porch = 20,
577                 .h_active = 1366,
578                 .v_active = 768,
579                 .h_front_porch = 64,
580                 .v_front_porch = 25,
581         },
582 };
583
584 static struct tegra_dc_sd_settings cardhu_sd_settings = {
585         .enable = 1, /* enabled by default. */
586         .use_auto_pwm = false,
587         .hw_update_delay = 0,
588         .bin_width = -1,
589         .aggressiveness = 1,
590         .phase_in_adjustments = true,
591         .use_vid_luma = false,
592         /* Default video coefficients */
593         .coeff = {5, 9, 2},
594         .fc = {0, 0},
595         /* Immediate backlight changes */
596         .blp = {1024, 255},
597         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
598         /* Default BL TF */
599         .bltf = {
600                         {
601                                 {57, 65, 74, 83},
602                                 {93, 103, 114, 126},
603                                 {138, 151, 165, 179},
604                                 {194, 209, 225, 242},
605                         },
606                         {
607                                 {58, 66, 75, 84},
608                                 {94, 105, 116, 127},
609                                 {140, 153, 166, 181},
610                                 {196, 211, 227, 244},
611                         },
612                         {
613                                 {60, 68, 77, 87},
614                                 {97, 107, 119, 130},
615                                 {143, 156, 170, 184},
616                                 {199, 215, 231, 248},
617                         },
618                         {
619                                 {64, 73, 82, 91},
620                                 {102, 113, 124, 137},
621                                 {149, 163, 177, 192},
622                                 {207, 223, 240, 255},
623                         },
624                 },
625         /* Default LUT */
626         .lut = {
627                         {
628                                 {250, 250, 250},
629                                 {194, 194, 194},
630                                 {149, 149, 149},
631                                 {113, 113, 113},
632                                 {82, 82, 82},
633                                 {56, 56, 56},
634                                 {34, 34, 34},
635                                 {15, 15, 15},
636                                 {0, 0, 0},
637                         },
638                         {
639                                 {246, 246, 246},
640                                 {191, 191, 191},
641                                 {147, 147, 147},
642                                 {111, 111, 111},
643                                 {80, 80, 80},
644                                 {55, 55, 55},
645                                 {33, 33, 33},
646                                 {14, 14, 14},
647                                 {0, 0, 0},
648                         },
649                         {
650                                 {239, 239, 239},
651                                 {185, 185, 185},
652                                 {142, 142, 142},
653                                 {107, 107, 107},
654                                 {77, 77, 77},
655                                 {52, 52, 52},
656                                 {30, 30, 30},
657                                 {12, 12, 12},
658                                 {0, 0, 0},
659                         },
660                         {
661                                 {224, 224, 224},
662                                 {173, 173, 173},
663                                 {133, 133, 133},
664                                 {99, 99, 99},
665                                 {70, 70, 70},
666                                 {46, 46, 46},
667                                 {25, 25, 25},
668                                 {7, 7, 7},
669                                 {0, 0, 0},
670                         },
671                 },
672         .sd_brightness = &sd_brightness,
673         .bl_device = &cardhu_backlight_device,
674 };
675
676 #ifdef CONFIG_TEGRA_DC
677 static struct tegra_fb_data cardhu_fb_data = {
678         .win            = 0,
679         .xres           = 1366,
680         .yres           = 768,
681         .bits_per_pixel = 32,
682         .flags          = TEGRA_FB_FLIP_ON_PROBE,
683 };
684
685 static struct tegra_fb_data cardhu_hdmi_fb_data = {
686         .win            = 0,
687         .xres           = 640,
688         .yres           = 480,
689         .bits_per_pixel = 32,
690         .flags          = TEGRA_FB_FLIP_ON_PROBE,
691 };
692
693 static struct tegra_dc_out cardhu_disp2_out = {
694         .type           = TEGRA_DC_OUT_HDMI,
695         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
696         .parent_clk     = "pll_d2_out0",
697
698         .dcc_bus        = 3,
699         .hotplug_gpio   = cardhu_hdmi_hpd,
700
701         .max_pixclock   = KHZ2PICOS(148500),
702
703         .align          = TEGRA_DC_ALIGN_MSB,
704         .order          = TEGRA_DC_ORDER_RED_BLUE,
705
706         .enable         = cardhu_hdmi_enable,
707         .disable        = cardhu_hdmi_disable,
708
709         .postsuspend    = cardhu_hdmi_vddio_disable,
710         .hotplug_init   = cardhu_hdmi_vddio_enable,
711 };
712
713 static struct tegra_dc_platform_data cardhu_disp2_pdata = {
714         .flags          = TEGRA_DC_FLAG_ENABLED,
715         .default_out    = &cardhu_disp2_out,
716         .fb             = &cardhu_hdmi_fb_data,
717         .emc_clk_rate   = 300000000,
718 };
719 #endif
720
721 static int cardhu_dsi_panel_enable(void)
722 {
723         int ret;
724
725         if (cardhu_dsi_reg == NULL) {
726                 cardhu_dsi_reg = regulator_get(NULL, "avdd_dsi_csi");
727                 if (IS_ERR_OR_NULL(cardhu_dsi_reg)) {
728                         pr_err("dsi: Could not get regulator avdd_dsi_csi\n");
729                         cardhu_dsi_reg = NULL;
730                         return PTR_ERR(cardhu_dsi_reg);
731                 }
732         }
733
734         regulator_enable(cardhu_dsi_reg);
735
736         if (!is_panel_1506) {
737                 ret = gpio_request(AVDD_LCD, "avdd_lcd");
738                 if (ret < 0)
739                         gpio_free(AVDD_LCD);
740                 ret = gpio_direction_output(AVDD_LCD, 1);
741                 if (ret < 0)
742                         gpio_free(AVDD_LCD);
743         }
744
745         if (is_panel_219) {
746                 ret = gpio_request(cardhu_bl_pwm, "bl_pwm");
747                 if (ret < 0)
748                         return ret;
749                 ret = gpio_direction_output(cardhu_bl_pwm, 0);
750                 if (ret < 0) {
751                         gpio_free(cardhu_bl_pwm);
752                         return ret;
753                 }
754
755                 ret = gpio_request(cardhu_bl_enb, "bl_enb");
756                 if (ret < 0)
757                         return ret;
758                 ret = gpio_direction_output(cardhu_bl_enb, 0);
759                 if (ret < 0) {
760                         gpio_free(cardhu_bl_enb);
761                         return ret;
762                 }
763
764                 gpio_set_value(cardhu_lvds_shutdown, 1);
765                 mdelay(20);
766                 gpio_set_value(cardhu_bl_pwm, 1);
767                 mdelay(10);
768                 gpio_set_value(cardhu_bl_enb, 1);
769                 mdelay(15);
770         } else if (is_panel_1506) {
771                 ret = gpio_request(e1506_dsi_vddio, "e1506_dsi_vddio");
772                 if (ret < 0)
773                         return ret;
774                 ret = gpio_direction_output(e1506_dsi_vddio, 0);
775                 if (ret < 0) {
776                         gpio_free(e1506_dsi_vddio);
777                         return ret;
778                 }
779
780                 ret = gpio_request(e1506_panel_enb, "e1506_panel_enb");
781                 if (ret < 0)
782                         return ret;
783                 ret = gpio_direction_output(e1506_panel_enb, 0);
784                 if (ret < 0) {
785                         gpio_free(e1506_panel_enb);
786                         return ret;
787                 }
788
789                 ret = gpio_request(e1506_bl_enb, "e1506_bl_enb");
790                 if (ret < 0)
791                         return ret;
792                 ret = gpio_direction_output(e1506_bl_enb, 0);
793                 if (ret < 0) {
794                         gpio_free(e1506_bl_enb);
795                         return ret;
796                 }
797
798                 gpio_set_value(e1506_dsi_vddio, 1);
799                 mdelay(1);
800                 gpio_set_value(e1506_panel_enb, 1);
801                 mdelay(10);
802                 gpio_set_value(e1506_bl_enb, 1);
803                 mdelay(15);
804         }
805
806 #if DSI_PANEL_RESET
807         if (is_panel_218) {
808                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
809                 if (ret < 0)
810                         return ret;
811
812                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
813                 if (ret < 0) {
814                         gpio_free(cardhu_dsi_pnl_reset);
815                         return ret;
816                 }
817
818                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
819                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
820                 mdelay(2);
821                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
822                 mdelay(2);
823         } else if (is_panel_219) {
824                 ret = gpio_request(cardhu_dsi_219_pnl_reset, "dsi_panel_reset");
825                 if (ret < 0)
826                         return ret;
827                 ret = gpio_direction_output(cardhu_dsi_219_pnl_reset, 0);
828                 if (ret < 0) {
829                         gpio_free(cardhu_dsi_219_pnl_reset);
830                         return ret;
831                 }
832
833                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
834                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
835                 mdelay(10);
836                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
837                 mdelay(10);
838                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
839                 mdelay(15);
840         } else if (is_panel_1506) {
841                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
842                 if (ret < 0)
843                         return ret;
844                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
845                 if (ret < 0) {
846                         gpio_free(cardhu_dsi_pnl_reset);
847                         return ret;
848                 }
849
850                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
851                 mdelay(1);
852                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
853                 mdelay(1);
854                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
855                 mdelay(20);
856         }
857 #endif
858
859         return 0;
860 }
861
862 static int cardhu_dsi_panel_disable(void)
863 {
864         int err;
865
866         err = 0;
867
868         if (is_panel_219) {
869                 gpio_free(cardhu_dsi_219_pnl_reset);
870                 gpio_free(cardhu_bl_enb);
871                 gpio_free(cardhu_bl_pwm);
872                 gpio_free(cardhu_lvds_shutdown);
873         } else if (is_panel_218) {
874                 gpio_free(cardhu_dsi_pnl_reset);
875         } else if (is_panel_1506) {
876                 tegra_gpio_disable(e1506_bl_enb);
877                 gpio_free(e1506_bl_enb);
878                 tegra_gpio_disable(cardhu_dsi_pnl_reset);
879                 gpio_free(cardhu_dsi_pnl_reset);
880                 tegra_gpio_disable(e1506_panel_enb);
881                 gpio_free(e1506_panel_enb);
882                 tegra_gpio_disable(e1506_dsi_vddio);
883                 gpio_free(e1506_dsi_vddio);
884         }
885         return err;
886 }
887
888 static int cardhu_dsi_panel_postsuspend(void)
889 {
890         int err;
891
892         err = 0;
893         printk(KERN_INFO "DSI panel postsuspend\n");
894
895         if (cardhu_dsi_reg) {
896                 err = regulator_disable(cardhu_dsi_reg);
897                 if (err < 0)
898                         printk(KERN_ERR
899                         "DSI regulator avdd_dsi_csi disable failed\n");
900                 regulator_put(cardhu_dsi_reg);
901                 cardhu_dsi_reg = NULL;
902         }
903
904         if (is_panel_218)
905                 gpio_free(AVDD_LCD);
906
907         return err;
908 }
909
910 static struct tegra_dsi_cmd dsi_init_cmd[] = {
911         DSI_CMD_SHORT(0x05, 0x11, 0x00),
912         DSI_DLY_MS(150),
913 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
914         DSI_CMD_SHORT(0x15, 0x35, 0x00),
915 #endif
916         DSI_CMD_SHORT(0x05, 0x29, 0x00),
917         DSI_DLY_MS(20),
918 };
919
920 u8 password_array[] = {0xb9, 0xff, 0x83, 0x92};
921
922 static struct tegra_dsi_cmd dsi_init_cmd_1506[] = {
923         DSI_CMD_SHORT(0x05, 0x11, 0x00),
924         DSI_DLY_MS(150),
925         DSI_CMD_LONG(0x39, password_array),
926         DSI_DLY_MS(10),
927         DSI_CMD_SHORT(0x15, 0xd4, 0x0c),
928         DSI_DLY_MS(10),
929         DSI_CMD_SHORT(0x15, 0xba, 0x11),
930         DSI_DLY_MS(10),
931 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
932         DSI_CMD_SHORT(0x15, 0x35, 0x00),
933 #endif
934         DSI_CMD_SHORT(0x05, 0x29, 0x00),
935         DSI_DLY_MS(20),
936 };
937
938 static struct tegra_dsi_cmd dsi_early_suspend_cmd[] = {
939         DSI_CMD_SHORT(0x05, 0x28, 0x00),
940         DSI_DLY_MS(20),
941 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
942         DSI_CMD_SHORT(0x05, 0x34, 0x00),
943 #endif
944 };
945
946 static struct tegra_dsi_cmd dsi_late_resume_cmd[] = {
947 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
948         DSI_CMD_SHORT(0x15, 0x35, 0x00),
949 #endif
950         DSI_CMD_SHORT(0x05, 0x29, 0x00),
951         DSI_DLY_MS(20),
952 };
953
954 static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
955         DSI_CMD_SHORT(0x05, 0x28, 0x00),
956         DSI_DLY_MS(120),
957 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
958         DSI_CMD_SHORT(0x05, 0x34, 0x00),
959 #endif
960         DSI_CMD_SHORT(0x05, 0x10, 0x00),
961         DSI_DLY_MS(5),
962 };
963
964 static struct tegra_dsi_cmd dsi_suspend_cmd_1506[] = {
965         DSI_CMD_SHORT(0x05, 0x28, 0x00),
966         DSI_CMD_SHORT(0x05, 0x10, 0x00),
967         DSI_DLY_MS(120),
968 };
969
970 struct tegra_dsi_out cardhu_dsi = {
971         .n_data_lanes = 2,
972         .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
973
974 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
975         /*
976          * The one-shot frame time must be shorter than the time between TE.
977          * Increasing refresh_rate will result in a decrease in the frame time
978          * for one-shot. rated_refresh_rate is only an approximation of the
979          * TE rate, and is only used to report refresh rate to upper layers.
980          */
981         .refresh_rate = 66,
982         .rated_refresh_rate = 60,
983 #else
984         .refresh_rate = 60,
985 #endif
986         .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
987
988         .panel_has_frame_buffer = true,
989 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
990         .dsi_instance = 1,
991 #else
992         .dsi_instance = 0,
993 #endif
994         .panel_reset = DSI_PANEL_RESET,
995         .power_saving_suspend = true,
996
997         .n_early_suspend_cmd = ARRAY_SIZE(dsi_early_suspend_cmd),
998         .dsi_early_suspend_cmd = dsi_early_suspend_cmd,
999
1000         .n_late_resume_cmd = ARRAY_SIZE(dsi_late_resume_cmd),
1001         .dsi_late_resume_cmd = dsi_late_resume_cmd,
1002
1003         .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
1004         .dsi_suspend_cmd = dsi_suspend_cmd,
1005
1006         .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
1007         .lp_cmd_mode_freq_khz = 430000,
1008 };
1009
1010 static struct tegra_dc_mode cardhu_dsi_modes_219[] = {
1011         {
1012                 .pclk = 10000000,
1013                 .h_ref_to_sync = 4,
1014                 .v_ref_to_sync = 1,
1015                 .h_sync_width = 16,
1016                 .v_sync_width = 1,
1017                 .h_back_porch = 32,
1018                 .v_back_porch = 1,
1019                 .h_active = 540,
1020                 .v_active = 960,
1021                 .h_front_porch = 32,
1022                 .v_front_porch = 2,
1023         },
1024 };
1025
1026 static struct tegra_dc_mode cardhu_dsi_modes_218[] = {
1027         {
1028                 .pclk = 323000000,
1029                 .h_ref_to_sync = 11,
1030                 .v_ref_to_sync = 1,
1031                 .h_sync_width = 16,
1032                 .v_sync_width = 4,
1033                 .h_back_porch = 16,
1034                 .v_back_porch = 4,
1035                 .h_active = 864,
1036                 .v_active = 480,
1037                 .h_front_porch = 16,
1038                 .v_front_porch = 4,
1039         },
1040 };
1041
1042 static struct tegra_dc_mode cardhu_dsi_modes_1506[] = {
1043         {
1044                 .pclk = 61417000,
1045                 .h_ref_to_sync = 2,
1046                 .v_ref_to_sync = 2,
1047                 .h_sync_width = 4,
1048                 .v_sync_width = 4,
1049                 .h_back_porch = 100,
1050                 .v_back_porch = 14,
1051                 .h_active = 720,
1052                 .v_active = 1280,
1053                 .h_front_porch = 4,
1054                 .v_front_porch = 4,
1055         },
1056 };
1057
1058
1059 static struct tegra_fb_data cardhu_dsi_fb_data = {
1060         .win            = 0,
1061         .bits_per_pixel = 32,
1062         .flags          = TEGRA_FB_FLIP_ON_PROBE,
1063 };
1064
1065 static struct tegra_dc_out cardhu_disp1_out = {
1066         .align          = TEGRA_DC_ALIGN_MSB,
1067         .order          = TEGRA_DC_ORDER_RED_BLUE,
1068         .sd_settings    = &cardhu_sd_settings,
1069         .parent_clk     = "pll_d_out0",
1070
1071 };
1072
1073 #ifdef CONFIG_TEGRA_DC
1074 static struct tegra_dc_platform_data cardhu_disp1_pdata = {
1075         .flags          = TEGRA_DC_FLAG_ENABLED,
1076         .default_out    = &cardhu_disp1_out,
1077         .emc_clk_rate   = 300000000,
1078 };
1079
1080 static struct nvhost_device cardhu_disp1_device = {
1081         .name           = "tegradc",
1082         .id             = 0,
1083         .resource       = cardhu_disp1_resources,
1084         .num_resources  = ARRAY_SIZE(cardhu_disp1_resources),
1085         .dev = {
1086                 .platform_data = &cardhu_disp1_pdata,
1087         },
1088 };
1089
1090 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1091 {
1092         return info->device == &cardhu_disp1_device.dev;
1093 }
1094
1095 static struct nvhost_device cardhu_disp2_device = {
1096         .name           = "tegradc",
1097         .id             = 1,
1098         .resource       = cardhu_disp2_resources,
1099         .num_resources  = ARRAY_SIZE(cardhu_disp2_resources),
1100         .dev = {
1101                 .platform_data = &cardhu_disp2_pdata,
1102         },
1103 };
1104 #else
1105 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1106 {
1107         return 0;
1108 }
1109 #endif
1110
1111 #if defined(CONFIG_TEGRA_NVMAP)
1112 static struct nvmap_platform_carveout cardhu_carveouts[] = {
1113         [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
1114         [1] = {
1115                 .name           = "generic-0",
1116                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
1117                 .base           = 0,    /* Filled in by cardhu_panel_init() */
1118                 .size           = 0,    /* Filled in by cardhu_panel_init() */
1119                 .buddy_size     = SZ_32K,
1120         },
1121 };
1122
1123 static struct nvmap_platform_data cardhu_nvmap_data = {
1124         .carveouts      = cardhu_carveouts,
1125         .nr_carveouts   = ARRAY_SIZE(cardhu_carveouts),
1126 };
1127
1128 static struct platform_device cardhu_nvmap_device = {
1129         .name   = "tegra-nvmap",
1130         .id     = -1,
1131         .dev    = {
1132                 .platform_data = &cardhu_nvmap_data,
1133         },
1134 };
1135 #endif
1136
1137 #if defined(CONFIG_ION_TEGRA)
1138
1139 static struct platform_device tegra_iommu_device = {
1140         .name = "tegra_iommu_device",
1141         .id = -1,
1142         .dev = {
1143                 .platform_data = (void *)((1 << HWGRP_COUNT) - 1),
1144         },
1145 };
1146
1147 static struct ion_platform_data tegra_ion_data = {
1148         .nr = 4,
1149         .heaps = {
1150                 {
1151                         .type = ION_HEAP_TYPE_CARVEOUT,
1152                         .id = TEGRA_ION_HEAP_CARVEOUT,
1153                         .name = "carveout",
1154                         .base = 0,
1155                         .size = 0,
1156                 },
1157                 {
1158                         .type = ION_HEAP_TYPE_CARVEOUT,
1159                         .id = TEGRA_ION_HEAP_IRAM,
1160                         .name = "iram",
1161                         .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
1162                         .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
1163                 },
1164                 {
1165                         .type = ION_HEAP_TYPE_CARVEOUT,
1166                         .id = TEGRA_ION_HEAP_VPR,
1167                         .name = "vpr",
1168                         .base = 0,
1169                         .size = 0,
1170                 },
1171                 {
1172                         .type = ION_HEAP_TYPE_IOMMU,
1173                         .id = TEGRA_ION_HEAP_IOMMU,
1174                         .name = "iommu",
1175                         .base = TEGRA_SMMU_BASE,
1176                         .size = TEGRA_SMMU_SIZE,
1177                         .priv = &tegra_iommu_device.dev,
1178                 },
1179         },
1180 };
1181
1182 static struct platform_device tegra_ion_device = {
1183         .name = "ion-tegra",
1184         .id = -1,
1185         .dev = {
1186                 .platform_data = &tegra_ion_data,
1187         },
1188 };
1189 #endif
1190
1191 static struct platform_device *cardhu_gfx_devices[] __initdata = {
1192 #if defined(CONFIG_TEGRA_NVMAP)
1193         &cardhu_nvmap_device,
1194 #endif
1195 #if defined(CONFIG_ION_TEGRA)
1196         &tegra_ion_device,
1197 #endif
1198         &tegra_pwfm0_device,
1199         &cardhu_backlight_device,
1200 };
1201
1202
1203 #ifdef CONFIG_HAS_EARLYSUSPEND
1204 /* put early_suspend/late_resume handlers here for the display in order
1205  * to keep the code out of the display driver, keeping it closer to upstream
1206  */
1207 struct early_suspend cardhu_panel_early_suspender;
1208
1209 static void cardhu_panel_early_suspend(struct early_suspend *h)
1210 {
1211         /* power down LCD, add use a black screen for HDMI */
1212         if (num_registered_fb > 0)
1213                 fb_blank(registered_fb[0], FB_BLANK_POWERDOWN);
1214         if (num_registered_fb > 1)
1215                 fb_blank(registered_fb[1], FB_BLANK_NORMAL);
1216 }
1217
1218 static void cardhu_panel_late_resume(struct early_suspend *h)
1219 {
1220         unsigned i;
1221         for (i = 0; i < num_registered_fb; i++)
1222                 fb_blank(registered_fb[i], FB_BLANK_UNBLANK);
1223 }
1224 #endif
1225
1226 static void cardhu_panel_preinit(void)
1227 {
1228         if (display_board_info.board_id == BOARD_DISPLAY_E1213)
1229                 is_panel_218 = true;
1230         else if (display_board_info.board_id == BOARD_DISPLAY_E1253)
1231                 is_panel_219 = true;
1232         else if (display_board_info.board_id == BOARD_DISPLAY_E1506)
1233                 is_panel_1506 = true;
1234
1235         if (!is_dsi_panel()) {
1236                 cardhu_disp1_out.parent_clk_backup = "pll_d2_out0";
1237                 cardhu_disp1_out.type = TEGRA_DC_OUT_RGB;
1238                 cardhu_disp1_out.depth = 18;
1239                 cardhu_disp1_out.dither = TEGRA_DC_ORDERED_DITHER;
1240                 cardhu_disp1_out.modes = cardhu_panel_modes;
1241                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes);
1242                 cardhu_disp1_out.enable = cardhu_panel_enable;
1243                 cardhu_disp1_out.disable = cardhu_panel_disable;
1244
1245                 cardhu_disp1_pdata.fb = &cardhu_fb_data;
1246         } else {
1247                 cardhu_disp1_out.flags = DC_CTRL_MODE;
1248                 cardhu_disp1_out.type = TEGRA_DC_OUT_DSI;
1249                 cardhu_disp1_out.dsi = &cardhu_dsi;
1250                 cardhu_disp1_out.enable = cardhu_dsi_panel_enable;
1251                 cardhu_disp1_out.disable = cardhu_dsi_panel_disable;
1252                 cardhu_disp1_out.postsuspend = cardhu_dsi_panel_postsuspend;
1253
1254                 cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd);
1255                 cardhu_dsi.dsi_init_cmd = dsi_init_cmd;
1256                 cardhu_dsi.n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd);
1257                 cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd;
1258
1259                 if (is_panel_218) {
1260                         cardhu_disp1_out.modes  = cardhu_dsi_modes_218;
1261                         cardhu_disp1_out.n_modes =
1262                                 ARRAY_SIZE(cardhu_dsi_modes_218);
1263                         cardhu_dsi_fb_data.xres = 864;
1264                         cardhu_dsi_fb_data.yres = 480;
1265                 } else if (is_panel_219) {
1266                         cardhu_disp1_out.modes  = cardhu_dsi_modes_219;
1267                         cardhu_disp1_out.n_modes =
1268                                 ARRAY_SIZE(cardhu_dsi_modes_219);
1269                         cardhu_dsi_fb_data.xres = 540;
1270                         cardhu_dsi_fb_data.yres = 960;
1271                 } else if (is_panel_1506) {
1272                         cardhu_disp1_out.modes  = cardhu_dsi_modes_1506;
1273                         cardhu_disp1_out.n_modes =
1274                                 ARRAY_SIZE(cardhu_dsi_modes_1506);
1275                         cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd_1506);
1276                         cardhu_dsi.dsi_init_cmd = dsi_init_cmd_1506;
1277                         cardhu_dsi.n_suspend_cmd =
1278                                 ARRAY_SIZE(dsi_suspend_cmd_1506);
1279                         cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd_1506;
1280                         cardhu_dsi.panel_send_dc_frames = true,
1281                         cardhu_dsi_fb_data.xres = 720;
1282                         cardhu_dsi_fb_data.yres = 1280;
1283                 }
1284
1285                 cardhu_disp1_pdata.fb = &cardhu_dsi_fb_data;
1286         }
1287 }
1288
1289 int __init cardhu_panel_init(void)
1290 {
1291         int err;
1292         struct resource __maybe_unused *res;
1293
1294         tegra_get_board_info(&board_info);
1295         tegra_get_display_board_info(&display_board_info);
1296
1297 #if defined(CONFIG_TEGRA_NVMAP)
1298         cardhu_carveouts[1].base = tegra_carveout_start;
1299         cardhu_carveouts[1].size = tegra_carveout_size;
1300 #endif
1301
1302 #if defined(CONFIG_ION_TEGRA)
1303         tegra_ion_data.heaps[0].base = tegra_carveout_start;
1304         tegra_ion_data.heaps[0].size = tegra_carveout_size;
1305 #endif
1306
1307         cardhu_panel_preinit();
1308         if (is_dsi_panel())
1309                 goto skip_lvds;
1310 #if defined(CONFIG_TEGRA_DC)
1311         if (WARN_ON(board_info.board_id == BOARD_E1291 &&
1312                 ((board_info.sku & SKU_TOUCHSCREEN_MECH_FIX) == 0))) {
1313                 /* use 55Hz panel timings to reduce noise on sensitive touch */
1314                 printk("Using cardhu_panel_modes_55hz\n");
1315                 cardhu_disp1_out.parent_clk = "pll_p";
1316                 cardhu_disp1_out.modes = cardhu_panel_modes_55hz;
1317                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes_55hz);
1318         }
1319
1320         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
1321                 /* initialize the values */
1322 #if defined(PM313_LVDS_PANEL_19X12)
1323                 cardhu_disp1_out.modes = panel_19X12_modes;
1324                 cardhu_disp1_out.n_modes = ARRAY_SIZE(panel_19X12_modes);
1325                 cardhu_disp1_out.parent_clk = "pll_d_out0";
1326 #if (PM313_LVDS_PANEL_BPP == 1)
1327                 cardhu_disp1_out.depth = 18;
1328 #else
1329                 cardhu_disp1_out.depth = 24;
1330 #endif
1331                 cardhu_fb_data.xres = 1920;
1332                 cardhu_fb_data.yres = 1200;
1333
1334                 cardhu_disp2_out.parent_clk = "pll_d2_out0";
1335                 cardhu_hdmi_fb_data.xres = 1920;
1336                 cardhu_hdmi_fb_data.yres = 1200;
1337 #endif
1338
1339                 /* lvds configuration */
1340                 err = gpio_request(pm313_R_FDE, "R_FDE");
1341                 err |= gpio_direction_output(pm313_R_FDE, 1);
1342
1343                 err |= gpio_request(pm313_R_FB, "R_FB");
1344                 err |= gpio_direction_output(pm313_R_FB, 1);
1345
1346                 err |= gpio_request(pm313_MODE0, "MODE0");
1347                 err |= gpio_direction_output(pm313_MODE0, 1);
1348
1349                 err |= gpio_request(pm313_MODE1, "MODE1");
1350                 err |= gpio_direction_output(pm313_MODE1, 0);
1351
1352                 err |= gpio_request(pm313_BPP, "BPP");
1353                 err |= gpio_direction_output(pm313_BPP, PM313_LVDS_PANEL_BPP);
1354
1355                 err = gpio_request(pm313_lvds_shutdown, "lvds_shutdown");
1356                 /* free ride provided by bootloader */
1357                 err |= gpio_direction_output(pm313_lvds_shutdown, 1);
1358
1359                 if (err)
1360                         printk(KERN_ERR "ERROR(s) in LVDS configuration\n");
1361         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
1362                                 board_info.board_id == BOARD_PM269) ||
1363                                 (board_info.board_id == BOARD_E1257) ||
1364                                 (board_info.board_id == BOARD_PM305) ||
1365                                 (board_info.board_id == BOARD_PM311)) {
1366                 gpio_request(e1247_pm269_lvds_shutdown, "lvds_shutdown");
1367                 gpio_direction_output(e1247_pm269_lvds_shutdown, 1);
1368         } else {
1369                 gpio_request(cardhu_lvds_shutdown, "lvds_shutdown");
1370                 gpio_direction_output(cardhu_lvds_shutdown, 1);
1371         }
1372 #endif
1373
1374 skip_lvds:
1375         gpio_request(cardhu_hdmi_hpd, "hdmi_hpd");
1376         gpio_direction_input(cardhu_hdmi_hpd);
1377
1378 #if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
1379         tegra_gpio_enable(e1506_lcd_te);
1380         gpio_request(e1506_lcd_te, "lcd_te");
1381         gpio_direction_input(e1506_lcd_te);
1382 #endif
1383
1384 #ifdef CONFIG_HAS_EARLYSUSPEND
1385         cardhu_panel_early_suspender.suspend = cardhu_panel_early_suspend;
1386         cardhu_panel_early_suspender.resume = cardhu_panel_late_resume;
1387         cardhu_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
1388         register_early_suspend(&cardhu_panel_early_suspender);
1389 #endif
1390
1391 #ifdef CONFIG_TEGRA_GRHOST
1392         err = tegra3_register_host1x_devices();
1393         if (err)
1394                 return err;
1395 #endif
1396
1397         err = platform_add_devices(cardhu_gfx_devices,
1398                                 ARRAY_SIZE(cardhu_gfx_devices));
1399
1400 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1401         res = nvhost_get_resource_byname(&cardhu_disp1_device,
1402                                          IORESOURCE_MEM, "fbmem");
1403         res->start = tegra_fb_start;
1404         res->end = tegra_fb_start + tegra_fb_size - 1;
1405 #endif
1406
1407         /* Copy the bootloader fb to the fb. */
1408         tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
1409                                 min(tegra_fb_size, tegra_bootloader_fb_size));
1410
1411 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1412         if (!err)
1413                 err = nvhost_device_register(&cardhu_disp1_device);
1414
1415         res = nvhost_get_resource_byname(&cardhu_disp2_device,
1416                                          IORESOURCE_MEM, "fbmem");
1417         res->start = tegra_fb2_start;
1418         res->end = tegra_fb2_start + tegra_fb2_size - 1;
1419
1420         /* Copy the bootloader fb to the fb2. */
1421         tegra_move_framebuffer(tegra_fb2_start, tegra_bootloader_fb_start,
1422                                 min(tegra_fb2_size, tegra_bootloader_fb_size));
1423
1424         if (!err)
1425                 err = nvhost_device_register(&cardhu_disp2_device);
1426 #endif
1427
1428 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
1429         if (!err)
1430                 err = nvhost_device_register(&nvavp_device);
1431 #endif
1432         return err;
1433 }