video: tegra: cardhu: Default bpp from hardware
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-panel.c
1 /*
2  * arch/arm/mach-tegra/board-cardhu-panel.c
3  *
4  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/delay.h>
22 #include <linux/ion.h>
23 #include <linux/tegra_ion.h>
24 #include <linux/gpio.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/resource.h>
27 #include <asm/mach-types.h>
28 #include <linux/platform_device.h>
29 #include <linux/pwm_backlight.h>
30 #include <asm/atomic.h>
31 #include <linux/nvhost.h>
32 #include <linux/nvmap.h>
33 #include <mach/irqs.h>
34 #include <mach/iomap.h>
35 #include <mach/dc.h>
36 #include <mach/fb.h>
37 #include <mach/smmu.h>
38 #include <mach/gpio-tegra.h>
39
40 #include "board.h"
41 #include "clock.h"
42 #include "dvfs.h"
43 #include "board-cardhu.h"
44 #include "devices.h"
45 #include "gpio-names.h"
46 #include "tegra3_host1x_devices.h"
47
48 #define DC_CTRL_MODE    (TEGRA_DC_OUT_ONE_SHOT_MODE | \
49                          TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
50
51 #define AVDD_LCD PMU_TCA6416_GPIO_PORT17
52 #define DSI_PANEL_RESET 1
53
54 /* Select LVDS panel resolution. 13X7 is default */
55 #define PM313_LVDS_PANEL_19X12                  1
56 #define PM313_LVDS_PANEL_BPP                    0 /* 0:24bpp, 1:18bpp */
57
58 /* PM313 display board specific pins */
59 #define pm313_R_FDE                     TEGRA_GPIO_PW0
60 #define pm313_R_FB                      TEGRA_GPIO_PN4
61 #define pm313_MODE0                     TEGRA_GPIO_PZ4
62 #define pm313_MODE1                     TEGRA_GPIO_PW1
63 #define pm313_BPP                       TEGRA_GPIO_PN6 /* 0:24bpp, 1:18bpp */
64 #define pm313_lvds_shutdown             TEGRA_GPIO_PL2
65
66 /* E1506 display board pins */
67 #define e1506_lcd_te            TEGRA_GPIO_PJ1
68 #define e1506_dsi_vddio         TEGRA_GPIO_PH1
69 #define e1506_dsia_bl_pwm       TEGRA_GPIO_PH0
70 #define e1506_panel_enb         TEGRA_GPIO_PW1
71 #define e1506_bl_enb            TEGRA_GPIO_PH2
72
73 /* E1247 reworked for pm269 pins */
74 #define e1247_pm269_lvds_shutdown       TEGRA_GPIO_PN6
75
76 /* E1247 cardhu default display board pins */
77 #define cardhu_lvds_shutdown            TEGRA_GPIO_PL2
78
79 /* common pins( backlight ) for all display boards */
80 #define cardhu_bl_enb                   TEGRA_GPIO_PH2
81 #define cardhu_bl_pwm                   TEGRA_GPIO_PH0
82 #define cardhu_hdmi_hpd                 TEGRA_GPIO_PN7
83
84 /* common dsi panel pins */
85 #define cardhu_dsia_bl_enb              TEGRA_GPIO_PW1
86 #define cardhu_dsib_bl_enb              TEGRA_GPIO_PW0
87 #define cardhu_dsi_pnl_reset            TEGRA_GPIO_PD2
88 #define cardhu_dsi_219_pnl_reset        TEGRA_GPIO_PW0
89
90 #ifdef CONFIG_TEGRA_DC
91 static struct regulator *cardhu_hdmi_reg = NULL;
92 static struct regulator *cardhu_hdmi_pll = NULL;
93 static struct regulator *cardhu_hdmi_vddio = NULL;
94 #endif
95
96 static atomic_t sd_brightness = ATOMIC_INIT(255);
97
98 static struct regulator *cardhu_dsi_reg = NULL;
99 static struct regulator *cardhu_lvds_reg = NULL;
100 static struct regulator *cardhu_lvds_vdd_bl = NULL;
101 static struct regulator *cardhu_lvds_vdd_panel = NULL;
102
103 static struct board_info board_info;
104 static struct board_info display_board_info;
105
106 static tegra_dc_bl_output cardhu_bl_output_measured = {
107         0, 1, 2, 3, 4, 5, 6, 7,
108         8, 9, 10, 11, 12, 13, 14, 15,
109         16, 17, 18, 19, 20, 21, 22, 23,
110         24, 25, 26, 27, 28, 29, 30, 31,
111         32, 33, 34, 35, 36, 37, 38, 39,
112         40, 41, 42, 43, 44, 45, 46, 47,
113         48, 49, 49, 50, 51, 52, 53, 54,
114         55, 56, 57, 58, 59, 60, 61, 62,
115         63, 64, 65, 66, 67, 68, 69, 70,
116         70, 72, 73, 74, 75, 76, 77, 78,
117         79, 80, 81, 82, 83, 84, 85, 86,
118         87, 88, 89, 90, 91, 92, 93, 94,
119         95, 96, 97, 98, 99, 100, 101, 102,
120         103, 104, 105, 106, 107, 108, 110, 111,
121         112, 113, 114, 115, 116, 117, 118, 119,
122         120, 121, 122, 123, 124, 124, 125, 126,
123         127, 128, 129, 130, 131, 132, 133, 133,
124         134, 135, 136, 137, 138, 139, 140, 141,
125         142, 143, 144, 145, 146, 147, 148, 148,
126         149, 150, 151, 152, 153, 154, 155, 156,
127         157, 158, 159, 160, 161, 162, 163, 164,
128         165, 166, 167, 168, 169, 170, 171, 172,
129         173, 174, 175, 176, 177, 179, 180, 181,
130         182, 184, 185, 186, 187, 188, 189, 190,
131         191, 192, 193, 194, 195, 196, 197, 198,
132         199, 200, 201, 202, 203, 204, 205, 206,
133         207, 208, 209, 211, 212, 213, 214, 215,
134         216, 217, 218, 219, 220, 221, 222, 223,
135         224, 225, 226, 227, 228, 229, 230, 231,
136         232, 233, 234, 235, 236, 237, 238, 239,
137         240, 241, 242, 243, 244, 245, 246, 247,
138         248, 249, 250, 251, 252, 253, 254, 255
139 };
140
141 static p_tegra_dc_bl_output bl_output = cardhu_bl_output_measured;
142
143 static bool is_panel_218;
144 static bool is_panel_219;
145 static bool is_panel_1506;
146
147 static bool is_dsi_panel(void)
148 {
149         return is_panel_218 || is_panel_219 || is_panel_1506;
150 }
151
152 static int cardhu_backlight_init(struct device *dev)
153 {
154         int ret = 0;
155
156         if (WARN_ON(ARRAY_SIZE(cardhu_bl_output_measured) != 256))
157                 pr_err("bl_output array does not have 256 elements\n");
158
159         if (!is_dsi_panel()) {
160                 ret = gpio_request(cardhu_bl_enb, "backlight_enb");
161                 if (ret < 0)
162                         return ret;
163
164                 ret = gpio_direction_output(cardhu_bl_enb, 1);
165                 if (ret < 0)
166                         gpio_free(cardhu_bl_enb);
167         } else if (is_panel_218) {
168                 /* Enable back light for DSIa panel */
169                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
170                 if (ret < 0)
171                         return ret;
172
173                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
174                 if (ret < 0)
175                         gpio_free(cardhu_dsia_bl_enb);
176
177                 /* Enable back light for DSIb panel */
178                 ret = gpio_request(cardhu_dsib_bl_enb, "dsib_bl_enable");
179                 if (ret < 0)
180                         return ret;
181
182                 ret = gpio_direction_output(cardhu_dsib_bl_enb, 1);
183                 if (ret < 0)
184                         gpio_free(cardhu_dsib_bl_enb);
185         } else if (is_panel_219) {
186                 /* Enable back light for DSIa panel */
187                 ret = gpio_request(cardhu_dsia_bl_enb, "dsia_bl_enable");
188                 if (ret < 0)
189                         return ret;
190
191                 ret = gpio_direction_output(cardhu_dsia_bl_enb, 1);
192                 if (ret < 0)
193                         gpio_free(cardhu_dsia_bl_enb);
194         }
195
196         return ret;
197 };
198
199 static void cardhu_backlight_exit(struct device *dev)
200 {
201         if (!is_dsi_panel()) {
202                 /* int ret; */
203                 /*ret = gpio_request(cardhu_bl_enb, "backlight_enb");*/
204                 gpio_set_value(cardhu_bl_enb, 0);
205                 gpio_free(cardhu_bl_enb);
206         } else if (is_panel_218) {
207                 /* Disable back light for DSIa panel */
208                 gpio_set_value(cardhu_dsia_bl_enb, 0);
209                 gpio_free(cardhu_dsia_bl_enb);
210
211                 /* Disable back light for DSIb panel */
212                 gpio_set_value(cardhu_dsib_bl_enb, 0);
213                 gpio_free(cardhu_dsib_bl_enb);
214
215                 gpio_set_value(cardhu_lvds_shutdown, 1);
216                 mdelay(20);
217         } else if (is_panel_219) {
218                 /* Disable back light for DSIa panel */
219                 gpio_set_value(cardhu_dsia_bl_enb, 0);
220                 gpio_free(cardhu_dsia_bl_enb);
221
222                 gpio_set_value(cardhu_lvds_shutdown, 1);
223                 mdelay(20);
224         }
225 }
226
227 static int cardhu_backlight_notify(struct device *unused, int brightness)
228 {
229         int cur_sd_brightness = atomic_read(&sd_brightness);
230
231         if (!is_dsi_panel()) {
232                 /* Set the backlight GPIO pin mode to 'backlight_enable' */
233                 gpio_set_value(cardhu_bl_enb, !!brightness);
234         } else if (is_panel_218) {
235                 /* DSIa */
236                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
237
238                 /* DSIb */
239                 gpio_set_value(cardhu_dsib_bl_enb, !!brightness);
240         } else if (is_panel_219) {
241                 /* DSIa */
242                 gpio_set_value(cardhu_dsia_bl_enb, !!brightness);
243         } else if (is_panel_1506) {
244                 /* DSIa */
245                 gpio_set_value(e1506_bl_enb, !!brightness);
246         }
247
248         /* SD brightness is a percentage, 8-bit value. */
249         brightness = (brightness * cur_sd_brightness) / 255;
250
251         /* Apply any backlight response curve */
252         if (brightness > 255) {
253                 pr_info("Error: Brightness > 255!\n");
254         } else {
255                 brightness = bl_output[brightness];
256         }
257
258         return brightness;
259 }
260
261 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info);
262
263 static struct platform_pwm_backlight_data cardhu_backlight_data = {
264         .pwm_id         = 0,
265         .max_brightness = 255,
266         .dft_brightness = 224,
267         .pwm_period_ns  = 1000000,
268         .init           = cardhu_backlight_init,
269         .exit           = cardhu_backlight_exit,
270         .notify         = cardhu_backlight_notify,
271         /* Only toggle backlight on fb blank notifications for disp1 */
272         .check_fb       = cardhu_disp1_check_fb,
273 };
274
275 static struct platform_device cardhu_backlight_device = {
276         .name   = "pwm-backlight",
277         .id     = -1,
278         .dev    = {
279                 .platform_data = &cardhu_backlight_data,
280         },
281 };
282
283 static int cardhu_panel_enable(void)
284 {
285         if (cardhu_lvds_reg == NULL) {
286                 cardhu_lvds_reg = regulator_get(NULL, "vdd_lvds");
287                 if (WARN_ON(IS_ERR(cardhu_lvds_reg)))
288                         pr_err("%s: couldn't get regulator vdd_lvds: %ld\n",
289                                 __func__, PTR_ERR(cardhu_lvds_reg));
290                 else
291                         regulator_enable(cardhu_lvds_reg);
292         }
293
294         if (cardhu_lvds_vdd_bl == NULL) {
295                 cardhu_lvds_vdd_bl = regulator_get(NULL, "vdd_backlight");
296                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_bl)))
297                         pr_err("%s: couldn't get regulator vdd_backlight: %ld\n",
298                                 __func__, PTR_ERR(cardhu_lvds_vdd_bl));
299                 else
300                         regulator_enable(cardhu_lvds_vdd_bl);
301         }
302
303         if (cardhu_lvds_vdd_panel == NULL) {
304                 cardhu_lvds_vdd_panel = regulator_get(NULL, "vdd_lcd_panel");
305                 if (WARN_ON(IS_ERR(cardhu_lvds_vdd_panel)))
306                         pr_err("%s: couldn't get regulator vdd_lcd_panel: %ld\n",
307                                 __func__, PTR_ERR(cardhu_lvds_vdd_panel));
308                 else
309                         regulator_enable(cardhu_lvds_vdd_panel);
310         }
311
312         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
313                 /* lvds configuration */
314                 gpio_set_value(pm313_R_FDE, 1);
315                 gpio_set_value(pm313_R_FB, 1);
316                 gpio_set_value(pm313_MODE0, 1);
317                 gpio_set_value(pm313_MODE1, 0);
318                 gpio_set_value(pm313_BPP, PM313_LVDS_PANEL_BPP);
319
320                 /* FIXME : it may require more or less delay for latching
321                   values correctly before enabling RGB2LVDS */
322                 mdelay(100);
323                 gpio_set_value(pm313_lvds_shutdown, 1);
324         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
325                         board_info.board_id == BOARD_PM269) ||
326                         (board_info.board_id == BOARD_E1257) ||
327                         (board_info.board_id == BOARD_PM305) ||
328                         (board_info.board_id == BOARD_PM311))
329                 gpio_set_value(e1247_pm269_lvds_shutdown, 1);
330         else
331                 gpio_set_value(cardhu_lvds_shutdown, 1);
332
333         return 0;
334 }
335
336 static int cardhu_panel_disable(void)
337 {
338         regulator_disable(cardhu_lvds_reg);
339         regulator_put(cardhu_lvds_reg);
340         cardhu_lvds_reg = NULL;
341
342         regulator_disable(cardhu_lvds_vdd_bl);
343         regulator_put(cardhu_lvds_vdd_bl);
344         cardhu_lvds_vdd_bl = NULL;
345
346         regulator_disable(cardhu_lvds_vdd_panel);
347         regulator_put(cardhu_lvds_vdd_panel);
348
349         cardhu_lvds_vdd_panel= NULL;
350
351         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
352                 gpio_set_value(pm313_lvds_shutdown, 0);
353         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
354                         board_info.board_id == BOARD_PM269) ||
355                         (board_info.board_id == BOARD_E1257) ||
356                         (board_info.board_id == BOARD_PM305) ||
357                         (board_info.board_id == BOARD_PM311)) {
358                 gpio_set_value(e1247_pm269_lvds_shutdown, 0);
359         } else {
360                 gpio_set_value(cardhu_lvds_shutdown, 0);
361         }
362         return 0;
363 }
364
365 #ifdef CONFIG_TEGRA_DC
366 static int cardhu_hdmi_vddio_enable(void)
367 {
368         int ret;
369         if (!cardhu_hdmi_vddio) {
370                 cardhu_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
371                 if (IS_ERR_OR_NULL(cardhu_hdmi_vddio)) {
372                         ret = PTR_ERR(cardhu_hdmi_vddio);
373                         pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
374                         cardhu_hdmi_vddio = NULL;
375                         return ret;
376                 }
377         }
378         ret = regulator_enable(cardhu_hdmi_vddio);
379         if (ret < 0) {
380                 pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
381                 regulator_put(cardhu_hdmi_vddio);
382                 cardhu_hdmi_vddio = NULL;
383                 return ret;
384         }
385         return ret;
386 }
387
388 static int cardhu_hdmi_vddio_disable(void)
389 {
390         if (cardhu_hdmi_vddio) {
391                 regulator_disable(cardhu_hdmi_vddio);
392                 regulator_put(cardhu_hdmi_vddio);
393                 cardhu_hdmi_vddio = NULL;
394         }
395         return 0;
396 }
397
398 static int cardhu_hdmi_enable(void)
399 {
400         int ret;
401         if (!cardhu_hdmi_reg) {
402                 cardhu_hdmi_reg = regulator_get(NULL, "avdd_hdmi");
403                 if (IS_ERR_OR_NULL(cardhu_hdmi_reg)) {
404                         pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
405                         cardhu_hdmi_reg = NULL;
406                         return PTR_ERR(cardhu_hdmi_reg);
407                 }
408         }
409         ret = regulator_enable(cardhu_hdmi_reg);
410         if (ret < 0) {
411                 pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
412                 return ret;
413         }
414         if (!cardhu_hdmi_pll) {
415                 cardhu_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll");
416                 if (IS_ERR_OR_NULL(cardhu_hdmi_pll)) {
417                         pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
418                         cardhu_hdmi_pll = NULL;
419                         regulator_put(cardhu_hdmi_reg);
420                         cardhu_hdmi_reg = NULL;
421                         return PTR_ERR(cardhu_hdmi_pll);
422                 }
423         }
424         ret = regulator_enable(cardhu_hdmi_pll);
425         if (ret < 0) {
426                 pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
427                 return ret;
428         }
429         return 0;
430 }
431
432 static int cardhu_hdmi_disable(void)
433 {
434         regulator_disable(cardhu_hdmi_reg);
435         regulator_put(cardhu_hdmi_reg);
436         cardhu_hdmi_reg = NULL;
437
438         regulator_disable(cardhu_hdmi_pll);
439         regulator_put(cardhu_hdmi_pll);
440         cardhu_hdmi_pll = NULL;
441         return 0;
442 }
443
444 static struct resource cardhu_disp1_resources[] = {
445         {
446                 .name   = "irq",
447                 .start  = INT_DISPLAY_GENERAL,
448                 .end    = INT_DISPLAY_GENERAL,
449                 .flags  = IORESOURCE_IRQ,
450         },
451         {
452                 .name   = "regs",
453                 .start  = TEGRA_DISPLAY_BASE,
454                 .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
455                 .flags  = IORESOURCE_MEM,
456         },
457         {
458                 .name   = "fbmem",
459                 .start  = 0,    /* Filled in by cardhu_panel_init() */
460                 .end    = 0,    /* Filled in by cardhu_panel_init() */
461                 .flags  = IORESOURCE_MEM,
462         },
463 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
464         {
465                 .name   = "dsi_regs",
466                 .start  = TEGRA_DSIB_BASE,
467                 .end    = TEGRA_DSIB_BASE + TEGRA_DSIB_SIZE - 1,
468                 .flags  = IORESOURCE_MEM,
469         },
470 #else
471         {
472                 .name   = "dsi_regs",
473                 .start  = TEGRA_DSI_BASE,
474                 .end    = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1,
475                 .flags  = IORESOURCE_MEM,
476         },
477 #endif
478 };
479
480 static struct resource cardhu_disp2_resources[] = {
481         {
482                 .name   = "irq",
483                 .start  = INT_DISPLAY_B_GENERAL,
484                 .end    = INT_DISPLAY_B_GENERAL,
485                 .flags  = IORESOURCE_IRQ,
486         },
487         {
488                 .name   = "regs",
489                 .start  = TEGRA_DISPLAY2_BASE,
490                 .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
491                 .flags  = IORESOURCE_MEM,
492         },
493         {
494                 .name   = "fbmem",
495                 .flags  = IORESOURCE_MEM,
496                 .start  = 0,
497                 .end    = 0,
498         },
499         {
500                 .name   = "hdmi_regs",
501                 .start  = TEGRA_HDMI_BASE,
502                 .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
503                 .flags  = IORESOURCE_MEM,
504         },
505 };
506 #endif
507
508 static struct tegra_dc_mode panel_19X12_modes[] = {
509         {
510                 .pclk = 154000000,
511                 .h_ref_to_sync = 11,
512                 .v_ref_to_sync = 1,
513                 .h_sync_width = 32,
514                 .v_sync_width = 6,
515                 .h_back_porch = 80,
516                 .v_back_porch = 26,
517                 .h_active = 1920,
518                 .v_active = 1200,
519                 .h_front_porch = 48,
520                 .v_front_porch = 3,
521         },
522 };
523
524 static struct tegra_dc_mode cardhu_panel_modes[] = {
525         {
526                 /* 1366x768@60Hz */
527                 .pclk = 74180000,
528                 .h_ref_to_sync = 1,
529                 .v_ref_to_sync = 1,
530                 .h_sync_width = 30,
531                 .v_sync_width = 5,
532                 .h_back_porch = 52,
533                 .v_back_porch = 20,
534                 .h_active = 1366,
535                 .v_active = 768,
536                 .h_front_porch = 64,
537                 .v_front_porch = 25,
538         },
539         {
540                 /* 1366x768@50Hz */
541                 .pclk = 74180000,
542                 .h_ref_to_sync = 1,
543                 .v_ref_to_sync = 1,
544                 .h_sync_width = 30,
545                 .v_sync_width = 5,
546                 .h_back_porch = 56,
547                 .v_back_porch = 80,
548                 .h_active = 1366,
549                 .v_active = 768,
550                 .h_front_porch = 64,
551                 .v_front_porch = 125,
552         },
553         {
554                 /* 1366x768@48 */
555                 .pclk = 74180000,
556                 .h_ref_to_sync = 1,
557                 .v_ref_to_sync = 1,
558                 .h_sync_width = 30,
559                 .v_sync_width = 5,
560                 .h_back_porch = 52,
561                 .v_back_porch = 98,
562                 .h_active = 1366,
563                 .v_active = 768,
564                 .h_front_porch = 64,
565                 .v_front_porch = 152,
566         },
567 };
568
569 static struct tegra_dc_mode cardhu_panel_modes_55hz[] = {
570         {
571                 /* 1366x768p 55Hz */
572                 .pclk = 68000000,
573                 .h_ref_to_sync = 0,
574                 .v_ref_to_sync = 12,
575                 .h_sync_width = 30,
576                 .v_sync_width = 5,
577                 .h_back_porch = 52,
578                 .v_back_porch = 20,
579                 .h_active = 1366,
580                 .v_active = 768,
581                 .h_front_porch = 64,
582                 .v_front_porch = 25,
583         },
584 };
585
586 static struct tegra_dc_sd_settings cardhu_sd_settings = {
587         .enable = 1, /* enabled by default. */
588         .use_auto_pwm = false,
589         .hw_update_delay = 0,
590         .bin_width = -1,
591         .aggressiveness = 1,
592         .phase_in_adjustments = true,
593         .use_vid_luma = false,
594         /* Default video coefficients */
595         .coeff = {5, 9, 2},
596         .fc = {0, 0},
597         /* Immediate backlight changes */
598         .blp = {1024, 255},
599         /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
600         /* Default BL TF */
601         .bltf = {
602                         {
603                                 {57, 65, 74, 83},
604                                 {93, 103, 114, 126},
605                                 {138, 151, 165, 179},
606                                 {194, 209, 225, 242},
607                         },
608                         {
609                                 {58, 66, 75, 84},
610                                 {94, 105, 116, 127},
611                                 {140, 153, 166, 181},
612                                 {196, 211, 227, 244},
613                         },
614                         {
615                                 {60, 68, 77, 87},
616                                 {97, 107, 119, 130},
617                                 {143, 156, 170, 184},
618                                 {199, 215, 231, 248},
619                         },
620                         {
621                                 {64, 73, 82, 91},
622                                 {102, 113, 124, 137},
623                                 {149, 163, 177, 192},
624                                 {207, 223, 240, 255},
625                         },
626                 },
627         /* Default LUT */
628         .lut = {
629                         {
630                                 {250, 250, 250},
631                                 {194, 194, 194},
632                                 {149, 149, 149},
633                                 {113, 113, 113},
634                                 {82, 82, 82},
635                                 {56, 56, 56},
636                                 {34, 34, 34},
637                                 {15, 15, 15},
638                                 {0, 0, 0},
639                         },
640                         {
641                                 {246, 246, 246},
642                                 {191, 191, 191},
643                                 {147, 147, 147},
644                                 {111, 111, 111},
645                                 {80, 80, 80},
646                                 {55, 55, 55},
647                                 {33, 33, 33},
648                                 {14, 14, 14},
649                                 {0, 0, 0},
650                         },
651                         {
652                                 {239, 239, 239},
653                                 {185, 185, 185},
654                                 {142, 142, 142},
655                                 {107, 107, 107},
656                                 {77, 77, 77},
657                                 {52, 52, 52},
658                                 {30, 30, 30},
659                                 {12, 12, 12},
660                                 {0, 0, 0},
661                         },
662                         {
663                                 {224, 224, 224},
664                                 {173, 173, 173},
665                                 {133, 133, 133},
666                                 {99, 99, 99},
667                                 {70, 70, 70},
668                                 {46, 46, 46},
669                                 {25, 25, 25},
670                                 {7, 7, 7},
671                                 {0, 0, 0},
672                         },
673                 },
674         .sd_brightness = &sd_brightness,
675         .bl_device = &cardhu_backlight_device,
676 };
677
678 #ifdef CONFIG_TEGRA_DC
679 static struct tegra_fb_data cardhu_fb_data = {
680         .win            = 0,
681         .xres           = 1366,
682         .yres           = 768,
683 #ifdef CONFIG_TEGRA_DC_USE_HW_BPP
684         .bits_per_pixel = -1,
685 #else
686         .bits_per_pixel = 32,
687 #endif
688         .flags          = TEGRA_FB_FLIP_ON_PROBE,
689 };
690
691 static struct tegra_fb_data cardhu_hdmi_fb_data = {
692         .win            = 0,
693         .xres           = 640,
694         .yres           = 480,
695 #ifdef CONFIG_TEGRA_DC_USE_HW_BPP
696         .bits_per_pixel = -1,
697 #else
698         .bits_per_pixel = 32,
699 #endif
700         .flags          = TEGRA_FB_FLIP_ON_PROBE,
701 };
702
703 static struct tegra_dc_out cardhu_disp2_out = {
704         .type           = TEGRA_DC_OUT_HDMI,
705         .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
706         .parent_clk     = "pll_d2_out0",
707
708         .dcc_bus        = 3,
709         .hotplug_gpio   = cardhu_hdmi_hpd,
710
711         .max_pixclock   = KHZ2PICOS(148500),
712
713         .align          = TEGRA_DC_ALIGN_MSB,
714         .order          = TEGRA_DC_ORDER_RED_BLUE,
715
716         .enable         = cardhu_hdmi_enable,
717         .disable        = cardhu_hdmi_disable,
718
719         .postsuspend    = cardhu_hdmi_vddio_disable,
720         .hotplug_init   = cardhu_hdmi_vddio_enable,
721 };
722
723 static struct tegra_dc_platform_data cardhu_disp2_pdata = {
724         .flags          = TEGRA_DC_FLAG_ENABLED,
725         .default_out    = &cardhu_disp2_out,
726         .fb             = &cardhu_hdmi_fb_data,
727         .emc_clk_rate   = 300000000,
728 };
729 #endif
730
731 static int cardhu_dsi_panel_enable(void)
732 {
733         int ret;
734
735         if (cardhu_dsi_reg == NULL) {
736                 cardhu_dsi_reg = regulator_get(NULL, "avdd_dsi_csi");
737                 if (IS_ERR_OR_NULL(cardhu_dsi_reg)) {
738                         pr_err("dsi: Could not get regulator avdd_dsi_csi\n");
739                         cardhu_dsi_reg = NULL;
740                         return PTR_ERR(cardhu_dsi_reg);
741                 }
742         }
743
744         regulator_enable(cardhu_dsi_reg);
745
746         if (!is_panel_1506) {
747                 ret = gpio_request(AVDD_LCD, "avdd_lcd");
748                 if (ret < 0)
749                         gpio_free(AVDD_LCD);
750                 ret = gpio_direction_output(AVDD_LCD, 1);
751                 if (ret < 0)
752                         gpio_free(AVDD_LCD);
753         }
754
755         if (is_panel_219) {
756                 ret = gpio_request(cardhu_bl_pwm, "bl_pwm");
757                 if (ret < 0)
758                         return ret;
759                 ret = gpio_direction_output(cardhu_bl_pwm, 0);
760                 if (ret < 0) {
761                         gpio_free(cardhu_bl_pwm);
762                         return ret;
763                 }
764
765                 ret = gpio_request(cardhu_bl_enb, "bl_enb");
766                 if (ret < 0)
767                         return ret;
768                 ret = gpio_direction_output(cardhu_bl_enb, 0);
769                 if (ret < 0) {
770                         gpio_free(cardhu_bl_enb);
771                         return ret;
772                 }
773
774                 gpio_set_value(cardhu_lvds_shutdown, 1);
775                 mdelay(20);
776                 gpio_set_value(cardhu_bl_pwm, 1);
777                 mdelay(10);
778                 gpio_set_value(cardhu_bl_enb, 1);
779                 mdelay(15);
780         } else if (is_panel_1506) {
781                 ret = gpio_request(e1506_dsi_vddio, "e1506_dsi_vddio");
782                 if (ret < 0)
783                         return ret;
784                 ret = gpio_direction_output(e1506_dsi_vddio, 0);
785                 if (ret < 0) {
786                         gpio_free(e1506_dsi_vddio);
787                         return ret;
788                 }
789
790                 ret = gpio_request(e1506_panel_enb, "e1506_panel_enb");
791                 if (ret < 0)
792                         return ret;
793                 ret = gpio_direction_output(e1506_panel_enb, 0);
794                 if (ret < 0) {
795                         gpio_free(e1506_panel_enb);
796                         return ret;
797                 }
798
799                 ret = gpio_request(e1506_bl_enb, "e1506_bl_enb");
800                 if (ret < 0)
801                         return ret;
802                 ret = gpio_direction_output(e1506_bl_enb, 0);
803                 if (ret < 0) {
804                         gpio_free(e1506_bl_enb);
805                         return ret;
806                 }
807
808                 gpio_set_value(e1506_dsi_vddio, 1);
809                 mdelay(1);
810                 gpio_set_value(e1506_panel_enb, 1);
811                 mdelay(10);
812                 gpio_set_value(e1506_bl_enb, 1);
813                 mdelay(15);
814         }
815
816 #if DSI_PANEL_RESET
817         if (is_panel_218) {
818                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
819                 if (ret < 0)
820                         return ret;
821
822                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
823                 if (ret < 0) {
824                         gpio_free(cardhu_dsi_pnl_reset);
825                         return ret;
826                 }
827
828                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
829                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
830                 mdelay(2);
831                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
832                 mdelay(2);
833         } else if (is_panel_219) {
834                 ret = gpio_request(cardhu_dsi_219_pnl_reset, "dsi_panel_reset");
835                 if (ret < 0)
836                         return ret;
837                 ret = gpio_direction_output(cardhu_dsi_219_pnl_reset, 0);
838                 if (ret < 0) {
839                         gpio_free(cardhu_dsi_219_pnl_reset);
840                         return ret;
841                 }
842
843                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
844                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
845                 mdelay(10);
846                 gpio_set_value(cardhu_dsi_219_pnl_reset, 0);
847                 mdelay(10);
848                 gpio_set_value(cardhu_dsi_219_pnl_reset, 1);
849                 mdelay(15);
850         } else if (is_panel_1506) {
851                 ret = gpio_request(cardhu_dsi_pnl_reset, "dsi_panel_reset");
852                 if (ret < 0)
853                         return ret;
854                 ret = gpio_direction_output(cardhu_dsi_pnl_reset, 0);
855                 if (ret < 0) {
856                         gpio_free(cardhu_dsi_pnl_reset);
857                         return ret;
858                 }
859
860                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
861                 mdelay(1);
862                 gpio_set_value(cardhu_dsi_pnl_reset, 0);
863                 mdelay(1);
864                 gpio_set_value(cardhu_dsi_pnl_reset, 1);
865                 mdelay(20);
866         }
867 #endif
868
869         return 0;
870 }
871
872 static int cardhu_dsi_panel_disable(void)
873 {
874         int err;
875
876         err = 0;
877
878         if (is_panel_219) {
879                 gpio_free(cardhu_dsi_219_pnl_reset);
880                 gpio_free(cardhu_bl_enb);
881                 gpio_free(cardhu_bl_pwm);
882                 gpio_free(cardhu_lvds_shutdown);
883         } else if (is_panel_218) {
884                 gpio_free(cardhu_dsi_pnl_reset);
885         } else if (is_panel_1506) {
886                 gpio_free(e1506_bl_enb);
887                 gpio_free(cardhu_dsi_pnl_reset);
888                 gpio_free(e1506_panel_enb);
889                 gpio_free(e1506_dsi_vddio);
890         }
891         return err;
892 }
893
894 static int cardhu_dsi_panel_postsuspend(void)
895 {
896         int err;
897
898         err = 0;
899         printk(KERN_INFO "DSI panel postsuspend\n");
900
901         if (cardhu_dsi_reg) {
902                 err = regulator_disable(cardhu_dsi_reg);
903                 if (err < 0)
904                         printk(KERN_ERR
905                         "DSI regulator avdd_dsi_csi disable failed\n");
906                 regulator_put(cardhu_dsi_reg);
907                 cardhu_dsi_reg = NULL;
908         }
909
910         if (is_panel_218)
911                 gpio_free(AVDD_LCD);
912
913         return err;
914 }
915
916 static struct tegra_dsi_cmd dsi_init_cmd[] = {
917         DSI_CMD_SHORT(0x05, 0x11, 0x00),
918         DSI_DLY_MS(150),
919 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
920         DSI_CMD_SHORT(0x15, 0x35, 0x00),
921 #endif
922         DSI_CMD_SHORT(0x05, 0x29, 0x00),
923         DSI_DLY_MS(20),
924 };
925
926 u8 password_array[] = {0xb9, 0xff, 0x83, 0x92};
927
928 static struct tegra_dsi_cmd dsi_init_cmd_1506[] = {
929         DSI_CMD_SHORT(0x05, 0x11, 0x00),
930         DSI_DLY_MS(150),
931         DSI_CMD_LONG(0x39, password_array),
932         DSI_DLY_MS(10),
933         DSI_CMD_SHORT(0x15, 0xd4, 0x0c),
934         DSI_DLY_MS(10),
935         DSI_CMD_SHORT(0x15, 0xba, 0x11),
936         DSI_DLY_MS(10),
937 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
938         DSI_CMD_SHORT(0x15, 0x35, 0x00),
939 #endif
940         DSI_CMD_SHORT(0x05, 0x29, 0x00),
941         DSI_DLY_MS(20),
942 };
943
944 static struct tegra_dsi_cmd dsi_early_suspend_cmd[] = {
945         DSI_CMD_SHORT(0x05, 0x28, 0x00),
946         DSI_DLY_MS(20),
947 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
948         DSI_CMD_SHORT(0x05, 0x34, 0x00),
949 #endif
950 };
951
952 static struct tegra_dsi_cmd dsi_late_resume_cmd[] = {
953 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
954         DSI_CMD_SHORT(0x15, 0x35, 0x00),
955 #endif
956         DSI_CMD_SHORT(0x05, 0x29, 0x00),
957         DSI_DLY_MS(20),
958 };
959
960 static struct tegra_dsi_cmd dsi_suspend_cmd[] = {
961         DSI_CMD_SHORT(0x05, 0x28, 0x00),
962         DSI_DLY_MS(120),
963 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
964         DSI_CMD_SHORT(0x05, 0x34, 0x00),
965 #endif
966         DSI_CMD_SHORT(0x05, 0x10, 0x00),
967         DSI_DLY_MS(5),
968 };
969
970 static struct tegra_dsi_cmd dsi_suspend_cmd_1506[] = {
971         DSI_CMD_SHORT(0x05, 0x28, 0x00),
972         DSI_CMD_SHORT(0x05, 0x10, 0x00),
973         DSI_DLY_MS(120),
974 };
975
976 struct tegra_dsi_out cardhu_dsi = {
977         .n_data_lanes = 2,
978         .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P,
979
980 #if (DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
981         /*
982          * The one-shot frame time must be shorter than the time between TE.
983          * Increasing refresh_rate will result in a decrease in the frame time
984          * for one-shot. rated_refresh_rate is only an approximation of the
985          * TE rate, and is only used to report refresh rate to upper layers.
986          */
987         .refresh_rate = 66,
988         .rated_refresh_rate = 60,
989 #else
990         .refresh_rate = 60,
991 #endif
992         .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0,
993
994         .panel_has_frame_buffer = true,
995 #ifdef CONFIG_TEGRA_DSI_INSTANCE_1
996         .dsi_instance = 1,
997 #else
998         .dsi_instance = 0,
999 #endif
1000         .panel_reset = DSI_PANEL_RESET,
1001         .power_saving_suspend = true,
1002
1003         .n_early_suspend_cmd = ARRAY_SIZE(dsi_early_suspend_cmd),
1004         .dsi_early_suspend_cmd = dsi_early_suspend_cmd,
1005
1006         .n_late_resume_cmd = ARRAY_SIZE(dsi_late_resume_cmd),
1007         .dsi_late_resume_cmd = dsi_late_resume_cmd,
1008
1009         .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd),
1010         .dsi_suspend_cmd = dsi_suspend_cmd,
1011
1012         .video_data_type = TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE,
1013         .lp_cmd_mode_freq_khz = 430000,
1014 };
1015
1016 static struct tegra_dc_mode cardhu_dsi_modes_219[] = {
1017         {
1018                 .pclk = 10000000,
1019                 .h_ref_to_sync = 4,
1020                 .v_ref_to_sync = 1,
1021                 .h_sync_width = 16,
1022                 .v_sync_width = 1,
1023                 .h_back_porch = 32,
1024                 .v_back_porch = 1,
1025                 .h_active = 540,
1026                 .v_active = 960,
1027                 .h_front_porch = 32,
1028                 .v_front_porch = 2,
1029         },
1030 };
1031
1032 static struct tegra_dc_mode cardhu_dsi_modes_218[] = {
1033         {
1034                 .pclk = 323000000,
1035                 .h_ref_to_sync = 11,
1036                 .v_ref_to_sync = 1,
1037                 .h_sync_width = 16,
1038                 .v_sync_width = 4,
1039                 .h_back_porch = 16,
1040                 .v_back_porch = 4,
1041                 .h_active = 864,
1042                 .v_active = 480,
1043                 .h_front_porch = 16,
1044                 .v_front_porch = 4,
1045         },
1046 };
1047
1048 static struct tegra_dc_mode cardhu_dsi_modes_1506[] = {
1049         {
1050                 .pclk = 61417000,
1051                 .h_ref_to_sync = 2,
1052                 .v_ref_to_sync = 2,
1053                 .h_sync_width = 4,
1054                 .v_sync_width = 4,
1055                 .h_back_porch = 100,
1056                 .v_back_porch = 14,
1057                 .h_active = 720,
1058                 .v_active = 1280,
1059                 .h_front_porch = 4,
1060                 .v_front_porch = 4,
1061         },
1062 };
1063
1064
1065 static struct tegra_fb_data cardhu_dsi_fb_data = {
1066         .win            = 0,
1067         .bits_per_pixel = 32,
1068         .flags          = TEGRA_FB_FLIP_ON_PROBE,
1069 };
1070
1071 static struct tegra_dc_out cardhu_disp1_out = {
1072         .align          = TEGRA_DC_ALIGN_MSB,
1073         .order          = TEGRA_DC_ORDER_RED_BLUE,
1074         .sd_settings    = &cardhu_sd_settings,
1075         .parent_clk     = "pll_d_out0",
1076
1077 };
1078
1079 #ifdef CONFIG_TEGRA_DC
1080 static struct tegra_dc_platform_data cardhu_disp1_pdata = {
1081         .flags          = TEGRA_DC_FLAG_ENABLED,
1082         .default_out    = &cardhu_disp1_out,
1083         .emc_clk_rate   = 300000000,
1084 };
1085
1086 static struct nvhost_device cardhu_disp1_device = {
1087         .name           = "tegradc",
1088         .id             = 0,
1089         .resource       = cardhu_disp1_resources,
1090         .num_resources  = ARRAY_SIZE(cardhu_disp1_resources),
1091         .dev = {
1092                 .platform_data = &cardhu_disp1_pdata,
1093         },
1094 };
1095
1096 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1097 {
1098         return info->device == &cardhu_disp1_device.dev;
1099 }
1100
1101 static struct nvhost_device cardhu_disp2_device = {
1102         .name           = "tegradc",
1103         .id             = 1,
1104         .resource       = cardhu_disp2_resources,
1105         .num_resources  = ARRAY_SIZE(cardhu_disp2_resources),
1106         .dev = {
1107                 .platform_data = &cardhu_disp2_pdata,
1108         },
1109 };
1110 #else
1111 static int cardhu_disp1_check_fb(struct device *dev, struct fb_info *info)
1112 {
1113         return 0;
1114 }
1115 #endif
1116
1117 #if defined(CONFIG_TEGRA_NVMAP)
1118 static struct nvmap_platform_carveout cardhu_carveouts[] = {
1119         [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
1120         [1] = {
1121                 .name           = "generic-0",
1122                 .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
1123                 .base           = 0,    /* Filled in by cardhu_panel_init() */
1124                 .size           = 0,    /* Filled in by cardhu_panel_init() */
1125                 .buddy_size     = SZ_32K,
1126         },
1127 };
1128
1129 static struct nvmap_platform_data cardhu_nvmap_data = {
1130         .carveouts      = cardhu_carveouts,
1131         .nr_carveouts   = ARRAY_SIZE(cardhu_carveouts),
1132 };
1133
1134 static struct platform_device cardhu_nvmap_device = {
1135         .name   = "tegra-nvmap",
1136         .id     = -1,
1137         .dev    = {
1138                 .platform_data = &cardhu_nvmap_data,
1139         },
1140 };
1141 #endif
1142
1143 #if defined(CONFIG_ION_TEGRA)
1144
1145 static struct platform_device tegra_iommu_device = {
1146         .name = "tegra_iommu_device",
1147         .id = -1,
1148         .dev = {
1149                 .platform_data = (void *)((1 << HWGRP_COUNT) - 1),
1150         },
1151 };
1152
1153 static struct ion_platform_data tegra_ion_data = {
1154         .nr = 4,
1155         .heaps = {
1156                 {
1157                         .type = ION_HEAP_TYPE_CARVEOUT,
1158                         .id = TEGRA_ION_HEAP_CARVEOUT,
1159                         .name = "carveout",
1160                         .base = 0,
1161                         .size = 0,
1162                 },
1163                 {
1164                         .type = ION_HEAP_TYPE_CARVEOUT,
1165                         .id = TEGRA_ION_HEAP_IRAM,
1166                         .name = "iram",
1167                         .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
1168                         .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
1169                 },
1170                 {
1171                         .type = ION_HEAP_TYPE_CARVEOUT,
1172                         .id = TEGRA_ION_HEAP_VPR,
1173                         .name = "vpr",
1174                         .base = 0,
1175                         .size = 0,
1176                 },
1177                 {
1178                         .type = ION_HEAP_TYPE_IOMMU,
1179                         .id = TEGRA_ION_HEAP_IOMMU,
1180                         .name = "iommu",
1181                         .base = TEGRA_SMMU_BASE,
1182                         .size = TEGRA_SMMU_SIZE,
1183                         .priv = &tegra_iommu_device.dev,
1184                 },
1185         },
1186 };
1187
1188 static struct platform_device tegra_ion_device = {
1189         .name = "ion-tegra",
1190         .id = -1,
1191         .dev = {
1192                 .platform_data = &tegra_ion_data,
1193         },
1194 };
1195 #endif
1196
1197 static struct platform_device *cardhu_gfx_devices[] __initdata = {
1198 #if defined(CONFIG_TEGRA_NVMAP)
1199         &cardhu_nvmap_device,
1200 #endif
1201 #if defined(CONFIG_ION_TEGRA)
1202         &tegra_ion_device,
1203 #endif
1204         &tegra_pwfm0_device,
1205         &cardhu_backlight_device,
1206 };
1207
1208 static void cardhu_panel_preinit(void)
1209 {
1210         if (display_board_info.board_id == BOARD_DISPLAY_E1213)
1211                 is_panel_218 = true;
1212         else if (display_board_info.board_id == BOARD_DISPLAY_E1253)
1213                 is_panel_219 = true;
1214         else if (display_board_info.board_id == BOARD_DISPLAY_E1506)
1215                 is_panel_1506 = true;
1216
1217         if (!is_dsi_panel()) {
1218                 cardhu_disp1_out.parent_clk_backup = "pll_d2_out0";
1219                 cardhu_disp1_out.type = TEGRA_DC_OUT_RGB;
1220                 cardhu_disp1_out.depth = 18;
1221                 cardhu_disp1_out.dither = TEGRA_DC_ORDERED_DITHER;
1222                 cardhu_disp1_out.modes = cardhu_panel_modes;
1223                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes);
1224                 cardhu_disp1_out.enable = cardhu_panel_enable;
1225                 cardhu_disp1_out.disable = cardhu_panel_disable;
1226                 /* Set height and width in mm. */
1227                 cardhu_disp1_out.height = 125;
1228                 cardhu_disp1_out.width = 223;
1229
1230                 cardhu_disp1_pdata.fb = &cardhu_fb_data;
1231         } else {
1232                 cardhu_disp1_out.flags = DC_CTRL_MODE;
1233                 cardhu_disp1_out.type = TEGRA_DC_OUT_DSI;
1234                 cardhu_disp1_out.dsi = &cardhu_dsi;
1235                 cardhu_disp1_out.enable = cardhu_dsi_panel_enable;
1236                 cardhu_disp1_out.disable = cardhu_dsi_panel_disable;
1237                 cardhu_disp1_out.postsuspend = cardhu_dsi_panel_postsuspend;
1238
1239                 cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd);
1240                 cardhu_dsi.dsi_init_cmd = dsi_init_cmd;
1241                 cardhu_dsi.n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd);
1242                 cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd;
1243
1244                 if (is_panel_218) {
1245                         cardhu_disp1_out.modes  = cardhu_dsi_modes_218;
1246                         cardhu_disp1_out.n_modes =
1247                                 ARRAY_SIZE(cardhu_dsi_modes_218);
1248                         cardhu_dsi_fb_data.xres = 864;
1249                         cardhu_dsi_fb_data.yres = 480;
1250                         /* Set height and width in mm. */
1251                         cardhu_disp1_out.height = 47;
1252                         cardhu_disp1_out.width = 84;
1253                 } else if (is_panel_219) {
1254                         cardhu_disp1_out.modes  = cardhu_dsi_modes_219;
1255                         cardhu_disp1_out.n_modes =
1256                                 ARRAY_SIZE(cardhu_dsi_modes_219);
1257                         cardhu_dsi_fb_data.xres = 540;
1258                         cardhu_dsi_fb_data.yres = 960;
1259                         /* Set height and width in mm. */
1260                         cardhu_disp1_out.height = 95;
1261                         cardhu_disp1_out.width = 53;
1262                 } else if (is_panel_1506) {
1263                         cardhu_disp1_out.modes  = cardhu_dsi_modes_1506;
1264                         cardhu_disp1_out.n_modes =
1265                                 ARRAY_SIZE(cardhu_dsi_modes_1506);
1266                         cardhu_dsi.n_init_cmd = ARRAY_SIZE(dsi_init_cmd_1506);
1267                         cardhu_dsi.dsi_init_cmd = dsi_init_cmd_1506;
1268                         cardhu_dsi.n_suspend_cmd =
1269                                 ARRAY_SIZE(dsi_suspend_cmd_1506);
1270                         cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd_1506;
1271                         cardhu_dsi.panel_send_dc_frames = true;
1272                         cardhu_dsi.suspend_aggr = DSI_HOST_SUSPEND_LV0;
1273                         cardhu_dsi_fb_data.xres = 720;
1274                         cardhu_dsi_fb_data.yres = 1280;
1275                         /* Set height and width in mm. */
1276                         cardhu_disp1_out.height = 95;
1277                         cardhu_disp1_out.width = 53;
1278                 }
1279
1280                 cardhu_disp1_pdata.fb = &cardhu_dsi_fb_data;
1281         }
1282 }
1283
1284 int __init cardhu_panel_init(void)
1285 {
1286         int err;
1287         struct resource __maybe_unused *res;
1288
1289         tegra_get_board_info(&board_info);
1290         tegra_get_display_board_info(&display_board_info);
1291
1292 #if defined(CONFIG_TEGRA_NVMAP)
1293         cardhu_carveouts[1].base = tegra_carveout_start;
1294         cardhu_carveouts[1].size = tegra_carveout_size;
1295 #endif
1296
1297 #if defined(CONFIG_ION_TEGRA)
1298         tegra_ion_data.heaps[0].base = tegra_carveout_start;
1299         tegra_ion_data.heaps[0].size = tegra_carveout_size;
1300 #endif
1301
1302         cardhu_panel_preinit();
1303         if (is_dsi_panel()) {
1304                 if (is_panel_1506) {
1305                         /*
1306                          * HACK: To be Removed
1307                          */
1308                         int i;
1309                         struct clk *c = tegra_get_clock_by_name("dsia");
1310
1311                         for (i = 0; i < c->dvfs->num_freqs; i++)
1312                                 c->dvfs->freqs[i] = 500000000;
1313                 }
1314                 goto skip_lvds;
1315         }
1316 #if defined(CONFIG_TEGRA_DC)
1317         if (WARN_ON(board_info.board_id == BOARD_E1291 &&
1318                 ((board_info.sku & SKU_TOUCHSCREEN_MECH_FIX) == 0))) {
1319                 /* use 55Hz panel timings to reduce noise on sensitive touch */
1320                 printk("Using cardhu_panel_modes_55hz\n");
1321                 cardhu_disp1_out.parent_clk = "pll_p";
1322                 cardhu_disp1_out.modes = cardhu_panel_modes_55hz;
1323                 cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes_55hz);
1324         }
1325
1326         if (display_board_info.board_id == BOARD_DISPLAY_PM313) {
1327                 /* initialize the values */
1328 #if defined(PM313_LVDS_PANEL_19X12)
1329                 cardhu_disp1_out.modes = panel_19X12_modes;
1330                 cardhu_disp1_out.n_modes = ARRAY_SIZE(panel_19X12_modes);
1331                 cardhu_disp1_out.parent_clk = "pll_d_out0";
1332 #if (PM313_LVDS_PANEL_BPP == 1)
1333                 cardhu_disp1_out.depth = 18;
1334 #else
1335                 cardhu_disp1_out.depth = 24;
1336 #endif
1337                 /* Set height and width in mm. */
1338                 cardhu_disp1_out.height = 135;
1339                 cardhu_disp1_out.width = 217;
1340                 cardhu_fb_data.xres = 1920;
1341                 cardhu_fb_data.yres = 1200;
1342
1343                 cardhu_disp2_out.parent_clk = "pll_d2_out0";
1344                 cardhu_hdmi_fb_data.xres = 1920;
1345                 cardhu_hdmi_fb_data.yres = 1200;
1346 #endif
1347
1348                 /* lvds configuration */
1349                 err = gpio_request(pm313_R_FDE, "R_FDE");
1350                 err |= gpio_direction_output(pm313_R_FDE, 1);
1351
1352                 err |= gpio_request(pm313_R_FB, "R_FB");
1353                 err |= gpio_direction_output(pm313_R_FB, 1);
1354
1355                 err |= gpio_request(pm313_MODE0, "MODE0");
1356                 err |= gpio_direction_output(pm313_MODE0, 1);
1357
1358                 err |= gpio_request(pm313_MODE1, "MODE1");
1359                 err |= gpio_direction_output(pm313_MODE1, 0);
1360
1361                 err |= gpio_request(pm313_BPP, "BPP");
1362                 err |= gpio_direction_output(pm313_BPP, PM313_LVDS_PANEL_BPP);
1363
1364                 err = gpio_request(pm313_lvds_shutdown, "lvds_shutdown");
1365                 /* free ride provided by bootloader */
1366                 err |= gpio_direction_output(pm313_lvds_shutdown, 1);
1367
1368                 if (err)
1369                         printk(KERN_ERR "ERROR(s) in LVDS configuration\n");
1370         } else if ((display_board_info.board_id == BOARD_DISPLAY_E1247 &&
1371                                 board_info.board_id == BOARD_PM269) ||
1372                                 (board_info.board_id == BOARD_E1257) ||
1373                                 (board_info.board_id == BOARD_PM305) ||
1374                                 (board_info.board_id == BOARD_PM311)) {
1375                 gpio_request(e1247_pm269_lvds_shutdown, "lvds_shutdown");
1376                 gpio_direction_output(e1247_pm269_lvds_shutdown, 1);
1377         } else {
1378                 gpio_request(cardhu_lvds_shutdown, "lvds_shutdown");
1379                 gpio_direction_output(cardhu_lvds_shutdown, 1);
1380         }
1381 #endif
1382
1383 skip_lvds:
1384         gpio_request(cardhu_hdmi_hpd, "hdmi_hpd");
1385         gpio_direction_input(cardhu_hdmi_hpd);
1386
1387 #if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE)
1388         gpio_request(e1506_lcd_te, "lcd_te");
1389         gpio_direction_input(e1506_lcd_te);
1390 #endif
1391
1392 #ifdef CONFIG_TEGRA_GRHOST
1393         err = tegra3_register_host1x_devices();
1394         if (err)
1395                 return err;
1396 #endif
1397
1398         err = platform_add_devices(cardhu_gfx_devices,
1399                                 ARRAY_SIZE(cardhu_gfx_devices));
1400
1401 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1402         res = nvhost_get_resource_byname(&cardhu_disp1_device,
1403                                          IORESOURCE_MEM, "fbmem");
1404         res->start = tegra_fb_start;
1405         res->end = tegra_fb_start + tegra_fb_size - 1;
1406 #endif
1407
1408         /* Copy the bootloader fb to the fb. */
1409         tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
1410                                 min(tegra_fb_size, tegra_bootloader_fb_size));
1411
1412 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
1413         if (!err)
1414                 err = nvhost_device_register(&cardhu_disp1_device);
1415
1416         res = nvhost_get_resource_byname(&cardhu_disp2_device,
1417                                          IORESOURCE_MEM, "fbmem");
1418         res->start = tegra_fb2_start;
1419         res->end = tegra_fb2_start + tegra_fb2_size - 1;
1420
1421         /* Copy the bootloader fb to the fb2. */
1422         tegra_move_framebuffer(tegra_fb2_start, tegra_bootloader_fb_start,
1423                                 min(tegra_fb2_size, tegra_bootloader_fb_size));
1424
1425         if (!err)
1426                 err = nvhost_device_register(&cardhu_disp2_device);
1427 #endif
1428
1429 #if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
1430         if (!err)
1431                 err = nvhost_device_register(&nvavp_device);
1432 #endif
1433         return err;
1434 }