ARM: tegra: cardhu: Add 533MHz entry to EMC DFS table
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-memory.c
1 /*
2  * Copyright (C) 2011 NVIDIA, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21
22 #include "board-cardhu.h"
23 #include "tegra3_emc.h"
24
25
26 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
27         {
28                 0x30,           /* Rev 3.0 */
29                 27000,          /* SDRAM frquency */
30                 {
31                         0x00000001,   /* EMC_RC */
32                         0x00000004,   /* EMC_RFC */
33                         0x00000000,   /* EMC_RAS */
34                         0x00000000,   /* EMC_RP */
35                         0x00000002,   /* EMC_R2W */
36                         0x0000000A,   /* EMC_W2R */
37                         0x00000003,   /* EMC_R2P */
38                         0x0000000B,   /* EMC_W2P */
39                         0x00000000,   /* EMC_RD_RCD */
40                         0x00000000,   /* EMC_WR_RCD */
41                         0x00000003,   /* EMC_RRD */
42                         0x00000001,   /* EMC_REXT */
43                         0x00000000,   /* EMC_WEXT */
44                         0x00000005,   /* EMC_WDV */
45                         0x00000003,   /* EMC_QUSE */
46                         0x00000004,   /* EMC_QRST */
47                         0x00000007,   /* EMC_QSAFE */
48                         0x0000000B,   /* EMC_RDV */
49                         0x000000CB,   /* EMC_REFRESH */
50                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
51                         0x00000032,   /* EMC_PRE_REFRESH_REQ_CNT */
52                         0x00000002,   /* EMC_PDEX2WR */
53                         0x00000002,   /* EMC_PDEX2RD */
54                         0x00000001,   /* EMC_PCHG2PDEN */
55                         0x00000000,   /* EMC_ACT2PDEN */
56                         0x00000007,   /* EMC_AR2PDEN */
57                         0x0000000F,   /* EMC_RW2PDEN */
58                         0x00000005,   /* EMC_TXSR */
59                         0x00000005,   /* EMC_TXSRDLL */
60                         0x00000004,   /* EMC_TCKE */
61                         0x00000001,   /* EMC_TFAW */
62                         0x00000000,   /* EMC_TRPAB */
63                         0x00000004,   /* EMC_TCLKSTABLE */
64                         0x00000005,   /* EMC_TCLKSTOP */
65                         0x000000D3,   /* EMC_TREFBW */
66                         0x00000000,   /* EMC_QUSE_EXTRA */
67                         0x00000004,   /* EMC_FBIO_CFG6 */
68                         0x00000000,   /* EMC_ODT_WRITE */
69                         0x00000000,   /* EMC_ODT_READ */
70                         0x00008088,   /* EMC_FBIO_CFG5 */
71                         0x00780004,   /* EMC_CFG_DIG_DLL */
72                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
73                         0x00000010,   /* EMC_DLL_XFORM_DQS0 */
74                         0x00000010,   /* EMC_DLL_XFORM_DQS1 */
75                         0x00000010,   /* EMC_DLL_XFORM_DQS2 */
76                         0x00000010,   /* EMC_DLL_XFORM_DQS3 */
77                         0x00000010,   /* EMC_DLL_XFORM_DQS4 */
78                         0x00000010,   /* EMC_DLL_XFORM_DQS5 */
79                         0x00000010,   /* EMC_DLL_XFORM_DQS6 */
80                         0x00000010,   /* EMC_DLL_XFORM_DQS7 */
81                         0x00000018,   /* EMC_DLL_XFORM_QUSE0 */
82                         0x00000018,   /* EMC_DLL_XFORM_QUSE1 */
83                         0x00000018,   /* EMC_DLL_XFORM_QUSE2 */
84                         0x00000018,   /* EMC_DLL_XFORM_QUSE3 */
85                         0x00000018,   /* EMC_DLL_XFORM_QUSE4 */
86                         0x00000018,   /* EMC_DLL_XFORM_QUSE5 */
87                         0x00000018,   /* EMC_DLL_XFORM_QUSE6 */
88                         0x00000018,   /* EMC_DLL_XFORM_QUSE7 */
89                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
90                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
91                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
92                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
93                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
94                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
95                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
96                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
97                         0x0000A010,   /* EMC_DLL_XFORM_DQ0 */
98                         0x0000A010,   /* EMC_DLL_XFORM_DQ1 */
99                         0x0000A010,   /* EMC_DLL_XFORM_DQ2 */
100                         0x0000A010,   /* EMC_DLL_XFORM_DQ3 */
101                         0x000002A0,   /* EMC_XM2CMDPADCTRL */
102                         0x0800211D,   /* EMC_XM2DQSPADCTRL2 */
103                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
104                         0x77FFC084,   /* EMC_XM2CLKPADCTRL */
105                         0x01F1F108,   /* EMC_XM2COMPPADCTRL */
106                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
107                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
108                         0x0800012D,   /* EMC_XM2QUSEPADCTRL */
109                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
110                         0x00000802,   /* EMC_CTT_TERM_CTRL */
111                         0x00000000,   /* EMC_ZCAL_INTERVAL */
112                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
113                         0x000C000C,   /* EMC_MRS_WAIT_CNT */
114                         0xE0F11111,   /* EMC_AUTO_CAL_CONFIG */
115                         0x00000000,   /* EMC_CTT */
116                         0x00000000,   /* EMC_CTT_DURATION */
117                         0x8000029E,   /* EMC_DYN_SELF_REF_CONTROL */
118                         0x00010001,   /* MC_EMEM_ARB_CFG */
119                         0x8000000A,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
120                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
121                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
122                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
123                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
124                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
125                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
126                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
127                         0x0000000F,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
128                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
129                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
130                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
131                         0x0000000F,   /* MC_EMEM_ARB_TIMING_W2R */
132                         0x0F070506,   /* MC_EMEM_ARB_DA_TURNS */
133                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
134                         0x78430306,   /* MC_EMEM_ARB_MISC0 */
135                         0x001F0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
136                 },
137                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
138                 0x00000000,     /* EMC_AUTO_CAL_INTERVAL */
139                 0x00001221,     /* DDR3 Mode Register 0 */
140                 0x00100003,     /* DDR3 Mode Register 1 */
141                 0x00200008,     /* DDR3 Mode Register 2 */
142         },
143         {
144                 0x30,           /* Rev 3.0 */
145                 54000,          /* SDRAM frquency */
146                 {
147                         0x00000002,   /* EMC_RC */
148                         0x00000008,   /* EMC_RFC */
149                         0x00000001,   /* EMC_RAS */
150                         0x00000000,   /* EMC_RP */
151                         0x00000002,   /* EMC_R2W */
152                         0x0000000A,   /* EMC_W2R */
153                         0x00000003,   /* EMC_R2P */
154                         0x0000000B,   /* EMC_W2P */
155                         0x00000000,   /* EMC_RD_RCD */
156                         0x00000000,   /* EMC_WR_RCD */
157                         0x00000003,   /* EMC_RRD */
158                         0x00000001,   /* EMC_REXT */
159                         0x00000000,   /* EMC_WEXT */
160                         0x00000005,   /* EMC_WDV */
161                         0x00000003,   /* EMC_QUSE */
162                         0x00000004,   /* EMC_QRST */
163                         0x00000007,   /* EMC_QSAFE */
164                         0x0000000B,   /* EMC_RDV */
165                         0x00000198,   /* EMC_REFRESH */
166                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
167                         0x00000066,   /* EMC_PRE_REFRESH_REQ_CNT */
168                         0x00000002,   /* EMC_PDEX2WR */
169                         0x00000002,   /* EMC_PDEX2RD */
170                         0x00000001,   /* EMC_PCHG2PDEN */
171                         0x00000000,   /* EMC_ACT2PDEN */
172                         0x00000007,   /* EMC_AR2PDEN */
173                         0x0000000F,   /* EMC_RW2PDEN */
174                         0x0000000A,   /* EMC_TXSR */
175                         0x0000000A,   /* EMC_TXSRDLL */
176                         0x00000004,   /* EMC_TCKE */
177                         0x00000002,   /* EMC_TFAW */
178                         0x00000000,   /* EMC_TRPAB */
179                         0x00000004,   /* EMC_TCLKSTABLE */
180                         0x00000005,   /* EMC_TCLKSTOP */
181                         0x000001A6,   /* EMC_TREFBW */
182                         0x00000000,   /* EMC_QUSE_EXTRA */
183                         0x00000004,   /* EMC_FBIO_CFG6 */
184                         0x00000000,   /* EMC_ODT_WRITE */
185                         0x00000000,   /* EMC_ODT_READ */
186                         0x00008088,   /* EMC_FBIO_CFG5 */
187                         0x00780004,   /* EMC_CFG_DIG_DLL */
188                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
189                         0x00000010,   /* EMC_DLL_XFORM_DQS0 */
190                         0x00000010,   /* EMC_DLL_XFORM_DQS1 */
191                         0x00000010,   /* EMC_DLL_XFORM_DQS2 */
192                         0x00000010,   /* EMC_DLL_XFORM_DQS3 */
193                         0x00000010,   /* EMC_DLL_XFORM_DQS4 */
194                         0x00000010,   /* EMC_DLL_XFORM_DQS5 */
195                         0x00000010,   /* EMC_DLL_XFORM_DQS6 */
196                         0x00000010,   /* EMC_DLL_XFORM_DQS7 */
197                         0x00000018,   /* EMC_DLL_XFORM_QUSE0 */
198                         0x00000018,   /* EMC_DLL_XFORM_QUSE1 */
199                         0x00000018,   /* EMC_DLL_XFORM_QUSE2 */
200                         0x00000018,   /* EMC_DLL_XFORM_QUSE3 */
201                         0x00000018,   /* EMC_DLL_XFORM_QUSE4 */
202                         0x00000018,   /* EMC_DLL_XFORM_QUSE5 */
203                         0x00000018,   /* EMC_DLL_XFORM_QUSE6 */
204                         0x00000018,   /* EMC_DLL_XFORM_QUSE7 */
205                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
206                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
207                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
208                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
209                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
210                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
211                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
212                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
213                         0x0000A010,   /* EMC_DLL_XFORM_DQ0 */
214                         0x0000A010,   /* EMC_DLL_XFORM_DQ1 */
215                         0x0000A010,   /* EMC_DLL_XFORM_DQ2 */
216                         0x0000A010,   /* EMC_DLL_XFORM_DQ3 */
217                         0x000002A0,   /* EMC_XM2CMDPADCTRL */
218                         0x0800211D,   /* EMC_XM2DQSPADCTRL2 */
219                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
220                         0x77FFC084,   /* EMC_XM2CLKPADCTRL */
221                         0x01F1F108,   /* EMC_XM2COMPPADCTRL */
222                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
223                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
224                         0x0800012D,   /* EMC_XM2QUSEPADCTRL */
225                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
226                         0x00000802,   /* EMC_CTT_TERM_CTRL */
227                         0x00000000,   /* EMC_ZCAL_INTERVAL */
228                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
229                         0x000C000C,   /* EMC_MRS_WAIT_CNT */
230                         0xE0F11111,   /* EMC_AUTO_CAL_CONFIG */
231                         0x00000000,   /* EMC_CTT */
232                         0x00000000,   /* EMC_CTT_DURATION */
233                         0x80000439,   /* EMC_DYN_SELF_REF_CONTROL */
234                         0x00000001,   /* MC_EMEM_ARB_CFG */
235                         0x80000014,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
236                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
237                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
238                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
239                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
240                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
241                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
242                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
243                         0x0000000F,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
244                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
245                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
246                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
247                         0x0000000F,   /* MC_EMEM_ARB_TIMING_W2R */
248                         0x0F070506,   /* MC_EMEM_ARB_DA_TURNS */
249                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
250                         0x78430506,   /* MC_EMEM_ARB_MISC0 */
251                         0x001F0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
252                 },
253                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
254                 0x00000000,     /* EMC_AUTO_CAL_INTERVAL */
255                 0x00001221,     /* DDR3 Mode Register 0 */
256                 0x00100003,     /* DDR3 Mode Register 1 */
257                 0x00200008,     /* DDR3 Mode Register 2 */
258         },
259         {
260                 0x30,           /* Rev 3.0 */
261                 108000,         /* SDRAM frquency */
262                 {
263                         0x00000005,   /* EMC_RC */
264                         0x00000011,   /* EMC_RFC */
265                         0x00000003,   /* EMC_RAS */
266                         0x00000001,   /* EMC_RP */
267                         0x00000002,   /* EMC_R2W */
268                         0x0000000A,   /* EMC_W2R */
269                         0x00000003,   /* EMC_R2P */
270                         0x0000000B,   /* EMC_W2P */
271                         0x00000001,   /* EMC_RD_RCD */
272                         0x00000001,   /* EMC_WR_RCD */
273                         0x00000003,   /* EMC_RRD */
274                         0x00000001,   /* EMC_REXT */
275                         0x00000000,   /* EMC_WEXT */
276                         0x00000005,   /* EMC_WDV */
277                         0x00000003,   /* EMC_QUSE */
278                         0x00000004,   /* EMC_QRST */
279                         0x00000007,   /* EMC_QSAFE */
280                         0x0000000B,   /* EMC_RDV */
281                         0x00000330,   /* EMC_REFRESH */
282                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
283                         0x000000CC,   /* EMC_PRE_REFRESH_REQ_CNT */
284                         0x00000002,   /* EMC_PDEX2WR */
285                         0x00000002,   /* EMC_PDEX2RD */
286                         0x00000001,   /* EMC_PCHG2PDEN */
287                         0x00000000,   /* EMC_ACT2PDEN */
288                         0x00000007,   /* EMC_AR2PDEN */
289                         0x0000000F,   /* EMC_RW2PDEN */
290                         0x00000013,   /* EMC_TXSR */
291                         0x00000013,   /* EMC_TXSRDLL */
292                         0x00000004,   /* EMC_TCKE */
293                         0x00000004,   /* EMC_TFAW */
294                         0x00000000,   /* EMC_TRPAB */
295                         0x00000004,   /* EMC_TCLKSTABLE */
296                         0x00000005,   /* EMC_TCLKSTOP */
297                         0x0000034B,   /* EMC_TREFBW */
298                         0x00000000,   /* EMC_QUSE_EXTRA */
299                         0x00000004,   /* EMC_FBIO_CFG6 */
300                         0x00000000,   /* EMC_ODT_WRITE */
301                         0x00000000,   /* EMC_ODT_READ */
302                         0x00008088,   /* EMC_FBIO_CFG5 */
303                         0x00780004,   /* EMC_CFG_DIG_DLL */
304                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
305                         0x00000010,   /* EMC_DLL_XFORM_DQS0 */
306                         0x00000010,   /* EMC_DLL_XFORM_DQS1 */
307                         0x00000010,   /* EMC_DLL_XFORM_DQS2 */
308                         0x00000010,   /* EMC_DLL_XFORM_DQS3 */
309                         0x00000010,   /* EMC_DLL_XFORM_DQS4 */
310                         0x00000010,   /* EMC_DLL_XFORM_DQS5 */
311                         0x00000010,   /* EMC_DLL_XFORM_DQS6 */
312                         0x00000010,   /* EMC_DLL_XFORM_DQS7 */
313                         0x00000018,   /* EMC_DLL_XFORM_QUSE0 */
314                         0x00000018,   /* EMC_DLL_XFORM_QUSE1 */
315                         0x00000018,   /* EMC_DLL_XFORM_QUSE2 */
316                         0x00000018,   /* EMC_DLL_XFORM_QUSE3 */
317                         0x00000018,   /* EMC_DLL_XFORM_QUSE4 */
318                         0x00000018,   /* EMC_DLL_XFORM_QUSE5 */
319                         0x00000018,   /* EMC_DLL_XFORM_QUSE6 */
320                         0x00000018,   /* EMC_DLL_XFORM_QUSE7 */
321                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
322                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
323                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
324                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
325                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
326                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
327                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
328                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
329                         0x0000A010,   /* EMC_DLL_XFORM_DQ0 */
330                         0x0000A010,   /* EMC_DLL_XFORM_DQ1 */
331                         0x0000A010,   /* EMC_DLL_XFORM_DQ2 */
332                         0x0000A010,   /* EMC_DLL_XFORM_DQ3 */
333                         0x000002A0,   /* EMC_XM2CMDPADCTRL */
334                         0x0800211D,   /* EMC_XM2DQSPADCTRL2 */
335                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
336                         0x77FFC084,   /* EMC_XM2CLKPADCTRL */
337                         0x01F1F108,   /* EMC_XM2COMPPADCTRL */
338                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
339                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
340                         0x0800012D,   /* EMC_XM2QUSEPADCTRL */
341                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
342                         0x00000802,   /* EMC_CTT_TERM_CTRL */
343                         0x00000000,   /* EMC_ZCAL_INTERVAL */
344                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
345                         0x000C000C,   /* EMC_MRS_WAIT_CNT */
346                         0xE0F11111,   /* EMC_AUTO_CAL_CONFIG */
347                         0x00000000,   /* EMC_CTT */
348                         0x00000000,   /* EMC_CTT_DURATION */
349                         0x8000076E,   /* EMC_DYN_SELF_REF_CONTROL */
350                         0x00000003,   /* MC_EMEM_ARB_CFG */
351                         0x80000027,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
352                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
353                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
354                         0x00000006,   /* MC_EMEM_ARB_TIMING_RC */
355                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAS */
356                         0x00000003,   /* MC_EMEM_ARB_TIMING_FAW */
357                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
358                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
359                         0x0000000F,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
360                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
361                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
362                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
363                         0x0000000F,   /* MC_EMEM_ARB_TIMING_W2R */
364                         0x0F070506,   /* MC_EMEM_ARB_DA_TURNS */
365                         0x00140906,   /* MC_EMEM_ARB_DA_COVERS */
366                         0x78440A07,   /* MC_EMEM_ARB_MISC0 */
367                         0x001F0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
368                 },
369                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
370                 0x00000000,     /* EMC_AUTO_CAL_INTERVAL */
371                 0x00001221,     /* DDR3 Mode Register 0 */
372                 0x00100003,     /* DDR3 Mode Register 1 */
373                 0x00200008,     /* DDR3 Mode Register 2 */
374         },
375         {
376                 0x30,           /* Rev 3.0 */
377                 333500,         /* SDRAM frquency */
378                 {
379                         0x00000010,   /* EMC_RC */
380                         0x00000035,   /* EMC_RFC */
381                         0x0000000B,   /* EMC_RAS */
382                         0x00000004,   /* EMC_RP */
383                         0x00000003,   /* EMC_R2W */
384                         0x00000009,   /* EMC_W2R */
385                         0x00000003,   /* EMC_R2P */
386                         0x0000000A,   /* EMC_W2P */
387                         0x00000004,   /* EMC_RD_RCD */
388                         0x00000004,   /* EMC_WR_RCD */
389                         0x00000003,   /* EMC_RRD */
390                         0x00000001,   /* EMC_REXT */
391                         0x00000000,   /* EMC_WEXT */
392                         0x00000004,   /* EMC_WDV */
393                         0x00000004,   /* EMC_QUSE */
394                         0x00000004,   /* EMC_QRST */
395                         0x00000008,   /* EMC_QSAFE */
396                         0x0000000D,   /* EMC_RDV */
397                         0x000009E9,   /* EMC_REFRESH */
398                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
399                         0x0000027A,   /* EMC_PRE_REFRESH_REQ_CNT */
400                         0x00000002,   /* EMC_PDEX2WR */
401                         0x00000002,   /* EMC_PDEX2RD */
402                         0x00000001,   /* EMC_PCHG2PDEN */
403                         0x00000000,   /* EMC_ACT2PDEN */
404                         0x00000007,   /* EMC_AR2PDEN */
405                         0x0000000E,   /* EMC_RW2PDEN */
406                         0x00000039,   /* EMC_TXSR */
407                         0x00000200,   /* EMC_TXSRDLL */
408                         0x00000004,   /* EMC_TCKE */
409                         0x0000000A,   /* EMC_TFAW */
410                         0x00000000,   /* EMC_TRPAB */
411                         0x00000004,   /* EMC_TCLKSTABLE */
412                         0x00000005,   /* EMC_TCLKSTOP */
413                         0x00000A2A,   /* EMC_TREFBW */
414                         0x00000000,   /* EMC_QUSE_EXTRA */
415                         0x00000004,   /* EMC_FBIO_CFG6 */
416                         0x00000000,   /* EMC_ODT_WRITE */
417                         0x00000000,   /* EMC_ODT_READ */
418                         0x00008088,   /* EMC_FBIO_CFG5 */
419                         0x00260004,   /* EMC_CFG_DIG_DLL */
420                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
421                         0x00000010,   /* EMC_DLL_XFORM_DQS0 */
422                         0x00000010,   /* EMC_DLL_XFORM_DQS1 */
423                         0x00000010,   /* EMC_DLL_XFORM_DQS2 */
424                         0x00000010,   /* EMC_DLL_XFORM_DQS3 */
425                         0x00000010,   /* EMC_DLL_XFORM_DQS4 */
426                         0x00000010,   /* EMC_DLL_XFORM_DQS5 */
427                         0x00000010,   /* EMC_DLL_XFORM_DQS6 */
428                         0x00000010,   /* EMC_DLL_XFORM_DQS7 */
429                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
430                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
431                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
432                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
433                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
434                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
435                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
436                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
437                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
438                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
439                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
440                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
441                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
442                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
443                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
444                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
445                         0x0000A010,   /* EMC_DLL_XFORM_DQ0 */
446                         0x0000A010,   /* EMC_DLL_XFORM_DQ1 */
447                         0x0000A010,   /* EMC_DLL_XFORM_DQ2 */
448                         0x0000A010,   /* EMC_DLL_XFORM_DQ3 */
449                         0x000002A0,   /* EMC_XM2CMDPADCTRL */
450                         0x0800013D,   /* EMC_XM2DQSPADCTRL2 */
451                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
452                         0x77FFC084,   /* EMC_XM2CLKPADCTRL */
453                         0x01F1F508,   /* EMC_XM2COMPPADCTRL */
454                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
455                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
456                         0x0800011D,   /* EMC_XM2QUSEPADCTRL */
457                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
458                         0x00000802,   /* EMC_CTT_TERM_CTRL */
459                         0x00000000,   /* EMC_ZCAL_INTERVAL */
460                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
461                         0x01CB000C,   /* EMC_MRS_WAIT_CNT */
462                         0xE0F11111,   /* EMC_AUTO_CAL_CONFIG */
463                         0x00000000,   /* EMC_CTT */
464                         0x00000000,   /* EMC_CTT_DURATION */
465                         0x800014D4,   /* EMC_DYN_SELF_REF_CONTROL */
466                         0x0000000A,   /* MC_EMEM_ARB_CFG */
467                         0x80000079,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
468                         0x00000003,   /* MC_EMEM_ARB_TIMING_RCD */
469                         0x00000006,   /* MC_EMEM_ARB_TIMING_RP */
470                         0x00000010,   /* MC_EMEM_ARB_TIMING_RC */
471                         0x0000000A,   /* MC_EMEM_ARB_TIMING_RAS */
472                         0x00000009,   /* MC_EMEM_ARB_TIMING_FAW */
473                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
474                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
475                         0x0000000E,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
476                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
477                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
478                         0x00000008,   /* MC_EMEM_ARB_TIMING_R2W */
479                         0x0000000E,   /* MC_EMEM_ARB_TIMING_W2R */
480                         0x0E080506,   /* MC_EMEM_ARB_DA_TURNS */
481                         0x00170D10,   /* MC_EMEM_ARB_DA_COVERS */
482                         0x784A1F11,   /* MC_EMEM_ARB_MISC0 */
483                         0x001F0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
484                 },
485                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
486                 0x00000000,     /* EMC_AUTO_CAL_INTERVAL */
487                 0x00001321,     /* DDR3 Mode Register 0 */
488                 0x00100002,     /* DDR3 Mode Register 1 */
489                 0x00200000,     /* DDR3 Mode Register 2 */
490         },
491         {
492                 0x30,           /* Rev 2.0 */
493                 533000,         /* SDRAM frquency */
494                 {
495                         0x00000018,   /* EMC_RC */
496                         0x00000054,   /* EMC_RFC */
497                         0x00000011,   /* EMC_RAS */
498                         0x00000006,   /* EMC_RP */
499                         0x00000003,   /* EMC_R2W */
500                         0x00000009,   /* EMC_W2R */
501                         0x00000002,   /* EMC_R2P */
502                         0x0000000D,   /* EMC_W2P */
503                         0x00000006,   /* EMC_RD_RCD */
504                         0x00000006,   /* EMC_WR_RCD */
505                         0x00000002,   /* EMC_RRD */
506                         0x00000001,   /* EMC_REXT */
507                         0x00000000,   /* EMC_WEXT */
508                         0x00000005,   /* EMC_WDV */
509                         0x00000008,   /* EMC_QUSE */
510                         0x00000006,   /* EMC_QRST */
511                         0x0000000A,   /* EMC_QSAFE */
512                         0x00000010,   /* EMC_RDV */
513                         0x00000FFD,   /* EMC_REFRESH */
514                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
515                         0x000003FF,   /* EMC_PRE_REFRESH_REQ_CNT */
516                         0x00000002,   /* EMC_PDEX2WR */
517                         0x00000002,   /* EMC_PDEX2RD */
518                         0x00000001,   /* EMC_PCHG2PDEN */
519                         0x00000000,   /* EMC_ACT2PDEN */
520                         0x0000000A,   /* EMC_AR2PDEN */
521                         0x00000012,   /* EMC_RW2PDEN */
522                         0x0000005B,   /* EMC_TXSR */
523                         0x00000200,   /* EMC_TXSRDLL */
524                         0x00000004,   /* EMC_TCKE */
525                         0x00000010,   /* EMC_TFAW */
526                         0x00000000,   /* EMC_TRPAB */
527                         0x00000005,   /* EMC_TCLKSTABLE */
528                         0x00000006,   /* EMC_TCLKSTOP */
529                         0x0000103E,   /* EMC_TREFBW */
530                         0x00000000,   /* EMC_QUSE_EXTRA */
531                         0x00000006,   /* EMC_FBIO_CFG6 */
532                         0x00000000,   /* EMC_ODT_WRITE */
533                         0x00000000,   /* EMC_ODT_READ */
534                         0x00007088,   /* EMC_FBIO_CFG5 */
535                         0xF0120441,   /* EMC_CFG_DIG_DLL */
536                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
537                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
538                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
539                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
540                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
541                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
542                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
543                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
544                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
545                         0x00008000,   /* EMC_DLL_XFORM_QUSE0 */
546                         0x00008000,   /* EMC_DLL_XFORM_QUSE1 */
547                         0x00008000,   /* EMC_DLL_XFORM_QUSE2 */
548                         0x00008000,   /* EMC_DLL_XFORM_QUSE3 */
549                         0x00008000,   /* EMC_DLL_XFORM_QUSE4 */
550                         0x00008000,   /* EMC_DLL_XFORM_QUSE5 */
551                         0x00008000,   /* EMC_DLL_XFORM_QUSE6 */
552                         0x00008000,   /* EMC_DLL_XFORM_QUSE7 */
553                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
554                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
555                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
556                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
557                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
558                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
559                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
560                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
561                         0x00020000,   /* EMC_DLL_XFORM_DQ0 */
562                         0x00020000,   /* EMC_DLL_XFORM_DQ1 */
563                         0x00020000,   /* EMC_DLL_XFORM_DQ2 */
564                         0x00020000,   /* EMC_DLL_XFORM_DQ3 */
565                         0x000202A0,   /* EMC_XM2CMDPADCTRL */
566                         0x0800013D,   /* EMC_XM2DQSPADCTRL2 */
567                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
568                         0x77FFD884,   /* EMC_XM2CLKPADCTRL */
569                         0x01F1F508,   /* EMC_XM2COMPPADCTRL */
570                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
571                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
572                         0x0800011D,   /* EMC_XM2QUSEPADCTRL */
573                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
574                         0x00000802,   /* EMC_CTT_TERM_CTRL */
575                         0x00020000,   /* EMC_ZCAL_INTERVAL */
576                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
577                         0x012B000C,   /* EMC_MRS_WAIT_CNT */
578                         0xA0F10000,   /* EMC_AUTO_CAL_CONFIG */
579                         0x00000000,   /* EMC_CTT */
580                         0x00000000,   /* EMC_CTT_DURATION */
581                         0x800020AE,   /* EMC_DYN_SELF_REF_CONTROL */
582                         0x00000008,   /* MC_EMEM_ARB_CFG */
583                         0x80000060,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
584                         0x00000002,   /* MC_EMEM_ARB_TIMING_RCD */
585                         0x00000003,   /* MC_EMEM_ARB_TIMING_RP */
586                         0x0000000D,   /* MC_EMEM_ARB_TIMING_RC */
587                         0x00000008,   /* MC_EMEM_ARB_TIMING_RAS */
588                         0x00000007,   /* MC_EMEM_ARB_TIMING_FAW */
589                         0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
590                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
591                         0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
592                         0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
593                         0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
594                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
595                         0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
596                         0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
597                         0x0010090D,   /* MC_EMEM_ARB_DA_COVERS */
598                         0x7028180E,   /* MC_EMEM_ARB_MISC0 */
599                         0x001F0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
600                 },
601                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
602                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
603                 0x00001941,     /* DDR3 Mode Register 0 */
604                 0x00100002,     /* DDR3 Mode Register 1 */
605                 0x00200008,     /* DDR3 Mode Register 2 */
606         },
607         {
608                 0x30,           /* Rev 3.0 */
609                 667000,         /* SDRAM frquency */
610                 {
611                         0x00000021,   /* EMC_RC */
612                         0x00000073,   /* EMC_RFC */
613                         0x00000018,   /* EMC_RAS */
614                         0x0000000A,   /* EMC_RP */
615                         0x00000006,   /* EMC_R2W */
616                         0x0000000E,   /* EMC_W2R */
617                         0x00000005,   /* EMC_R2P */
618                         0x00000013,   /* EMC_W2P */
619                         0x0000000A,   /* EMC_RD_RCD */
620                         0x0000000A,   /* EMC_WR_RCD */
621                         0x00000004,   /* EMC_RRD */
622                         0x00000003,   /* EMC_REXT */
623                         0x00000002,   /* EMC_WEXT */
624                         0x00000007,   /* EMC_WDV */
625                         0x0000000A,   /* EMC_QUSE */
626                         0x00000009,   /* EMC_QRST */
627                         0x00000008,   /* EMC_QSAFE */
628                         0x00000013,   /* EMC_RDV */
629                         0x000013AE,   /* EMC_REFRESH */
630                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
631                         0x00000504,   /* EMC_PRE_REFRESH_REQ_CNT */
632                         0x00000006,   /* EMC_PDEX2WR */
633                         0x00000006,   /* EMC_PDEX2RD */
634                         0x00000005,   /* EMC_PCHG2PDEN */
635                         0x00000004,   /* EMC_ACT2PDEN */
636                         0x00000010,   /* EMC_AR2PDEN */
637                         0x0000001A,   /* EMC_RW2PDEN */
638                         0x0000007C,   /* EMC_TXSR */
639                         0x0000020A,   /* EMC_TXSRDLL */
640                         0x00000009,   /* EMC_TCKE */
641                         0x00000019,   /* EMC_TFAW */
642                         0x00000000,   /* EMC_TRPAB */
643                         0x00000008,   /* EMC_TCLKSTABLE */
644                         0x00000009,   /* EMC_TCLKSTOP */
645                         0x000014B7,   /* EMC_TREFBW */
646                         0x00000000,   /* EMC_QUSE_EXTRA */
647                         0x00000004,   /* EMC_FBIO_CFG6 */
648                         0x00000000,   /* EMC_ODT_WRITE */
649                         0x00000000,   /* EMC_ODT_READ */
650                         0x00009088,   /* EMC_FBIO_CFG5 */
651                         0xF00B0401,   /* EMC_CFG_DIG_DLL */
652                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
653                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
654                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
655                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
656                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
657                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
658                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
659                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
660                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
661                         0x00014000,   /* EMC_DLL_XFORM_QUSE0 */
662                         0x00014000,   /* EMC_DLL_XFORM_QUSE1 */
663                         0x00014000,   /* EMC_DLL_XFORM_QUSE2 */
664                         0x00014000,   /* EMC_DLL_XFORM_QUSE3 */
665                         0x00014000,   /* EMC_DLL_XFORM_QUSE4 */
666                         0x00014000,   /* EMC_DLL_XFORM_QUSE5 */
667                         0x00014000,   /* EMC_DLL_XFORM_QUSE6 */
668                         0x00014000,   /* EMC_DLL_XFORM_QUSE7 */
669                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
670                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
671                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
672                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
673                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
674                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
675                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
676                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
677                         0x0000400C,   /* EMC_DLL_XFORM_DQ0 */
678                         0x0000400C,   /* EMC_DLL_XFORM_DQ1 */
679                         0x0000400C,   /* EMC_DLL_XFORM_DQ2 */
680                         0x0000400C,   /* EMC_DLL_XFORM_DQ3 */
681                         0x000002A0,   /* EMC_XM2CMDPADCTRL */
682                         0x0800013D,   /* EMC_XM2DQSPADCTRL2 */
683                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
684                         0x77FFC084,   /* EMC_XM2CLKPADCTRL */
685                         0x01F1F508,   /* EMC_XM2COMPPADCTRL */
686                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
687                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
688                         0x0800011D,   /* EMC_XM2QUSEPADCTRL */
689                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
690                         0x00000802,   /* EMC_CTT_TERM_CTRL */
691                         0x00000000,   /* EMC_ZCAL_INTERVAL */
692                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
693                         0x0196000C,   /* EMC_MRS_WAIT_CNT */
694                         0xA0F10000,   /* EMC_AUTO_CAL_CONFIG */
695                         0x00000000,   /* EMC_CTT */
696                         0x00000000,   /* EMC_CTT_DURATION */
697                         0x800028A5,   /* EMC_DYN_SELF_REF_CONTROL */
698                         0x0000000A,   /* MC_EMEM_ARB_CFG */
699                         0x80000079,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
700                         0x00000004,   /* MC_EMEM_ARB_TIMING_RCD */
701                         0x00000005,   /* MC_EMEM_ARB_TIMING_RP */
702                         0x00000012,   /* MC_EMEM_ARB_TIMING_RC */
703                         0x0000000B,   /* MC_EMEM_ARB_TIMING_RAS */
704                         0x0000000C,   /* MC_EMEM_ARB_TIMING_FAW */
705                         0x00000002,   /* MC_EMEM_ARB_TIMING_RRD */
706                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
707                         0x0000000C,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
708                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2R */
709                         0x00000003,   /* MC_EMEM_ARB_TIMING_W2W */
710                         0x00000005,   /* MC_EMEM_ARB_TIMING_R2W */
711                         0x00000009,   /* MC_EMEM_ARB_TIMING_W2R */
712                         0x09050303,   /* MC_EMEM_ARB_DA_TURNS */
713                         0x00170F12,   /* MC_EMEM_ARB_DA_COVERS */
714                         0x706A1F13,   /* MC_EMEM_ARB_MISC0 */
715                         0x001F0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
716                 },
717                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
718                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
719                 0x00001b71,     /* DDR3 Mode Register 0 */
720                 0x00100002,     /* DDR3 Mode Register 1 */
721                 0x00200018,     /* DDR3 Mode Register 2 */
722         }
723 };
724
725 int cardhu_emc_init(void)
726 {
727         tegra_init_emc(cardhu_emc_tables_h5tc2g,
728                 ARRAY_SIZE(cardhu_emc_tables_h5tc2g));
729         return 0;
730 }