arm: tegra: cardhu: update DVFS tables to latest
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-memory.c
1 /*
2  * Copyright (C) 2011 NVIDIA, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21
22 #include "board.h"
23 #include "board-cardhu.h"
24 #include "tegra3_emc.h"
25 #include "fuse.h"
26
27
28 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
29         {
30                 0x30,           /* Rev 3.0 */
31                 27000,          /* SDRAM frquency */
32                 {
33                         0x00000001,   /* EMC_RC */
34                         0x00000004,   /* EMC_RFC */
35                         0x00000000,   /* EMC_RAS */
36                         0x00000000,   /* EMC_RP */
37                         0x00000002,   /* EMC_R2W */
38                         0x0000000a,   /* EMC_W2R */
39                         0x00000003,   /* EMC_R2P */
40                         0x0000000b,   /* EMC_W2P */
41                         0x00000000,   /* EMC_RD_RCD */
42                         0x00000000,   /* EMC_WR_RCD */
43                         0x00000003,   /* EMC_RRD */
44                         0x00000001,   /* EMC_REXT */
45                         0x00000000,   /* EMC_WEXT */
46                         0x00000005,   /* EMC_WDV */
47                         0x00000005,   /* EMC_QUSE */
48                         0x00000004,   /* EMC_QRST */
49                         0x00000007,   /* EMC_QSAFE */
50                         0x0000000d,   /* EMC_RDV */
51                         0x000000cb,   /* EMC_REFRESH */
52                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
53                         0x00000032,   /* EMC_PRE_REFRESH_REQ_CNT */
54                         0x00000002,   /* EMC_PDEX2WR */
55                         0x00000002,   /* EMC_PDEX2RD */
56                         0x00000001,   /* EMC_PCHG2PDEN */
57                         0x00000000,   /* EMC_ACT2PDEN */
58                         0x00000007,   /* EMC_AR2PDEN */
59                         0x0000000f,   /* EMC_RW2PDEN */
60                         0x00000005,   /* EMC_TXSR */
61                         0x00000005,   /* EMC_TXSRDLL */
62                         0x00000004,   /* EMC_TCKE */
63                         0x00000001,   /* EMC_TFAW */
64                         0x00000000,   /* EMC_TRPAB */
65                         0x00000004,   /* EMC_TCLKSTABLE */
66                         0x00000005,   /* EMC_TCLKSTOP */
67                         0x000000d3,   /* EMC_TREFBW */
68                         0x00000000,   /* EMC_QUSE_EXTRA */
69                         0x00000004,   /* EMC_FBIO_CFG6 */
70                         0x00000000,   /* EMC_ODT_WRITE */
71                         0x00000000,   /* EMC_ODT_READ */
72                         0x00006288,   /* EMC_FBIO_CFG5 */
73                         0xd0780421,   /* EMC_CFG_DIG_DLL */
74                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
75                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
76                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
77                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
78                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
79                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
80                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
81                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
82                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
83                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
84                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
85                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
86                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
87                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
88                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
89                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
90                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
91                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
92                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
93                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
94                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
95                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
96                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
97                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
98                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
99                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
100                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
101                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
102                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
103                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
104                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
105                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
106                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
107                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
108                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
109                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
110                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
111                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
112                         0x00000802,   /* EMC_CTT_TERM_CTRL */
113                         0x00000000,   /* EMC_ZCAL_INTERVAL */
114                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
115                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
116                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
117                         0x00000000,   /* EMC_CTT */
118                         0x00000000,   /* EMC_CTT_DURATION */
119                         0x8000029e,   /* EMC_DYN_SELF_REF_CONTROL */
120                         0x00000001,   /* MC_EMEM_ARB_CFG */
121                         0x8000000d,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
122                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
123                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
124                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
125                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
126                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
127                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
128                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
129                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
130                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
131                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
132                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
133                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
134                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
135                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
136                         0x78430306,   /* MC_EMEM_ARB_MISC0 */
137                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
138                 },
139                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
140                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
141                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
142                 0x00001221,     /* Mode Register 0 */
143                 0x00100003,     /* Mode Register 1 */
144                 0x00200008,     /* Mode Register 2 */
145         },
146         {
147                 0x30,           /* Rev 3.0 */
148                 54000,          /* SDRAM frquency */
149                 {
150                         0x00000002,   /* EMC_RC */
151                         0x00000008,   /* EMC_RFC */
152                         0x00000001,   /* EMC_RAS */
153                         0x00000000,   /* EMC_RP */
154                         0x00000002,   /* EMC_R2W */
155                         0x0000000a,   /* EMC_W2R */
156                         0x00000003,   /* EMC_R2P */
157                         0x0000000b,   /* EMC_W2P */
158                         0x00000000,   /* EMC_RD_RCD */
159                         0x00000000,   /* EMC_WR_RCD */
160                         0x00000003,   /* EMC_RRD */
161                         0x00000001,   /* EMC_REXT */
162                         0x00000000,   /* EMC_WEXT */
163                         0x00000005,   /* EMC_WDV */
164                         0x00000005,   /* EMC_QUSE */
165                         0x00000004,   /* EMC_QRST */
166                         0x00000007,   /* EMC_QSAFE */
167                         0x0000000d,   /* EMC_RDV */
168                         0x00000198,   /* EMC_REFRESH */
169                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
170                         0x00000066,   /* EMC_PRE_REFRESH_REQ_CNT */
171                         0x00000002,   /* EMC_PDEX2WR */
172                         0x00000002,   /* EMC_PDEX2RD */
173                         0x00000001,   /* EMC_PCHG2PDEN */
174                         0x00000000,   /* EMC_ACT2PDEN */
175                         0x00000007,   /* EMC_AR2PDEN */
176                         0x0000000f,   /* EMC_RW2PDEN */
177                         0x0000000a,   /* EMC_TXSR */
178                         0x0000000a,   /* EMC_TXSRDLL */
179                         0x00000004,   /* EMC_TCKE */
180                         0x00000002,   /* EMC_TFAW */
181                         0x00000000,   /* EMC_TRPAB */
182                         0x00000004,   /* EMC_TCLKSTABLE */
183                         0x00000005,   /* EMC_TCLKSTOP */
184                         0x000001a6,   /* EMC_TREFBW */
185                         0x00000000,   /* EMC_QUSE_EXTRA */
186                         0x00000004,   /* EMC_FBIO_CFG6 */
187                         0x00000000,   /* EMC_ODT_WRITE */
188                         0x00000000,   /* EMC_ODT_READ */
189                         0x00006288,   /* EMC_FBIO_CFG5 */
190                         0xd0780421,   /* EMC_CFG_DIG_DLL */
191                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
192                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
193                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
194                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
195                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
196                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
197                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
198                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
199                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
200                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
201                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
202                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
203                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
204                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
205                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
206                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
207                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
208                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
209                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
210                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
211                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
212                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
213                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
214                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
215                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
216                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
217                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
218                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
219                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
220                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
221                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
222                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
223                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
224                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
225                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
226                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
227                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
228                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
229                         0x00000802,   /* EMC_CTT_TERM_CTRL */
230                         0x00000000,   /* EMC_ZCAL_INTERVAL */
231                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
232                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
233                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
234                         0x00000000,   /* EMC_CTT */
235                         0x00000000,   /* EMC_CTT_DURATION */
236                         0x80000439,   /* EMC_DYN_SELF_REF_CONTROL */
237                         0x00000001,   /* MC_EMEM_ARB_CFG */
238                         0x80000014,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
239                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
240                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
241                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
242                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
243                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
244                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
245                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
246                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
247                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
248                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
249                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
250                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
251                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
252                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
253                         0x78430506,   /* MC_EMEM_ARB_MISC0 */
254                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
255                 },
256                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
257                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
258                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
259                 0x00001221,     /* Mode Register 0 */
260                 0x00100003,     /* Mode Register 1 */
261                 0x00200008,     /* Mode Register 2 */
262         },
263         {
264                 0x30,           /* Rev 3.0 */
265                 108000,         /* SDRAM frquency */
266                 {
267                         0x00000005,   /* EMC_RC */
268                         0x00000011,   /* EMC_RFC */
269                         0x00000003,   /* EMC_RAS */
270                         0x00000001,   /* EMC_RP */
271                         0x00000002,   /* EMC_R2W */
272                         0x0000000a,   /* EMC_W2R */
273                         0x00000003,   /* EMC_R2P */
274                         0x0000000b,   /* EMC_W2P */
275                         0x00000001,   /* EMC_RD_RCD */
276                         0x00000001,   /* EMC_WR_RCD */
277                         0x00000003,   /* EMC_RRD */
278                         0x00000001,   /* EMC_REXT */
279                         0x00000000,   /* EMC_WEXT */
280                         0x00000005,   /* EMC_WDV */
281                         0x00000005,   /* EMC_QUSE */
282                         0x00000004,   /* EMC_QRST */
283                         0x00000007,   /* EMC_QSAFE */
284                         0x0000000d,   /* EMC_RDV */
285                         0x00000330,   /* EMC_REFRESH */
286                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
287                         0x000000cc,   /* EMC_PRE_REFRESH_REQ_CNT */
288                         0x00000002,   /* EMC_PDEX2WR */
289                         0x00000002,   /* EMC_PDEX2RD */
290                         0x00000001,   /* EMC_PCHG2PDEN */
291                         0x00000000,   /* EMC_ACT2PDEN */
292                         0x00000007,   /* EMC_AR2PDEN */
293                         0x0000000f,   /* EMC_RW2PDEN */
294                         0x00000013,   /* EMC_TXSR */
295                         0x00000013,   /* EMC_TXSRDLL */
296                         0x00000004,   /* EMC_TCKE */
297                         0x00000004,   /* EMC_TFAW */
298                         0x00000000,   /* EMC_TRPAB */
299                         0x00000004,   /* EMC_TCLKSTABLE */
300                         0x00000005,   /* EMC_TCLKSTOP */
301                         0x0000034b,   /* EMC_TREFBW */
302                         0x00000000,   /* EMC_QUSE_EXTRA */
303                         0x00000004,   /* EMC_FBIO_CFG6 */
304                         0x00000000,   /* EMC_ODT_WRITE */
305                         0x00000000,   /* EMC_ODT_READ */
306                         0x00006288,   /* EMC_FBIO_CFG5 */
307                         0xd0780421,   /* EMC_CFG_DIG_DLL */
308                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
309                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
310                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
311                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
312                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
313                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
314                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
315                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
316                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
317                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
318                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
319                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
320                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
321                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
322                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
323                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
324                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
325                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
326                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
327                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
328                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
329                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
330                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
331                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
332                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
333                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
334                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
335                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
336                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
337                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
338                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
339                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
340                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
341                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
342                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
343                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
344                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
345                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
346                         0x00000802,   /* EMC_CTT_TERM_CTRL */
347                         0x00000000,   /* EMC_ZCAL_INTERVAL */
348                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
349                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
350                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
351                         0x00000000,   /* EMC_CTT */
352                         0x00000000,   /* EMC_CTT_DURATION */
353                         0x8000076e,   /* EMC_DYN_SELF_REF_CONTROL */
354                         0x00000003,   /* MC_EMEM_ARB_CFG */
355                         0x80000027,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
356                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
357                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
358                         0x00000006,   /* MC_EMEM_ARB_TIMING_RC */
359                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAS */
360                         0x00000003,   /* MC_EMEM_ARB_TIMING_FAW */
361                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
362                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
363                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
364                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
365                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
366                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
367                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
368                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
369                         0x00140906,   /* MC_EMEM_ARB_DA_COVERS */
370                         0x78440a07,   /* MC_EMEM_ARB_MISC0 */
371                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
372                 },
373                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
374                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
375                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
376                 0x00001221,     /* Mode Register 0 */
377                 0x00100003,     /* Mode Register 1 */
378                 0x00200008,     /* Mode Register 2 */
379         },
380         {
381                 0x30,           /* Rev 3.0 */
382                 416000,         /* SDRAM frequency */
383                 {
384                         0x00000013,   /* EMC_RC */
385                         0x00000041,   /* EMC_RFC */
386                         0x0000000d,   /* EMC_RAS */
387                         0x00000004,   /* EMC_RP */
388                         0x00000002,   /* EMC_R2W */
389                         0x00000009,   /* EMC_W2R */
390                         0x00000002,   /* EMC_R2P */
391                         0x0000000c,   /* EMC_W2P */
392                         0x00000004,   /* EMC_RD_RCD */
393                         0x00000004,   /* EMC_WR_RCD */
394                         0x00000002,   /* EMC_RRD */
395                         0x00000001,   /* EMC_REXT */
396                         0x00000000,   /* EMC_WEXT */
397                         0x00000005,   /* EMC_WDV */
398                         0x00000008,   /* EMC_QUSE */
399                         0x00000006,   /* EMC_QRST */
400                         0x00000008,   /* EMC_QSAFE */
401                         0x00000010,   /* EMC_RDV */
402                         0x00000c6c,   /* EMC_REFRESH */
403                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
404                         0x0000031b,   /* EMC_PRE_REFRESH_REQ_CNT */
405                         0x00000001,   /* EMC_PDEX2WR */
406                         0x00000001,   /* EMC_PDEX2RD */
407                         0x00000001,   /* EMC_PCHG2PDEN */
408                         0x00000000,   /* EMC_ACT2PDEN */
409                         0x00000008,   /* EMC_AR2PDEN */
410                         0x00000011,   /* EMC_RW2PDEN */
411                         0x00000047,   /* EMC_TXSR */
412                         0x00000200,   /* EMC_TXSRDLL */
413                         0x00000004,   /* EMC_TCKE */
414                         0x0000000d,   /* EMC_TFAW */
415                         0x00000000,   /* EMC_TRPAB */
416                         0x00000004,   /* EMC_TCLKSTABLE */
417                         0x00000005,   /* EMC_TCLKSTOP */
418                         0x00000cad,   /* EMC_TREFBW */
419                         0x00000000,   /* EMC_QUSE_EXTRA */
420                         0x00000006,   /* EMC_FBIO_CFG6 */
421                         0x00000000,   /* EMC_ODT_WRITE */
422                         0x00000000,   /* EMC_ODT_READ */
423                         0x00007088,   /* EMC_FBIO_CFG5 */
424                         0xf0120441,   /* EMC_CFG_DIG_DLL */
425                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
426                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
427                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
428                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
429                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
430                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
431                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
432                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
433                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
434                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
435                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
436                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
437                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
438                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
439                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
440                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
441                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
442                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
443                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
444                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
445                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
446                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
447                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
448                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
449                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
450                         0x00020000,   /* EMC_DLL_XFORM_DQ0 */
451                         0x00020000,   /* EMC_DLL_XFORM_DQ1 */
452                         0x00020000,   /* EMC_DLL_XFORM_DQ2 */
453                         0x00020000,   /* EMC_DLL_XFORM_DQ3 */
454                         0x000006a0,   /* EMC_XM2CMDPADCTRL */
455                         0x0800013d,   /* EMC_XM2DQSPADCTRL2 */
456                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
457                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
458                         0x01f1f50f,   /* EMC_XM2COMPPADCTRL */
459                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
460                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
461                         0x0800011d,   /* EMC_XM2QUSEPADCTRL */
462                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
463                         0x00000802,   /* EMC_CTT_TERM_CTRL */
464                         0x00000000,   /* EMC_ZCAL_INTERVAL */
465                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
466                         0x01be000c,   /* EMC_MRS_WAIT_CNT */
467                         0xa0f10404,   /* EMC_AUTO_CAL_CONFIG */
468                         0x00000000,   /* EMC_CTT */
469                         0x00000000,   /* EMC_CTT_DURATION */
470                         0x000020ae,   /* EMC_DYN_SELF_REF_CONTROL */
471                         0x00000006,   /* MC_EMEM_ARB_CFG */
472                         0x8000004b,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
473                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
474                         0x00000002,   /* MC_EMEM_ARB_TIMING_RP */
475                         0x0000000a,   /* MC_EMEM_ARB_TIMING_RC */
476                         0x00000006,   /* MC_EMEM_ARB_TIMING_RAS */
477                         0x00000006,   /* MC_EMEM_ARB_TIMING_FAW */
478                         0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
479                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
480                         0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
481                         0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
482                         0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
483                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
484                         0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
485                         0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
486                         0x000e070a,   /* MC_EMEM_ARB_DA_COVERS */
487                         0x7027130b,   /* MC_EMEM_ARB_MISC0 */
488                         0x001f0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
489                 },
490                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
491                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
492                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
493                 0x00001941,     /* Mode Register 0 */
494                 0x00100002,     /* Mode Register 1 */
495                 0x00200008,     /* Mode Register 2 */
496         },
497         {
498                 0x30,           /* Rev 3.0 */
499                 533000,         /* SDRAM frquency */
500                 {
501                         0x00000018,   /* EMC_RC */
502                         0x00000054,   /* EMC_RFC */
503                         0x00000011,   /* EMC_RAS */
504                         0x00000006,   /* EMC_RP */
505                         0x00000003,   /* EMC_R2W */
506                         0x00000009,   /* EMC_W2R */
507                         0x00000002,   /* EMC_R2P */
508                         0x0000000d,   /* EMC_W2P */
509                         0x00000006,   /* EMC_RD_RCD */
510                         0x00000006,   /* EMC_WR_RCD */
511                         0x00000002,   /* EMC_RRD */
512                         0x00000001,   /* EMC_REXT */
513                         0x00000000,   /* EMC_WEXT */
514                         0x00000005,   /* EMC_WDV */
515                         0x00000008,   /* EMC_QUSE */
516                         0x00000006,   /* EMC_QRST */
517                         0x00000008,   /* EMC_QSAFE */
518                         0x00000010,   /* EMC_RDV */
519                         0x00000ffd,   /* EMC_REFRESH */
520                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
521                         0x000003ff,   /* EMC_PRE_REFRESH_REQ_CNT */
522                         0x00000002,   /* EMC_PDEX2WR */
523                         0x00000002,   /* EMC_PDEX2RD */
524                         0x00000001,   /* EMC_PCHG2PDEN */
525                         0x00000000,   /* EMC_ACT2PDEN */
526                         0x0000000a,   /* EMC_AR2PDEN */
527                         0x00000012,   /* EMC_RW2PDEN */
528                         0x0000005b,   /* EMC_TXSR */
529                         0x00000200,   /* EMC_TXSRDLL */
530                         0x00000004,   /* EMC_TCKE */
531                         0x00000010,   /* EMC_TFAW */
532                         0x00000000,   /* EMC_TRPAB */
533                         0x00000005,   /* EMC_TCLKSTABLE */
534                         0x00000006,   /* EMC_TCLKSTOP */
535                         0x0000103e,   /* EMC_TREFBW */
536                         0x00000000,   /* EMC_QUSE_EXTRA */
537                         0x00000006,   /* EMC_FBIO_CFG6 */
538                         0x00000000,   /* EMC_ODT_WRITE */
539                         0x00000000,   /* EMC_ODT_READ */
540                         0x00007088,   /* EMC_FBIO_CFG5 */
541                         0xf0120441,   /* EMC_CFG_DIG_DLL */
542                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
543                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
544                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
545                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
546                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
547                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
548                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
549                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
550                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
551                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
552                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
553                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
554                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
555                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
556                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
557                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
558                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
559                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
560                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
561                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
562                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
563                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
564                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
565                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
566                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
567                         0x00020000,   /* EMC_DLL_XFORM_DQ0 */
568                         0x00020000,   /* EMC_DLL_XFORM_DQ1 */
569                         0x00020000,   /* EMC_DLL_XFORM_DQ2 */
570                         0x00020000,   /* EMC_DLL_XFORM_DQ3 */
571                         0x000006a0,   /* EMC_XM2CMDPADCTRL */
572                         0x0800013d,   /* EMC_XM2DQSPADCTRL2 */
573                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
574                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
575                         0x01f1f50f,   /* EMC_XM2COMPPADCTRL */
576                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
577                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
578                         0x0800011d,   /* EMC_XM2QUSEPADCTRL */
579                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
580                         0x00000802,   /* EMC_CTT_TERM_CTRL */
581                         0x00000000,   /* EMC_ZCAL_INTERVAL */
582                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
583                         0x01ab000c,   /* EMC_MRS_WAIT_CNT */
584                         0xa0f10404,   /* EMC_AUTO_CAL_CONFIG */
585                         0x00000000,   /* EMC_CTT */
586                         0x00000000,   /* EMC_CTT_DURATION */
587                         0x000020ae,   /* EMC_DYN_SELF_REF_CONTROL */
588                         0x00000008,   /* MC_EMEM_ARB_CFG */
589                         0x80000060,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
590                         0x00000002,   /* MC_EMEM_ARB_TIMING_RCD */
591                         0x00000003,   /* MC_EMEM_ARB_TIMING_RP */
592                         0x0000000d,   /* MC_EMEM_ARB_TIMING_RC */
593                         0x00000008,   /* MC_EMEM_ARB_TIMING_RAS */
594                         0x00000007,   /* MC_EMEM_ARB_TIMING_FAW */
595                         0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
596                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
597                         0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
598                         0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
599                         0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
600                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
601                         0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
602                         0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
603                         0x0010090d,   /* MC_EMEM_ARB_DA_COVERS */
604                         0x7028180e,   /* MC_EMEM_ARB_MISC0 */
605                         0x001f0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
606                 },
607                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
608                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
609                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
610                 0x00001941,     /* Mode Register 0 */
611                 0x00100002,     /* Mode Register 1 */
612                 0x00200008,     /* Mode Register 2 */
613         },
614 };
615
616 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
617         {
618                 0x30,       /* Rev 3.0 */
619                 25500,      /* SDRAM frequency */
620                 {
621                         0x00000001, /* EMC_RC */
622                         0x00000003, /* EMC_RFC */
623                         0x00000000, /* EMC_RAS */
624                         0x00000000, /* EMC_RP */
625                         0x00000002, /* EMC_R2W */
626                         0x0000000a, /* EMC_W2R */
627                         0x00000003, /* EMC_R2P */
628                         0x0000000b, /* EMC_W2P */
629                         0x00000000, /* EMC_RD_RCD */
630                         0x00000000, /* EMC_WR_RCD */
631                         0x00000003, /* EMC_RRD */
632                         0x00000001, /* EMC_REXT */
633                         0x00000000, /* EMC_WEXT */
634                         0x00000005, /* EMC_WDV */
635                         0x00000005, /* EMC_QUSE */
636                         0x00000004, /* EMC_QRST */
637                         0x00000007, /* EMC_QSAFE */
638                         0x0000000c, /* EMC_RDV */
639                         0x000000bd, /* EMC_REFRESH */
640                         0x00000000, /* EMC_BURST_REFRESH_NUM */
641                         0x0000002f, /* EMC_PRE_REFRESH_REQ_CNT */
642                         0x00000002, /* EMC_PDEX2WR */
643                         0x00000002, /* EMC_PDEX2RD */
644                         0x00000001, /* EMC_PCHG2PDEN */
645                         0x00000000, /* EMC_ACT2PDEN */
646                         0x00000007, /* EMC_AR2PDEN */
647                         0x0000000f, /* EMC_RW2PDEN */
648                         0x00000005, /* EMC_TXSR */
649                         0x00000005, /* EMC_TXSRDLL */
650                         0x00000004, /* EMC_TCKE */
651                         0x00000001, /* EMC_TFAW */
652                         0x00000000, /* EMC_TRPAB */
653                         0x00000004, /* EMC_TCLKSTABLE */
654                         0x00000005, /* EMC_TCLKSTOP */
655                         0x000000c3, /* EMC_TREFBW */
656                         0x00000000, /* EMC_QUSE_EXTRA */
657                         0x00000004, /* EMC_FBIO_CFG6 */
658                         0x00000000, /* EMC_ODT_WRITE */
659                         0x00000000, /* EMC_ODT_READ */
660                         0x00006288, /* EMC_FBIO_CFG5 */
661                         0x007800a4, /* EMC_CFG_DIG_DLL */
662                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
663                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
664                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
665                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
666                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
667                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
668                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
669                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
670                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
671                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
672                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
673                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
674                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
675                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
676                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
677                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
678                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
679                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
680                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
681                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
682                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
683                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
684                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
685                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
686                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
687                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
688                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
689                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
690                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
691                         0x000002a0, /* EMC_XM2CMDPADCTRL */
692                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
693                         0x00000000, /* EMC_XM2DQPADCTRL2 */
694                         0x77fff884, /* EMC_XM2CLKPADCTRL */
695                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
696                         0x03037404, /* EMC_XM2VTTGENPADCTRL */
697                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
698                         0x08000168, /* EMC_XM2QUSEPADCTRL */
699                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
700                         0x00000802, /* EMC_CTT_TERM_CTRL */
701                         0x00000000, /* EMC_ZCAL_INTERVAL */
702                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
703                         0x000c000c, /* EMC_MRS_WAIT_CNT */
704                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
705                         0x00000000, /* EMC_CTT */
706                         0x00000000, /* EMC_CTT_DURATION */
707                         0x80000280, /* EMC_DYN_SELF_REF_CONTROL */
708                         0x00020001, /* MC_EMEM_ARB_CFG */
709                         0x80000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
710                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
711                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
712                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
713                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
714                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
715                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
716                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
717                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
718                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
719                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
720                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
721                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
722                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
723                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
724                         0x74430303, /* MC_EMEM_ARB_MISC0 */
725                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
726                 },
727                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
728                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
729                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
730                 0x80001221, /* Mode Register 0 */
731                 0x80100003, /* Mode Register 1 */
732                 0x80200008, /* Mode Register 2 */
733         },
734         {
735                 0x30,       /* Rev 3.0 */
736                 51000,      /* SDRAM frequency */
737                 {
738                         0x00000002, /* EMC_RC */
739                         0x00000008, /* EMC_RFC */
740                         0x00000001, /* EMC_RAS */
741                         0x00000000, /* EMC_RP */
742                         0x00000002, /* EMC_R2W */
743                         0x0000000a, /* EMC_W2R */
744                         0x00000003, /* EMC_R2P */
745                         0x0000000b, /* EMC_W2P */
746                         0x00000000, /* EMC_RD_RCD */
747                         0x00000000, /* EMC_WR_RCD */
748                         0x00000003, /* EMC_RRD */
749                         0x00000001, /* EMC_REXT */
750                         0x00000000, /* EMC_WEXT */
751                         0x00000005, /* EMC_WDV */
752                         0x00000005, /* EMC_QUSE */
753                         0x00000004, /* EMC_QRST */
754                         0x00000007, /* EMC_QSAFE */
755                         0x0000000c, /* EMC_RDV */
756                         0x00000181, /* EMC_REFRESH */
757                         0x00000000, /* EMC_BURST_REFRESH_NUM */
758                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
759                         0x00000002, /* EMC_PDEX2WR */
760                         0x00000002, /* EMC_PDEX2RD */
761                         0x00000001, /* EMC_PCHG2PDEN */
762                         0x00000000, /* EMC_ACT2PDEN */
763                         0x00000007, /* EMC_AR2PDEN */
764                         0x0000000f, /* EMC_RW2PDEN */
765                         0x00000009, /* EMC_TXSR */
766                         0x00000009, /* EMC_TXSRDLL */
767                         0x00000004, /* EMC_TCKE */
768                         0x00000002, /* EMC_TFAW */
769                         0x00000000, /* EMC_TRPAB */
770                         0x00000004, /* EMC_TCLKSTABLE */
771                         0x00000005, /* EMC_TCLKSTOP */
772                         0x0000018e, /* EMC_TREFBW */
773                         0x00000000, /* EMC_QUSE_EXTRA */
774                         0x00000004, /* EMC_FBIO_CFG6 */
775                         0x00000000, /* EMC_ODT_WRITE */
776                         0x00000000, /* EMC_ODT_READ */
777                         0x00006288, /* EMC_FBIO_CFG5 */
778                         0x007800a4, /* EMC_CFG_DIG_DLL */
779                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
780                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
781                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
782                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
783                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
784                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
785                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
786                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
787                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
788                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
789                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
790                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
791                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
792                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
793                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
794                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
795                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
796                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
797                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
798                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
799                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
800                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
801                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
802                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
803                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
804                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
805                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
806                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
807                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
808                         0x000002a0, /* EMC_XM2CMDPADCTRL */
809                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
810                         0x00000000, /* EMC_XM2DQPADCTRL2 */
811                         0x77fff884, /* EMC_XM2CLKPADCTRL */
812                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
813                         0x03037404, /* EMC_XM2VTTGENPADCTRL */
814                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
815                         0x08000168, /* EMC_XM2QUSEPADCTRL */
816                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
817                         0x00000802, /* EMC_CTT_TERM_CTRL */
818                         0x00000000, /* EMC_ZCAL_INTERVAL */
819                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
820                         0x000c000c, /* EMC_MRS_WAIT_CNT */
821                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
822                         0x00000000, /* EMC_CTT */
823                         0x00000000, /* EMC_CTT_DURATION */
824                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
825                         0x00000001, /* MC_EMEM_ARB_CFG */
826                         0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
827                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
828                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
829                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
830                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
831                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
832                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
833                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
834                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
835                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
836                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
837                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
838                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
839                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
840                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
841                         0x73430303, /* MC_EMEM_ARB_MISC0 */
842                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
843                 },
844                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
845                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
846                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
847                 0x80001221, /* Mode Register 0 */
848                 0x80100003, /* Mode Register 1 */
849                 0x80200008, /* Mode Register 2 */
850         },
851         {
852                 0x30,       /* Rev 3.0 */
853                 102000,     /* SDRAM frequency */
854                 {
855                         0x00000004, /* EMC_RC */
856                         0x00000010, /* EMC_RFC */
857                         0x00000003, /* EMC_RAS */
858                         0x00000001, /* EMC_RP */
859                         0x00000002, /* EMC_R2W */
860                         0x0000000a, /* EMC_W2R */
861                         0x00000003, /* EMC_R2P */
862                         0x0000000b, /* EMC_W2P */
863                         0x00000001, /* EMC_RD_RCD */
864                         0x00000001, /* EMC_WR_RCD */
865                         0x00000003, /* EMC_RRD */
866                         0x00000001, /* EMC_REXT */
867                         0x00000000, /* EMC_WEXT */
868                         0x00000005, /* EMC_WDV */
869                         0x00000005, /* EMC_QUSE */
870                         0x00000004, /* EMC_QRST */
871                         0x00000007, /* EMC_QSAFE */
872                         0x0000000c, /* EMC_RDV */
873                         0x00000303, /* EMC_REFRESH */
874                         0x00000000, /* EMC_BURST_REFRESH_NUM */
875                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
876                         0x00000002, /* EMC_PDEX2WR */
877                         0x00000002, /* EMC_PDEX2RD */
878                         0x00000001, /* EMC_PCHG2PDEN */
879                         0x00000000, /* EMC_ACT2PDEN */
880                         0x00000007, /* EMC_AR2PDEN */
881                         0x0000000f, /* EMC_RW2PDEN */
882                         0x00000012, /* EMC_TXSR */
883                         0x00000012, /* EMC_TXSRDLL */
884                         0x00000004, /* EMC_TCKE */
885                         0x00000004, /* EMC_TFAW */
886                         0x00000000, /* EMC_TRPAB */
887                         0x00000004, /* EMC_TCLKSTABLE */
888                         0x00000005, /* EMC_TCLKSTOP */
889                         0x0000031c, /* EMC_TREFBW */
890                         0x00000000, /* EMC_QUSE_EXTRA */
891                         0x00000004, /* EMC_FBIO_CFG6 */
892                         0x00000000, /* EMC_ODT_WRITE */
893                         0x00000000, /* EMC_ODT_READ */
894                         0x00006288, /* EMC_FBIO_CFG5 */
895                         0x007800a4, /* EMC_CFG_DIG_DLL */
896                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
897                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
898                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
899                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
900                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
901                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
902                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
903                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
904                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
905                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
906                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
907                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
908                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
909                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
910                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
911                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
912                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
913                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
914                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
915                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
916                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
917                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
918                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
919                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
920                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
921                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
922                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
923                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
924                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
925                         0x000002a0, /* EMC_XM2CMDPADCTRL */
926                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
927                         0x00000000, /* EMC_XM2DQPADCTRL2 */
928                         0x77fff884, /* EMC_XM2CLKPADCTRL */
929                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
930                         0x03037404, /* EMC_XM2VTTGENPADCTRL */
931                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
932                         0x08000168, /* EMC_XM2QUSEPADCTRL */
933                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
934                         0x00000802, /* EMC_CTT_TERM_CTRL */
935                         0x00000000, /* EMC_ZCAL_INTERVAL */
936                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
937                         0x000c000c, /* EMC_MRS_WAIT_CNT */
938                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
939                         0x00000000, /* EMC_CTT */
940                         0x00000000, /* EMC_CTT_DURATION */
941                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
942                         0x00000001, /* MC_EMEM_ARB_CFG */
943                         0x80000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
944                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
945                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
946                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
947                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
948                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
949                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
950                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
951                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
952                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
953                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
954                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
955                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
956                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
957                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
958                         0x72830504, /* MC_EMEM_ARB_MISC0 */
959                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
960                 },
961                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
962                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
963                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
964                 0x80001221, /* Mode Register 0 */
965                 0x80100003, /* Mode Register 1 */
966                 0x80200008, /* Mode Register 2 */
967         },
968         {
969                 0x30,       /* Rev 3.0 */
970                 408000,     /* SDRAM frequency */
971                 {
972                         0x00000012, /* EMC_RC */
973                         0x00000040, /* EMC_RFC */
974                         0x0000000d, /* EMC_RAS */
975                         0x00000004, /* EMC_RP */
976                         0x00000002, /* EMC_R2W */
977                         0x00000009, /* EMC_W2R */
978                         0x00000002, /* EMC_R2P */
979                         0x0000000c, /* EMC_W2P */
980                         0x00000004, /* EMC_RD_RCD */
981                         0x00000004, /* EMC_WR_RCD */
982                         0x00000002, /* EMC_RRD */
983                         0x00000001, /* EMC_REXT */
984                         0x00000000, /* EMC_WEXT */
985                         0x00000005, /* EMC_WDV */
986                         0x00000007, /* EMC_QUSE */
987                         0x00000005, /* EMC_QRST */
988                         0x00000008, /* EMC_QSAFE */
989                         0x0000000e, /* EMC_RDV */
990                         0x00000c2e, /* EMC_REFRESH */
991                         0x00000000, /* EMC_BURST_REFRESH_NUM */
992                         0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
993                         0x00000008, /* EMC_PDEX2WR */
994                         0x00000008, /* EMC_PDEX2RD */
995                         0x00000001, /* EMC_PCHG2PDEN */
996                         0x00000000, /* EMC_ACT2PDEN */
997                         0x00000008, /* EMC_AR2PDEN */
998                         0x00000011, /* EMC_RW2PDEN */
999                         0x00000046, /* EMC_TXSR */
1000                         0x00000200, /* EMC_TXSRDLL */
1001                         0x0000000a, /* EMC_TCKE */
1002                         0x0000000d, /* EMC_TFAW */
1003                         0x00000000, /* EMC_TRPAB */
1004                         0x00000004, /* EMC_TCLKSTABLE */
1005                         0x00000005, /* EMC_TCLKSTOP */
1006                         0x00000c6f, /* EMC_TREFBW */
1007                         0x00000000, /* EMC_QUSE_EXTRA */
1008                         0x00000006, /* EMC_FBIO_CFG6 */
1009                         0x00000000, /* EMC_ODT_WRITE */
1010                         0x00000000, /* EMC_ODT_READ */
1011                         0x00007088, /* EMC_FBIO_CFG5 */
1012                         0x001c0084, /* EMC_CFG_DIG_DLL */
1013                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1014                         0x00014000, /* EMC_DLL_XFORM_DQS0 */
1015                         0x00014000, /* EMC_DLL_XFORM_DQS1 */
1016                         0x00014000, /* EMC_DLL_XFORM_DQS2 */
1017                         0x00014000, /* EMC_DLL_XFORM_DQS3 */
1018                         0x00014000, /* EMC_DLL_XFORM_DQS4 */
1019                         0x00014000, /* EMC_DLL_XFORM_DQS5 */
1020                         0x00014000, /* EMC_DLL_XFORM_DQS6 */
1021                         0x00014000, /* EMC_DLL_XFORM_DQS7 */
1022                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1023                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1024                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1025                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1026                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1027                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1028                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1029                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1030                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1031                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1032                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1033                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1034                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1035                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1036                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1037                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1038                         0x00020000, /* EMC_DLL_XFORM_DQ0 */
1039                         0x00020000, /* EMC_DLL_XFORM_DQ1 */
1040                         0x00020000, /* EMC_DLL_XFORM_DQ2 */
1041                         0x00020000, /* EMC_DLL_XFORM_DQ3 */
1042                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1043                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1044                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1045                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1046                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1047                         0x03037404, /* EMC_XM2VTTGENPADCTRL */
1048                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1049                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1050                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1051                         0x00000802, /* EMC_CTT_TERM_CTRL */
1052                         0x00020000, /* EMC_ZCAL_INTERVAL */
1053                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1054                         0x017f000c, /* EMC_MRS_WAIT_CNT */
1055                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1056                         0x00000000, /* EMC_CTT */
1057                         0x00000000, /* EMC_CTT_DURATION */
1058                         0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
1059                         0x00000006, /* MC_EMEM_ARB_CFG */
1060                         0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1061                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1062                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1063                         0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
1064                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1065                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1066                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1067                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1068                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1069                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1070                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1071                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1072                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1073                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1074                         0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
1075                         0x7547130b, /* MC_EMEM_ARB_MISC0 */
1076                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1077                 },
1078                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1079                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1080                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1081                 0x80000731, /* Mode Register 0 */
1082                 0x80100002, /* Mode Register 1 */
1083                 0x80200008, /* Mode Register 2 */
1084         },
1085         {
1086                 0x30,       /* Rev 3.0 */
1087                 533000,     /* SDRAM frequency */
1088                 {
1089                         0x00000018, /* EMC_RC */
1090                         0x00000054, /* EMC_RFC */
1091                         0x00000011, /* EMC_RAS */
1092                         0x00000006, /* EMC_RP */
1093                         0x00000003, /* EMC_R2W */
1094                         0x00000009, /* EMC_W2R */
1095                         0x00000002, /* EMC_R2P */
1096                         0x0000000d, /* EMC_W2P */
1097                         0x00000006, /* EMC_RD_RCD */
1098                         0x00000006, /* EMC_WR_RCD */
1099                         0x00000002, /* EMC_RRD */
1100                         0x00000001, /* EMC_REXT */
1101                         0x00000000, /* EMC_WEXT */
1102                         0x00000005, /* EMC_WDV */
1103                         0x00000008, /* EMC_QUSE */
1104                         0x00000006, /* EMC_QRST */
1105                         0x00000008, /* EMC_QSAFE */
1106                         0x00000010, /* EMC_RDV */
1107                         0x00000ffd, /* EMC_REFRESH */
1108                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1109                         0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */
1110                         0x0000000b, /* EMC_PDEX2WR */
1111                         0x0000000b, /* EMC_PDEX2RD */
1112                         0x00000001, /* EMC_PCHG2PDEN */
1113                         0x00000000, /* EMC_ACT2PDEN */
1114                         0x0000000a, /* EMC_AR2PDEN */
1115                         0x00000012, /* EMC_RW2PDEN */
1116                         0x0000005b, /* EMC_TXSR */
1117                         0x00000200, /* EMC_TXSRDLL */
1118                         0x0000000d, /* EMC_TCKE */
1119                         0x00000010, /* EMC_TFAW */
1120                         0x00000000, /* EMC_TRPAB */
1121                         0x00000005, /* EMC_TCLKSTABLE */
1122                         0x00000006, /* EMC_TCLKSTOP */
1123                         0x0000103e, /* EMC_TREFBW */
1124                         0x00000000, /* EMC_QUSE_EXTRA */
1125                         0x00000006, /* EMC_FBIO_CFG6 */
1126                         0x00000000, /* EMC_ODT_WRITE */
1127                         0x00000000, /* EMC_ODT_READ */
1128                         0x00007088, /* EMC_FBIO_CFG5 */
1129                         0x00120084, /* EMC_CFG_DIG_DLL */
1130                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1131                         0x00010000, /* EMC_DLL_XFORM_DQS0 */
1132                         0x00010000, /* EMC_DLL_XFORM_DQS1 */
1133                         0x00010000, /* EMC_DLL_XFORM_DQS2 */
1134                         0x00010000, /* EMC_DLL_XFORM_DQS3 */
1135                         0x00010000, /* EMC_DLL_XFORM_DQS4 */
1136                         0x00010000, /* EMC_DLL_XFORM_DQS5 */
1137                         0x00010000, /* EMC_DLL_XFORM_DQS6 */
1138                         0x00010000, /* EMC_DLL_XFORM_DQS7 */
1139                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1140                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1141                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1142                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1143                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1144                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1145                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1146                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1147                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1148                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1149                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1150                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1151                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1152                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1153                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1154                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1155                         0x00020000, /* EMC_DLL_XFORM_DQ0 */
1156                         0x00020000, /* EMC_DLL_XFORM_DQ1 */
1157                         0x00020000, /* EMC_DLL_XFORM_DQ2 */
1158                         0x00020000, /* EMC_DLL_XFORM_DQ3 */
1159                         0x000006a0, /* EMC_XM2CMDPADCTRL */
1160                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1161                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1162                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1163                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1164                         0x03037404, /* EMC_XM2VTTGENPADCTRL */
1165                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1166                         0x08000168, /* EMC_XM2QUSEPADCTRL */
1167                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1168                         0x00000802, /* EMC_CTT_TERM_CTRL */
1169                         0x00000000, /* EMC_ZCAL_INTERVAL */
1170                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
1171                         0x01ab000c, /* EMC_MRS_WAIT_CNT */
1172                         0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
1173                         0x00000000, /* EMC_CTT */
1174                         0x00000000, /* EMC_CTT_DURATION */
1175                         0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */
1176                         0x00000008, /* MC_EMEM_ARB_CFG */
1177                         0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1178                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1179                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1180                         0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
1181                         0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
1182                         0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
1183                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1184                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1185                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1186                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1187                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1188                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1189                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1190                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1191                         0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
1192                         0x7028180e, /* MC_EMEM_ARB_MISC0 */
1193                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1194                 },
1195                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1196                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1197                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1198                 0x80000941, /* Mode Register 0 */
1199                 0x80100002, /* Mode Register 1 */
1200                 0x80200008, /* Mode Register 2 */
1201         },
1202 };
1203
1204 static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
1205         {
1206                 0x31,       /* Rev 3.1 */
1207                 25500,      /* SDRAM frequency */
1208                 {
1209                         0x00000001, /* EMC_RC */
1210                         0x00000003, /* EMC_RFC */
1211                         0x00000002, /* EMC_RAS */
1212                         0x00000002, /* EMC_RP */
1213                         0x00000004, /* EMC_R2W */
1214                         0x00000004, /* EMC_W2R */
1215                         0x00000001, /* EMC_R2P */
1216                         0x00000005, /* EMC_W2P */
1217                         0x00000002, /* EMC_RD_RCD */
1218                         0x00000002, /* EMC_WR_RCD */
1219                         0x00000001, /* EMC_RRD */
1220                         0x00000001, /* EMC_REXT */
1221                         0x00000000, /* EMC_WEXT */
1222                         0x00000001, /* EMC_WDV */
1223                         0x00000003, /* EMC_QUSE */
1224                         0x00000001, /* EMC_QRST */
1225                         0x00000009, /* EMC_QSAFE */
1226                         0x0000000a, /* EMC_RDV */
1227                         0x0000005e, /* EMC_REFRESH */
1228                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1229                         0x00000017, /* EMC_PRE_REFRESH_REQ_CNT */
1230                         0x00000001, /* EMC_PDEX2WR */
1231                         0x00000001, /* EMC_PDEX2RD */
1232                         0x00000002, /* EMC_PCHG2PDEN */
1233                         0x00000000, /* EMC_ACT2PDEN */
1234                         0x00000001, /* EMC_AR2PDEN */
1235                         0x00000007, /* EMC_RW2PDEN */
1236                         0x00000004, /* EMC_TXSR */
1237                         0x00000004, /* EMC_TXSRDLL */
1238                         0x00000003, /* EMC_TCKE */
1239                         0x00000008, /* EMC_TFAW */
1240                         0x00000004, /* EMC_TRPAB */
1241                         0x00000004, /* EMC_TCLKSTABLE */
1242                         0x00000002, /* EMC_TCLKSTOP */
1243                         0x00000068, /* EMC_TREFBW */
1244                         0x00000004, /* EMC_QUSE_EXTRA */
1245                         0x00000004, /* EMC_FBIO_CFG6 */
1246                         0x00000000, /* EMC_ODT_WRITE */
1247                         0x00000000, /* EMC_ODT_READ */
1248                         0x00004282, /* EMC_FBIO_CFG5 */
1249                         0x00780084, /* EMC_CFG_DIG_DLL */
1250                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1251                         0x00098000, /* EMC_DLL_XFORM_DQS0 */
1252                         0x00098000, /* EMC_DLL_XFORM_DQS1 */
1253                         0x00098000, /* EMC_DLL_XFORM_DQS2 */
1254                         0x00098000, /* EMC_DLL_XFORM_DQS3 */
1255                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
1256                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
1257                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
1258                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
1259                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1260                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1261                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1262                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1263                         0x00000008, /* EMC_DLL_XFORM_QUSE4 */
1264                         0x00000008, /* EMC_DLL_XFORM_QUSE5 */
1265                         0x00000008, /* EMC_DLL_XFORM_QUSE6 */
1266                         0x00000008, /* EMC_DLL_XFORM_QUSE7 */
1267                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1268                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1269                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1270                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1271                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1272                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1273                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1274                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1275                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1276                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1277                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1278                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1279                         0x00100220, /* EMC_XM2CMDPADCTRL */
1280                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
1281                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1282                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1283                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
1284                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1285                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1286                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1287                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1288                         0x00000802, /* EMC_CTT_TERM_CTRL */
1289                         0x00064000, /* EMC_ZCAL_INTERVAL */
1290                         0x0000000a, /* EMC_ZCAL_WAIT_CNT */
1291                         0x00090009, /* EMC_MRS_WAIT_CNT */
1292                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1293                         0x00000000, /* EMC_CTT */
1294                         0x00000000, /* EMC_CTT_DURATION */
1295                         0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */
1296                         0x00020001, /* MC_EMEM_ARB_CFG */
1297                         0x80000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1298                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1299                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1300                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
1301                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
1302                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
1303                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1304                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1305                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1306                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
1307                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1308                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1309                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
1310                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
1311                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
1312                         0x74030303, /* MC_EMEM_ARB_MISC0 */
1313                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1314                         0x50000000, /* EMC_FBIO_SPARE */
1315                         0xff00ff00, /* EMC_CFG_RSV */
1316                 },
1317                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
1318                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1319                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1320                 0x00000000, /* Mode Register 0 */
1321                 0x00010022, /* Mode Register 1 */
1322                 0x00020001, /* Mode Register 2 */
1323         },
1324         {
1325                 0x31,       /* Rev 3.1 */
1326                 51000,      /* SDRAM frequency */
1327                 {
1328                         0x00000003, /* EMC_RC */
1329                         0x00000006, /* EMC_RFC */
1330                         0x00000002, /* EMC_RAS */
1331                         0x00000002, /* EMC_RP */
1332                         0x00000004, /* EMC_R2W */
1333                         0x00000004, /* EMC_W2R */
1334                         0x00000001, /* EMC_R2P */
1335                         0x00000005, /* EMC_W2P */
1336                         0x00000002, /* EMC_RD_RCD */
1337                         0x00000002, /* EMC_WR_RCD */
1338                         0x00000001, /* EMC_RRD */
1339                         0x00000001, /* EMC_REXT */
1340                         0x00000000, /* EMC_WEXT */
1341                         0x00000001, /* EMC_WDV */
1342                         0x00000003, /* EMC_QUSE */
1343                         0x00000001, /* EMC_QRST */
1344                         0x00000009, /* EMC_QSAFE */
1345                         0x0000000a, /* EMC_RDV */
1346                         0x000000c0, /* EMC_REFRESH */
1347                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1348                         0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
1349                         0x00000001, /* EMC_PDEX2WR */
1350                         0x00000001, /* EMC_PDEX2RD */
1351                         0x00000002, /* EMC_PCHG2PDEN */
1352                         0x00000000, /* EMC_ACT2PDEN */
1353                         0x00000001, /* EMC_AR2PDEN */
1354                         0x00000007, /* EMC_RW2PDEN */
1355                         0x00000008, /* EMC_TXSR */
1356                         0x00000008, /* EMC_TXSRDLL */
1357                         0x00000003, /* EMC_TCKE */
1358                         0x00000008, /* EMC_TFAW */
1359                         0x00000004, /* EMC_TRPAB */
1360                         0x00000004, /* EMC_TCLKSTABLE */
1361                         0x00000002, /* EMC_TCLKSTOP */
1362                         0x000000d5, /* EMC_TREFBW */
1363                         0x00000004, /* EMC_QUSE_EXTRA */
1364                         0x00000004, /* EMC_FBIO_CFG6 */
1365                         0x00000000, /* EMC_ODT_WRITE */
1366                         0x00000000, /* EMC_ODT_READ */
1367                         0x00004282, /* EMC_FBIO_CFG5 */
1368                         0x00780084, /* EMC_CFG_DIG_DLL */
1369                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1370                         0x000a0000, /* EMC_DLL_XFORM_DQS0 */
1371                         0x000a0000, /* EMC_DLL_XFORM_DQS1 */
1372                         0x000a0000, /* EMC_DLL_XFORM_DQS2 */
1373                         0x000a0000, /* EMC_DLL_XFORM_DQS3 */
1374                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
1375                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
1376                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
1377                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
1378                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1379                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1380                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1381                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1382                         0x00000018, /* EMC_DLL_XFORM_QUSE4 */
1383                         0x00000018, /* EMC_DLL_XFORM_QUSE5 */
1384                         0x00000018, /* EMC_DLL_XFORM_QUSE6 */
1385                         0x00000018, /* EMC_DLL_XFORM_QUSE7 */
1386                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1387                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1388                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1389                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1390                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1391                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1392                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1393                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1394                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1395                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1396                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1397                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1398                         0x00100220, /* EMC_XM2CMDPADCTRL */
1399                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
1400                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1401                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1402                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
1403                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1404                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1405                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1406                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1407                         0x00000802, /* EMC_CTT_TERM_CTRL */
1408                         0x00064000, /* EMC_ZCAL_INTERVAL */
1409                         0x00000013, /* EMC_ZCAL_WAIT_CNT */
1410                         0x00090009, /* EMC_MRS_WAIT_CNT */
1411                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1412                         0x00000000, /* EMC_CTT */
1413                         0x00000000, /* EMC_CTT_DURATION */
1414                         0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
1415                         0x00010001, /* MC_EMEM_ARB_CFG */
1416                         0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1417                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1418                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1419                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
1420                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
1421                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
1422                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1423                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1424                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1425                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
1426                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1427                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1428                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
1429                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
1430                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
1431                         0x72c30303, /* MC_EMEM_ARB_MISC0 */
1432                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1433                         0x50000000, /* EMC_FBIO_SPARE */
1434                         0xff00ff00, /* EMC_CFG_RSV */
1435                 },
1436                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
1437                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1438                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1439                 0x00000000, /* Mode Register 0 */
1440                 0x00010022, /* Mode Register 1 */
1441                 0x00020001, /* Mode Register 2 */
1442         },
1443         {
1444                 0x31,       /* Rev 3.1 */
1445                 102000,     /* SDRAM frequency */
1446                 {
1447                         0x00000006, /* EMC_RC */
1448                         0x0000000d, /* EMC_RFC */
1449                         0x00000004, /* EMC_RAS */
1450                         0x00000002, /* EMC_RP */
1451                         0x00000004, /* EMC_R2W */
1452                         0x00000004, /* EMC_W2R */
1453                         0x00000001, /* EMC_R2P */
1454                         0x00000005, /* EMC_W2P */
1455                         0x00000002, /* EMC_RD_RCD */
1456                         0x00000002, /* EMC_WR_RCD */
1457                         0x00000001, /* EMC_RRD */
1458                         0x00000001, /* EMC_REXT */
1459                         0x00000000, /* EMC_WEXT */
1460                         0x00000001, /* EMC_WDV */
1461                         0x00000003, /* EMC_QUSE */
1462                         0x00000001, /* EMC_QRST */
1463                         0x00000009, /* EMC_QSAFE */
1464                         0x00000009, /* EMC_RDV */
1465                         0x00000181, /* EMC_REFRESH */
1466                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1467                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
1468                         0x00000001, /* EMC_PDEX2WR */
1469                         0x00000001, /* EMC_PDEX2RD */
1470                         0x00000002, /* EMC_PCHG2PDEN */
1471                         0x00000000, /* EMC_ACT2PDEN */
1472                         0x00000001, /* EMC_AR2PDEN */
1473                         0x00000007, /* EMC_RW2PDEN */
1474                         0x0000000f, /* EMC_TXSR */
1475                         0x0000000f, /* EMC_TXSRDLL */
1476                         0x00000003, /* EMC_TCKE */
1477                         0x00000008, /* EMC_TFAW */
1478                         0x00000004, /* EMC_TRPAB */
1479                         0x00000004, /* EMC_TCLKSTABLE */
1480                         0x00000002, /* EMC_TCLKSTOP */
1481                         0x000001a9, /* EMC_TREFBW */
1482                         0x00000004, /* EMC_QUSE_EXTRA */
1483                         0x00000004, /* EMC_FBIO_CFG6 */
1484                         0x00000000, /* EMC_ODT_WRITE */
1485                         0x00000000, /* EMC_ODT_READ */
1486                         0x00004282, /* EMC_FBIO_CFG5 */
1487                         0x00780084, /* EMC_CFG_DIG_DLL */
1488                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1489                         0x000a0000, /* EMC_DLL_XFORM_DQS0 */
1490                         0x000a0000, /* EMC_DLL_XFORM_DQS1 */
1491                         0x000a0000, /* EMC_DLL_XFORM_DQS2 */
1492                         0x000a0000, /* EMC_DLL_XFORM_DQS3 */
1493                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
1494                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
1495                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
1496                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
1497                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1498                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1499                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1500                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1501                         0x00000008, /* EMC_DLL_XFORM_QUSE4 */
1502                         0x00000008, /* EMC_DLL_XFORM_QUSE5 */
1503                         0x00000008, /* EMC_DLL_XFORM_QUSE6 */
1504                         0x00000008, /* EMC_DLL_XFORM_QUSE7 */
1505                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1506                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1507                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1508                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1509                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1510                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1511                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1512                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1513                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1514                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1515                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1516                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1517                         0x00120220, /* EMC_XM2CMDPADCTRL */
1518                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
1519                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1520                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1521                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
1522                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1523                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1524                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1525                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1526                         0x00000802, /* EMC_CTT_TERM_CTRL */
1527                         0x00064000, /* EMC_ZCAL_INTERVAL */
1528                         0x00000025, /* EMC_ZCAL_WAIT_CNT */
1529                         0x00090009, /* EMC_MRS_WAIT_CNT */
1530                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1531                         0x00000000, /* EMC_CTT */
1532                         0x00000000, /* EMC_CTT_DURATION */
1533                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
1534                         0x00000001, /* MC_EMEM_ARB_CFG */
1535                         0x80000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1536                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1537                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1538                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
1539                         0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
1540                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
1541                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1542                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1543                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1544                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
1545                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1546                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1547                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
1548                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
1549                         0x00060403, /* MC_EMEM_ARB_DA_COVERS */
1550                         0x72430504, /* MC_EMEM_ARB_MISC0 */
1551                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1552                         0x10000000, /* EMC_FBIO_SPARE */
1553                         0xff00ff00, /* EMC_CFG_RSV */
1554                 },
1555                 0x0000000a, /* EMC_ZCAL_WAIT_CNT after clock change */
1556                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1557                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1558                 0x00000000, /* Mode Register 0 */
1559                 0x00010022, /* Mode Register 1 */
1560                 0x00020001, /* Mode Register 2 */
1561         },
1562         {
1563                 0x31,       /* Rev 3.1 */
1564                 204000,     /* SDRAM frequency */
1565                 {
1566                         0x0000000c, /* EMC_RC */
1567                         0x0000001a, /* EMC_RFC */
1568                         0x00000008, /* EMC_RAS */
1569                         0x00000003, /* EMC_RP */
1570                         0x00000005, /* EMC_R2W */
1571                         0x00000004, /* EMC_W2R */
1572                         0x00000001, /* EMC_R2P */
1573                         0x00000006, /* EMC_W2P */
1574                         0x00000003, /* EMC_RD_RCD */
1575                         0x00000003, /* EMC_WR_RCD */
1576                         0x00000002, /* EMC_RRD */
1577                         0x00000002, /* EMC_REXT */
1578                         0x00000000, /* EMC_WEXT */
1579                         0x00000001, /* EMC_WDV */
1580                         0x00000003, /* EMC_QUSE */
1581                         0x00000001, /* EMC_QRST */
1582                         0x0000000a, /* EMC_QSAFE */
1583                         0x0000000a, /* EMC_RDV */
1584                         0x00000303, /* EMC_REFRESH */
1585                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1586                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
1587                         0x00000001, /* EMC_PDEX2WR */
1588                         0x00000001, /* EMC_PDEX2RD */
1589                         0x00000003, /* EMC_PCHG2PDEN */
1590                         0x00000000, /* EMC_ACT2PDEN */
1591                         0x00000001, /* EMC_AR2PDEN */
1592                         0x00000007, /* EMC_RW2PDEN */
1593                         0x0000001d, /* EMC_TXSR */
1594                         0x0000001d, /* EMC_TXSRDLL */
1595                         0x00000004, /* EMC_TCKE */
1596                         0x0000000b, /* EMC_TFAW */
1597                         0x00000005, /* EMC_TRPAB */
1598                         0x00000004, /* EMC_TCLKSTABLE */
1599                         0x00000002, /* EMC_TCLKSTOP */
1600                         0x00000351, /* EMC_TREFBW */
1601                         0x00000004, /* EMC_QUSE_EXTRA */
1602                         0x00000006, /* EMC_FBIO_CFG6 */
1603                         0x00000000, /* EMC_ODT_WRITE */
1604                         0x00000000, /* EMC_ODT_READ */
1605                         0x00004282, /* EMC_FBIO_CFG5 */
1606                         0x00440084, /* EMC_CFG_DIG_DLL */
1607                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1608                         0x00074000, /* EMC_DLL_XFORM_DQS0 */
1609                         0x00074000, /* EMC_DLL_XFORM_DQS1 */
1610                         0x00074000, /* EMC_DLL_XFORM_DQS2 */
1611                         0x00074000, /* EMC_DLL_XFORM_DQS3 */
1612                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
1613                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
1614                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
1615                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
1616                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1617                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1618                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1619                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1620                         0x00000018, /* EMC_DLL_XFORM_QUSE4 */
1621                         0x00000018, /* EMC_DLL_XFORM_QUSE5 */
1622                         0x00000018, /* EMC_DLL_XFORM_QUSE6 */
1623                         0x00000018, /* EMC_DLL_XFORM_QUSE7 */
1624                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1625                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1626                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1627                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1628                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1629                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1630                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1631                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1632                         0x00078000, /* EMC_DLL_XFORM_DQ0 */
1633                         0x00078000, /* EMC_DLL_XFORM_DQ1 */
1634                         0x00078000, /* EMC_DLL_XFORM_DQ2 */
1635                         0x00078000, /* EMC_DLL_XFORM_DQ3 */
1636                         0x00100220, /* EMC_XM2CMDPADCTRL */
1637                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
1638                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1639                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1640                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
1641                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1642                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1643                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1644                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1645                         0x00000802, /* EMC_CTT_TERM_CTRL */
1646                         0x00064000, /* EMC_ZCAL_INTERVAL */
1647                         0x0000004a, /* EMC_ZCAL_WAIT_CNT */
1648                         0x00090009, /* EMC_MRS_WAIT_CNT */
1649                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1650                         0x00000000, /* EMC_CTT */
1651                         0x00000000, /* EMC_CTT_DURATION */
1652                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
1653                         0x00000003, /* MC_EMEM_ARB_CFG */
1654                         0x80000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1655                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1656                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1657                         0x00000006, /* MC_EMEM_ARB_TIMING_RC */
1658                         0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
1659                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
1660                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1661                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1662                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1663                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
1664                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1665                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1666                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
1667                         0x02030001, /* MC_EMEM_ARB_DA_TURNS */
1668                         0x00070506, /* MC_EMEM_ARB_DA_COVERS */
1669                         0x71e40a07, /* MC_EMEM_ARB_MISC0 */
1670                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1671                         0x50000000, /* EMC_FBIO_SPARE */
1672                         0xff00ff00, /* EMC_CFG_RSV */
1673                 },
1674                 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
1675                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1676                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1677                 0x00000000, /* Mode Register 0 */
1678                 0x00010042, /* Mode Register 1 */
1679                 0x00020001, /* Mode Register 2 */
1680         },
1681         {
1682                 0x31,       /* Rev 3.1 */
1683                 533000,     /* SDRAM frequency */
1684                 {
1685                         0x0000001f, /* EMC_RC */
1686                         0x00000045, /* EMC_RFC */
1687                         0x00000016, /* EMC_RAS */
1688                         0x00000009, /* EMC_RP */
1689                         0x00000008, /* EMC_R2W */
1690                         0x00000009, /* EMC_W2R */
1691                         0x00000003, /* EMC_R2P */
1692                         0x0000000d, /* EMC_W2P */
1693                         0x00000009, /* EMC_RD_RCD */
1694                         0x00000009, /* EMC_WR_RCD */
1695                         0x00000005, /* EMC_RRD */
1696                         0x00000003, /* EMC_REXT */
1697                         0x00000000, /* EMC_WEXT */
1698                         0x00000004, /* EMC_WDV */
1699                         0x0000000a, /* EMC_QUSE */
1700                         0x00000006, /* EMC_QRST */
1701                         0x0000000b, /* EMC_QSAFE */
1702                         0x00000010, /* EMC_RDV */
1703                         0x000007df, /* EMC_REFRESH */
1704                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1705                         0x000001f7, /* EMC_PRE_REFRESH_REQ_CNT */
1706                         0x00000003, /* EMC_PDEX2WR */
1707                         0x00000003, /* EMC_PDEX2RD */
1708                         0x00000009, /* EMC_PCHG2PDEN */
1709                         0x00000000, /* EMC_ACT2PDEN */
1710                         0x00000001, /* EMC_AR2PDEN */
1711                         0x0000000f, /* EMC_RW2PDEN */
1712                         0x0000004b, /* EMC_TXSR */
1713                         0x0000004b, /* EMC_TXSRDLL */
1714                         0x00000008, /* EMC_TCKE */
1715                         0x0000001b, /* EMC_TFAW */
1716                         0x0000000c, /* EMC_TRPAB */
1717                         0x00000004, /* EMC_TCLKSTABLE */
1718                         0x00000002, /* EMC_TCLKSTOP */
1719                         0x000008aa, /* EMC_TREFBW */
1720                         0x00000000, /* EMC_QUSE_EXTRA */
1721                         0x00000004, /* EMC_FBIO_CFG6 */
1722                         0x00000000, /* EMC_ODT_WRITE */
1723                         0x00000000, /* EMC_ODT_READ */
1724                         0x00006282, /* EMC_FBIO_CFG5 */
1725                         0x00120084, /* EMC_CFG_DIG_DLL */
1726                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1727                         0x00018000, /* EMC_DLL_XFORM_DQS0 */
1728                         0x00018000, /* EMC_DLL_XFORM_DQS1 */
1729                         0x00018000, /* EMC_DLL_XFORM_DQS2 */
1730                         0x00018000, /* EMC_DLL_XFORM_DQS3 */
1731                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
1732                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
1733                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
1734                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
1735                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1736                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1737                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1738                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1739                         0x00000008, /* EMC_DLL_XFORM_QUSE4 */
1740                         0x00000008, /* EMC_DLL_XFORM_QUSE5 */
1741                         0x00000008, /* EMC_DLL_XFORM_QUSE6 */
1742                         0x00000008, /* EMC_DLL_XFORM_QUSE7 */
1743                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1744                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1745                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1746                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1747                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1748                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1749                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1750                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1751                         0x0002c000, /* EMC_DLL_XFORM_DQ0 */
1752                         0x0002c000, /* EMC_DLL_XFORM_DQ1 */
1753                         0x0002c000, /* EMC_DLL_XFORM_DQ2 */
1754                         0x0002c000, /* EMC_DLL_XFORM_DQ3 */
1755                         0x000b0220, /* EMC_XM2CMDPADCTRL */
1756                         0x0800003d, /* EMC_XM2DQSPADCTRL2 */
1757                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1758                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
1759                         0x01f1f408, /* EMC_XM2COMPPADCTRL */
1760                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
1761                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
1762                         0x08000068, /* EMC_XM2QUSEPADCTRL */
1763                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1764                         0x00000802, /* EMC_CTT_TERM_CTRL */
1765                         0x00064000, /* EMC_ZCAL_INTERVAL */
1766                         0x000000c0, /* EMC_ZCAL_WAIT_CNT */
1767                         0x000e000e, /* EMC_MRS_WAIT_CNT */
1768                         0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
1769                         0x00000000, /* EMC_CTT */
1770                         0x00000000, /* EMC_CTT_DURATION */
1771                         0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */
1772                         0x00000008, /* MC_EMEM_ARB_CFG */
1773                         0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1774                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
1775                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
1776                         0x00000010, /* MC_EMEM_ARB_TIMING_RC */
1777                         0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
1778                         0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
1779                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1780                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1781                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1782                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1783                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
1784                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1785                         0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
1786                         0x05040002, /* MC_EMEM_ARB_DA_TURNS */
1787                         0x00110b10, /* MC_EMEM_ARB_DA_COVERS */
1788                         0x71c81811, /* MC_EMEM_ARB_MISC0 */
1789                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1790                         0xd0000000, /* EMC_FBIO_SPARE */
1791                         0xff00ff00, /* EMC_CFG_RSV */
1792                 },
1793                 0x00000030, /* EMC_ZCAL_WAIT_CNT after clock change */
1794                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1795                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1796                 0x00000000, /* Mode Register 0 */
1797                 0x000100c2, /* Mode Register 1 */
1798                 0x00020006, /* Mode Register 2 */
1799         },
1800 };
1801
1802 int cardhu_emc_init(void)
1803 {
1804         struct board_info board;
1805
1806         tegra_get_board_info(&board);
1807
1808         switch (board.board_id) {
1809         case BOARD_PM269:
1810                 tegra_init_emc(cardhu_emc_tables_k4p8g304eb,
1811                                 ARRAY_SIZE(cardhu_emc_tables_k4p8g304eb));
1812                 break;
1813         default:
1814                 if (tegra_get_revision() == TEGRA_REVISION_A01)
1815                         tegra_init_emc(cardhu_emc_tables_h5tc2g,
1816                                 ARRAY_SIZE(cardhu_emc_tables_h5tc2g));
1817                 else
1818                         tegra_init_emc(cardhu_emc_tables_h5tc2g_a2,
1819                                 ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2));
1820                 break;
1821         }
1822
1823         return 0;
1824 }