arm: tegra: cardhu: add support for PM315
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-memory.c
1 /*
2  * Copyright (C) 2011-2012 NVIDIA Corporation. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_data/tegra_emc.h>
22 #include <mach/hardware.h>
23
24 #include "board.h"
25 #include "board-cardhu.h"
26 #include "tegra3_emc.h"
27 #include "fuse.h"
28 #include "devices.h"
29
30 static const struct tegra30_emc_table cardhu_emc_tables_h5tc4g83mfr[] = {
31         {
32                 0x32,       /* Rev 3.2 */
33                 51000,      /* SDRAM frequency */
34                 {
35                         0x00000002, /* EMC_RC */
36                         0x0000000d, /* EMC_RFC */
37                         0x00000001, /* EMC_RAS */
38                         0x00000000, /* EMC_RP */
39                         0x00000002, /* EMC_R2W */
40                         0x0000000a, /* EMC_W2R */
41                         0x00000003, /* EMC_R2P */
42                         0x0000000b, /* EMC_W2P */
43                         0x00000000, /* EMC_RD_RCD */
44                         0x00000000, /* EMC_WR_RCD */
45                         0x00000003, /* EMC_RRD */
46                         0x00000001, /* EMC_REXT */
47                         0x00000000, /* EMC_WEXT */
48                         0x00000005, /* EMC_WDV */
49                         0x00000005, /* EMC_QUSE */
50                         0x00000004, /* EMC_QRST */
51                         0x00000009, /* EMC_QSAFE */
52                         0x0000000b, /* EMC_RDV */
53                         0x00000181, /* EMC_REFRESH */
54                         0x00000000, /* EMC_BURST_REFRESH_NUM */
55                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
56                         0x00000002, /* EMC_PDEX2WR */
57                         0x00000002, /* EMC_PDEX2RD */
58                         0x00000001, /* EMC_PCHG2PDEN */
59                         0x00000000, /* EMC_ACT2PDEN */
60                         0x00000007, /* EMC_AR2PDEN */
61                         0x0000000f, /* EMC_RW2PDEN */
62                         0x0000000e, /* EMC_TXSR */
63                         0x0000000e, /* EMC_TXSRDLL */
64                         0x00000004, /* EMC_TCKE */
65                         0x00000002, /* EMC_TFAW */
66                         0x00000000, /* EMC_TRPAB */
67                         0x00000004, /* EMC_TCLKSTABLE */
68                         0x00000005, /* EMC_TCLKSTOP */
69                         0x0000018e, /* EMC_TREFBW */
70                         0x00000006, /* EMC_QUSE_EXTRA */
71                         0x00000004, /* EMC_FBIO_CFG6 */
72                         0x00000000, /* EMC_ODT_WRITE */
73                         0x00000000, /* EMC_ODT_READ */
74                         0x00004288, /* EMC_FBIO_CFG5 */
75                         0x007800a4, /* EMC_CFG_DIG_DLL */
76                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
77                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
78                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
79                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
80                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
81                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
82                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
83                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
84                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
85                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
86                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
87                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
88                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
89                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
90                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
91                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
92                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
93                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
94                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
95                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
96                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
97                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
98                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
99                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
100                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
101                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
102                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
103                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
104                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
105                         0x000002a0, /* EMC_XM2CMDPADCTRL */
106                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
107                         0x00000000, /* EMC_XM2DQPADCTRL2 */
108                         0x77fff884, /* EMC_XM2CLKPADCTRL */
109                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
110                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
111                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
112                         0x08000168, /* EMC_XM2QUSEPADCTRL */
113                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
114                         0x00000802, /* EMC_CTT_TERM_CTRL */
115                         0x00000000, /* EMC_ZCAL_INTERVAL */
116                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
117                         0x000c000c, /* EMC_MRS_WAIT_CNT */
118                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
119                         0x00000000, /* EMC_CTT */
120                         0x00000000, /* EMC_CTT_DURATION */
121                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
122                         0x00010003, /* MC_EMEM_ARB_CFG */
123                         0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
124                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
125                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
126                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
127                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
128                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
129                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
130                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
131                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
132                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
133                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
134                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
135                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
136                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
137                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
138                         0x74630303, /* MC_EMEM_ARB_MISC0 */
139                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
140                         0xe8000000, /* EMC_FBIO_SPARE */
141                         0xff00ff00, /* EMC_CFG_RSV */
142                 },
143                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
144                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
145                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
146                 0x80001221, /* Mode Register 0 */
147                 0x80100003, /* Mode Register 1 */
148                 0x80200008, /* Mode Register 2 */
149                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
150         },
151         {
152                 0x32,       /* Rev 3.2 */
153                 102000,     /* SDRAM frequency */
154                 {
155                         0x00000004, /* EMC_RC */
156                         0x0000001a, /* EMC_RFC */
157                         0x00000003, /* EMC_RAS */
158                         0x00000001, /* EMC_RP */
159                         0x00000002, /* EMC_R2W */
160                         0x0000000a, /* EMC_W2R */
161                         0x00000003, /* EMC_R2P */
162                         0x0000000b, /* EMC_W2P */
163                         0x00000001, /* EMC_RD_RCD */
164                         0x00000001, /* EMC_WR_RCD */
165                         0x00000003, /* EMC_RRD */
166                         0x00000001, /* EMC_REXT */
167                         0x00000000, /* EMC_WEXT */
168                         0x00000005, /* EMC_WDV */
169                         0x00000005, /* EMC_QUSE */
170                         0x00000004, /* EMC_QRST */
171                         0x00000009, /* EMC_QSAFE */
172                         0x0000000b, /* EMC_RDV */
173                         0x00000303, /* EMC_REFRESH */
174                         0x00000000, /* EMC_BURST_REFRESH_NUM */
175                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
176                         0x00000002, /* EMC_PDEX2WR */
177                         0x00000002, /* EMC_PDEX2RD */
178                         0x00000001, /* EMC_PCHG2PDEN */
179                         0x00000000, /* EMC_ACT2PDEN */
180                         0x00000007, /* EMC_AR2PDEN */
181                         0x0000000f, /* EMC_RW2PDEN */
182                         0x0000001c, /* EMC_TXSR */
183                         0x0000001c, /* EMC_TXSRDLL */
184                         0x00000004, /* EMC_TCKE */
185                         0x00000004, /* EMC_TFAW */
186                         0x00000000, /* EMC_TRPAB */
187                         0x00000004, /* EMC_TCLKSTABLE */
188                         0x00000005, /* EMC_TCLKSTOP */
189                         0x0000031c, /* EMC_TREFBW */
190                         0x00000006, /* EMC_QUSE_EXTRA */
191                         0x00000004, /* EMC_FBIO_CFG6 */
192                         0x00000000, /* EMC_ODT_WRITE */
193                         0x00000000, /* EMC_ODT_READ */
194                         0x00004288, /* EMC_FBIO_CFG5 */
195                         0x007800a4, /* EMC_CFG_DIG_DLL */
196                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
197                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
198                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
199                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
200                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
201                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
202                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
203                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
204                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
205                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
206                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
207                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
208                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
209                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
210                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
211                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
212                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
213                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
214                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
215                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
216                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
217                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
218                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
219                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
220                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
221                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
222                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
223                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
224                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
225                         0x000002a0, /* EMC_XM2CMDPADCTRL */
226                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
227                         0x00000000, /* EMC_XM2DQPADCTRL2 */
228                         0x77fff884, /* EMC_XM2CLKPADCTRL */
229                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
230                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
231                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
232                         0x08000168, /* EMC_XM2QUSEPADCTRL */
233                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
234                         0x00000802, /* EMC_CTT_TERM_CTRL */
235                         0x00000000, /* EMC_ZCAL_INTERVAL */
236                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
237                         0x000c000c, /* EMC_MRS_WAIT_CNT */
238                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
239                         0x00000000, /* EMC_CTT */
240                         0x00000000, /* EMC_CTT_DURATION */
241                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
242                         0x00000001, /* MC_EMEM_ARB_CFG */
243                         0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
244                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
245                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
246                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
247                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
248                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
249                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
250                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
251                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
252                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
253                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
254                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
255                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
256                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
257                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
258                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
259                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
260                         0xe8000000, /* EMC_FBIO_SPARE */
261                         0xff00ff00, /* EMC_CFG_RSV */
262                 },
263                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
264                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
265                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
266                 0x80001221, /* Mode Register 0 */
267                 0x80100003, /* Mode Register 1 */
268                 0x80200008, /* Mode Register 2 */
269                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
270         },
271         {
272                 0x32,       /* Rev 3.2 */
273                 204000,     /* SDRAM frequency */
274                 {
275                         0x00000009, /* EMC_RC */
276                         0x00000035, /* EMC_RFC */
277                         0x00000007, /* EMC_RAS */
278                         0x00000002, /* EMC_RP */
279                         0x00000002, /* EMC_R2W */
280                         0x0000000a, /* EMC_W2R */
281                         0x00000003, /* EMC_R2P */
282                         0x0000000b, /* EMC_W2P */
283                         0x00000002, /* EMC_RD_RCD */
284                         0x00000002, /* EMC_WR_RCD */
285                         0x00000003, /* EMC_RRD */
286                         0x00000001, /* EMC_REXT */
287                         0x00000000, /* EMC_WEXT */
288                         0x00000005, /* EMC_WDV */
289                         0x00000005, /* EMC_QUSE */
290                         0x00000004, /* EMC_QRST */
291                         0x00000009, /* EMC_QSAFE */
292                         0x0000000b, /* EMC_RDV */
293                         0x00000607, /* EMC_REFRESH */
294                         0x00000000, /* EMC_BURST_REFRESH_NUM */
295                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
296                         0x00000002, /* EMC_PDEX2WR */
297                         0x00000002, /* EMC_PDEX2RD */
298                         0x00000001, /* EMC_PCHG2PDEN */
299                         0x00000000, /* EMC_ACT2PDEN */
300                         0x00000007, /* EMC_AR2PDEN */
301                         0x0000000f, /* EMC_RW2PDEN */
302                         0x00000038, /* EMC_TXSR */
303                         0x00000038, /* EMC_TXSRDLL */
304                         0x00000004, /* EMC_TCKE */
305                         0x00000007, /* EMC_TFAW */
306                         0x00000000, /* EMC_TRPAB */
307                         0x00000004, /* EMC_TCLKSTABLE */
308                         0x00000005, /* EMC_TCLKSTOP */
309                         0x00000638, /* EMC_TREFBW */
310                         0x00000006, /* EMC_QUSE_EXTRA */
311                         0x00000004, /* EMC_FBIO_CFG6 */
312                         0x00000000, /* EMC_ODT_WRITE */
313                         0x00000000, /* EMC_ODT_READ */
314                         0x00004288, /* EMC_FBIO_CFG5 */
315                         0x004400a4, /* EMC_CFG_DIG_DLL */
316                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
317                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
318                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
319                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
320                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
321                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
322                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
323                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
324                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
325                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
326                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
327                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
328                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
329                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
330                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
331                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
332                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
333                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
334                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
335                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
336                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
337                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
338                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
339                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
340                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
341                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
342                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
343                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
344                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
345                         0x000002a0, /* EMC_XM2CMDPADCTRL */
346                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
347                         0x00000000, /* EMC_XM2DQPADCTRL2 */
348                         0x77fff884, /* EMC_XM2CLKPADCTRL */
349                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
350                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
351                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
352                         0x08000168, /* EMC_XM2QUSEPADCTRL */
353                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
354                         0x00000802, /* EMC_CTT_TERM_CTRL */
355                         0x00020000, /* EMC_ZCAL_INTERVAL */
356                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
357                         0x000c000c, /* EMC_MRS_WAIT_CNT */
358                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
359                         0x00000000, /* EMC_CTT */
360                         0x00000000, /* EMC_CTT_DURATION */
361                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
362                         0x00000003, /* MC_EMEM_ARB_CFG */
363                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
364                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
365                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
366                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
367                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
368                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
369                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
370                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
371                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
372                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
373                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
374                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
375                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
376                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
377                         0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
378                         0x73840a06, /* MC_EMEM_ARB_MISC0 */
379                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
380                         0xe8000000, /* EMC_FBIO_SPARE */
381                         0xff00ff00, /* EMC_CFG_RSV */
382                 },
383                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
384                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
385                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
386                 0x80001221, /* Mode Register 0 */
387                 0x80100003, /* Mode Register 1 */
388                 0x80200008, /* Mode Register 2 */
389                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
390         },
391         {
392                 0x32,       /* Rev 3.2 */
393                 400000,     /* SDRAM frequency */
394                 {
395                         0x00000012, /* EMC_RC */
396                         0x00000066, /* EMC_RFC */
397                         0x0000000c, /* EMC_RAS */
398                         0x00000004, /* EMC_RP */
399                         0x00000003, /* EMC_R2W */
400                         0x00000008, /* EMC_W2R */
401                         0x00000002, /* EMC_R2P */
402                         0x0000000a, /* EMC_W2P */
403                         0x00000004, /* EMC_RD_RCD */
404                         0x00000004, /* EMC_WR_RCD */
405                         0x00000002, /* EMC_RRD */
406                         0x00000001, /* EMC_REXT */
407                         0x00000000, /* EMC_WEXT */
408                         0x00000004, /* EMC_WDV */
409                         0x00000006, /* EMC_QUSE */
410                         0x00000004, /* EMC_QRST */
411                         0x0000000a, /* EMC_QSAFE */
412                         0x0000000d, /* EMC_RDV */
413                         0x00000bf0, /* EMC_REFRESH */
414                         0x00000000, /* EMC_BURST_REFRESH_NUM */
415                         0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */
416                         0x00000001, /* EMC_PDEX2WR */
417                         0x00000008, /* EMC_PDEX2RD */
418                         0x00000001, /* EMC_PCHG2PDEN */
419                         0x00000000, /* EMC_ACT2PDEN */
420                         0x00000008, /* EMC_AR2PDEN */
421                         0x0000000f, /* EMC_RW2PDEN */
422                         0x0000006c, /* EMC_TXSR */
423                         0x00000200, /* EMC_TXSRDLL */
424                         0x00000004, /* EMC_TCKE */
425                         0x0000000c, /* EMC_TFAW */
426                         0x00000000, /* EMC_TRPAB */
427                         0x00000004, /* EMC_TCLKSTABLE */
428                         0x00000005, /* EMC_TCLKSTOP */
429                         0x00000c30, /* EMC_TREFBW */
430                         0x00000000, /* EMC_QUSE_EXTRA */
431                         0x00000006, /* EMC_FBIO_CFG6 */
432                         0x00000000, /* EMC_ODT_WRITE */
433                         0x00000000, /* EMC_ODT_READ */
434                         0x00007088, /* EMC_FBIO_CFG5 */
435                         0x001d0084, /* EMC_CFG_DIG_DLL */
436                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
437                         0x00038000, /* EMC_DLL_XFORM_DQS0 */
438                         0x00038000, /* EMC_DLL_XFORM_DQS1 */
439                         0x00038000, /* EMC_DLL_XFORM_DQS2 */
440                         0x00038000, /* EMC_DLL_XFORM_DQS3 */
441                         0x00038000, /* EMC_DLL_XFORM_DQS4 */
442                         0x00038000, /* EMC_DLL_XFORM_DQS5 */
443                         0x00038000, /* EMC_DLL_XFORM_DQS6 */
444                         0x00038000, /* EMC_DLL_XFORM_DQS7 */
445                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
446                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
447                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
448                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
449                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
450                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
451                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
452                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
453                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
454                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
455                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
456                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
457                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
458                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
459                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
460                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
461                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
462                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
463                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
464                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
465                         0x000002a0, /* EMC_XM2CMDPADCTRL */
466                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
467                         0x00000000, /* EMC_XM2DQPADCTRL2 */
468                         0x77fff884, /* EMC_XM2CLKPADCTRL */
469                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
470                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
471                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
472                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
473                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
474                         0x00000802, /* EMC_CTT_TERM_CTRL */
475                         0x00020000, /* EMC_ZCAL_INTERVAL */
476                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
477                         0x0158000c, /* EMC_MRS_WAIT_CNT */
478                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
479                         0x00000000, /* EMC_CTT */
480                         0x00000000, /* EMC_CTT_DURATION */
481                         0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
482                         0x00000006, /* MC_EMEM_ARB_CFG */
483                         0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
484                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
485                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
486                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
487                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
488                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
489                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
490                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
491                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
492                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
493                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
494                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
495                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
496                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
497                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
498                         0x7086120a, /* MC_EMEM_ARB_MISC0 */
499                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
500                         0xe8000000, /* EMC_FBIO_SPARE */
501                         0xff00ff89, /* EMC_CFG_RSV */
502                 },
503                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
504                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
505                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
506                 0x80000521, /* Mode Register 0 */
507                 0x80100002, /* Mode Register 1 */
508                 0x80200000, /* Mode Register 2 */
509                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
510         },
511         {
512                 0x32,       /* Rev 3.2 */
513                 800000,     /* SDRAM frequency */
514                 {
515                         0x00000025, /* EMC_RC */
516                         0x000000ee, /* EMC_RFC */
517                         0x0000001a, /* EMC_RAS */
518                         0x00000009, /* EMC_RP */
519                         0x00000005, /* EMC_R2W */
520                         0x0000000d, /* EMC_W2R */
521                         0x00000004, /* EMC_R2P */
522                         0x00000013, /* EMC_W2P */
523                         0x00000009, /* EMC_RD_RCD */
524                         0x00000009, /* EMC_WR_RCD */
525                         0x00000003, /* EMC_RRD */
526                         0x00000001, /* EMC_REXT */
527                         0x00000000, /* EMC_WEXT */
528                         0x00000007, /* EMC_WDV */
529                         0x0000000b, /* EMC_QUSE */
530                         0x00000009, /* EMC_QRST */
531                         0x0000000b, /* EMC_QSAFE */
532                         0x00000012, /* EMC_RDV */
533                         0x00001820, /* EMC_REFRESH */
534                         0x00000000, /* EMC_BURST_REFRESH_NUM */
535                         0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
536                         0x00000003, /* EMC_PDEX2WR */
537                         0x00000012, /* EMC_PDEX2RD */
538                         0x00000001, /* EMC_PCHG2PDEN */
539                         0x00000000, /* EMC_ACT2PDEN */
540                         0x0000000f, /* EMC_AR2PDEN */
541                         0x00000018, /* EMC_RW2PDEN */
542                         0x000000f8, /* EMC_TXSR */
543                         0x00000200, /* EMC_TXSRDLL */
544                         0x00000005, /* EMC_TCKE */
545                         0x00000018, /* EMC_TFAW */
546                         0x00000000, /* EMC_TRPAB */
547                         0x00000007, /* EMC_TCLKSTABLE */
548                         0x00000008, /* EMC_TCLKSTOP */
549                         0x00001860, /* EMC_TREFBW */
550                         0x0000000c, /* EMC_QUSE_EXTRA */
551                         0x00000004, /* EMC_FBIO_CFG6 */
552                         0x00000000, /* EMC_ODT_WRITE */
553                         0x00000000, /* EMC_ODT_READ */
554                         0x00005088, /* EMC_FBIO_CFG5 */
555                         0xf0070191, /* EMC_CFG_DIG_DLL */
556                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
557                         0x0000c00a, /* EMC_DLL_XFORM_DQS0 */
558                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
559                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
560                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
561                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
562                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
563                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
564                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
565                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
566                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
567                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
568                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
569                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
570                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
571                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
572                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
573                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
574                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
575                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
576                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
577                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
578                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
579                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
580                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
581                         0x0000000a, /* EMC_DLL_XFORM_DQ0 */
582                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
583                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
584                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
585                         0x000002a0, /* EMC_XM2CMDPADCTRL */
586                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
587                         0x22220000, /* EMC_XM2DQPADCTRL2 */
588                         0x77fff884, /* EMC_XM2CLKPADCTRL */
589                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
590                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
591                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
592                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
593                         0x06000021, /* EMC_XM2DQSPADCTRL3 */
594                         0x00000802, /* EMC_CTT_TERM_CTRL */
595                         0x00020000, /* EMC_ZCAL_INTERVAL */
596                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
597                         0x00d0000c, /* EMC_MRS_WAIT_CNT */
598                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
599                         0x00000000, /* EMC_CTT */
600                         0x00000000, /* EMC_CTT_DURATION */
601                         0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
602                         0x0000000c, /* MC_EMEM_ARB_CFG */
603                         0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
604                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
605                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
606                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
607                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
608                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
609                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
610                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
611                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
612                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
613                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
614                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
615                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
616                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
617                         0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
618                         0x712c2414, /* MC_EMEM_ARB_MISC0 */
619                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
620                         0xe8000000, /* EMC_FBIO_SPARE */
621                         0xff00ff49, /* EMC_CFG_RSV */
622                 },
623                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
624                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
625                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
626                 0x80000d71, /* Mode Register 0 */
627                 0x80100002, /* Mode Register 1 */
628                 0x80200018, /* Mode Register 2 */
629                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
630         }
631 };
632
633 static const struct tegra30_emc_table cardhu_emc_tables_h5tc2g[] = {
634         {
635                 0x30,           /* Rev 3.0 */
636                 27000,          /* SDRAM frquency */
637                 {
638                         0x00000001,   /* EMC_RC */
639                         0x00000004,   /* EMC_RFC */
640                         0x00000000,   /* EMC_RAS */
641                         0x00000000,   /* EMC_RP */
642                         0x00000002,   /* EMC_R2W */
643                         0x0000000a,   /* EMC_W2R */
644                         0x00000003,   /* EMC_R2P */
645                         0x0000000b,   /* EMC_W2P */
646                         0x00000000,   /* EMC_RD_RCD */
647                         0x00000000,   /* EMC_WR_RCD */
648                         0x00000003,   /* EMC_RRD */
649                         0x00000001,   /* EMC_REXT */
650                         0x00000000,   /* EMC_WEXT */
651                         0x00000005,   /* EMC_WDV */
652                         0x00000005,   /* EMC_QUSE */
653                         0x00000004,   /* EMC_QRST */
654                         0x00000007,   /* EMC_QSAFE */
655                         0x0000000d,   /* EMC_RDV */
656                         0x000000cb,   /* EMC_REFRESH */
657                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
658                         0x00000032,   /* EMC_PRE_REFRESH_REQ_CNT */
659                         0x00000002,   /* EMC_PDEX2WR */
660                         0x00000002,   /* EMC_PDEX2RD */
661                         0x00000001,   /* EMC_PCHG2PDEN */
662                         0x00000000,   /* EMC_ACT2PDEN */
663                         0x00000007,   /* EMC_AR2PDEN */
664                         0x0000000f,   /* EMC_RW2PDEN */
665                         0x00000005,   /* EMC_TXSR */
666                         0x00000005,   /* EMC_TXSRDLL */
667                         0x00000004,   /* EMC_TCKE */
668                         0x00000001,   /* EMC_TFAW */
669                         0x00000000,   /* EMC_TRPAB */
670                         0x00000004,   /* EMC_TCLKSTABLE */
671                         0x00000005,   /* EMC_TCLKSTOP */
672                         0x000000d3,   /* EMC_TREFBW */
673                         0x00000000,   /* EMC_QUSE_EXTRA */
674                         0x00000004,   /* EMC_FBIO_CFG6 */
675                         0x00000000,   /* EMC_ODT_WRITE */
676                         0x00000000,   /* EMC_ODT_READ */
677                         0x00006288,   /* EMC_FBIO_CFG5 */
678                         0xd0780421,   /* EMC_CFG_DIG_DLL */
679                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
680                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
681                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
682                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
683                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
684                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
685                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
686                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
687                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
688                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
689                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
690                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
691                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
692                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
693                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
694                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
695                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
696                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
697                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
698                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
699                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
700                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
701                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
702                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
703                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
704                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
705                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
706                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
707                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
708                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
709                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
710                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
711                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
712                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
713                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
714                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
715                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
716                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
717                         0x00000802,   /* EMC_CTT_TERM_CTRL */
718                         0x00000000,   /* EMC_ZCAL_INTERVAL */
719                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
720                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
721                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
722                         0x00000000,   /* EMC_CTT */
723                         0x00000000,   /* EMC_CTT_DURATION */
724                         0x8000029e,   /* EMC_DYN_SELF_REF_CONTROL */
725                         0x00000001,   /* MC_EMEM_ARB_CFG */
726                         0x8000000d,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
727                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
728                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
729                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
730                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
731                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
732                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
733                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
734                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
735                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
736                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
737                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
738                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
739                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
740                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
741                         0x78430306,   /* MC_EMEM_ARB_MISC0 */
742                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
743                 },
744                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
745                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
746                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
747                 0x00001221,     /* Mode Register 0 */
748                 0x00100003,     /* Mode Register 1 */
749                 0x00200008,     /* Mode Register 2 */
750         },
751         {
752                 0x30,           /* Rev 3.0 */
753                 54000,          /* SDRAM frquency */
754                 {
755                         0x00000002,   /* EMC_RC */
756                         0x00000008,   /* EMC_RFC */
757                         0x00000001,   /* EMC_RAS */
758                         0x00000000,   /* EMC_RP */
759                         0x00000002,   /* EMC_R2W */
760                         0x0000000a,   /* EMC_W2R */
761                         0x00000003,   /* EMC_R2P */
762                         0x0000000b,   /* EMC_W2P */
763                         0x00000000,   /* EMC_RD_RCD */
764                         0x00000000,   /* EMC_WR_RCD */
765                         0x00000003,   /* EMC_RRD */
766                         0x00000001,   /* EMC_REXT */
767                         0x00000000,   /* EMC_WEXT */
768                         0x00000005,   /* EMC_WDV */
769                         0x00000005,   /* EMC_QUSE */
770                         0x00000004,   /* EMC_QRST */
771                         0x00000007,   /* EMC_QSAFE */
772                         0x0000000d,   /* EMC_RDV */
773                         0x00000198,   /* EMC_REFRESH */
774                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
775                         0x00000066,   /* EMC_PRE_REFRESH_REQ_CNT */
776                         0x00000002,   /* EMC_PDEX2WR */
777                         0x00000002,   /* EMC_PDEX2RD */
778                         0x00000001,   /* EMC_PCHG2PDEN */
779                         0x00000000,   /* EMC_ACT2PDEN */
780                         0x00000007,   /* EMC_AR2PDEN */
781                         0x0000000f,   /* EMC_RW2PDEN */
782                         0x0000000a,   /* EMC_TXSR */
783                         0x0000000a,   /* EMC_TXSRDLL */
784                         0x00000004,   /* EMC_TCKE */
785                         0x00000002,   /* EMC_TFAW */
786                         0x00000000,   /* EMC_TRPAB */
787                         0x00000004,   /* EMC_TCLKSTABLE */
788                         0x00000005,   /* EMC_TCLKSTOP */
789                         0x000001a6,   /* EMC_TREFBW */
790                         0x00000000,   /* EMC_QUSE_EXTRA */
791                         0x00000004,   /* EMC_FBIO_CFG6 */
792                         0x00000000,   /* EMC_ODT_WRITE */
793                         0x00000000,   /* EMC_ODT_READ */
794                         0x00006288,   /* EMC_FBIO_CFG5 */
795                         0xd0780421,   /* EMC_CFG_DIG_DLL */
796                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
797                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
798                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
799                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
800                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
801                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
802                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
803                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
804                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
805                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
806                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
807                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
808                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
809                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
810                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
811                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
812                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
813                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
814                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
815                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
816                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
817                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
818                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
819                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
820                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
821                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
822                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
823                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
824                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
825                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
826                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
827                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
828                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
829                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
830                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
831                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
832                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
833                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
834                         0x00000802,   /* EMC_CTT_TERM_CTRL */
835                         0x00000000,   /* EMC_ZCAL_INTERVAL */
836                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
837                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
838                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
839                         0x00000000,   /* EMC_CTT */
840                         0x00000000,   /* EMC_CTT_DURATION */
841                         0x80000439,   /* EMC_DYN_SELF_REF_CONTROL */
842                         0x00000001,   /* MC_EMEM_ARB_CFG */
843                         0x80000014,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
844                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
845                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
846                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
847                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
848                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
849                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
850                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
851                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
852                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
853                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
854                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
855                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
856                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
857                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
858                         0x78430506,   /* MC_EMEM_ARB_MISC0 */
859                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
860                 },
861                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
862                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
863                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
864                 0x00001221,     /* Mode Register 0 */
865                 0x00100003,     /* Mode Register 1 */
866                 0x00200008,     /* Mode Register 2 */
867         },
868         {
869                 0x30,           /* Rev 3.0 */
870                 108000,         /* SDRAM frquency */
871                 {
872                         0x00000005,   /* EMC_RC */
873                         0x00000011,   /* EMC_RFC */
874                         0x00000003,   /* EMC_RAS */
875                         0x00000001,   /* EMC_RP */
876                         0x00000002,   /* EMC_R2W */
877                         0x0000000a,   /* EMC_W2R */
878                         0x00000003,   /* EMC_R2P */
879                         0x0000000b,   /* EMC_W2P */
880                         0x00000001,   /* EMC_RD_RCD */
881                         0x00000001,   /* EMC_WR_RCD */
882                         0x00000003,   /* EMC_RRD */
883                         0x00000001,   /* EMC_REXT */
884                         0x00000000,   /* EMC_WEXT */
885                         0x00000005,   /* EMC_WDV */
886                         0x00000005,   /* EMC_QUSE */
887                         0x00000004,   /* EMC_QRST */
888                         0x00000007,   /* EMC_QSAFE */
889                         0x0000000d,   /* EMC_RDV */
890                         0x00000330,   /* EMC_REFRESH */
891                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
892                         0x000000cc,   /* EMC_PRE_REFRESH_REQ_CNT */
893                         0x00000002,   /* EMC_PDEX2WR */
894                         0x00000002,   /* EMC_PDEX2RD */
895                         0x00000001,   /* EMC_PCHG2PDEN */
896                         0x00000000,   /* EMC_ACT2PDEN */
897                         0x00000007,   /* EMC_AR2PDEN */
898                         0x0000000f,   /* EMC_RW2PDEN */
899                         0x00000013,   /* EMC_TXSR */
900                         0x00000013,   /* EMC_TXSRDLL */
901                         0x00000004,   /* EMC_TCKE */
902                         0x00000004,   /* EMC_TFAW */
903                         0x00000000,   /* EMC_TRPAB */
904                         0x00000004,   /* EMC_TCLKSTABLE */
905                         0x00000005,   /* EMC_TCLKSTOP */
906                         0x0000034b,   /* EMC_TREFBW */
907                         0x00000000,   /* EMC_QUSE_EXTRA */
908                         0x00000004,   /* EMC_FBIO_CFG6 */
909                         0x00000000,   /* EMC_ODT_WRITE */
910                         0x00000000,   /* EMC_ODT_READ */
911                         0x00006288,   /* EMC_FBIO_CFG5 */
912                         0xd0780421,   /* EMC_CFG_DIG_DLL */
913                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
914                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
915                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
916                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
917                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
918                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
919                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
920                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
921                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
922                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
923                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
924                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
925                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
926                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
927                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
928                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
929                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
930                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
931                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
932                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
933                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
934                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
935                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
936                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
937                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
938                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
939                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
940                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
941                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
942                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
943                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
944                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
945                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
946                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
947                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
948                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
949                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
950                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
951                         0x00000802,   /* EMC_CTT_TERM_CTRL */
952                         0x00000000,   /* EMC_ZCAL_INTERVAL */
953                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
954                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
955                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
956                         0x00000000,   /* EMC_CTT */
957                         0x00000000,   /* EMC_CTT_DURATION */
958                         0x8000076e,   /* EMC_DYN_SELF_REF_CONTROL */
959                         0x00000003,   /* MC_EMEM_ARB_CFG */
960                         0x80000027,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
961                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
962                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
963                         0x00000006,   /* MC_EMEM_ARB_TIMING_RC */
964                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAS */
965                         0x00000003,   /* MC_EMEM_ARB_TIMING_FAW */
966                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
967                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
968                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
969                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
970                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
971                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
972                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
973                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
974                         0x00140906,   /* MC_EMEM_ARB_DA_COVERS */
975                         0x78440a07,   /* MC_EMEM_ARB_MISC0 */
976                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
977                 },
978                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
979                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
980                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
981                 0x00001221,     /* Mode Register 0 */
982                 0x00100003,     /* Mode Register 1 */
983                 0x00200008,     /* Mode Register 2 */
984         },
985         {
986                 0x30,           /* Rev 3.0 */
987                 416000,         /* SDRAM frequency */
988                 {
989                         0x00000013,   /* EMC_RC */
990                         0x00000041,   /* EMC_RFC */
991                         0x0000000d,   /* EMC_RAS */
992                         0x00000004,   /* EMC_RP */
993                         0x00000002,   /* EMC_R2W */
994                         0x00000009,   /* EMC_W2R */
995                         0x00000002,   /* EMC_R2P */
996                         0x0000000c,   /* EMC_W2P */
997                         0x00000004,   /* EMC_RD_RCD */
998                         0x00000004,   /* EMC_WR_RCD */
999                         0x00000002,   /* EMC_RRD */
1000                         0x00000001,   /* EMC_REXT */
1001                         0x00000000,   /* EMC_WEXT */
1002                         0x00000005,   /* EMC_WDV */
1003                         0x00000008,   /* EMC_QUSE */
1004                         0x00000006,   /* EMC_QRST */
1005                         0x00000008,   /* EMC_QSAFE */
1006                         0x00000010,   /* EMC_RDV */
1007                         0x00000c6c,   /* EMC_REFRESH */
1008                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
1009                         0x0000031b,   /* EMC_PRE_REFRESH_REQ_CNT */
1010                         0x00000001,   /* EMC_PDEX2WR */
1011                         0x00000001,   /* EMC_PDEX2RD */
1012                         0x00000001,   /* EMC_PCHG2PDEN */
1013                         0x00000000,   /* EMC_ACT2PDEN */
1014                         0x00000008,   /* EMC_AR2PDEN */
1015                         0x00000011,   /* EMC_RW2PDEN */
1016                         0x00000047,   /* EMC_TXSR */
1017                         0x00000200,   /* EMC_TXSRDLL */
1018                         0x00000004,   /* EMC_TCKE */
1019                         0x0000000d,   /* EMC_TFAW */
1020                         0x00000000,   /* EMC_TRPAB */
1021                         0x00000004,   /* EMC_TCLKSTABLE */
1022                         0x00000005,   /* EMC_TCLKSTOP */
1023                         0x00000cad,   /* EMC_TREFBW */
1024                         0x00000000,   /* EMC_QUSE_EXTRA */
1025                         0x00000006,   /* EMC_FBIO_CFG6 */
1026                         0x00000000,   /* EMC_ODT_WRITE */
1027                         0x00000000,   /* EMC_ODT_READ */
1028                         0x00007088,   /* EMC_FBIO_CFG5 */
1029                         0xf0120441,   /* EMC_CFG_DIG_DLL */
1030                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
1031                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
1032                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
1033                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
1034                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
1035                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
1036                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
1037                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
1038                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
1039                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
1040                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
1041                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
1042                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
1043                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
1044                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
1045                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
1046                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
1047                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
1048                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
1049                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
1050                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
1051                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
1052                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
1053                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
1054                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
1055                         0x00020000,   /* EMC_DLL_XFORM_DQ0 */
1056                         0x00020000,   /* EMC_DLL_XFORM_DQ1 */
1057                         0x00020000,   /* EMC_DLL_XFORM_DQ2 */
1058                         0x00020000,   /* EMC_DLL_XFORM_DQ3 */
1059                         0x000006a0,   /* EMC_XM2CMDPADCTRL */
1060                         0x0800013d,   /* EMC_XM2DQSPADCTRL2 */
1061                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
1062                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
1063                         0x01f1f50f,   /* EMC_XM2COMPPADCTRL */
1064                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
1065                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
1066                         0x0800011d,   /* EMC_XM2QUSEPADCTRL */
1067                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
1068                         0x00000802,   /* EMC_CTT_TERM_CTRL */
1069                         0x00000000,   /* EMC_ZCAL_INTERVAL */
1070                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
1071                         0x01be000c,   /* EMC_MRS_WAIT_CNT */
1072                         0xa0f10404,   /* EMC_AUTO_CAL_CONFIG */
1073                         0x00000000,   /* EMC_CTT */
1074                         0x00000000,   /* EMC_CTT_DURATION */
1075                         0x000020ae,   /* EMC_DYN_SELF_REF_CONTROL */
1076                         0x00000006,   /* MC_EMEM_ARB_CFG */
1077                         0x8000004b,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
1078                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
1079                         0x00000002,   /* MC_EMEM_ARB_TIMING_RP */
1080                         0x0000000a,   /* MC_EMEM_ARB_TIMING_RC */
1081                         0x00000006,   /* MC_EMEM_ARB_TIMING_RAS */
1082                         0x00000006,   /* MC_EMEM_ARB_TIMING_FAW */
1083                         0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
1084                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
1085                         0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
1086                         0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
1087                         0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
1088                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
1089                         0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
1090                         0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
1091                         0x000e070a,   /* MC_EMEM_ARB_DA_COVERS */
1092                         0x7027130b,   /* MC_EMEM_ARB_MISC0 */
1093                         0x001f0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
1094                 },
1095                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
1096                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
1097                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
1098                 0x00001941,     /* Mode Register 0 */
1099                 0x00100002,     /* Mode Register 1 */
1100                 0x00200008,     /* Mode Register 2 */
1101         },
1102         {
1103                 0x30,           /* Rev 3.0 */
1104                 533000,         /* SDRAM frquency */
1105                 {
1106                         0x00000018,   /* EMC_RC */
1107                         0x00000054,   /* EMC_RFC */
1108                         0x00000011,   /* EMC_RAS */
1109                         0x00000006,   /* EMC_RP */
1110                         0x00000003,   /* EMC_R2W */
1111                         0x00000009,   /* EMC_W2R */
1112                         0x00000002,   /* EMC_R2P */
1113                         0x0000000d,   /* EMC_W2P */
1114                         0x00000006,   /* EMC_RD_RCD */
1115                         0x00000006,   /* EMC_WR_RCD */
1116                         0x00000002,   /* EMC_RRD */
1117                         0x00000001,   /* EMC_REXT */
1118                         0x00000000,   /* EMC_WEXT */
1119                         0x00000005,   /* EMC_WDV */
1120                         0x00000008,   /* EMC_QUSE */
1121                         0x00000006,   /* EMC_QRST */
1122                         0x00000008,   /* EMC_QSAFE */
1123                         0x00000010,   /* EMC_RDV */
1124                         0x00000ffd,   /* EMC_REFRESH */
1125                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
1126                         0x000003ff,   /* EMC_PRE_REFRESH_REQ_CNT */
1127                         0x00000002,   /* EMC_PDEX2WR */
1128                         0x00000002,   /* EMC_PDEX2RD */
1129                         0x00000001,   /* EMC_PCHG2PDEN */
1130                         0x00000000,   /* EMC_ACT2PDEN */
1131                         0x0000000a,   /* EMC_AR2PDEN */
1132                         0x00000012,   /* EMC_RW2PDEN */
1133                         0x0000005b,   /* EMC_TXSR */
1134                         0x00000200,   /* EMC_TXSRDLL */
1135                         0x00000004,   /* EMC_TCKE */
1136                         0x00000010,   /* EMC_TFAW */
1137                         0x00000000,   /* EMC_TRPAB */
1138                         0x00000005,   /* EMC_TCLKSTABLE */
1139                         0x00000006,   /* EMC_TCLKSTOP */
1140                         0x0000103e,   /* EMC_TREFBW */
1141                         0x00000000,   /* EMC_QUSE_EXTRA */
1142                         0x00000006,   /* EMC_FBIO_CFG6 */
1143                         0x00000000,   /* EMC_ODT_WRITE */
1144                         0x00000000,   /* EMC_ODT_READ */
1145                         0x00007088,   /* EMC_FBIO_CFG5 */
1146                         0xf0120441,   /* EMC_CFG_DIG_DLL */
1147                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
1148                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
1149                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
1150                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
1151                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
1152                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
1153                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
1154                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
1155                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
1156                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
1157                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
1158                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
1159                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
1160                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
1161                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
1162                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
1163                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
1164                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
1165                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
1166                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
1167                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
1168                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
1169                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
1170                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
1171                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
1172                         0x00020000,   /* EMC_DLL_XFORM_DQ0 */
1173                         0x00020000,   /* EMC_DLL_XFORM_DQ1 */
1174                         0x00020000,   /* EMC_DLL_XFORM_DQ2 */
1175                         0x00020000,   /* EMC_DLL_XFORM_DQ3 */
1176                         0x000006a0,   /* EMC_XM2CMDPADCTRL */
1177                         0x0800013d,   /* EMC_XM2DQSPADCTRL2 */
1178                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
1179                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
1180                         0x01f1f50f,   /* EMC_XM2COMPPADCTRL */
1181                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
1182                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
1183                         0x0800011d,   /* EMC_XM2QUSEPADCTRL */
1184                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
1185                         0x00000802,   /* EMC_CTT_TERM_CTRL */
1186                         0x00000000,   /* EMC_ZCAL_INTERVAL */
1187                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
1188                         0x01ab000c,   /* EMC_MRS_WAIT_CNT */
1189                         0xa0f10404,   /* EMC_AUTO_CAL_CONFIG */
1190                         0x00000000,   /* EMC_CTT */
1191                         0x00000000,   /* EMC_CTT_DURATION */
1192                         0x000020ae,   /* EMC_DYN_SELF_REF_CONTROL */
1193                         0x00000008,   /* MC_EMEM_ARB_CFG */
1194                         0x80000060,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
1195                         0x00000002,   /* MC_EMEM_ARB_TIMING_RCD */
1196                         0x00000003,   /* MC_EMEM_ARB_TIMING_RP */
1197                         0x0000000d,   /* MC_EMEM_ARB_TIMING_RC */
1198                         0x00000008,   /* MC_EMEM_ARB_TIMING_RAS */
1199                         0x00000007,   /* MC_EMEM_ARB_TIMING_FAW */
1200                         0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
1201                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
1202                         0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
1203                         0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
1204                         0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
1205                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
1206                         0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
1207                         0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
1208                         0x0010090d,   /* MC_EMEM_ARB_DA_COVERS */
1209                         0x7028180e,   /* MC_EMEM_ARB_MISC0 */
1210                         0x001f0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
1211                 },
1212                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
1213                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
1214                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
1215                 0x00001941,     /* Mode Register 0 */
1216                 0x00100002,     /* Mode Register 1 */
1217                 0x00200008,     /* Mode Register 2 */
1218         },
1219 };
1220
1221 static const struct tegra30_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
1222         {
1223                 0x32,       /* Rev 3.2 */
1224                 25500,      /* SDRAM frequency */
1225                 {
1226                         0x00000001, /* EMC_RC */
1227                         0x00000003, /* EMC_RFC */
1228                         0x00000000, /* EMC_RAS */
1229                         0x00000000, /* EMC_RP */
1230                         0x00000002, /* EMC_R2W */
1231                         0x0000000a, /* EMC_W2R */
1232                         0x00000003, /* EMC_R2P */
1233                         0x0000000b, /* EMC_W2P */
1234                         0x00000000, /* EMC_RD_RCD */
1235                         0x00000000, /* EMC_WR_RCD */
1236                         0x00000003, /* EMC_RRD */
1237                         0x00000001, /* EMC_REXT */
1238                         0x00000000, /* EMC_WEXT */
1239                         0x00000005, /* EMC_WDV */
1240                         0x00000005, /* EMC_QUSE */
1241                         0x00000004, /* EMC_QRST */
1242                         0x00000007, /* EMC_QSAFE */
1243                         0x0000000c, /* EMC_RDV */
1244                         0x000000bd, /* EMC_REFRESH */
1245                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1246                         0x0000002f, /* EMC_PRE_REFRESH_REQ_CNT */
1247                         0x00000002, /* EMC_PDEX2WR */
1248                         0x00000002, /* EMC_PDEX2RD */
1249                         0x00000001, /* EMC_PCHG2PDEN */
1250                         0x00000000, /* EMC_ACT2PDEN */
1251                         0x00000007, /* EMC_AR2PDEN */
1252                         0x0000000f, /* EMC_RW2PDEN */
1253                         0x00000005, /* EMC_TXSR */
1254                         0x00000005, /* EMC_TXSRDLL */
1255                         0x00000004, /* EMC_TCKE */
1256                         0x00000001, /* EMC_TFAW */
1257                         0x00000000, /* EMC_TRPAB */
1258                         0x00000004, /* EMC_TCLKSTABLE */
1259                         0x00000005, /* EMC_TCLKSTOP */
1260                         0x000000c3, /* EMC_TREFBW */
1261                         0x00000000, /* EMC_QUSE_EXTRA */
1262                         0x00000004, /* EMC_FBIO_CFG6 */
1263                         0x00000000, /* EMC_ODT_WRITE */
1264                         0x00000000, /* EMC_ODT_READ */
1265                         0x00006288, /* EMC_FBIO_CFG5 */
1266                         0x007800a4, /* EMC_CFG_DIG_DLL */
1267                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1268                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
1269                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
1270                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
1271                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
1272                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
1273                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
1274                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
1275                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
1276                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1277                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1278                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1279                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1280                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1281                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1282                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1283                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1284                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1285                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1286                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1287                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1288                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1289                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1290                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1291                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1292                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1293                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1294                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1295                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1296                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1297                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
1298                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1299                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
1300                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
1301                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1302                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1303                         0x08000168, /* EMC_XM2QUSEPADCTRL */
1304                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1305                         0x00000802, /* EMC_CTT_TERM_CTRL */
1306                         0x00000000, /* EMC_ZCAL_INTERVAL */
1307                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
1308                         0x000c000c, /* EMC_MRS_WAIT_CNT */
1309                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1310                         0x00000000, /* EMC_CTT */
1311                         0x00000000, /* EMC_CTT_DURATION */
1312                         0x80000280, /* EMC_DYN_SELF_REF_CONTROL */
1313                         0x00030003, /* MC_EMEM_ARB_CFG */
1314                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1315                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1316                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1317                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
1318                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
1319                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
1320                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1321                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1322                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1323                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1324                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1325                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1326                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1327                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
1328                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
1329                         0x74430303, /* MC_EMEM_ARB_MISC0 */
1330                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1331                         0xd8000000, /* EMC_FBIO_SPARE */
1332                         0xff00ff00, /* EMC_CFG_RSV */
1333                 },
1334                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1335                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1336                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1337                 0x80001221, /* Mode Register 0 */
1338                 0x80100003, /* Mode Register 1 */
1339                 0x80200008, /* Mode Register 2 */
1340                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1341         },
1342         {
1343                 0x32,       /* Rev 3.2 */
1344                 51000,      /* SDRAM frequency */
1345                 {
1346                         0x00000002, /* EMC_RC */
1347                         0x00000008, /* EMC_RFC */
1348                         0x00000001, /* EMC_RAS */
1349                         0x00000000, /* EMC_RP */
1350                         0x00000002, /* EMC_R2W */
1351                         0x0000000a, /* EMC_W2R */
1352                         0x00000003, /* EMC_R2P */
1353                         0x0000000b, /* EMC_W2P */
1354                         0x00000000, /* EMC_RD_RCD */
1355                         0x00000000, /* EMC_WR_RCD */
1356                         0x00000003, /* EMC_RRD */
1357                         0x00000001, /* EMC_REXT */
1358                         0x00000000, /* EMC_WEXT */
1359                         0x00000005, /* EMC_WDV */
1360                         0x00000005, /* EMC_QUSE */
1361                         0x00000004, /* EMC_QRST */
1362                         0x00000007, /* EMC_QSAFE */
1363                         0x0000000c, /* EMC_RDV */
1364                         0x00000181, /* EMC_REFRESH */
1365                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1366                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
1367                         0x00000002, /* EMC_PDEX2WR */
1368                         0x00000002, /* EMC_PDEX2RD */
1369                         0x00000001, /* EMC_PCHG2PDEN */
1370                         0x00000000, /* EMC_ACT2PDEN */
1371                         0x00000007, /* EMC_AR2PDEN */
1372                         0x0000000f, /* EMC_RW2PDEN */
1373                         0x00000009, /* EMC_TXSR */
1374                         0x00000009, /* EMC_TXSRDLL */
1375                         0x00000004, /* EMC_TCKE */
1376                         0x00000002, /* EMC_TFAW */
1377                         0x00000000, /* EMC_TRPAB */
1378                         0x00000004, /* EMC_TCLKSTABLE */
1379                         0x00000005, /* EMC_TCLKSTOP */
1380                         0x0000018e, /* EMC_TREFBW */
1381                         0x00000000, /* EMC_QUSE_EXTRA */
1382                         0x00000004, /* EMC_FBIO_CFG6 */
1383                         0x00000000, /* EMC_ODT_WRITE */
1384                         0x00000000, /* EMC_ODT_READ */
1385                         0x00006288, /* EMC_FBIO_CFG5 */
1386                         0x007800a4, /* EMC_CFG_DIG_DLL */
1387                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1388                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
1389                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
1390                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
1391                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
1392                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
1393                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
1394                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
1395                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
1396                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1397                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1398                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1399                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1400                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1401                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1402                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1403                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1404                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1405                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1406                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1407                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1408                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1409                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1410                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1411                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1412                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1413                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1414                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1415                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1416                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1417                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
1418                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1419                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
1420                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
1421                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1422                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1423                         0x08000168, /* EMC_XM2QUSEPADCTRL */
1424                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1425                         0x00000802, /* EMC_CTT_TERM_CTRL */
1426                         0x00000000, /* EMC_ZCAL_INTERVAL */
1427                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
1428                         0x000c000c, /* EMC_MRS_WAIT_CNT */
1429                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1430                         0x00000000, /* EMC_CTT */
1431                         0x00000000, /* EMC_CTT_DURATION */
1432                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
1433                         0x00010003, /* MC_EMEM_ARB_CFG */
1434                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1435                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1436                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1437                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
1438                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
1439                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
1440                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1441                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1442                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1443                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1444                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1445                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1446                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1447                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
1448                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
1449                         0x73430303, /* MC_EMEM_ARB_MISC0 */
1450                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1451                         0xd8000000, /* EMC_FBIO_SPARE */
1452                         0xff00ff00, /* EMC_CFG_RSV */
1453                 },
1454                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1455                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1456                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1457                 0x80001221, /* Mode Register 0 */
1458                 0x80100003, /* Mode Register 1 */
1459                 0x80200008, /* Mode Register 2 */
1460                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1461         },
1462         {
1463                 0x32,       /* Rev 3.2 */
1464                 102000,     /* SDRAM frequency */
1465                 {
1466                         0x00000004, /* EMC_RC */
1467                         0x00000010, /* EMC_RFC */
1468                         0x00000003, /* EMC_RAS */
1469                         0x00000001, /* EMC_RP */
1470                         0x00000002, /* EMC_R2W */
1471                         0x0000000a, /* EMC_W2R */
1472                         0x00000003, /* EMC_R2P */
1473                         0x0000000b, /* EMC_W2P */
1474                         0x00000001, /* EMC_RD_RCD */
1475                         0x00000001, /* EMC_WR_RCD */
1476                         0x00000003, /* EMC_RRD */
1477                         0x00000001, /* EMC_REXT */
1478                         0x00000000, /* EMC_WEXT */
1479                         0x00000005, /* EMC_WDV */
1480                         0x00000005, /* EMC_QUSE */
1481                         0x00000004, /* EMC_QRST */
1482                         0x00000007, /* EMC_QSAFE */
1483                         0x0000000c, /* EMC_RDV */
1484                         0x00000303, /* EMC_REFRESH */
1485                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1486                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
1487                         0x00000002, /* EMC_PDEX2WR */
1488                         0x00000002, /* EMC_PDEX2RD */
1489                         0x00000001, /* EMC_PCHG2PDEN */
1490                         0x00000000, /* EMC_ACT2PDEN */
1491                         0x00000007, /* EMC_AR2PDEN */
1492                         0x0000000f, /* EMC_RW2PDEN */
1493                         0x00000012, /* EMC_TXSR */
1494                         0x00000012, /* EMC_TXSRDLL */
1495                         0x00000004, /* EMC_TCKE */
1496                         0x00000004, /* EMC_TFAW */
1497                         0x00000000, /* EMC_TRPAB */
1498                         0x00000004, /* EMC_TCLKSTABLE */
1499                         0x00000005, /* EMC_TCLKSTOP */
1500                         0x0000031c, /* EMC_TREFBW */
1501                         0x00000000, /* EMC_QUSE_EXTRA */
1502                         0x00000004, /* EMC_FBIO_CFG6 */
1503                         0x00000000, /* EMC_ODT_WRITE */
1504                         0x00000000, /* EMC_ODT_READ */
1505                         0x00006288, /* EMC_FBIO_CFG5 */
1506                         0x007800a4, /* EMC_CFG_DIG_DLL */
1507                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1508                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
1509                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
1510                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
1511                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
1512                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
1513                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
1514                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
1515                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
1516                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1517                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1518                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1519                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1520                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1521                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1522                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1523                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1524                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1525                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1526                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1527                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1528                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1529                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1530                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1531                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1532                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1533                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1534                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1535                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1536                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1537                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
1538                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1539                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
1540                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
1541                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1542                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1543                         0x08000168, /* EMC_XM2QUSEPADCTRL */
1544                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1545                         0x00000802, /* EMC_CTT_TERM_CTRL */
1546                         0x00000000, /* EMC_ZCAL_INTERVAL */
1547                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
1548                         0x000c000c, /* EMC_MRS_WAIT_CNT */
1549                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1550                         0x00000000, /* EMC_CTT */
1551                         0x00000000, /* EMC_CTT_DURATION */
1552                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
1553                         0x00000003, /* MC_EMEM_ARB_CFG */
1554                         0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1555                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1556                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1557                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
1558                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
1559                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
1560                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1561                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1562                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1563                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1564                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1565                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1566                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1567                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
1568                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
1569                         0x72830504, /* MC_EMEM_ARB_MISC0 */
1570                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1571                         0xd8000000, /* EMC_FBIO_SPARE */
1572                         0xff00ff00, /* EMC_CFG_RSV */
1573                 },
1574                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1575                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1576                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1577                 0x80001221, /* Mode Register 0 */
1578                 0x80100003, /* Mode Register 1 */
1579                 0x80200008, /* Mode Register 2 */
1580                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1581         },
1582         {
1583                 0x32,       /* Rev 3.2 */
1584                 204000,     /* SDRAM frequency */
1585                 {
1586                         0x00000009, /* EMC_RC */
1587                         0x00000020, /* EMC_RFC */
1588                         0x00000007, /* EMC_RAS */
1589                         0x00000002, /* EMC_RP */
1590                         0x00000002, /* EMC_R2W */
1591                         0x0000000a, /* EMC_W2R */
1592                         0x00000005, /* EMC_R2P */
1593                         0x0000000b, /* EMC_W2P */
1594                         0x00000002, /* EMC_RD_RCD */
1595                         0x00000002, /* EMC_WR_RCD */
1596                         0x00000003, /* EMC_RRD */
1597                         0x00000001, /* EMC_REXT */
1598                         0x00000000, /* EMC_WEXT */
1599                         0x00000005, /* EMC_WDV */
1600                         0x00000005, /* EMC_QUSE */
1601                         0x00000004, /* EMC_QRST */
1602                         0x00000009, /* EMC_QSAFE */
1603                         0x0000000b, /* EMC_RDV */
1604                         0x00000607, /* EMC_REFRESH */
1605                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1606                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
1607                         0x00000002, /* EMC_PDEX2WR */
1608                         0x00000002, /* EMC_PDEX2RD */
1609                         0x00000001, /* EMC_PCHG2PDEN */
1610                         0x00000000, /* EMC_ACT2PDEN */
1611                         0x00000007, /* EMC_AR2PDEN */
1612                         0x0000000f, /* EMC_RW2PDEN */
1613                         0x00000023, /* EMC_TXSR */
1614                         0x00000023, /* EMC_TXSRDLL */
1615                         0x00000004, /* EMC_TCKE */
1616                         0x00000007, /* EMC_TFAW */
1617                         0x00000000, /* EMC_TRPAB */
1618                         0x00000004, /* EMC_TCLKSTABLE */
1619                         0x00000005, /* EMC_TCLKSTOP */
1620                         0x00000638, /* EMC_TREFBW */
1621                         0x00000006, /* EMC_QUSE_EXTRA */
1622                         0x00000004, /* EMC_FBIO_CFG6 */
1623                         0x00000000, /* EMC_ODT_WRITE */
1624                         0x00000000, /* EMC_ODT_READ */
1625                         0x00004288, /* EMC_FBIO_CFG5 */
1626                         0x004400a4, /* EMC_CFG_DIG_DLL */
1627                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1628                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
1629                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
1630                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
1631                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
1632                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
1633                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
1634                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
1635                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
1636                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1637                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1638                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1639                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1640                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1641                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1642                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1643                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1644                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1645                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1646                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1647                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1648                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1649                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1650                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1651                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1652                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1653                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1654                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1655                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1656                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1657                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
1658                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1659                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1660                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
1661                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1662                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1663                         0x08000168, /* EMC_XM2QUSEPADCTRL */
1664                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1665                         0x00000802, /* EMC_CTT_TERM_CTRL */
1666                         0x00020000, /* EMC_ZCAL_INTERVAL */
1667                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1668                         0x000c000c, /* EMC_MRS_WAIT_CNT */
1669                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1670                         0x00000000, /* EMC_CTT */
1671                         0x00000000, /* EMC_CTT_DURATION */
1672                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
1673                         0x00000006, /* MC_EMEM_ARB_CFG */
1674                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1675                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1676                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1677                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
1678                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
1679                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
1680                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1681                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1682                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1683                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1684                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1685                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1686                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1687                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
1688                         0x000a0505, /* MC_EMEM_ARB_DA_COVERS */
1689                         0x72440a06, /* MC_EMEM_ARB_MISC0 */
1690                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1691                         0xe8000000, /* EMC_FBIO_SPARE */
1692                         0xff00ff00, /* EMC_CFG_RSV */
1693                 },
1694                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1695                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1696                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1697                 0x80001221, /* Mode Register 0 */
1698                 0x80100003, /* Mode Register 1 */
1699                 0x80200008, /* Mode Register 2 */
1700                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1701         },
1702         {
1703                 0x32,       /* Rev 3.2 */
1704                 375000,     /* SDRAM frequency */
1705                 {
1706                         0x00000011, /* EMC_RC */
1707                         0x0000003a, /* EMC_RFC */
1708                         0x0000000c, /* EMC_RAS */
1709                         0x00000004, /* EMC_RP */
1710                         0x00000003, /* EMC_R2W */
1711                         0x00000008, /* EMC_W2R */
1712                         0x00000002, /* EMC_R2P */
1713                         0x0000000a, /* EMC_W2P */
1714                         0x00000004, /* EMC_RD_RCD */
1715                         0x00000004, /* EMC_WR_RCD */
1716                         0x00000002, /* EMC_RRD */
1717                         0x00000001, /* EMC_REXT */
1718                         0x00000000, /* EMC_WEXT */
1719                         0x00000004, /* EMC_WDV */
1720                         0x00000006, /* EMC_QUSE */
1721                         0x00000004, /* EMC_QRST */
1722                         0x00000008, /* EMC_QSAFE */
1723                         0x0000000d, /* EMC_RDV */
1724                         0x00000b2d, /* EMC_REFRESH */
1725                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1726                         0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
1727                         0x00000008, /* EMC_PDEX2WR */
1728                         0x00000008, /* EMC_PDEX2RD */
1729                         0x00000001, /* EMC_PCHG2PDEN */
1730                         0x00000000, /* EMC_ACT2PDEN */
1731                         0x00000007, /* EMC_AR2PDEN */
1732                         0x0000000f, /* EMC_RW2PDEN */
1733                         0x00000040, /* EMC_TXSR */
1734                         0x00000200, /* EMC_TXSRDLL */
1735                         0x00000009, /* EMC_TCKE */
1736                         0x0000000c, /* EMC_TFAW */
1737                         0x00000000, /* EMC_TRPAB */
1738                         0x00000004, /* EMC_TCLKSTABLE */
1739                         0x00000005, /* EMC_TCLKSTOP */
1740                         0x00000b6d, /* EMC_TREFBW */
1741                         0x00000000, /* EMC_QUSE_EXTRA */
1742                         0x00000006, /* EMC_FBIO_CFG6 */
1743                         0x00000000, /* EMC_ODT_WRITE */
1744                         0x00000000, /* EMC_ODT_READ */
1745                         0x00007088, /* EMC_FBIO_CFG5 */
1746                         0x00200084, /* EMC_CFG_DIG_DLL */
1747                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1748                         0x0003c000, /* EMC_DLL_XFORM_DQS0 */
1749                         0x0003c000, /* EMC_DLL_XFORM_DQS1 */
1750                         0x0003c000, /* EMC_DLL_XFORM_DQS2 */
1751                         0x0003c000, /* EMC_DLL_XFORM_DQS3 */
1752                         0x0003c000, /* EMC_DLL_XFORM_DQS4 */
1753                         0x0003c000, /* EMC_DLL_XFORM_DQS5 */
1754                         0x0003c000, /* EMC_DLL_XFORM_DQS6 */
1755                         0x0003c000, /* EMC_DLL_XFORM_DQS7 */
1756                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1757                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1758                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1759                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1760                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1761                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1762                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1763                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1764                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1765                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1766                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1767                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1768                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1769                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1770                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1771                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1772                         0x00040000, /* EMC_DLL_XFORM_DQ0 */
1773                         0x00040000, /* EMC_DLL_XFORM_DQ1 */
1774                         0x00040000, /* EMC_DLL_XFORM_DQ2 */
1775                         0x00040000, /* EMC_DLL_XFORM_DQ3 */
1776                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1777                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1778                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1779                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1780                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1781                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1782                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1783                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1784                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1785                         0x00000802, /* EMC_CTT_TERM_CTRL */
1786                         0x00020000, /* EMC_ZCAL_INTERVAL */
1787                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1788                         0x0184000c, /* EMC_MRS_WAIT_CNT */
1789                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1790                         0x00000000, /* EMC_CTT */
1791                         0x00000000, /* EMC_CTT_DURATION */
1792                         0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
1793                         0x0000000b, /* MC_EMEM_ARB_CFG */
1794                         0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1795                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1796                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1797                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
1798                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
1799                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
1800                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1801                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1802                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1803                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1804                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1805                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1806                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1807                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1808                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
1809                         0x75c6110a, /* MC_EMEM_ARB_MISC0 */
1810                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1811                         0x58000000, /* EMC_FBIO_SPARE */
1812                         0xff00ff88, /* EMC_CFG_RSV */
1813                 },
1814                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1815                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1816                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1817                 0x80000521, /* Mode Register 0 */
1818                 0x80100002, /* Mode Register 1 */
1819                 0x80200000, /* Mode Register 2 */
1820                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1821         },
1822         {
1823                 0x32,       /* Rev 3.2 */
1824                 400000,     /* SDRAM frequency */
1825                 {
1826                         0x00000012, /* EMC_RC */
1827                         0x00000040, /* EMC_RFC */
1828                         0x0000000d, /* EMC_RAS */
1829                         0x00000004, /* EMC_RP */
1830                         0x00000002, /* EMC_R2W */
1831                         0x00000009, /* EMC_W2R */
1832                         0x00000002, /* EMC_R2P */
1833                         0x0000000c, /* EMC_W2P */
1834                         0x00000004, /* EMC_RD_RCD */
1835                         0x00000004, /* EMC_WR_RCD */
1836                         0x00000002, /* EMC_RRD */
1837                         0x00000001, /* EMC_REXT */
1838                         0x00000000, /* EMC_WEXT */
1839                         0x00000005, /* EMC_WDV */
1840                         0x00000007, /* EMC_QUSE */
1841                         0x00000005, /* EMC_QRST */
1842                         0x00000008, /* EMC_QSAFE */
1843                         0x0000000e, /* EMC_RDV */
1844                         0x00000c2e, /* EMC_REFRESH */
1845                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1846                         0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
1847                         0x00000008, /* EMC_PDEX2WR */
1848                         0x00000008, /* EMC_PDEX2RD */
1849                         0x00000001, /* EMC_PCHG2PDEN */
1850                         0x00000000, /* EMC_ACT2PDEN */
1851                         0x00000008, /* EMC_AR2PDEN */
1852                         0x00000011, /* EMC_RW2PDEN */
1853                         0x00000046, /* EMC_TXSR */
1854                         0x00000200, /* EMC_TXSRDLL */
1855                         0x0000000a, /* EMC_TCKE */
1856                         0x0000000d, /* EMC_TFAW */
1857                         0x00000000, /* EMC_TRPAB */
1858                         0x00000004, /* EMC_TCLKSTABLE */
1859                         0x00000005, /* EMC_TCLKSTOP */
1860                         0x00000c6f, /* EMC_TREFBW */
1861                         0x00000000, /* EMC_QUSE_EXTRA */
1862                         0x00000006, /* EMC_FBIO_CFG6 */
1863                         0x00000000, /* EMC_ODT_WRITE */
1864                         0x00000000, /* EMC_ODT_READ */
1865                         0x00007088, /* EMC_FBIO_CFG5 */
1866                         0x001c0084, /* EMC_CFG_DIG_DLL */
1867                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1868                         0x00034000, /* EMC_DLL_XFORM_DQS0 */
1869                         0x00034000, /* EMC_DLL_XFORM_DQS1 */
1870                         0x00034000, /* EMC_DLL_XFORM_DQS2 */
1871                         0x00034000, /* EMC_DLL_XFORM_DQS3 */
1872                         0x00034000, /* EMC_DLL_XFORM_DQS4 */
1873                         0x00034000, /* EMC_DLL_XFORM_DQS5 */
1874                         0x00034000, /* EMC_DLL_XFORM_DQS6 */
1875                         0x00034000, /* EMC_DLL_XFORM_DQS7 */
1876                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1877                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1878                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1879                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1880                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1881                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1882                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1883                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1884                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1885                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1886                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1887                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1888                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1889                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1890                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1891                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1892                         0x00040000, /* EMC_DLL_XFORM_DQ0 */
1893                         0x00040000, /* EMC_DLL_XFORM_DQ1 */
1894                         0x00040000, /* EMC_DLL_XFORM_DQ2 */
1895                         0x00040000, /* EMC_DLL_XFORM_DQ3 */
1896                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1897                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1898                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1899                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1900                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1901                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1902                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1903                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1904                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1905                         0x00000802, /* EMC_CTT_TERM_CTRL */
1906                         0x00020000, /* EMC_ZCAL_INTERVAL */
1907                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1908                         0x017f000c, /* EMC_MRS_WAIT_CNT */
1909                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1910                         0x00000000, /* EMC_CTT */
1911                         0x00000000, /* EMC_CTT_DURATION */
1912                         0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
1913                         0x0000000c, /* MC_EMEM_ARB_CFG */
1914                         0xc000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1915                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1916                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1917                         0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
1918                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1919                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1920                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1921                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1922                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1923                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1924                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1925                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1926                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1927                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1928                         0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
1929                         0x7547130b, /* MC_EMEM_ARB_MISC0 */
1930                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1931                         0x58000000, /* EMC_FBIO_SPARE */
1932                         0xff00ff88, /* EMC_CFG_RSV */
1933                 },
1934                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1935                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1936                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1937                 0x80000731, /* Mode Register 0 */
1938                 0x80100002, /* Mode Register 1 */
1939                 0x80200008, /* Mode Register 2 */
1940                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1941         },
1942         {
1943                 0x32,       /* Rev 3.2 */
1944                 450000,     /* SDRAM frequency */
1945                 {
1946                         0x00000014, /* EMC_RC */
1947                         0x00000046, /* EMC_RFC */
1948                         0x0000000e, /* EMC_RAS */
1949                         0x00000005, /* EMC_RP */
1950                         0x00000003, /* EMC_R2W */
1951                         0x00000009, /* EMC_W2R */
1952                         0x00000002, /* EMC_R2P */
1953                         0x0000000c, /* EMC_W2P */
1954                         0x00000005, /* EMC_RD_RCD */
1955                         0x00000005, /* EMC_WR_RCD */
1956                         0x00000002, /* EMC_RRD */
1957                         0x00000001, /* EMC_REXT */
1958                         0x00000000, /* EMC_WEXT */
1959                         0x00000005, /* EMC_WDV */
1960                         0x00000007, /* EMC_QUSE */
1961                         0x00000005, /* EMC_QRST */
1962                         0x0000000a, /* EMC_QSAFE */
1963                         0x0000000e, /* EMC_RDV */
1964                         0x00000d76, /* EMC_REFRESH */
1965                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1966                         0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */
1967                         0x00000001, /* EMC_PDEX2WR */
1968                         0x00000009, /* EMC_PDEX2RD */
1969                         0x00000001, /* EMC_PCHG2PDEN */
1970                         0x00000000, /* EMC_ACT2PDEN */
1971                         0x00000009, /* EMC_AR2PDEN */
1972                         0x00000011, /* EMC_RW2PDEN */
1973                         0x0000004d, /* EMC_TXSR */
1974                         0x00000200, /* EMC_TXSRDLL */
1975                         0x00000004, /* EMC_TCKE */
1976                         0x0000000e, /* EMC_TFAW */
1977                         0x00000000, /* EMC_TRPAB */
1978                         0x00000004, /* EMC_TCLKSTABLE */
1979                         0x00000005, /* EMC_TCLKSTOP */
1980                         0x00000db6, /* EMC_TREFBW */
1981                         0x00000000, /* EMC_QUSE_EXTRA */
1982                         0x00000006, /* EMC_FBIO_CFG6 */
1983                         0x00000000, /* EMC_ODT_WRITE */
1984                         0x00000000, /* EMC_ODT_READ */
1985                         0x00007088, /* EMC_FBIO_CFG5 */
1986                         0x00180084, /* EMC_CFG_DIG_DLL */
1987                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1988                         0x00022000, /* EMC_DLL_XFORM_DQS0 */
1989                         0x00022000, /* EMC_DLL_XFORM_DQS1 */
1990                         0x00022000, /* EMC_DLL_XFORM_DQS2 */
1991                         0x00022000, /* EMC_DLL_XFORM_DQS3 */
1992                         0x00022000, /* EMC_DLL_XFORM_DQS4 */
1993                         0x00022000, /* EMC_DLL_XFORM_DQS5 */
1994                         0x00022000, /* EMC_DLL_XFORM_DQS6 */
1995                         0x00022000, /* EMC_DLL_XFORM_DQS7 */
1996                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1997                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1998                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1999                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2000                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2001                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2002                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2003                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2004                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2005                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2006                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2007                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2008                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2009                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2010                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2011                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2012                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
2013                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
2014                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
2015                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
2016                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2017                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
2018                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2019                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2020                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
2021                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2022                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2023                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2024                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
2025                         0x00000802, /* EMC_CTT_TERM_CTRL */
2026                         0x00020000, /* EMC_ZCAL_INTERVAL */
2027                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2028                         0x0178000c, /* EMC_MRS_WAIT_CNT */
2029                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2030                         0x00000000, /* EMC_CTT */
2031                         0x00000000, /* EMC_CTT_DURATION */
2032                         0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
2033                         0x0000000d, /* MC_EMEM_ARB_CFG */
2034                         0xc0000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2035                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
2036                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
2037                         0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
2038                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
2039                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
2040                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2041                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2042                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2043                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2044                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2045                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2046                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2047                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
2048                         0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
2049                         0x70a7150c, /* MC_EMEM_ARB_MISC0 */
2050                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2051                         0xe8000000, /* EMC_FBIO_SPARE */
2052                         0xff00ff8b, /* EMC_CFG_RSV */
2053                 },
2054                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2055                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2056                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
2057                 0x80000731, /* Mode Register 0 */
2058                 0x80100002, /* Mode Register 1 */
2059                 0x80200008, /* Mode Register 2 */
2060                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2061         },
2062         {
2063                 0x32,       /* Rev 3.2 */
2064                 533000,     /* SDRAM frequency */
2065                 {
2066                         0x00000018, /* EMC_RC */
2067                         0x00000054, /* EMC_RFC */
2068                         0x00000011, /* EMC_RAS */
2069                         0x00000006, /* EMC_RP */
2070                         0x00000003, /* EMC_R2W */
2071                         0x00000009, /* EMC_W2R */
2072                         0x00000002, /* EMC_R2P */
2073                         0x0000000d, /* EMC_W2P */
2074                         0x00000006, /* EMC_RD_RCD */
2075                         0x00000006, /* EMC_WR_RCD */
2076                         0x00000002, /* EMC_RRD */
2077                         0x00000001, /* EMC_REXT */
2078                         0x00000000, /* EMC_WEXT */
2079                         0x00000005, /* EMC_WDV */
2080                         0x00000008, /* EMC_QUSE */
2081                         0x00000006, /* EMC_QRST */
2082                         0x00000008, /* EMC_QSAFE */
2083                         0x00000010, /* EMC_RDV */
2084                         0x00000ffd, /* EMC_REFRESH */
2085                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2086                         0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */
2087                         0x0000000b, /* EMC_PDEX2WR */
2088                         0x0000000b, /* EMC_PDEX2RD */
2089                         0x00000001, /* EMC_PCHG2PDEN */
2090                         0x00000000, /* EMC_ACT2PDEN */
2091                         0x0000000a, /* EMC_AR2PDEN */
2092                         0x00000012, /* EMC_RW2PDEN */
2093                         0x0000005b, /* EMC_TXSR */
2094                         0x00000200, /* EMC_TXSRDLL */
2095                         0x0000000d, /* EMC_TCKE */
2096                         0x00000010, /* EMC_TFAW */
2097                         0x00000000, /* EMC_TRPAB */
2098                         0x00000005, /* EMC_TCLKSTABLE */
2099                         0x00000006, /* EMC_TCLKSTOP */
2100                         0x0000103e, /* EMC_TREFBW */
2101                         0x00000000, /* EMC_QUSE_EXTRA */
2102                         0x00000006, /* EMC_FBIO_CFG6 */
2103                         0x00000000, /* EMC_ODT_WRITE */
2104                         0x00000000, /* EMC_ODT_READ */
2105                         0x00007088, /* EMC_FBIO_CFG5 */
2106                         0x00120084, /* EMC_CFG_DIG_DLL */
2107                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2108                         0x00010000, /* EMC_DLL_XFORM_DQS0 */
2109                         0x00010000, /* EMC_DLL_XFORM_DQS1 */
2110                         0x00010000, /* EMC_DLL_XFORM_DQS2 */
2111                         0x00010000, /* EMC_DLL_XFORM_DQS3 */
2112                         0x00010000, /* EMC_DLL_XFORM_DQS4 */
2113                         0x00010000, /* EMC_DLL_XFORM_DQS5 */
2114                         0x00010000, /* EMC_DLL_XFORM_DQS6 */
2115                         0x00010000, /* EMC_DLL_XFORM_DQS7 */
2116                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2117                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2118                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2119                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2120                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2121                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2122                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2123                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2124                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2125                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2126                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2127                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2128                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2129                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2130                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2131                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2132                         0x00020000, /* EMC_DLL_XFORM_DQ0 */
2133                         0x00020000, /* EMC_DLL_XFORM_DQ1 */
2134                         0x00020000, /* EMC_DLL_XFORM_DQ2 */
2135                         0x00020000, /* EMC_DLL_XFORM_DQ3 */
2136                         0x000006a0, /* EMC_XM2CMDPADCTRL */
2137                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
2138                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2139                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
2140                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
2141                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2142                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2143                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2144                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
2145                         0x00000802, /* EMC_CTT_TERM_CTRL */
2146                         0x00000000, /* EMC_ZCAL_INTERVAL */
2147                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2148                         0x01ab000c, /* EMC_MRS_WAIT_CNT */
2149                         0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
2150                         0x00000000, /* EMC_CTT */
2151                         0x00000000, /* EMC_CTT_DURATION */
2152                         0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */
2153                         0x0000000f, /* MC_EMEM_ARB_CFG */
2154                         0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2155                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
2156                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
2157                         0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
2158                         0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
2159                         0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
2160                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2161                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2162                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2163                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2164                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2165                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2166                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2167                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
2168                         0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
2169                         0x7028180e, /* MC_EMEM_ARB_MISC0 */
2170                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2171                         0x00000000, /* EMC_FBIO_SPARE */
2172                         0xff00ff00, /* EMC_CFG_RSV */
2173                 },
2174                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2175                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2176                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
2177                 0x80000941, /* Mode Register 0 */
2178                 0x80100002, /* Mode Register 1 */
2179                 0x80200008, /* Mode Register 2 */
2180                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2181         },
2182         {
2183                 0x32,       /* Rev 3.2 */
2184                 667000,     /* SDRAM frequency */
2185                 {
2186                         0x0000001f, /* EMC_RC */
2187                         0x00000069, /* EMC_RFC */
2188                         0x00000016, /* EMC_RAS */
2189                         0x00000008, /* EMC_RP */
2190                         0x00000004, /* EMC_R2W */
2191                         0x0000000c, /* EMC_W2R */
2192                         0x00000003, /* EMC_R2P */
2193                         0x00000011, /* EMC_W2P */
2194                         0x00000008, /* EMC_RD_RCD */
2195                         0x00000008, /* EMC_WR_RCD */
2196                         0x00000002, /* EMC_RRD */
2197                         0x00000001, /* EMC_REXT */
2198                         0x00000000, /* EMC_WEXT */
2199                         0x00000007, /* EMC_WDV */
2200                         0x0000000b, /* EMC_QUSE */
2201                         0x00000009, /* EMC_QRST */
2202                         0x0000000c, /* EMC_QSAFE */
2203                         0x00000011, /* EMC_RDV */
2204                         0x00001412, /* EMC_REFRESH */
2205                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2206                         0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */
2207                         0x0000000e, /* EMC_PDEX2WR */
2208                         0x0000000e, /* EMC_PDEX2RD */
2209                         0x00000001, /* EMC_PCHG2PDEN */
2210                         0x00000000, /* EMC_ACT2PDEN */
2211                         0x0000000c, /* EMC_AR2PDEN */
2212                         0x00000016, /* EMC_RW2PDEN */
2213                         0x00000072, /* EMC_TXSR */
2214                         0x00000200, /* EMC_TXSRDLL */
2215                         0x00000010, /* EMC_TCKE */
2216                         0x00000015, /* EMC_TFAW */
2217                         0x00000000, /* EMC_TRPAB */
2218                         0x00000006, /* EMC_TCLKSTABLE */
2219                         0x00000007, /* EMC_TCLKSTOP */
2220                         0x00001453, /* EMC_TREFBW */
2221                         0x0000000c, /* EMC_QUSE_EXTRA */
2222                         0x00000004, /* EMC_FBIO_CFG6 */
2223                         0x00000000, /* EMC_ODT_WRITE */
2224                         0x00000000, /* EMC_ODT_READ */
2225                         0x00005088, /* EMC_FBIO_CFG5 */
2226                         0x40070191, /* EMC_CFG_DIG_DLL */
2227                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2228                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
2229                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
2230                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
2231                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
2232                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
2233                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
2234                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
2235                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
2236                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2237                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2238                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2239                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2240                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2241                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2242                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2243                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2244                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2245                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2246                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2247                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2248                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2249                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2250                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2251                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2252                         0x00000008, /* EMC_DLL_XFORM_DQ0 */
2253                         0x00000008, /* EMC_DLL_XFORM_DQ1 */
2254                         0x00000008, /* EMC_DLL_XFORM_DQ2 */
2255                         0x00000008, /* EMC_DLL_XFORM_DQ3 */
2256                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2257                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2258                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2259                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2260                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
2261                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
2262                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2263                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2264                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
2265                         0x00000802, /* EMC_CTT_TERM_CTRL */
2266                         0x00020000, /* EMC_ZCAL_INTERVAL */
2267                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2268                         0x01d6000c, /* EMC_MRS_WAIT_CNT */
2269                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2270                         0x00000000, /* EMC_CTT */
2271                         0x00000000, /* EMC_CTT_DURATION */
2272                         0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
2273                         0x00000014, /* MC_EMEM_ARB_CFG */
2274                         0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2275                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
2276                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
2277                         0x00000010, /* MC_EMEM_ARB_TIMING_RC */
2278                         0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
2279                         0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
2280                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2281                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2282                         0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2283                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2284                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2285                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2286                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
2287                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
2288                         0x00140c10, /* MC_EMEM_ARB_DA_COVERS */
2289                         0x734a1f11, /* MC_EMEM_ARB_MISC0 */
2290                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2291                         0xf8000000, /* EMC_FBIO_SPARE */
2292                         0xff00ff01, /* EMC_CFG_RSV */
2293                 },
2294                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2295                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2296                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2297                 0x80000b71, /* Mode Register 0 */
2298                 0x80100002, /* Mode Register 1 */
2299                 0x80200018, /* Mode Register 2 */
2300                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2301         },
2302         {
2303                 0x32,       /* Rev 3.2 */
2304                 750000,     /* SDRAM frequency */
2305                 {
2306                         0x00000025, /* EMC_RC */
2307                         0x0000007e, /* EMC_RFC */
2308                         0x0000001a, /* EMC_RAS */
2309                         0x00000009, /* EMC_RP */
2310                         0x00000004, /* EMC_R2W */
2311                         0x0000000d, /* EMC_W2R */
2312                         0x00000004, /* EMC_R2P */
2313                         0x00000013, /* EMC_W2P */
2314                         0x00000009, /* EMC_RD_RCD */
2315                         0x00000009, /* EMC_WR_RCD */
2316                         0x00000003, /* EMC_RRD */
2317                         0x00000001, /* EMC_REXT */
2318                         0x00000000, /* EMC_WEXT */
2319                         0x00000007, /* EMC_WDV */
2320                         0x0000000b, /* EMC_QUSE */
2321                         0x00000009, /* EMC_QRST */
2322                         0x0000000c, /* EMC_QSAFE */
2323                         0x00000011, /* EMC_RDV */
2324                         0x0000169a, /* EMC_REFRESH */
2325                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2326                         0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
2327                         0x00000012, /* EMC_PDEX2WR */
2328                         0x00000012, /* EMC_PDEX2RD */
2329                         0x00000001, /* EMC_PCHG2PDEN */
2330                         0x00000000, /* EMC_ACT2PDEN */
2331                         0x0000000f, /* EMC_AR2PDEN */
2332                         0x00000018, /* EMC_RW2PDEN */
2333                         0x00000088, /* EMC_TXSR */
2334                         0x00000200, /* EMC_TXSRDLL */
2335                         0x00000014, /* EMC_TCKE */
2336                         0x00000018, /* EMC_TFAW */
2337                         0x00000000, /* EMC_TRPAB */
2338                         0x00000007, /* EMC_TCLKSTABLE */
2339                         0x00000008, /* EMC_TCLKSTOP */
2340                         0x00001860, /* EMC_TREFBW */
2341                         0x0000000c, /* EMC_QUSE_EXTRA */
2342                         0x00000004, /* EMC_FBIO_CFG6 */
2343                         0x00000000, /* EMC_ODT_WRITE */
2344                         0x00000000, /* EMC_ODT_READ */
2345                         0x00005088, /* EMC_FBIO_CFG5 */
2346                         0xf0080191, /* EMC_CFG_DIG_DLL */
2347                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2348                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
2349                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
2350                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
2351                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
2352                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
2353                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
2354                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
2355                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
2356                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2357                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2358                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2359                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2360                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2361                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2362                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2363                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2364                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2365                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2366                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2367                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2368                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2369                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2370                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2371                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2372                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
2373                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
2374                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
2375                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
2376                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2377                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2378                         0x22220000, /* EMC_XM2DQPADCTRL2 */
2379                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2380                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
2381                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
2382                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2383                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2384                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
2385                         0x00000802, /* EMC_CTT_TERM_CTRL */
2386                         0x00020000, /* EMC_ZCAL_INTERVAL */
2387                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2388                         0x0180000c, /* EMC_MRS_WAIT_CNT */
2389                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2390                         0x00000000, /* EMC_CTT */
2391                         0x00000000, /* EMC_CTT_DURATION */
2392                         0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
2393                         0x00000016, /* MC_EMEM_ARB_CFG */
2394                         0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2395                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
2396                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
2397                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
2398                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
2399                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
2400                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2401                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2402                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2403                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2404                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2405                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2406                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
2407                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
2408                         0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
2409                         0x72ac2414, /* MC_EMEM_ARB_MISC0 */
2410                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2411                         0xf8000000, /* EMC_FBIO_SPARE */
2412                         0xff00ff49, /* EMC_CFG_RSV */
2413                 },
2414                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2415                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2416                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2417                 0x80000d71, /* Mode Register 0 */
2418                 0x80100002, /* Mode Register 1 */
2419                 0x80200018, /* Mode Register 2 */
2420                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2421         },
2422         {
2423                 0x32,       /* Rev 3.2 */
2424                 800000,     /* SDRAM frequency */
2425                 {
2426                         0x00000025, /* EMC_RC */
2427                         0x0000007e, /* EMC_RFC */
2428                         0x0000001a, /* EMC_RAS */
2429                         0x00000009, /* EMC_RP */
2430                         0x00000004, /* EMC_R2W */
2431                         0x0000000d, /* EMC_W2R */
2432                         0x00000004, /* EMC_R2P */
2433                         0x00000013, /* EMC_W2P */
2434                         0x00000009, /* EMC_RD_RCD */
2435                         0x00000009, /* EMC_WR_RCD */
2436                         0x00000003, /* EMC_RRD */
2437                         0x00000001, /* EMC_REXT */
2438                         0x00000000, /* EMC_WEXT */
2439                         0x00000007, /* EMC_WDV */
2440                         0x0000000b, /* EMC_QUSE */
2441                         0x00000009, /* EMC_QRST */
2442                         0x0000000c, /* EMC_QSAFE */
2443                         0x00000011, /* EMC_RDV */
2444                         0x00001820, /* EMC_REFRESH */
2445                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2446                         0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
2447                         0x00000012, /* EMC_PDEX2WR */
2448                         0x00000012, /* EMC_PDEX2RD */
2449                         0x00000001, /* EMC_PCHG2PDEN */
2450                         0x00000000, /* EMC_ACT2PDEN */
2451                         0x0000000f, /* EMC_AR2PDEN */
2452                         0x00000018, /* EMC_RW2PDEN */
2453                         0x00000088, /* EMC_TXSR */
2454                         0x00000200, /* EMC_TXSRDLL */
2455                         0x00000014, /* EMC_TCKE */
2456                         0x00000018, /* EMC_TFAW */
2457                         0x00000000, /* EMC_TRPAB */
2458                         0x00000007, /* EMC_TCLKSTABLE */
2459                         0x00000008, /* EMC_TCLKSTOP */
2460                         0x00001860, /* EMC_TREFBW */
2461                         0x0000000c, /* EMC_QUSE_EXTRA */
2462                         0x00000004, /* EMC_FBIO_CFG6 */
2463                         0x00000000, /* EMC_ODT_WRITE */
2464                         0x00000000, /* EMC_ODT_READ */
2465                         0x00005088, /* EMC_FBIO_CFG5 */
2466                         0xf0070191, /* EMC_CFG_DIG_DLL */
2467                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2468                         0x0000800a, /* EMC_DLL_XFORM_DQS0 */
2469                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2470                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
2471                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2472                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
2473                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
2474                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
2475                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
2476                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2477                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2478                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2479                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2480                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2481                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2482                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2483                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2484                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2485                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2486                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2487                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2488                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2489                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2490                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2491                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2492                         0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
2493                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2494                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
2495                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
2496                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2497                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2498                         0x22220000, /* EMC_XM2DQPADCTRL2 */
2499                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2500                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
2501                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
2502                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2503                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2504                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
2505                         0x00000802, /* EMC_CTT_TERM_CTRL */
2506                         0x00020000, /* EMC_ZCAL_INTERVAL */
2507                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2508                         0x0180000c, /* EMC_MRS_WAIT_CNT */
2509                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2510                         0x00000000, /* EMC_CTT */
2511                         0x00000000, /* EMC_CTT_DURATION */
2512                         0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
2513                         0x00000018, /* MC_EMEM_ARB_CFG */
2514                         0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2515                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
2516                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
2517                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
2518                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
2519                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
2520                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2521                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2522                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2523                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2524                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2525                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2526                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
2527                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
2528                         0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
2529                         0x72ac2414, /* MC_EMEM_ARB_MISC0 */
2530                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2531                         0xf8000000, /* EMC_FBIO_SPARE */
2532                         0xff00ff49, /* EMC_CFG_RSV */
2533                 },
2534                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2535                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2536                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2537                 0x80000d71, /* Mode Register 0 */
2538                 0x80100002, /* Mode Register 1 */
2539                 0x80200018, /* Mode Register 2 */
2540                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2541         },
2542         {
2543                 0x32,       /* Rev 3.2 */
2544                 900000,     /* SDRAM frequency */
2545                 {
2546                         0x0000002a, /* EMC_RC */
2547                         0x0000008e, /* EMC_RFC */
2548                         0x0000001e, /* EMC_RAS */
2549                         0x0000000b, /* EMC_RP */
2550                         0x00000006, /* EMC_R2W */
2551                         0x0000000f, /* EMC_W2R */
2552                         0x00000005, /* EMC_R2P */
2553                         0x00000016, /* EMC_W2P */
2554                         0x0000000b, /* EMC_RD_RCD */
2555                         0x0000000b, /* EMC_WR_RCD */
2556                         0x00000004, /* EMC_RRD */
2557                         0x00000001, /* EMC_REXT */
2558                         0x00000000, /* EMC_WEXT */
2559                         0x00000008, /* EMC_WDV */
2560                         0x0000000d, /* EMC_QUSE */
2561                         0x0000000b, /* EMC_QRST */
2562                         0x0000000b, /* EMC_QSAFE */
2563                         0x00000014, /* EMC_RDV */
2564                         0x00001b2c, /* EMC_REFRESH */
2565                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2566                         0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */
2567                         0x00000004, /* EMC_PDEX2WR */
2568                         0x00000014, /* EMC_PDEX2RD */
2569                         0x00000001, /* EMC_PCHG2PDEN */
2570                         0x00000000, /* EMC_ACT2PDEN */
2571                         0x00000011, /* EMC_AR2PDEN */
2572                         0x0000001b, /* EMC_RW2PDEN */
2573                         0x00000099, /* EMC_TXSR */
2574                         0x00000200, /* EMC_TXSRDLL */
2575                         0x00000006, /* EMC_TCKE */
2576                         0x0000001b, /* EMC_TFAW */
2577                         0x00000000, /* EMC_TRPAB */
2578                         0x00000008, /* EMC_TCLKSTABLE */
2579                         0x00000009, /* EMC_TCLKSTOP */
2580                         0x00001b6c, /* EMC_TREFBW */
2581                         0x0000000e, /* EMC_QUSE_EXTRA */
2582                         0x00000004, /* EMC_FBIO_CFG6 */
2583                         0x00000000, /* EMC_ODT_WRITE */
2584                         0x00000000, /* EMC_ODT_READ */
2585                         0x00005088, /* EMC_FBIO_CFG5 */
2586                         0xf0040191, /* EMC_CFG_DIG_DLL */
2587                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2588                         0x0000800a, /* EMC_DLL_XFORM_DQS0 */
2589                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
2590                         0x007fc00a, /* EMC_DLL_XFORM_DQS2 */
2591                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
2592                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
2593                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
2594                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
2595                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
2596                         0x0001c000, /* EMC_DLL_XFORM_QUSE0 */
2597                         0x0001c000, /* EMC_DLL_XFORM_QUSE1 */
2598                         0x0001c000, /* EMC_DLL_XFORM_QUSE2 */
2599                         0x0001c000, /* EMC_DLL_XFORM_QUSE3 */
2600                         0x0001c000, /* EMC_DLL_XFORM_QUSE4 */
2601                         0x0001c000, /* EMC_DLL_XFORM_QUSE5 */
2602                         0x0001c000, /* EMC_DLL_XFORM_QUSE6 */
2603                         0x0001c000, /* EMC_DLL_XFORM_QUSE7 */
2604                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2605                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2606                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2607                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2608                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2609                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2610                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2611                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2612                         0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
2613                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2614                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
2615                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
2616                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2617                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2618                         0x22220000, /* EMC_XM2DQPADCTRL2 */
2619                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2620                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
2621                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
2622                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2623                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2624                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
2625                         0x00000802, /* EMC_CTT_TERM_CTRL */
2626                         0x00020000, /* EMC_ZCAL_INTERVAL */
2627                         0x00000120, /* EMC_ZCAL_WAIT_CNT */
2628                         0x0128000c, /* EMC_MRS_WAIT_CNT */
2629                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2630                         0x00000000, /* EMC_CTT */
2631                         0x00000000, /* EMC_CTT_DURATION */
2632                         0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */
2633                         0x0000001b, /* MC_EMEM_ARB_CFG */
2634                         0xc00000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2635                         0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
2636                         0x00000006, /* MC_EMEM_ARB_TIMING_RP */
2637                         0x00000016, /* MC_EMEM_ARB_TIMING_RC */
2638                         0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
2639                         0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
2640                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2641                         0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2642                         0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2643                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2644                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2645                         0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
2646                         0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
2647                         0x09050202, /* MC_EMEM_ARB_DA_TURNS */
2648                         0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
2649                         0x714e2917, /* MC_EMEM_ARB_MISC0 */
2650                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2651                         0xe8000000, /* EMC_FBIO_SPARE */
2652                         0xff00ff4b, /* EMC_CFG_RSV */
2653                 },
2654                 0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */
2655                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2656                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2657                 0x80000f15, /* Mode Register 0 */
2658                 0x80100002, /* Mode Register 1 */
2659                 0x80200020, /* Mode Register 2 */
2660                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2661         },
2662 };
2663
2664 static const struct tegra30_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
2665         {
2666                 0x32,       /* Rev 3.2 */
2667                 51000,      /* SDRAM frequency */
2668                 {
2669                         0x00000002, /* EMC_RC */
2670                         0x0000000d, /* EMC_RFC */
2671                         0x00000001, /* EMC_RAS */
2672                         0x00000000, /* EMC_RP */
2673                         0x00000002, /* EMC_R2W */
2674                         0x0000000a, /* EMC_W2R */
2675                         0x00000003, /* EMC_R2P */
2676                         0x0000000b, /* EMC_W2P */
2677                         0x00000000, /* EMC_RD_RCD */
2678                         0x00000000, /* EMC_WR_RCD */
2679                         0x00000003, /* EMC_RRD */
2680                         0x00000001, /* EMC_REXT */
2681                         0x00000000, /* EMC_WEXT */
2682                         0x00000005, /* EMC_WDV */
2683                         0x00000005, /* EMC_QUSE */
2684                         0x00000004, /* EMC_QRST */
2685                         0x00000009, /* EMC_QSAFE */
2686                         0x0000000b, /* EMC_RDV */
2687                         0x00000181, /* EMC_REFRESH */
2688                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2689                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
2690                         0x00000002, /* EMC_PDEX2WR */
2691                         0x00000002, /* EMC_PDEX2RD */
2692                         0x00000001, /* EMC_PCHG2PDEN */
2693                         0x00000000, /* EMC_ACT2PDEN */
2694                         0x00000007, /* EMC_AR2PDEN */
2695                         0x0000000f, /* EMC_RW2PDEN */
2696                         0x0000000e, /* EMC_TXSR */
2697                         0x0000000e, /* EMC_TXSRDLL */
2698                         0x00000004, /* EMC_TCKE */
2699                         0x00000002, /* EMC_TFAW */
2700                         0x00000000, /* EMC_TRPAB */
2701                         0x00000004, /* EMC_TCLKSTABLE */
2702                         0x00000005, /* EMC_TCLKSTOP */
2703                         0x0000018e, /* EMC_TREFBW */
2704                         0x00000006, /* EMC_QUSE_EXTRA */
2705                         0x00000004, /* EMC_FBIO_CFG6 */
2706                         0x00000000, /* EMC_ODT_WRITE */
2707                         0x00000000, /* EMC_ODT_READ */
2708                         0x00004288, /* EMC_FBIO_CFG5 */
2709                         0x007800a4, /* EMC_CFG_DIG_DLL */
2710                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2711                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2712                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2713                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2714                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2715                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2716                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2717                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2718                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2719                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2720                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2721                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2722                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2723                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2724                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2725                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2726                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2727                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2728                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2729                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2730                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2731                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2732                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2733                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2734                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2735                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2736                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2737                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2738                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2739                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2740                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2741                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2742                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2743                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2744                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2745                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2746                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2747                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2748                         0x00000802, /* EMC_CTT_TERM_CTRL */
2749                         0x00000000, /* EMC_ZCAL_INTERVAL */
2750                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2751                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2752                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2753                         0x00000000, /* EMC_CTT */
2754                         0x00000000, /* EMC_CTT_DURATION */
2755                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
2756                         0x00010003, /* MC_EMEM_ARB_CFG */
2757                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2758                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2759                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2760                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2761                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2762                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2763                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2764                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2765                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2766                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2767                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2768                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2769                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2770                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2771                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2772                         0x74630303, /* MC_EMEM_ARB_MISC0 */
2773                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2774                         0xe8000000, /* EMC_FBIO_SPARE */
2775                         0xff00ff00, /* EMC_CFG_RSV */
2776                 },
2777                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2778                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2779                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2780                 0x80001221, /* Mode Register 0 */
2781                 0x80100003, /* Mode Register 1 */
2782                 0x80200008, /* Mode Register 2 */
2783                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2784         },
2785         {
2786                 0x32,       /* Rev 3.2 */
2787                 102000,     /* SDRAM frequency */
2788                 {
2789                         0x00000004, /* EMC_RC */
2790                         0x0000001a, /* EMC_RFC */
2791                         0x00000003, /* EMC_RAS */
2792                         0x00000001, /* EMC_RP */
2793                         0x00000002, /* EMC_R2W */
2794                         0x0000000a, /* EMC_W2R */
2795                         0x00000003, /* EMC_R2P */
2796                         0x0000000b, /* EMC_W2P */
2797                         0x00000001, /* EMC_RD_RCD */
2798                         0x00000001, /* EMC_WR_RCD */
2799                         0x00000003, /* EMC_RRD */
2800                         0x00000001, /* EMC_REXT */
2801                         0x00000000, /* EMC_WEXT */
2802                         0x00000005, /* EMC_WDV */
2803                         0x00000005, /* EMC_QUSE */
2804                         0x00000004, /* EMC_QRST */
2805                         0x00000009, /* EMC_QSAFE */
2806                         0x0000000b, /* EMC_RDV */
2807                         0x00000303, /* EMC_REFRESH */
2808                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2809                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
2810                         0x00000002, /* EMC_PDEX2WR */
2811                         0x00000002, /* EMC_PDEX2RD */
2812                         0x00000001, /* EMC_PCHG2PDEN */
2813                         0x00000000, /* EMC_ACT2PDEN */
2814                         0x00000007, /* EMC_AR2PDEN */
2815                         0x0000000f, /* EMC_RW2PDEN */
2816                         0x0000001c, /* EMC_TXSR */
2817                         0x0000001c, /* EMC_TXSRDLL */
2818                         0x00000004, /* EMC_TCKE */
2819                         0x00000004, /* EMC_TFAW */
2820                         0x00000000, /* EMC_TRPAB */
2821                         0x00000004, /* EMC_TCLKSTABLE */
2822                         0x00000005, /* EMC_TCLKSTOP */
2823                         0x0000031c, /* EMC_TREFBW */
2824                         0x00000006, /* EMC_QUSE_EXTRA */
2825                         0x00000004, /* EMC_FBIO_CFG6 */
2826                         0x00000000, /* EMC_ODT_WRITE */
2827                         0x00000000, /* EMC_ODT_READ */
2828                         0x00004288, /* EMC_FBIO_CFG5 */
2829                         0x007800a4, /* EMC_CFG_DIG_DLL */
2830                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2831                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2832                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2833                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2834                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2835                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2836                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2837                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2838                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2839                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2840                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2841                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2842                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2843                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2844                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2845                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2846                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2847                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2848                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2849                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2850                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2851                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2852                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2853                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2854                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2855                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2856                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2857                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2858                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2859                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2860                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2861                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2862                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2863                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2864                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2865                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2866                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2867                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2868                         0x00000802, /* EMC_CTT_TERM_CTRL */
2869                         0x00000000, /* EMC_ZCAL_INTERVAL */
2870                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2871                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2872                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2873                         0x00000000, /* EMC_CTT */
2874                         0x00000000, /* EMC_CTT_DURATION */
2875                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
2876                         0x00000003, /* MC_EMEM_ARB_CFG */
2877                         0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2878                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2879                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2880                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
2881                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2882                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2883                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2884                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2885                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2886                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2887                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2888                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2889                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2890                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2891                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
2892                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
2893                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2894                         0xe8000000, /* EMC_FBIO_SPARE */
2895                         0xff00ff00, /* EMC_CFG_RSV */
2896                 },
2897                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2898                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2899                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2900                 0x80001221, /* Mode Register 0 */
2901                 0x80100003, /* Mode Register 1 */
2902                 0x80200008, /* Mode Register 2 */
2903                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2904         },
2905         {
2906                 0x32,       /* Rev 3.2 */
2907                 204000,     /* SDRAM frequency */
2908                 {
2909                         0x00000009, /* EMC_RC */
2910                         0x00000035, /* EMC_RFC */
2911                         0x00000007, /* EMC_RAS */
2912                         0x00000002, /* EMC_RP */
2913                         0x00000002, /* EMC_R2W */
2914                         0x0000000a, /* EMC_W2R */
2915                         0x00000003, /* EMC_R2P */
2916                         0x0000000b, /* EMC_W2P */
2917                         0x00000002, /* EMC_RD_RCD */
2918                         0x00000002, /* EMC_WR_RCD */
2919                         0x00000003, /* EMC_RRD */
2920                         0x00000001, /* EMC_REXT */
2921                         0x00000000, /* EMC_WEXT */
2922                         0x00000005, /* EMC_WDV */
2923                         0x00000005, /* EMC_QUSE */
2924                         0x00000004, /* EMC_QRST */
2925                         0x00000009, /* EMC_QSAFE */
2926                         0x0000000b, /* EMC_RDV */
2927                         0x00000607, /* EMC_REFRESH */
2928                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2929                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
2930                         0x00000002, /* EMC_PDEX2WR */
2931                         0x00000002, /* EMC_PDEX2RD */
2932                         0x00000001, /* EMC_PCHG2PDEN */
2933                         0x00000000, /* EMC_ACT2PDEN */
2934                         0x00000007, /* EMC_AR2PDEN */
2935                         0x0000000f, /* EMC_RW2PDEN */
2936                         0x00000038, /* EMC_TXSR */
2937                         0x00000038, /* EMC_TXSRDLL */
2938                         0x00000004, /* EMC_TCKE */
2939                         0x00000007, /* EMC_TFAW */
2940                         0x00000000, /* EMC_TRPAB */
2941                         0x00000004, /* EMC_TCLKSTABLE */
2942                         0x00000005, /* EMC_TCLKSTOP */
2943                         0x00000638, /* EMC_TREFBW */
2944                         0x00000006, /* EMC_QUSE_EXTRA */
2945                         0x00000004, /* EMC_FBIO_CFG6 */
2946                         0x00000000, /* EMC_ODT_WRITE */
2947                         0x00000000, /* EMC_ODT_READ */
2948                         0x00004288, /* EMC_FBIO_CFG5 */
2949                         0x004400a4, /* EMC_CFG_DIG_DLL */
2950                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2951                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
2952                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
2953                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
2954                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
2955                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
2956                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
2957                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
2958                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
2959                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2960                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2961                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2962                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2963                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2964                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2965                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2966                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2967                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2968                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2969                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2970                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2971                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2972                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2973                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2974                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2975                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
2976                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
2977                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
2978                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
2979                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2980                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2981                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2982                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2983                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2984                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2985                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2986                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2987                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2988                         0x00000802, /* EMC_CTT_TERM_CTRL */
2989                         0x00020000, /* EMC_ZCAL_INTERVAL */
2990                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2991                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2992                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2993                         0x00000000, /* EMC_CTT */
2994                         0x00000000, /* EMC_CTT_DURATION */
2995                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
2996                         0x00000006, /* MC_EMEM_ARB_CFG */
2997                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2998                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2999                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3000                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
3001                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
3002                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3003                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3004                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3005                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3006                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3007                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3008                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3009                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3010                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3011                         0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
3012                         0x73840a06, /* MC_EMEM_ARB_MISC0 */
3013                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3014                         0xe8000000, /* EMC_FBIO_SPARE */
3015                         0xff00ff00, /* EMC_CFG_RSV */
3016                 },
3017                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3018                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3019                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3020                 0x80001221, /* Mode Register 0 */
3021                 0x80100003, /* Mode Register 1 */
3022                 0x80200008, /* Mode Register 2 */
3023                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3024         },
3025         {
3026                 0x32,       /* Rev 3.2 */
3027                 375000,     /* SDRAM frequency */
3028                 {
3029                         0x00000011, /* EMC_RC */
3030                         0x0000006f, /* EMC_RFC */
3031                         0x0000000c, /* EMC_RAS */
3032                         0x00000004, /* EMC_RP */
3033                         0x00000003, /* EMC_R2W */
3034                         0x00000008, /* EMC_W2R */
3035                         0x00000002, /* EMC_R2P */
3036                         0x0000000a, /* EMC_W2P */
3037                         0x00000004, /* EMC_RD_RCD */
3038                         0x00000004, /* EMC_WR_RCD */
3039                         0x00000002, /* EMC_RRD */
3040                         0x00000001, /* EMC_REXT */
3041                         0x00000000, /* EMC_WEXT */
3042                         0x00000004, /* EMC_WDV */
3043                         0x00000006, /* EMC_QUSE */
3044                         0x00000004, /* EMC_QRST */
3045                         0x0000000a, /* EMC_QSAFE */
3046                         0x0000000d, /* EMC_RDV */
3047                         0x00000b2d, /* EMC_REFRESH */
3048                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3049                         0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
3050                         0x00000001, /* EMC_PDEX2WR */
3051                         0x00000008, /* EMC_PDEX2RD */
3052                         0x00000001, /* EMC_PCHG2PDEN */
3053                         0x00000000, /* EMC_ACT2PDEN */
3054                         0x00000007, /* EMC_AR2PDEN */
3055                         0x0000000f, /* EMC_RW2PDEN */
3056                         0x00000075, /* EMC_TXSR */
3057                         0x00000200, /* EMC_TXSRDLL */
3058                         0x00000004, /* EMC_TCKE */
3059                         0x0000000c, /* EMC_TFAW */
3060                         0x00000000, /* EMC_TRPAB */
3061                         0x00000004, /* EMC_TCLKSTABLE */
3062                         0x00000005, /* EMC_TCLKSTOP */
3063                         0x00000b6d, /* EMC_TREFBW */
3064                         0x00000000, /* EMC_QUSE_EXTRA */
3065                         0x00000006, /* EMC_FBIO_CFG6 */
3066                         0x00000000, /* EMC_ODT_WRITE */
3067                         0x00000000, /* EMC_ODT_READ */
3068                         0x00007088, /* EMC_FBIO_CFG5 */
3069                         0x00200084, /* EMC_CFG_DIG_DLL */
3070                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3071                         0x0003c000, /* EMC_DLL_XFORM_DQS0 */
3072                         0x0003c000, /* EMC_DLL_XFORM_DQS1 */
3073                         0x0003c000, /* EMC_DLL_XFORM_DQS2 */
3074                         0x0003c000, /* EMC_DLL_XFORM_DQS3 */
3075                         0x0003c000, /* EMC_DLL_XFORM_DQS4 */
3076                         0x0003c000, /* EMC_DLL_XFORM_DQS5 */
3077                         0x0003c000, /* EMC_DLL_XFORM_DQS6 */
3078                         0x0003c000, /* EMC_DLL_XFORM_DQS7 */
3079                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3080                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3081                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3082                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3083                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3084                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3085                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3086                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3087                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3088                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3089                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3090                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3091                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3092                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3093                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3094                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3095                         0x00040000, /* EMC_DLL_XFORM_DQ0 */
3096                         0x00040000, /* EMC_DLL_XFORM_DQ1 */
3097                         0x00040000, /* EMC_DLL_XFORM_DQ2 */
3098                         0x00040000, /* EMC_DLL_XFORM_DQ3 */
3099                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3100                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
3101                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3102                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3103                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
3104                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3105                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3106                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3107                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
3108                         0x00000802, /* EMC_CTT_TERM_CTRL */
3109                         0x00020000, /* EMC_ZCAL_INTERVAL */
3110                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3111                         0x0150000c, /* EMC_MRS_WAIT_CNT */
3112                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3113                         0x00000000, /* EMC_CTT */
3114                         0x00000000, /* EMC_CTT_DURATION */
3115                         0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
3116                         0x0000000b, /* MC_EMEM_ARB_CFG */
3117                         0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3118                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3119                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3120                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
3121                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
3122                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
3123                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3124                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3125                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3126                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3127                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3128                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3129                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3130                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
3131                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
3132                         0x75c6110a, /* MC_EMEM_ARB_MISC0 */
3133                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3134                         0x58000000, /* EMC_FBIO_SPARE */
3135                         0xff00ff88, /* EMC_CFG_RSV */
3136                 },
3137                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3138                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3139                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
3140                 0x80000521, /* Mode Register 0 */
3141                 0x80100002, /* Mode Register 1 */
3142                 0x80200000, /* Mode Register 2 */
3143                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3144         },
3145         {
3146                 0x32,       /* Rev 3.2 */
3147                 400000,     /* SDRAM frequency */
3148                 {
3149                         0x00000012, /* EMC_RC */
3150                         0x00000066, /* EMC_RFC */
3151                         0x0000000c, /* EMC_RAS */
3152                         0x00000004, /* EMC_RP */
3153                         0x00000003, /* EMC_R2W */
3154                         0x00000008, /* EMC_W2R */
3155                         0x00000002, /* EMC_R2P */
3156                         0x0000000a, /* EMC_W2P */
3157                         0x00000004, /* EMC_RD_RCD */
3158                         0x00000004, /* EMC_WR_RCD */
3159                         0x00000002, /* EMC_RRD */
3160                         0x00000001, /* EMC_REXT */
3161                         0x00000000, /* EMC_WEXT */
3162                         0x00000004, /* EMC_WDV */
3163                         0x00000006, /* EMC_QUSE */
3164                         0x00000004, /* EMC_QRST */
3165                         0x0000000a, /* EMC_QSAFE */
3166                         0x0000000d, /* EMC_RDV */
3167                         0x00000bf0, /* EMC_REFRESH */
3168                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3169                         0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */
3170                         0x00000001, /* EMC_PDEX2WR */
3171                         0x00000008, /* EMC_PDEX2RD */
3172                         0x00000001, /* EMC_PCHG2PDEN */
3173                         0x00000000, /* EMC_ACT2PDEN */
3174                         0x00000008, /* EMC_AR2PDEN */
3175                         0x0000000f, /* EMC_RW2PDEN */
3176                         0x0000006c, /* EMC_TXSR */
3177                         0x00000200, /* EMC_TXSRDLL */
3178                         0x00000004, /* EMC_TCKE */
3179                         0x0000000c, /* EMC_TFAW */
3180                         0x00000000, /* EMC_TRPAB */
3181                         0x00000004, /* EMC_TCLKSTABLE */
3182                         0x00000005, /* EMC_TCLKSTOP */
3183                         0x00000c30, /* EMC_TREFBW */
3184                         0x00000000, /* EMC_QUSE_EXTRA */
3185                         0x00000006, /* EMC_FBIO_CFG6 */
3186                         0x00000000, /* EMC_ODT_WRITE */
3187                         0x00000000, /* EMC_ODT_READ */
3188                         0x00007088, /* EMC_FBIO_CFG5 */
3189                         0x001d0084, /* EMC_CFG_DIG_DLL */
3190                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3191                         0x00038000, /* EMC_DLL_XFORM_DQS0 */
3192                         0x00038000, /* EMC_DLL_XFORM_DQS1 */
3193                         0x00038000, /* EMC_DLL_XFORM_DQS2 */
3194                         0x00038000, /* EMC_DLL_XFORM_DQS3 */
3195                         0x00038000, /* EMC_DLL_XFORM_DQS4 */
3196                         0x00038000, /* EMC_DLL_XFORM_DQS5 */
3197                         0x00038000, /* EMC_DLL_XFORM_DQS6 */
3198                         0x00038000, /* EMC_DLL_XFORM_DQS7 */
3199                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3200                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3201                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3202                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3203                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3204                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3205                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3206                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3207                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3208                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3209                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3210                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3211                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3212                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3213                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3214                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3215                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
3216                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
3217                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
3218                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
3219                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3220                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
3221                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3222                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3223                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
3224                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3225                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3226                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3227                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
3228                         0x00000802, /* EMC_CTT_TERM_CTRL */
3229                         0x00020000, /* EMC_ZCAL_INTERVAL */
3230                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3231                         0x0158000c, /* EMC_MRS_WAIT_CNT */
3232                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3233                         0x00000000, /* EMC_CTT */
3234                         0x00000000, /* EMC_CTT_DURATION */
3235                         0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
3236                         0x0000000c, /* MC_EMEM_ARB_CFG */
3237                         0xc0000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3238                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3239                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3240                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
3241                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
3242                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
3243                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3244                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3245                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3246                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3247                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3248                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3249                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3250                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
3251                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
3252                         0x7086120a, /* MC_EMEM_ARB_MISC0 */
3253                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3254                         0xe8000000, /* EMC_FBIO_SPARE */
3255                         0xff00ff89, /* EMC_CFG_RSV */
3256                 },
3257                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3258                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3259                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
3260                 0x80000521, /* Mode Register 0 */
3261                 0x80100002, /* Mode Register 1 */
3262                 0x80200000, /* Mode Register 2 */
3263                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3264         },
3265         {
3266                 0x32,       /* Rev 3.2 */
3267                 667000,     /* SDRAM frequency */
3268                 {
3269                         0x00000023, /* EMC_RC */
3270                         0x000000df, /* EMC_RFC */
3271                         0x00000019, /* EMC_RAS */
3272                         0x00000009, /* EMC_RP */
3273                         0x00000005, /* EMC_R2W */
3274                         0x0000000d, /* EMC_W2R */
3275                         0x00000004, /* EMC_R2P */
3276                         0x00000013, /* EMC_W2P */
3277                         0x00000009, /* EMC_RD_RCD */
3278                         0x00000009, /* EMC_WR_RCD */
3279                         0x00000003, /* EMC_RRD */
3280                         0x00000001, /* EMC_REXT */
3281                         0x00000000, /* EMC_WEXT */
3282                         0x00000007, /* EMC_WDV */
3283                         0x0000000b, /* EMC_QUSE */
3284                         0x00000009, /* EMC_QRST */
3285                         0x0000000c, /* EMC_QSAFE */
3286                         0x00000011, /* EMC_RDV */
3287                         0x00001419, /* EMC_REFRESH */
3288                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3289                         0x000005a6, /* EMC_PRE_REFRESH_REQ_CNT */
3290                         0x00000003, /* EMC_PDEX2WR */
3291                         0x00000010, /* EMC_PDEX2RD */
3292                         0x00000001, /* EMC_PCHG2PDEN */
3293                         0x00000000, /* EMC_ACT2PDEN */
3294                         0x0000000e, /* EMC_AR2PDEN */
3295                         0x00000018, /* EMC_RW2PDEN */
3296                         0x000000e9, /* EMC_TXSR */
3297                         0x00000200, /* EMC_TXSRDLL */
3298                         0x00000005, /* EMC_TCKE */
3299                         0x00000017, /* EMC_TFAW */
3300                         0x00000000, /* EMC_TRPAB */
3301                         0x00000007, /* EMC_TCLKSTABLE */
3302                         0x00000008, /* EMC_TCLKSTOP */
3303                         0x000016da, /* EMC_TREFBW */
3304                         0x0000000c, /* EMC_QUSE_EXTRA */
3305                         0x00000004, /* EMC_FBIO_CFG6 */
3306                         0x00000000, /* EMC_ODT_WRITE */
3307                         0x00000000, /* EMC_ODT_READ */
3308                         0x00005088, /* EMC_FBIO_CFG5 */
3309                         0xf0080191, /* EMC_CFG_DIG_DLL */
3310                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3311                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
3312                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
3313                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
3314                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
3315                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
3316                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
3317                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
3318                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
3319                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3320                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3321                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3322                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3323                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3324                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3325                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3326                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3327                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3328                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3329                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3330                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3331                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3332                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3333                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3334                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3335                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
3336                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
3337                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
3338                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
3339                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3340                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
3341                         0x22220000, /* EMC_XM2DQPADCTRL2 */
3342                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3343                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
3344                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
3345                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
3346                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3347                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
3348                         0x00000802, /* EMC_CTT_TERM_CTRL */
3349                         0x00020000, /* EMC_ZCAL_INTERVAL */
3350                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3351                         0x00df000c, /* EMC_MRS_WAIT_CNT */
3352                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3353                         0x00000000, /* EMC_CTT */
3354                         0x00000000, /* EMC_CTT_DURATION */
3355                         0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
3356                         0x00000014, /* MC_EMEM_ARB_CFG */
3357                         0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3358                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3359                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3360                         0x00000012, /* MC_EMEM_ARB_TIMING_RC */
3361                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3362                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
3363                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3364                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3365                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3366                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3367                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3368                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3369                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3370                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
3371                         0x00160d12, /* MC_EMEM_ARB_DA_COVERS */
3372                         0x73cc2213, /* MC_EMEM_ARB_MISC0 */
3373                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3374                         0xf8000000, /* EMC_FBIO_SPARE */
3375                         0xff00ff49, /* EMC_CFG_RSV */
3376                 },
3377                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3378                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3379                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3380                 0x80000d71, /* Mode Register 0 */
3381                 0x80100002, /* Mode Register 1 */
3382                 0x80200018, /* Mode Register 2 */
3383                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3384         },
3385         {
3386                 0x32,       /* Rev 3.2 */
3387                 750000,     /* SDRAM frequency */
3388                 {
3389                         0x00000023, /* EMC_RC */
3390                         0x000000df, /* EMC_RFC */
3391                         0x00000019, /* EMC_RAS */
3392                         0x00000009, /* EMC_RP */
3393                         0x00000005, /* EMC_R2W */
3394                         0x0000000d, /* EMC_W2R */
3395                         0x00000004, /* EMC_R2P */
3396                         0x00000013, /* EMC_W2P */
3397                         0x00000009, /* EMC_RD_RCD */
3398                         0x00000009, /* EMC_WR_RCD */
3399                         0x00000003, /* EMC_RRD */
3400                         0x00000001, /* EMC_REXT */
3401                         0x00000000, /* EMC_WEXT */
3402                         0x00000007, /* EMC_WDV */
3403                         0x0000000b, /* EMC_QUSE */
3404                         0x00000009, /* EMC_QRST */
3405                         0x0000000c, /* EMC_QSAFE */
3406                         0x00000011, /* EMC_RDV */
3407                         0x0000169a, /* EMC_REFRESH */
3408                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3409                         0x000005a6, /* EMC_PRE_REFRESH_REQ_CNT */
3410                         0x00000003, /* EMC_PDEX2WR */
3411                         0x00000010, /* EMC_PDEX2RD */
3412                         0x00000001, /* EMC_PCHG2PDEN */
3413                         0x00000000, /* EMC_ACT2PDEN */
3414                         0x0000000e, /* EMC_AR2PDEN */
3415                         0x00000018, /* EMC_RW2PDEN */
3416                         0x000000e9, /* EMC_TXSR */
3417                         0x00000200, /* EMC_TXSRDLL */
3418                         0x00000005, /* EMC_TCKE */
3419                         0x00000017, /* EMC_TFAW */
3420                         0x00000000, /* EMC_TRPAB */
3421                         0x00000007, /* EMC_TCLKSTABLE */
3422                         0x00000008, /* EMC_TCLKSTOP */
3423                         0x000016da, /* EMC_TREFBW */
3424                         0x0000000c, /* EMC_QUSE_EXTRA */
3425                         0x00000004, /* EMC_FBIO_CFG6 */
3426                         0x00000000, /* EMC_ODT_WRITE */
3427                         0x00000000, /* EMC_ODT_READ */
3428                         0x00005088, /* EMC_FBIO_CFG5 */
3429                         0xf0080191, /* EMC_CFG_DIG_DLL */
3430                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3431                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
3432                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
3433                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
3434                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
3435                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
3436                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
3437                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
3438                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
3439                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3440                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3441                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3442                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3443                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3444                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3445                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3446                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3447                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3448                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3449                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3450                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3451                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3452                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3453                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3454                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3455                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
3456                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
3457                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
3458                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
3459                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3460                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
3461                         0x22220000, /* EMC_XM2DQPADCTRL2 */
3462                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3463                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
3464                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
3465                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
3466                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3467                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
3468                         0x00000802, /* EMC_CTT_TERM_CTRL */
3469                         0x00020000, /* EMC_ZCAL_INTERVAL */
3470                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3471                         0x00df000c, /* EMC_MRS_WAIT_CNT */
3472                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3473                         0x00000000, /* EMC_CTT */
3474                         0x00000000, /* EMC_CTT_DURATION */
3475                         0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
3476                         0x00000016, /* MC_EMEM_ARB_CFG */
3477                         0xc0000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3478                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3479                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3480                         0x00000012, /* MC_EMEM_ARB_TIMING_RC */
3481                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3482                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
3483                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3484                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3485                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3486                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3487                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3488                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3489                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3490                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
3491                         0x00160d12, /* MC_EMEM_ARB_DA_COVERS */
3492                         0x73cc2213, /* MC_EMEM_ARB_MISC0 */
3493                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3494                         0xf8000000, /* EMC_FBIO_SPARE */
3495                         0xff00ff49, /* EMC_CFG_RSV */
3496                 },
3497                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3498                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3499                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3500                 0x80000d71, /* Mode Register 0 */
3501                 0x80100002, /* Mode Register 1 */
3502                 0x80200018, /* Mode Register 2 */
3503                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3504         },
3505         {
3506                 0x32,       /* Rev 3.2 */
3507                 800000,     /* SDRAM frequency */
3508                 {
3509                         0x00000025, /* EMC_RC */
3510                         0x000000ce, /* EMC_RFC */
3511                         0x0000001a, /* EMC_RAS */
3512                         0x00000009, /* EMC_RP */
3513                         0x00000005, /* EMC_R2W */
3514                         0x0000000d, /* EMC_W2R */
3515                         0x00000004, /* EMC_R2P */
3516                         0x00000013, /* EMC_W2P */
3517                         0x00000009, /* EMC_RD_RCD */
3518                         0x00000009, /* EMC_WR_RCD */
3519                         0x00000003, /* EMC_RRD */
3520                         0x00000001, /* EMC_REXT */
3521                         0x00000000, /* EMC_WEXT */
3522                         0x00000007, /* EMC_WDV */
3523                         0x0000000b, /* EMC_QUSE */
3524                         0x00000009, /* EMC_QRST */
3525                         0x0000000c, /* EMC_QSAFE */
3526                         0x00000012, /* EMC_RDV */
3527                         0x00001820, /* EMC_REFRESH */
3528                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3529                         0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
3530                         0x00000003, /* EMC_PDEX2WR */
3531                         0x00000012, /* EMC_PDEX2RD */
3532                         0x00000001, /* EMC_PCHG2PDEN */
3533                         0x00000000, /* EMC_ACT2PDEN */
3534                         0x0000000f, /* EMC_AR2PDEN */
3535                         0x00000018, /* EMC_RW2PDEN */
3536                         0x000000d8, /* EMC_TXSR */
3537                         0x00000200, /* EMC_TXSRDLL */
3538                         0x00000005, /* EMC_TCKE */
3539                         0x00000018, /* EMC_TFAW */
3540                         0x00000000, /* EMC_TRPAB */
3541                         0x00000007, /* EMC_TCLKSTABLE */
3542                         0x00000008, /* EMC_TCLKSTOP */
3543                         0x00001860, /* EMC_TREFBW */
3544                         0x0000000c, /* EMC_QUSE_EXTRA */
3545                         0x00000004, /* EMC_FBIO_CFG6 */
3546                         0x00000000, /* EMC_ODT_WRITE */
3547                         0x00000000, /* EMC_ODT_READ */
3548                         0x00005088, /* EMC_FBIO_CFG5 */
3549                         0xf0070191, /* EMC_CFG_DIG_DLL */
3550                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3551                         0x0000c008, /* EMC_DLL_XFORM_DQS0 */
3552                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
3553                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
3554                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
3555                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
3556                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
3557                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
3558                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
3559                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3560                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3561                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3562                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3563                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3564                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3565                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3566                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3567                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3568                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3569                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3570                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3571                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3572                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3573                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3574                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3575                         0x007f800c, /* EMC_DLL_XFORM_DQ0 */
3576                         0x007f800c, /* EMC_DLL_XFORM_DQ1 */
3577                         0x007f800c, /* EMC_DLL_XFORM_DQ2 */
3578                         0x007f800c, /* EMC_DLL_XFORM_DQ3 */
3579                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3580                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
3581                         0x22220000, /* EMC_XM2DQPADCTRL2 */
3582                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3583                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
3584                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
3585                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
3586                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3587                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
3588                         0x00000802, /* EMC_CTT_TERM_CTRL */
3589                         0x00020000, /* EMC_ZCAL_INTERVAL */
3590                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3591                         0x00f0000c, /* EMC_MRS_WAIT_CNT */
3592                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3593                         0x00000000, /* EMC_CTT */
3594                         0x00000000, /* EMC_CTT_DURATION */
3595                         0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
3596                         0x00000018, /* MC_EMEM_ARB_CFG */
3597                         0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3598                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3599                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3600                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
3601                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3602                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
3603                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3604                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3605                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3606                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3607                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3608                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3609                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3610                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
3611                         0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
3612                         0x712c2414, /* MC_EMEM_ARB_MISC0 */
3613                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3614                         0xf8000000, /* EMC_FBIO_SPARE */
3615                         0xff00ff49, /* EMC_CFG_RSV */
3616                 },
3617                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3618                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3619                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3620                 0x80000d71, /* Mode Register 0 */
3621                 0x80100002, /* Mode Register 1 */
3622                 0x80200018, /* Mode Register 2 */
3623                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3624         },
3625 };
3626
3627 static const struct tegra30_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
3628         {
3629                 0x32,       /* Rev 3.2 */
3630                 25500,      /* SDRAM frequency */
3631                 {
3632                         0x00000001, /* EMC_RC */
3633                         0x00000006, /* EMC_RFC */
3634                         0x00000000, /* EMC_RAS */
3635                         0x00000000, /* EMC_RP */
3636                         0x00000002, /* EMC_R2W */
3637                         0x0000000a, /* EMC_W2R */
3638                         0x00000005, /* EMC_R2P */
3639                         0x0000000b, /* EMC_W2P */
3640                         0x00000000, /* EMC_RD_RCD */
3641                         0x00000000, /* EMC_WR_RCD */
3642                         0x00000003, /* EMC_RRD */
3643                         0x00000001, /* EMC_REXT */
3644                         0x00000000, /* EMC_WEXT */
3645                         0x00000005, /* EMC_WDV */
3646                         0x00000005, /* EMC_QUSE */
3647                         0x00000004, /* EMC_QRST */
3648                         0x00000009, /* EMC_QSAFE */
3649                         0x0000000b, /* EMC_RDV */
3650                         0x000000c0, /* EMC_REFRESH */
3651                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3652                         0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
3653                         0x00000002, /* EMC_PDEX2WR */
3654                         0x00000002, /* EMC_PDEX2RD */
3655                         0x00000001, /* EMC_PCHG2PDEN */
3656                         0x00000000, /* EMC_ACT2PDEN */
3657                         0x00000007, /* EMC_AR2PDEN */
3658                         0x0000000f, /* EMC_RW2PDEN */
3659                         0x00000007, /* EMC_TXSR */
3660                         0x00000007, /* EMC_TXSRDLL */
3661                         0x00000004, /* EMC_TCKE */
3662                         0x00000001, /* EMC_TFAW */
3663                         0x00000000, /* EMC_TRPAB */
3664                         0x00000004, /* EMC_TCLKSTABLE */
3665                         0x00000005, /* EMC_TCLKSTOP */
3666                         0x000000c7, /* EMC_TREFBW */
3667                         0x00000006, /* EMC_QUSE_EXTRA */
3668                         0x00000004, /* EMC_FBIO_CFG6 */
3669                         0x00000000, /* EMC_ODT_WRITE */
3670                         0x00000000, /* EMC_ODT_READ */
3671                         0x00004288, /* EMC_FBIO_CFG5 */
3672                         0x007800a4, /* EMC_CFG_DIG_DLL */
3673                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3674                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
3675                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
3676                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
3677                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
3678                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
3679                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
3680                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
3681                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
3682                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3683                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3684                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3685                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3686                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3687                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3688                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3689                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3690                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3691                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3692                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3693                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3694                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3695                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3696                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3697                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3698                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
3699                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
3700                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
3701                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
3702                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3703                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
3704                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3705                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3706                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
3707                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3708                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3709                         0x08000168, /* EMC_XM2QUSEPADCTRL */
3710                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
3711                         0x00000802, /* EMC_CTT_TERM_CTRL */
3712                         0x00000000, /* EMC_ZCAL_INTERVAL */
3713                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
3714                         0x000c000c, /* EMC_MRS_WAIT_CNT */
3715                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3716                         0x00000000, /* EMC_CTT */
3717                         0x00000000, /* EMC_CTT_DURATION */
3718                         0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
3719                         0x00030003, /* MC_EMEM_ARB_CFG */
3720                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3721                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3722                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3723                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
3724                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3725                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
3726                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3727                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3728                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3729                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3730                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3731                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3732                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3733                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3734                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
3735                         0x75830303, /* MC_EMEM_ARB_MISC0 */
3736                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3737                         0xe8000000, /* EMC_FBIO_SPARE */
3738                         0xff00ff00, /* EMC_CFG_RSV */
3739                 },
3740                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3741                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3742                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3743                 0x80001221, /* Mode Register 0 */
3744                 0x80100003, /* Mode Register 1 */
3745                 0x80200008, /* Mode Register 2 */
3746                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3747         },
3748         {
3749                 0x32,       /* Rev 3.2 */
3750                 51000,      /* SDRAM frequency */
3751                 {
3752                         0x00000002, /* EMC_RC */
3753                         0x0000000d, /* EMC_RFC */
3754                         0x00000001, /* EMC_RAS */
3755                         0x00000000, /* EMC_RP */
3756                         0x00000002, /* EMC_R2W */
3757                         0x0000000a, /* EMC_W2R */
3758                         0x00000005, /* EMC_R2P */
3759                         0x0000000b, /* EMC_W2P */
3760                         0x00000000, /* EMC_RD_RCD */
3761                         0x00000000, /* EMC_WR_RCD */
3762                         0x00000003, /* EMC_RRD */
3763                         0x00000001, /* EMC_REXT */
3764                         0x00000000, /* EMC_WEXT */
3765                         0x00000005, /* EMC_WDV */
3766                         0x00000005, /* EMC_QUSE */
3767                         0x00000004, /* EMC_QRST */
3768                         0x00000009, /* EMC_QSAFE */
3769                         0x0000000b, /* EMC_RDV */
3770                         0x00000181, /* EMC_REFRESH */
3771                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3772                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
3773                         0x00000002, /* EMC_PDEX2WR */
3774                         0x00000002, /* EMC_PDEX2RD */
3775                         0x00000001, /* EMC_PCHG2PDEN */
3776                         0x00000000, /* EMC_ACT2PDEN */
3777                         0x00000007, /* EMC_AR2PDEN */
3778                         0x0000000f, /* EMC_RW2PDEN */
3779                         0x0000000e, /* EMC_TXSR */
3780                         0x0000000e, /* EMC_TXSRDLL */
3781                         0x00000004, /* EMC_TCKE */
3782                         0x00000002, /* EMC_TFAW */
3783                         0x00000000, /* EMC_TRPAB */
3784                         0x00000004, /* EMC_TCLKSTABLE */
3785                         0x00000005, /* EMC_TCLKSTOP */
3786                         0x0000018e, /* EMC_TREFBW */
3787                         0x00000006, /* EMC_QUSE_EXTRA */
3788                         0x00000004, /* EMC_FBIO_CFG6 */
3789                         0x00000000, /* EMC_ODT_WRITE */
3790                         0x00000000, /* EMC_ODT_READ */
3791                         0x00004288, /* EMC_FBIO_CFG5 */
3792                         0x007800a4, /* EMC_CFG_DIG_DLL */
3793                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3794                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
3795                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
3796                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
3797                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
3798                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
3799                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
3800                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
3801                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
3802                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3803                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3804                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3805                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3806                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3807                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3808                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3809                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3810                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3811                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3812                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3813                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3814                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3815                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3816                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3817                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3818                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
3819                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
3820                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
3821                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
3822                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3823                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
3824                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3825                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3826                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
3827                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3828                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3829                         0x08000168, /* EMC_XM2QUSEPADCTRL */
3830                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
3831                         0x00000802, /* EMC_CTT_TERM_CTRL */
3832                         0x00000000, /* EMC_ZCAL_INTERVAL */
3833                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
3834                         0x000c000c, /* EMC_MRS_WAIT_CNT */
3835                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3836                         0x00000000, /* EMC_CTT */
3837                         0x00000000, /* EMC_CTT_DURATION */
3838                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
3839                         0x00010003, /* MC_EMEM_ARB_CFG */
3840                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3841                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3842                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3843                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
3844                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3845                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
3846                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3847                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3848                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3849                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3850                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3851                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3852                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3853                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3854                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
3855                         0x74630303, /* MC_EMEM_ARB_MISC0 */
3856                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3857                         0xe8000000, /* EMC_FBIO_SPARE */
3858                         0xff00ff00, /* EMC_CFG_RSV */
3859                 },
3860                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3861                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3862                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3863                 0x80001221, /* Mode Register 0 */
3864                 0x80100003, /* Mode Register 1 */
3865                 0x80200008, /* Mode Register 2 */
3866                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3867         },
3868         {
3869                 0x32,       /* Rev 3.2 */
3870                 102000,     /* SDRAM frequency */
3871                 {
3872                         0x00000004, /* EMC_RC */
3873                         0x0000001a, /* EMC_RFC */
3874                         0x00000003, /* EMC_RAS */
3875                         0x00000001, /* EMC_RP */
3876                         0x00000002, /* EMC_R2W */
3877                         0x0000000a, /* EMC_W2R */
3878                         0x00000005, /* EMC_R2P */
3879                         0x0000000b, /* EMC_W2P */
3880                         0x00000001, /* EMC_RD_RCD */
3881                         0x00000001, /* EMC_WR_RCD */
3882                         0x00000003, /* EMC_RRD */
3883                         0x00000001, /* EMC_REXT */
3884                         0x00000000, /* EMC_WEXT */
3885                         0x00000005, /* EMC_WDV */
3886                         0x00000005, /* EMC_QUSE */
3887                         0x00000004, /* EMC_QRST */
3888                         0x00000009, /* EMC_QSAFE */
3889                         0x0000000b, /* EMC_RDV */
3890                         0x00000303, /* EMC_REFRESH */
3891                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3892                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
3893                         0x00000002, /* EMC_PDEX2WR */
3894                         0x00000002, /* EMC_PDEX2RD */
3895                         0x00000001, /* EMC_PCHG2PDEN */
3896                         0x00000000, /* EMC_ACT2PDEN */
3897                         0x00000007, /* EMC_AR2PDEN */
3898                         0x0000000f, /* EMC_RW2PDEN */
3899                         0x0000001c, /* EMC_TXSR */
3900                         0x0000001c, /* EMC_TXSRDLL */
3901                         0x00000004, /* EMC_TCKE */
3902                         0x00000004, /* EMC_TFAW */
3903                         0x00000000, /* EMC_TRPAB */
3904                         0x00000004, /* EMC_TCLKSTABLE */
3905                         0x00000005, /* EMC_TCLKSTOP */
3906                         0x0000031c, /* EMC_TREFBW */
3907                         0x00000006, /* EMC_QUSE_EXTRA */
3908                         0x00000004, /* EMC_FBIO_CFG6 */
3909                         0x00000000, /* EMC_ODT_WRITE */
3910                         0x00000000, /* EMC_ODT_READ */
3911                         0x00004288, /* EMC_FBIO_CFG5 */
3912                         0x007800a4, /* EMC_CFG_DIG_DLL */
3913                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3914                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
3915                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
3916                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
3917                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
3918                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
3919                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
3920                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
3921                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
3922                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3923                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3924                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3925                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3926                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3927                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3928                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3929                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3930                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3931                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3932                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3933                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3934                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3935                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3936                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3937                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3938                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
3939                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
3940                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
3941                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
3942                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3943                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
3944                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3945                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3946                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
3947                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3948                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3949                         0x08000168, /* EMC_XM2QUSEPADCTRL */
3950                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
3951                         0x00000802, /* EMC_CTT_TERM_CTRL */
3952                         0x00000000, /* EMC_ZCAL_INTERVAL */
3953                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
3954                         0x000c000c, /* EMC_MRS_WAIT_CNT */
3955                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3956                         0x00000000, /* EMC_CTT */
3957                         0x00000000, /* EMC_CTT_DURATION */
3958                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
3959                         0x00000003, /* MC_EMEM_ARB_CFG */
3960                         0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3961                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3962                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3963                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
3964                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3965                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
3966                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3967                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3968                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3969                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3970                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3971                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3972                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3973                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3974                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
3975                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
3976                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3977                         0xe8000000, /* EMC_FBIO_SPARE */
3978                         0xff00ff00, /* EMC_CFG_RSV */
3979                 },
3980                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3981                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3982                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3983                 0x80001221, /* Mode Register 0 */
3984    &